ninja: Entering directory `out/gn'
[0/1] ACTION //clang/test:check-clang(//llvm/utils/gn/build/toolchain:unix)
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using clang: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using ld.lld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/ld.lld
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using lld-link: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/lld-link
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using ld64.lld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/ld64.lld
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using wasm-ld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/wasm-ld
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using ld.lld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/ld.lld
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using lld-link: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/lld-link
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using ld64.lld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/ld64.lld
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using wasm-ld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/wasm-ld
-- Testing: 27911 tests, 64 workers --
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c (1 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaeskf2_vi_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaeskf2.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaeskf2.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaeskf2_vi_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaeskf2.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaeskf2.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaeskf2_vi_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaeskf2_vi_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaeskf2.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaeskf2.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaeskf2_vi_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaeskf2.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaeskf2.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005642c34bdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005642c34bae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005642c34be62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc5cb933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5cb98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc5cb933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc5cb91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005642c3453bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005642c3453a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005642c34388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005642c30e7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005642c30e7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc5cb91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5cb91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5cb91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005642c30e7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c (2 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8ff_v_i8mf8x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8ff_v_i8mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8ff_v_i8mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8ff_v_i8m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8ff_v_i8m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8ff_v_u8mf8x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8ff_v_u8mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8ff_v_u8mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vec
# | ...
# `---data was truncated (10240/27595) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ef8547feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ef8547ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ef8548062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6b5fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6b5fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6b5fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6b5fc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ef85415bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ef85415a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ef853fa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ef850a9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ef850a9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6b5fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6b5fc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6b5fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ef850a9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c (3 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm3me_vv_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm3me_vv_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm3me_vv_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm3me_vv_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm3me_vv_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557f44533eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557f44530e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557f4453462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f2dd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f2dd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f2dd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f2dced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f444c9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557f444c9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557f444ae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557f4415de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557f4415db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2f2dceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f2dcef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f2dcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f4415da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/arm-neon-vcadd.c (4 of 27911)
******************** TEST 'Clang :: CodeGen/arm-neon-vcadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.3a-arm-none-eabi -target-cpu generic  -target-feature +fullfp16 -mfloat-abi soft -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c |  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.3a-arm-none-eabi -target-cpu generic -target-feature +fullfp16 -mfloat-abi soft -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8.3a-arm-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @foo16x4_rot90(<4 x half> noundef %a, <4 x half> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %result = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vcadd_rot90_f16.i = bitcast <8 x i8> %2 to <4 x half>
# |   %vcadd_rot90_f161.i = bitcast <8 x i8> %3 to <4 x half>
# |   %vcadd_rot90_f162.i = call <4 x half> @llvm.arm.neon.vcadd.rot90.v4f16(<4 x half> %vcadd_rot90_f16.i, <4 x half> %vcadd_rot90_f161.i)
# |   %vcadd_rot90_f163.i = bitcast <4 x half> %vcadd_rot90_f162.i to <8 x i8>
# |   store <8 x i8> %vcadd_rot90_f163.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x half>, ptr %__ret.i, align 8
# |   store <4 x half> %5, ptr %result, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @foo32x2_rot90(<2 x float> noundef %a, <2 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %result = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vcadd_rot90_f32.i = bitcast <8 x i8> %2 to <2 x float>
# |   %vcadd_rot90_f321.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vcadd_rot90_f322.i = call <2 x float> @llvm.arm.neon.vcadd.rot90.v2f32(<2 x float> %vcadd_rot90_f32.i, <2 x float> %vcadd_rot90_f321.i)
# |   %vcadd_rot90_f323.i = bitcast <2 x float> %vcadd_rot90_f322.i to <8 x i8>
# |   store <8 x i8> %vcadd_rot90_f323.i, ptr %ref.tmp.i, align 8
# |   %4 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %4, ptr %__ret.i, align 8
# |   %5 = load <2 x float>, ptr %__ret.i, align 8
# |   store <2 x float> %5, ptr %result, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @foo16x8_rot90(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 8
# |   %__p1.addr.i = alloca <8 x half>, align 8
# |   %__ret.i = alloca <8 x half>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %result = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   store <8 x half> %0, ptr %__p0.addr.i, align 8
# |   store <8 x half> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %vcaddq_rot90_f16.i = bitcast <16 x i8> %2 to <8 x half>
# |   %vcaddq_rot90_f161.i = bitcast <16 x i8> %3 to <8 x half>
# |   %vcaddq_rot90_f162.i = call <8 x half> @llvm.arm.neon.vcadd.rot90.v8f16(<8 x half> %vcaddq_rot90_f16.i, <8 x half> %vcaddq_rot90_f161.i)
# |   %vcaddq_rot90_f163.i = bitcast <8 x half> %vcaddq_rot90_f162.i to <16 x i8>
# |   store <16 x i8> %vcaddq_rot90_f163.i, ptr %ref.tmp.i, align 8
# |   %4 = load <8 x half>, ptr %ref.tmp.i, align 8
# |   store <8 x half> %4, ptr %__ret.i, align 8
# |   %5 = load <8 x half>, ptr %__ret.i, align 8
# |   store <8 x half> %5, ptr %result, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @foo32x4_rot90(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__p1.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %result = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %vcaddq_rot90_f32.i = bitcast <16 x i8> %2 to <4 x float>
# |   %vcaddq_rot90_f321.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vcaddq_rot90_f322.i = call <4 x float> @llvm.arm.neon.vcadd.rot90.v4f32(<4 x float> %vcaddq_rot90_f32.i, <4 x float> %vcaddq_rot90_f321.i)
# |   %vcaddq_rot90_f323.i = bitcast <4 x float> %vcaddq_rot90_f322.i to <16 x i8>
# |   store <16 x i8> %vcaddq_rot90_f323.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x float>, ptr %__ret.i, align 8
# |   store <4 x float> %5, ptr %result, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @foo16x4_rot270(<4 x half> noundef %a, <4 x half> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %result = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vcadd_rot270_f16.i = bitcast <8 x i8> %2 to <4 x half>
# |   %vcadd_rot270_f161.i = bitcast <8 x i8> %3 to <4 x half>
# |   %vcadd_rot270_f162.i = call <4 x half> @llvm.arm.neon.vcadd.rot270.v4f16(<4 x half> %vcadd_rot270_f16.i, <4 x half> %vcadd_rot270_f161.i)
# |   %vcadd_rot270_f163.i = bitcast <4 x half> %vcadd_rot270_f162.i to <8 x i8>
# |   store <8 x i8> %vcadd_rot270_f163.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x half>, ptr %__ret.i, align 8
# |   store <4 x half> %5, ptr %result, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @foo32x2_rot270(<2 x float> noundef %a, <2 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %result = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vcadd_rot270_f32.i = bitcast <8 x i8> %2 to <2 x float>
# |   %vcadd_rot270_f321.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vcadd_rot270_f322.i = call <2 x float> @llvm.arm.neon.vcadd.rot270.v2f32(<2 x float> %vcadd_rot270_f32.i, <2 x float> %vcadd_rot270_f321.i)
# |   %vcadd_rot270_f323.i = bitcast <2 x float> %vcadd_rot270_f322.i to <8 x i8>
# |   store <8 x i8> %vcadd_rot270_f323.i, ptr %ref.tmp.i, align 8
# |   %4 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %4, ptr %__ret.i, align 8
# |   %5 = load <2 x float>, ptr %__ret.i, align 8
# |   store <2 x float> %5, ptr %result, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @foo16x8_rot270(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 8
# |   %__p1.addr.i = alloca <8 x half>, align 8
# |   %__ret.i = alloca <8 x half>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %result = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   store <8 x half> %0, ptr %__p0.addr.i, align 8
# |   store <8 x half> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %vcaddq_rot270_f16.i = bitcast <16 x i8> %2 to <8 x half>
# |   %vcaddq_rot270_f161.i = bitcast <16 x i8> %3 to <8 x half>
# |   %vcaddq_rot270_f162.i = call <8 x half> @llvm.arm.neon.vcadd.rot270.v8f16(<8 x half> %vcaddq_rot270_f16.i, <8 x half> %vcaddq_rot270_f161.i)
# |   %vcaddq_rot270_f163.i = bitcast <8 x half> %vcaddq_rot270_f162.i to <16 x i8>
# |   store <16 x i8> %vcaddq_rot270_f163.i, ptr %ref.tmp.i, align 8
# |   %4 = load <8 x half>, ptr %ref.tmp.i, align 8
# |   store <8 x half> %4, ptr %__ret.i, align 8
# |   %5 = load <8 x half>, ptr %__ret.i, align 8
# |   store <8 x half> %5, ptr %result, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @foo32x4_rot270(<4 x float> noundef %a, <4 
# | ...
# `---data was truncated (10240/13572) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa -o -
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa -o -
# |  #0 0x000055919e109eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055919e106e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055919e10a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f723ed05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f723ed5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f723ed05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f723eced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055919e09fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055919e09fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055919e0848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055919dd33e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055919dd33b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f723eceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f723ecef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f723ecef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055919dd33a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c (5 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vunzipe_v_bf16mf4(<vscale x 2 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vunzipe_v_bf16mf2(<vscale x 4 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vunzipe_v_bf16m1(<vscale x 8 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vunzipe_v_bf16m2(<vscale x 16 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vunzipe_v_bf16m4(<vscale x 32 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005581244a4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005581244a1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005581244a562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f279dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f279dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f279dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f279dc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055812443abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055812443aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055812441f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005581240cee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005581240ceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f279dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f279dc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f279dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005581240cea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c (6 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8mf8x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8mf8x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   cal
# | ...
# `---data was truncated (10240/23487) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005602f084ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005602f0849e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005602f084d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0472d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0472d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0472d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0472d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005602f07e2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005602f07e2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005602f07c78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005602f0476e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005602f0476b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0472d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0472d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0472d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005602f0476a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c (7 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtsmul_f16(<vscale x 8 x half> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.ftsmul.x.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ftsmul.x.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtsmul_f32(<vscale x 4 x float> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.ftsmul.x.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ftsmul.x.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtsmul_f64(<vscale x 2 x double> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.ftsmul.x.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ftsmul.x.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i64>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055dd3b14feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dd3b14ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dd3b15062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc5f2e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5f2ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc5f2e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc5f2e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd3b0e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dd3b0e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dd3b0ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dd3ad79e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dd3ad79b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc5f2e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5f2e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5f2e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd3ad79a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c (8 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563d8019aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563d80197e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563d8019b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe3e5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe3e52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe3e5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe3e5231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d80130bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563d80130a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563d801158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563d7fdc4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563d7fdc4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe3e5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe3e52330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe3e52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d7fdc4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c (9 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64_v_f64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vle.mask.nxv1f64.p0.i64(<vscale x 1 x double> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x double> @llvm.riscv.vle.mask.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64_v_f64m2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vle.mask.nxv2f64.p0.i64(<vscale x 2 x double> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.riscv.vle.mask.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vle64_v_f64m4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.vle.mask.nxv4f64.p0.i64(<vscale x 4 x double> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x double> @llvm.riscv.vle.mask.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vle64_v_f64m8_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.vle.mask.nxv8f64.p0.i64(<vscale x 8 x double> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x double> @llvm.riscv.vle.mask.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64_v_i64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vle.mask.nxv1i64.p0.i64(<vscale x 1 x i64> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i64> @llvm.riscv.vle.mask.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64_v_i64m2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vle.mask.nxv2i64.p0.i64(<vscale x 2 x i64> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.riscv.vle.mask.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64_v_i64m4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vle.mask.nxv4i64.p0.i64(<vscale x 4 x i64> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i64> @llvm.riscv.vle.mask.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64_v_i64m8_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vle.mask.nxv8i64.p0.i64(<vscale x 8 x i64> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i64> @llvm.riscv.vle.mask.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64_v_u64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vle.mask.nxv1i64.p0.i64(<vscale x 1 x i64> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64_v_u64m2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vle.mask.nxv2i64.p0.i64(<vscale x 2 x i64> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64_v_u64m4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>,
# | ...
# `---data was truncated (10240/11969) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056068549ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560685499e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056068549d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff39e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff39e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff39e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff39e231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560685432bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560685432a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005606854178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005606850c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005606850c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff39e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff39e2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff39e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005606850c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c (10 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_xu_f_qf_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %1, <vscale x 1 x float> %2, float %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %1, <vscale x 2 x float> %2, float %3, <vscale x 2 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, al
# | ...
# `---data was truncated (10240/26756) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a62586aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a625867e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a62586b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f78fb533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f78fb58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f78fb533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f78fb51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a625800bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a625800a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a6257e58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a625494e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a625494b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f78fb51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f78fb51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f78fb51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a625494a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c (11 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf8x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_u8mf8x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_u8mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_u8mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_u8m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.
# | ...
# `---data was truncated (10240/18972) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e9d4edaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e9d4ed7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e9d4edb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f96ef505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f96ef55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f96ef505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f96ef4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e9d4e70bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e9d4e70a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e9d4e558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e9d4b04e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e9d4b04b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f96ef4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f96ef4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f96ef4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e9d4b04a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c (12 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", 
# | ...
# `---data was truncated (10240/16800) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005556d17e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005556d17e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005556d17ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd1ece49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd1ecea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd1ece49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd1ece31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005556d177fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005556d177fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005556d17648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005556d1413e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005556d1413b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd1ece32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd1ece330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd1ece330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005556d1413a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c (13 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmax_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmax_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmax_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmax_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmax_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmax_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmax_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmax_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmax_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmax_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmax_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/97639) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c5911afeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c5911ace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c5911b062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd775f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd775f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd775f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd775f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c591145bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c591145a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c59112a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c590dd9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c590dd9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd775f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd775f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd775f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c590dd9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c (14 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f16m1x7(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f32m1x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f64m1x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei64_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d83e0eaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d83e0e7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d83e0eb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd927f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd927f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd927f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd927f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d83e080bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d83e080a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d83e0658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d83dd14e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d83dd14b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd927f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd927f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd927f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d83dd14a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c (15 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_f16mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_f16mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_f16m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_f16m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_i16mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_i16mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_i16m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_i16m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_u16mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | ent
# | ...
# `---data was truncated (10240/31706) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560b4b158eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560b4b155e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560b4b15962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4df1933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4df198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4df1933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4df191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b4b0eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560b4b0eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560b4b0d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560b4ad82e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560b4ad82b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4df191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4df191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4df191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b4ad82a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c (16 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_f64m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_i64m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_u64m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee26a33eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ee26a30e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ee26a3462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7a97b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7a97b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7a97b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7a97aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee269c9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ee269c9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ee269ae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ee2665de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ee2665db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7a97aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7a97aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7a97aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee2665da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c (17 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_f32mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_f32m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_i32mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_i32m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_u32mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_u32m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_i32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_i32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry
# | ...
# `---data was truncated (10240/14002) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aaa9dbeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aaa9dbbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aaa9dbf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f45f3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f45f3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f45f3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f45f3f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aaa9d54bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aaa9d54a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aaa9d398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aaa99e8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aaa99e8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f45f3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f45f3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f45f3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aaa99e8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c (18 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_2x8x2_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_2x8x2_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_2x8x2_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_2x8x2_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac11421eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ac1141ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ac1142262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8564a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8564aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8564a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8564a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac113b7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ac113b7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ac1139c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ac1104be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ac1104bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8564a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8564a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8564a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac1104ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c (19 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwi
# | ...
# `---data was truncated (10240/44369) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558ebe324eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558ebe321e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558ebe32562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e4841bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e484725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e4841ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e48403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558ebe2babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558ebe2baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558ebe29f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558ebdf4ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558ebdf4eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6e48404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e484050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e484050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558ebdf4ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmovl.c (20 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmovl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
# |   %2 = sext <8 x i8> %1 to <8 x i16>
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
# |   %2 = sext <4 x i16> %1 to <4 x i32>
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
# |   %2 = zext <8 x i8> %1 to <8 x i16>
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
# |   %2 = zext <4 x i16> %1 to <4 x i32>
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovltq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
# |   %2 = sext <8 x i8> %1 to <8 x i16>
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovltq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
# |   %2 = sext <4 x i16> %1 to <4 x i32>
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovltq_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
# |   %2 = zext <8 x i8> %1 to <8 x i16>
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovltq_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
# |   %2 = zext <4 x i16> %1 to <4 x i32>
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_m_s8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, i32 0, i32 0, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8>, i32, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_m_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = call <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, i32 0, i32 0, <4 x i1> %3, <4 x i32> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16>, i32, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_m_u8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, i32 1, i32 0, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_m_u16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = call <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, i32 1, i32 0, <4 x i1> %3, <4 x i32> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovltq_m_s8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, i32 0, i32 1, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovltq_m_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = call <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, i32 0, i32 1, <4 x i1> %3, <4 x i32> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovltq_m_u8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, i32 1, i32 1, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovltq_m_u16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.ad
# | ...
# `---data was truncated (10240/16274) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c81938deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c81938ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c81938e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe3a4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe3a438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe3a4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe3a431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c819323bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c819323a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c8193088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c818fb7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c818fb7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe3a431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe3a431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe3a431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c818fb7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c (21 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m4_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.r
# | ...
# `---data was truncated (10240/53678) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d771cfaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d771cf7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d771cfb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f996d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f996d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f996d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f996d91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d771c90bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d771c90a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d771c758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d771924e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d771924b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f996d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f996d91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f996d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d771924a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c (22 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_v
# | ...
# `---data was truncated (10240/228865) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565013936eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565013933e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056501393762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff929849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff9298a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff929849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff929831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005650138ccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005650138cca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005650138b18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565013560e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565013560b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff929832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff9298330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff9298330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565013560a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c (23 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b79df0aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b79df07e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b79df0b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6445333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f644538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6445333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f644531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b79dea0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b79dea0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b79de858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b79db34e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b79db34b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f644531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f644531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f644531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b79db34a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c (24 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac66945eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ac66942e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ac6694662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f72933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f7298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f72933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f7291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac668dbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ac668dba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ac668c08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ac6656fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ac6656fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2f7291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f7291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f7291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac6656fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c (25 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1_tu(<vscale x 1 x double> %vd, <vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64.i64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x double> @test_sf_vfexpa_v_f64m2_tu(<vscale x 2 x double> %vd, <vscale x 2 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x double>, align 8
# |   %vs2.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64.i64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64.i64(<vscale x 2 x double>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x double> @test_sf_vfexpa_v_f64m4_tu(<vscale x 4 x double> %vd, <vscale x 4 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x double>, align 8
# |   %vs2.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64.i64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i64 %2)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64.i64(<vscale x 4 x double>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vfexpa_v_f64m8_tu(<vscale x 8 x double> %vd, <vscale x 8 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x double>, align 8
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64.i64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, i64 %2)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64.i64(<vscale x 8 x double>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1_tum(<vscale x 1 x i1> %vm, <vscale x 1 x double> %vd, <vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(<vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x double> @test_sf_vfexpa_v_f64m2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x double> %vd, <vscale x 2 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x double>, align 8
# |   %vs2.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 2 x double>, ptr %vs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(<vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x double> @test_sf_vfexpa_v_f64m4_tum(<vscale x 4 x i1> %vm, <vscale x 4 x double> %vd, <vscale x 4 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x double>, align 8
# |   %vs2.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 4 x double>, ptr %vs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(<vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(<vscale x 4 x double>, <vscale x 4 x double>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vfexpa_v_f64m8_tum(<vscale x 8 x i1> %vm, <vscale x 8 x double> %vd, <vscale x 8 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x double>, align 8
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(<vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(<vscale x 8 x double>, <vscale x 8 x double>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1_tumu(<vscale x 1 x i1> %vm, <vscale x 1 x double> %vd, <vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %vs2.addr, align
# | ...
# `---data was truncated (10240/18311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ea19749eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ea19746e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ea1974a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc5c8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5c818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc5c8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc5c811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ea196dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ea196dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ea196c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ea19373e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ea19373b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc5c811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5c811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5c811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ea19373a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c (26 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2ch_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2ch_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2ch_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2ch_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2ch_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2ch_vv_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2ch_vv_u64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2ch_vv_u64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | 
# | ...
# `---data was truncated (10240/12216) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005573a35beeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005573a35bbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005573a35bf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9ac2d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9ac2d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9ac2d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9ac2d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005573a3554bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005573a3554a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005573a35398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005573a31e8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005573a31e8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9ac2d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9ac2d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9ac2d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005573a31e8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c (27 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559813e70eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559813e6de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559813e7162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb003a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb003aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb003a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb003a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559813e06bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559813e06a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559813deb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559813a9ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559813a9ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb003a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb003a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb003a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559813a9aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c (28 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vcompress_vm_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vcompress_vm_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vcompress_vm_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vcompress_vm_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vcompress_vm_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x i1> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vcompress_vm_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, <vscale x 32 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x i1> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005613ca897eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005613ca894e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005613ca89862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff346b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff346b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff346b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff346b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005613ca82dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005613ca82da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005613ca8128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005613ca4c1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005613ca4c1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff346b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff346b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff346b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005613ca4c1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGenCoroutines/coro-gro4.cpp (29 of 27911)
******************** TEST 'Clang :: CodeGenCoroutines/coro-gro4.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 -O2 -disable-llvm-passes -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes='default<O0>,default<O2>' -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 -O2 -disable-llvm-passes -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | %struct.wrapper = type { %struct.task }
# | %struct.task = type { %"struct.std::coroutine_handle" }
# | %"struct.std::coroutine_handle" = type { %"struct.std::coroutine_handle.0" }
# | %"struct.std::coroutine_handle.0" = type { ptr }
# | %"struct.task::promise_type" = type { i8 }
# | %"struct.std::suspend_always" = type { i8 }
# | 
# | $_ZN4task12promise_type17get_return_objectEv = comdat any
# | 
# | $_ZN4task12promise_type15initial_suspendEv = comdat any
# | 
# | $_ZNSt14suspend_always11await_readyEv = comdat any
# | 
# | $_ZNSt14suspend_always13await_suspendESt16coroutine_handleIvE = comdat any
# | 
# | $_ZNSt16coroutine_handleIN4task12promise_typeEE12from_addressEPv = comdat any
# | 
# | $_ZNSt14suspend_always12await_resumeEv = comdat any
# | 
# | $_ZN4task12promise_type11return_voidEv = comdat any
# | 
# | $_ZN4task12promise_type13final_suspendEv = comdat any
# | 
# | $_ZN7wrapperC1EO4task = comdat any
# | 
# | $_ZN4taskD1Ev = comdat any
# | 
# | $_ZNSt16coroutine_handleIN4task12promise_typeEE12from_promiseERS1_ = comdat any
# | 
# | $_ZN4taskC1ESt16coroutine_handleINS_12promise_typeEE = comdat any
# | 
# | $_ZNSt16coroutine_handleIN4task12promise_typeEEC1Ev = comdat any
# | 
# | $_ZNSt16coroutine_handleIN4task12promise_typeEEC2Ev = comdat any
# | 
# | $_ZNSt16coroutine_handleIvEC2Ev = comdat any
# | 
# | $_ZN4taskC2ESt16coroutine_handleINS_12promise_typeEE = comdat any
# | 
# | $_ZN7wrapperC2EO4task = comdat any
# | 
# | $_ZN4taskC1EOS_ = comdat any
# | 
# | $_ZN4taskC2EOS_ = comdat any
# | 
# | $_ZNSt16coroutine_handleIvEaSEDn = comdat any
# | 
# | $_ZN4taskD2Ev = comdat any
# | 
# | $_ZNKSt16coroutine_handleIvEcvbEv = comdat any
# | 
# | $_ZNKSt16coroutine_handleIvE7destroyEv = comdat any
# | 
# | ; Function Attrs: mustprogress nounwind presplitcoroutine
# | define dso_local void @_Z2fnv(ptr dead_on_unwind noalias writable sret(%struct.wrapper) align 8 %agg.result) #0 {
# | entry:
# |   %result.ptr = alloca ptr, align 8
# |   %gro.active = alloca i1, align 1
# |   %__promise = alloca %"struct.task::promise_type", align 1
# |   %__coro_gro = alloca %struct.task, align 8, !coro.outside.frame !6
# |   %ref.tmp = alloca %"struct.std::suspend_always", align 1
# |   %undef.agg.tmp = alloca %"struct.std::suspend_always", align 1
# |   %ref.tmp2 = alloca %"struct.std::suspend_always", align 1
# |   %undef.agg.tmp3 = alloca %"struct.std::suspend_always", align 1
# |   store ptr %agg.result, ptr %result.ptr, align 8
# |   %0 = call token @llvm.coro.id(i32 16, ptr %__promise, ptr null, ptr null)
# |   %1 = call i1 @llvm.coro.alloc(token %0)
# |   br i1 %1, label %coro.alloc, label %coro.init
# | 
# | coro.alloc:                                       ; preds = %entry
# |   %2 = call i64 @llvm.coro.size.i64()
# |   %call = call noalias noundef nonnull ptr @_Znwm(i64 noundef %2) #14
# |   br label %coro.init
# | 
# | coro.init:                                        ; preds = %coro.alloc, %entry
# |   %3 = phi ptr [ null, %entry ], [ %call, %coro.alloc ]
# |   %4 = call ptr @llvm.coro.begin(token %0, ptr %3)
# |   store i1 false, ptr %gro.active, align 1
# |   call void @llvm.lifetime.start.p0(ptr %__promise) #9
# |   call void @llvm.lifetime.start.p0(ptr %__coro_gro) #9
# |   call void @_ZN4task12promise_type17get_return_objectEv(ptr dead_on_unwind writable sret(%struct.task) align 8 %__coro_gro, ptr noundef nonnull align 1 dereferenceable(1) %__promise) #9
# |   store i1 true, ptr %gro.active, align 1
# |   call void @llvm.lifetime.start.p0(ptr %ref.tmp) #9
# |   call void @_ZN4task12promise_type15initial_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise) #9
# |   %call1 = call noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp) #9
# |   br i1 %call1, label %init.ready, label %init.suspend
# | 
# | init.suspend:                                     ; preds = %coro.init
# |   %5 = call token @llvm.coro.save(ptr null)
# |   call void @llvm.coro.await.suspend.void(ptr %ref.tmp, ptr %4, ptr @_Z2fnv.__await_suspend_wrapper__init) #9
# |   %6 = call i8 @llvm.coro.suspend(token %5, i1 false)
# |   switch i8 %6, label %pre.gvo.conv [
# |     i8 0, label %init.ready
# |     i8 1, label %init.cleanup
# |   ]
# | 
# | init.cleanup:                                     ; preds = %init.suspend
# |   br label %cleanup
# | 
# | init.ready:                                       ; preds = %init.suspend, %coro.init
# |   call void @_ZNSt14suspend_always12await_resumeEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp) #9
# |   br label %cleanup
# | 
# | cleanup:                                          ; preds = %init.ready, %init.cleanup
# |   %cleanup.dest.slot.0 = phi i32 [ 0, %init.ready ], [ 2, %init.cleanup ]
# |   call void @llvm.lifetime.end.p0(ptr %ref.tmp) #9
# |   switch i32 %cleanup.dest.slot.0, label %unreachable [
# |     i32 0, label %cleanup.cont
# |     i32 2, label %coro.cleanup
# |   ]
# | 
# | cleanup.cont:                                     ; preds = %cleanup
# |   call void @_ZN4task12promise_type11return_voidEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise) #9
# |   br label %coro.final
# | 
# | coro.final:                                       ; preds = %cleanup.cont
# |   call void @llvm.lifetime.start.p0(ptr %ref.tmp2) #9
# |   call void @_ZN4task12promise_type13final_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise) #9
# |   %call4 = call noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp2) #9
# |   br i1 %call4, label %final.ready, label %final.suspend
# | 
# | final.suspend:                                    ; preds = %coro.final
# |   %7 = call token @llvm.coro.save(ptr null)
# |   call void @llvm.coro.await.suspend.void(ptr %ref.tmp2, ptr %4, ptr @_Z2fnv.__await_suspend_wrapper__final) #9
# |   %8 = call i8 @llvm.coro.suspend(token %7, i1 true)
# |   switch i8 %8, label %pre.gvo.conv [
# |     i8 0, label %final.ready
# |     i8 1, label %final.cleanup
# |   ]
# | 
# | final.cleanup:                                    ; preds = %final.suspend
# |   br label %cleanup5
# | 
# | final.ready:                                      ; preds = %final.suspend, %coro.final
# |   call void @_ZNSt14suspend_always12await_resumeEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp2) #9
# |   br label %cleanup5
# | 
# | cleanup5:                                         ; preds = %final.ready, %final.cleanup
# |   %cleanup.dest.slot.1 = phi i32 [ 0, %final.ready ], [ 2, %final.cleanup ]
# |   call void @llvm.lifetime.end.p0(ptr %ref.tmp2) #9
# |   switch i32 %cleanup.dest.slot.1, label %unreachable [
# |     i32 0, label %pre.gvo.conv
# |     i32 2, label %coro.cleanup
# |   ]
# | 
# | pre.gvo.conv:                                     ; preds = %cleanup5, %final.suspend, %init.suspend
# |   %9 = phi i1 [ true, %cleanup5 ], [ false, %final.suspend ], [ false, %init.suspend ]
# |   %InRamp = call i1 @llvm.coro.is_in_ramp()
# |   br i1 %InRamp, label %gro.conv, label %after.gro.conv
# | 
# | gro.conv:                                         ; preds = %pre.gvo.conv
# |   call void @_ZN7wrapperC1EO4task(ptr noundef nonnull align 8 dereferenceable(8) %agg.result, ptr noundef nonnull align 8 dereferenceable(8) %__coro_gro) #9
# |   %cleanup.is_active = load i1, ptr %gro.active, align 1
# |   br i1 %cleanup.is_active, label %cleanup.action, label %cleanup.done
# | 
# | cleanup.action:                                   ; preds = %gro.conv
# |   call void @_ZN4taskD1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) %__coro_gro) #9
# |   br label %cleanup.done
# | 
# | cleanup.done:                                     ; preds = %cleanup.action, %gro.conv
# |   br label %after.gro.conv
# | 
# | after.gro.conv:                                   ; preds = %cleanup.done, %pre.gvo.conv
# |   br i1 %9, label %cleanup.cont7, label %coro.ret
# | 
# | cleanup.cont7:                                    ; preds = %after.gro.conv
# |   br label %coro.cleanup
# | 
# | coro.cleanup:                                     ; preds = %cleanup.cont7, %cleanup5, %cleanup
# |   call void @llvm.lifetime.end.p0(ptr %__coro_gro) #9
# |   call void @llvm.lifetime.end.p0(ptr %__promise) #9
# |   %10 = call ptr @llvm.coro.free(token %0, ptr %4)
# |   %11 = icmp ne ptr %10, null
# |   br i1 %11, label %coro.free, label %after.coro.free
# | 
# | coro.free:                                        ; preds = %coro.cleanup
# |   %12 = call i64 @llvm.coro.size.i64()
# |   call void @_ZdlPvm(ptr noundef %10, i64 noundef %12) #9
# |   br label %after.coro.free
# | 
# | after.coro.free:                                  ; preds = %coro.cleanup, %coro.free
# |   call void @llvm.coro.dead(ptr %4)
# |   br label %coro.ret
# | 
# | coro.ret:                                         ; preds = %after.coro.free, %after.gro.conv
# |   call void @llvm.coro.end(ptr null, i1 false, token none)
# |   ret void
# | 
# | unreachable:                                      ; preds = %cleanup5, %cleanup
# |   unreachable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare token @llvm.coro.id(i32, ptr readnone, ptr readonly captures(none), ptr) #1
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare i1 @llvm.coro.alloc(token) #2
# | 
# | ; Function Attrs: nobuiltin allocsize(0)
# | declare noundef nonnull ptr @_Znwm(i64 noundef) #3
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare i64 @llvm.coro.size.i64() #2
# | 
# | ; Function Attrs: nounwind memory(argmem: readwrite)
# | declare ptr @llvm.coro.begin(token, ptr writeonly) #4
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.lifetime.start.p0(ptr captures(none)) #5
# | 
# | ; Function Attrs: mustprogress nounwind
# | define linkonce_odr void @_ZN4task12promise_type17get_return_objectEv(ptr dead_on_unwind noalias writable sret(%struct.task) align 8 %agg.result, ptr noundef nonnull align 1 dereferenceable(1) %this) #6 comdat align 2 {
# | entry:
# |   %result.ptr = alloca ptr, align 8
# |   %this.addr = alloca ptr, align 8
# |   %agg.tmp = alloca %"struct.std::coroutine_handle", align 8
# |   store ptr %agg.result, ptr %result.ptr, align 8
# |   store ptr %this, ptr %this.addr, align 8, !tbaa !7
# |   %this1 = load ptr, ptr %this.addr, align 8
# |   %call = call ptr @_ZNSt16coroutine_handleIN4task12promise_typeEE12from_promiseERS1_(ptr noundef nonnull align 1 dereferenceable(1) %this1)
# |   %coerce.dive = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %agg.tmp, i32 0, i32 0
# |   %coerce.dive2 = getelementptr inbounds nuw %"s
# | ...
# `---data was truncated (10240/31146) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt '-passes=default<O0>,default<O2>' -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=default<O0>,default<O2> -S
# |  #0 0x0000555a3c1daeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555a3c1d7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555a3c1db62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc96ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc96ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc96ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc96ab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555a3c170bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555a3c170a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555a3c1558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555a3be04e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555a3be04b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc96ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc96ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc96ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555a3be04a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c (30 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf8_u8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf4_u8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf2_u8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m1_u8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m2_u8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m4_u8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m8_u8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmaxu_vs_u16mf4_u16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmaxu_vs_u16mf2_u16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmaxu_vs_u16m1_u16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, pt
# | ...
# `---data was truncated (10240/52733) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560509b94eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560509b91e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560509b9562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f66d201bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f66d20725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f66d201ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f66d2003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560509b2abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560509b2aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560509b0f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005605097bee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005605097beb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f66d2004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f66d20050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f66d20050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005605097bea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c (31 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei16_v_i8mf8x8
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bac2475eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bac2472e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bac247662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9a88133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9a8818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9a88133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9a8811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bac240bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bac240ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bac23f08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bac209fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bac209fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9a8811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9a8811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9a8811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bac209fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c (32 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjx_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjx_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjx_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjx_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjx_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjx_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjx_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjx_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnjx_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnjx_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr 
# | ...
# `---data was truncated (10240/29202) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b03faaaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b03faa7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b03faab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7a4001bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7a400725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7a4001ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7a40003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b03fa40bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b03fa40a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b03fa258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b03f6d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b03f6d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7a40004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7a400050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7a400050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b03f6d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c (33 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560e5beafeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560e5beace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560e5beb062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3cd1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3cd1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3cd1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3cd1b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e5be45bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560e5be45a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560e5be2a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560e5bad9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560e5bad9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3cd1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3cd1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3cd1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e5bad9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c (34 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_4x8x4_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_4x8x4_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_4x8x4_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_4x8x4_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f4dd863eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f4dd860e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f4dd86462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f86d4b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f86d4b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f86d4b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f86d4aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f4dd7f9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f4dd7f9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f4dd7de8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f4dd48de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f4dd48db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f86d4aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f86d4aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f86d4aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f4dd48da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c (35 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmax_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmax_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmax_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   stor
# | ...
# `---data was truncated (10240/52599) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055883b419eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055883b416e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055883b41a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4859733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f485978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4859733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f485971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055883b3afbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055883b3afa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055883b3948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055883b043e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055883b043b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f485971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f485971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f485971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055883b043a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c (36 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vlse32_v_f32mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32.p0.i64(<vscale x 1 x float> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vlse32_v_f32m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32.p0.i64(<vscale x 2 x float> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vlse32_v_f32m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32.p0.i64(<vscale x 4 x float> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vlse32_v_f32m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32.p0.i64(<vscale x 8 x float> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vlse32_v_f32m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32.p0.i64(<vscale x 16 x float> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vlse32_v_i32mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.p0.i64(<vscale x 1 x i32> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vlse32_v_i32m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32.p0.i64(<vscale x 2 x i32> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vlse32_v_i32m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32.p0.i64(<vscale x 4 x i32> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vlse32_v_i32m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32.p0.i64(<vscale x 8 x i32> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vlse32_v_i32m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vlse.nxv16i32.p0.i64(<vscale x 16 x i32> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x i32> @llvm.riscv.vlse.nxv16i32.p0.i64(<vscale x 16 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vlse32_v_u32mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.p0.i64(<vscale x 1 x i32> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vlse32_v_u32m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, a
# | ...
# `---data was truncated (10240/29450) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055faf5cc6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055faf5cc3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055faf5cc762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f33a1a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f33a1a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f33a1a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f33a1a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055faf5c5cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055faf5c5ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055faf5c418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055faf58f0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055faf58f0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f33a1a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f33a1a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f33a1a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055faf58f0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c (37 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincp_n_s32_b8(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call i32 @llvm.aarch64.sve.sqincp.n32.nxv16i1(i32 %0, <vscale x 16 x i1> %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqincp.n32.nxv16i1(i32, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincp_n_s32_b16(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.sqincp.n32.nxv8i1(i32 %0, <vscale x 8 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqincp.n32.nxv8i1(i32, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincp_n_s32_b32(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.sqincp.n32.nxv4i1(i32 %0, <vscale x 4 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqincp.n32.nxv4i1(i32, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincp_n_s32_b64(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.sqincp.n32.nxv2i1(i32 %0, <vscale x 2 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqincp.n32.nxv2i1(i32, <vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincp_n_s64_b8(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i64 %op, ptr %op.addr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call i64 @llvm.aarch64.sve.sqincp.n64.nxv16i1(i64 %0, <vscale x 16 x i1> %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqincp.n64.nxv16i1(i64, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincp_n_s64_b16(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i64 %op, ptr %op.addr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %3 = call i64 @llvm.aarch64.sve.sqincp.n64.nxv8i1(i64 %0, <vscale x 8 x i1> %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqincp.n64.nxv8i1(i64, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincp_n_s64_b32(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i64 %op, ptr %op.addr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %3 = call i64 @llvm.aarch64.sve.sqincp.n64.nxv4i1(i64 %0, <vscale x 4 x i1> %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqincp.n64.nxv4i1(i64, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincp_n_s64_b64(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i64 %op, ptr %op.addr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %3 = call i64 @llvm.aarch64.sve.sqincp.n64.nxv2i1(i64 %0, <vscale x 2 x i1> %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqincp.n64.nxv2i1(i64, <vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincp_n_u32_b8(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call i32 @llvm.aarch64.sve.uqincp.n32.nxv16i1(i32 %0, <vscale x 16 x i1> %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqincp.n32.nxv16i1(i32, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincp_n_u32_b16(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.uqincp.n32.nxv8i1(i32 %0, <vscale x 8 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqincp.n32.nxv8i1(i32, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincp_n_u32_b32(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.uqincp.n32.nxv4i1(i32 %0, <vscale x 4 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqincp.n32.nxv4i1(i32, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincp_n_u32_b64(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.uqincp.n32.nxv2i1(i32 %0, <vscale x 2 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqincp.n32.nxv2i1(i32, <vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincp_n_u64_b8(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/19010) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055edbf105eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055edbf102e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055edbf10662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f49a9133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f49a918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f49a9133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f49a911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055edbf09bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055edbf09ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055edbf0808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055edbed2fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055edbed2fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f49a911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f49a911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f49a911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055edbed2fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c (38 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f16m1x3(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f16m2x3(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f32m1x3(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f32m2x3(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f64m1x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64
# | ...
# `---data was truncated (10240/99178) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b18356ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b183569e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b18356d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb3a1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb3a1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb3a1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb3a1b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b183502bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b183502a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b1834e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b183196e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b183196b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb3a1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb3a1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb3a1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b183196a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c (39 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfneg_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfneg_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfneg_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfneg_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfneg_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfneg_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfneg_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfneg_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfneg_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfneg_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfsgnjn.nxv8f32.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfsgnjn.nxv8f32.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfneg_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfsgnjn.nxv16f32.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfsgnjn.nxv16f32.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfneg_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, al
# | ...
# `---data was truncated (10240/30861) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561e11af3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561e11af0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561e11af462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f10c4d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f10c4d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f10c4d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f10c4d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561e11a89bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561e11a89a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561e11a6e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561e1171de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561e1171db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f10c4d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f10c4d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f10c4d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561e1171da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c (40 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfeq
# | ...
# `---data was truncated (10240/18668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056431e102eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056431e0ffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056431e10362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1b31d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1b31d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1b31d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1b31d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056431e098bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056431e098a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056431e07d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056431dd2ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056431dd2cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1b31d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1b31d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1b31d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056431dd2ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c (41 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_f16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_f16mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_f16m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_f16m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_i16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_i16mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_i16m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_i16m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_u16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store tar
# | ...
# `---data was truncated (10240/30818) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565247870eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056524786de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056524787162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbc0c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbc0c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbc0c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbc0c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565247806bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565247806a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005652477eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056524749ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056524749ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbc0c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbc0c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbc0c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056524749aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c (42 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x flo
# | ...
# `---data was truncated (10240/101584) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b9c0496eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b9c0493e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b9c049762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f64533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f6458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f64533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f6451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b9c042cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b9c042ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b9c04118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b9c00c0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b9c00c0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2f6451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f6451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f6451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b9c00c0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c (43 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -O0    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=O0
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -O0 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c -o -
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=O0
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=AFTER_MEM2REG
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @foo() #0 {
# | entry:
# |   %v_tuple = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @bar() #0 {
# | entry:
# |   %v_tuple = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple, align 4
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @baz(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple) #0 {
# | entry:
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @qux(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple) #0 {
# | entry:
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @quux(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple) #0 {
# | entry:
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %call = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @qux(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %call
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zicsr,+zve32x,+zvl32b" }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd5ddeaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fd5dde7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fd5ddeb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9f02849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9f028a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9f02849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9f02831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd5dd80bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fd5dd80a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fd5dd658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fd5da14e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fd5da14b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9f02832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9f028330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9f028330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd5da14a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=AFTER_MEM2REG
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=AFTER_MEM2REG
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c (44 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556911cf1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556911ceee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556911cf262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e1e305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e1e35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e1e305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e1e2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556911c87bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556911c87a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556911c6c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055691191be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055691191bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8e1e2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e1e2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e1e2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055691191ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c (45 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_e5m2_e5m2_w4_f8e5m2m8_f8e5m2m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055851e242eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055851e23fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055851e24362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbdd2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbdd2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbdd2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbdd2f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055851e1d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055851e1d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055851e1bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055851de6ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055851de6cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbdd2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbdd2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbdd2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055851de6ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c (46 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_f16mf4x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_f16mf2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_f16m1x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_f16m2x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_i16mf4x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_i16mf2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_i16m1x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_i16m2x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8
# | ...
# `---data was truncated (10240/15457) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cc2acc5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cc2acc2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cc2acc662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff55af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff55af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff55af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff55af1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc2ac5bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cc2ac5ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cc2ac408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cc2a8efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cc2a8efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff55af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff55af1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff55af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc2a8efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c (47 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f16m1x5(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f32m1x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f64m1x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558674b22eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558674b1fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558674b2362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6286933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f628698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6286933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f628691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558674ab8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558674ab8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558674a9d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055867474ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055867474cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f628691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f628691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f628691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055867474ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c (48 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte64_f64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vlte64.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte64_i64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte64_u64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e634ea4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e634ea1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e634ea562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f47133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f4718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f47133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f4711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e634e3abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e634e3aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e634e1f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e634acee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e634aceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2f4711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f4711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f4711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e634acea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c (49 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d     -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vpaire_vv_f16mf4(<vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vpaire.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vpaire.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vpaire_vv_f16mf2(<vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vpaire.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vpaire.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vpaire_vv_f16m1(<vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vpaire.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vpaire.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vpaire_vv_f16m2(<vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vpaire.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vpaire.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vpaire_vv_f16m4(<vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vpaire.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vpaire.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vpaire_vv_f16m8(<vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vpaire.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vpaire.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vpaire_vv_f32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vpaire.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vpaire.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vpaire_vv_f32m1(<vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vpaire.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vpaire.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vpaire_vv_f32m2(<vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vpaire.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vpaire.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vpaire_vv_f32m4(<vscale x 8 x float> %vs2, <vscale x 8 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 =
# | ...
# `---data was truncated (10240/125488) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558c1a10feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558c1a10ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558c1a11062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f514a505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f514a55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f514a505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f514a4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c1a0a5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558c1a0a5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558c1a08a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558c19d39e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558c19d39b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f514a4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f514a4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f514a4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c19d39a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c (50 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056377011eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056377011be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056377011f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdbf8249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdbf82a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdbf8249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdbf8231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005637700b4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005637700b4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005637700998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056376fd48e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056376fd48b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdbf8232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdbf82330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdbf82330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056376fd48a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c (51 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1(<vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x double> @test_sf_vfexpa_v_f64m2(<vscale x 2 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64.i64(<vscale x 2 x double> poison, <vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64.i64(<vscale x 2 x double>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x double> @test_sf_vfexpa_v_f64m4(<vscale x 4 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64.i64(<vscale x 4 x double> poison, <vscale x 4 x double> %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64.i64(<vscale x 4 x double>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vfexpa_v_f64m8(<vscale x 8 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64.i64(<vscale x 8 x double> poison, <vscale x 8 x double> %0, i64 %1)
# |   ret <vscale x 8 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64.i64(<vscale x 8 x double>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1_m(<vscale x 1 x i1> %vm, <vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x double> @test_sf_vfexpa_v_f64m2_m(<vscale x 2 x i1> %vm, <vscale x 2 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(<vscale x 2 x double> poison, <vscale x 2 x double> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x double> @test_sf_vfexpa_v_f64m4_m(<vscale x 4 x i1> %vm, <vscale x 4 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(<vscale x 4 x double> poison, <vscale x 4 x double> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(<vscale x 4 x double>, <vscale x 4 x double>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vfexpa_v_f64m8_m(<vscale x 8 x i1> %vm, <vscale x 8 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(<vscale x 8 x double> poison, <vscale x 8 x double> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(<vscale x 8 x double>, <vscale x 8 x double>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+xsfvfexpa,+xsfvfexpa64e,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfvfexpa0p2_xsfvfexpa64e0p2"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed68a46eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ed68a43e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ed68a4762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc90d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc90d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc90d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc90d31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed689dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ed689dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ed689c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ed68670e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ed68670b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc90d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc90d31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc90d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed68670a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c (52 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsac_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsac_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsac_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsac_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsac_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsac_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsac_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsac_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3
# | ...
# `---data was truncated (10240/64366) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e7ee5d2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e7ee5cfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e7ee5d362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f642f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f642f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f642f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f642f51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e7ee568bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e7ee568a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e7ee54d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e7ee1fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e7ee1fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f642f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f642f51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f642f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e7ee1fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c (53 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556e963e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556e963e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556e963e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3f6ef05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3f6ef5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3f6ef05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3f6eeed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e96379bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556e96379a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556e9635e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556e9600de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556e9600db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3f6eeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3f6eeef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3f6eeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e9600da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c (54 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f16m1x4(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f16m2x4(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f32m1x4(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f32m2x4(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f64m1x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tu
# | ...
# `---data was truncated (10240/99186) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558ffe75feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558ffe75ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558ffe76062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9afc049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9afc0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9afc049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9afc031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558ffe6f5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558ffe6f5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558ffe6da8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558ffe389e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558ffe389b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9afc032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9afc0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9afc0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558ffe389a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/absneg.c (55 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/absneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vabsq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %0)
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.fabs.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vabsq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %0)
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.fabs.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vabsq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = icmp slt <16 x i8> %0, zeroinitializer
# |   %2 = sub <16 x i8> zeroinitializer, %0
# |   %3 = select <16 x i1> %1, <16 x i8> %2, <16 x i8> %0
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vabsq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = icmp slt <8 x i16> %0, zeroinitializer
# |   %2 = sub <8 x i16> zeroinitializer, %0
# |   %3 = select <8 x i1> %1, <8 x i16> %2, <8 x i16> %0
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vabsq_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = icmp slt <4 x i32> %0, zeroinitializer
# |   %2 = sub <4 x i32> zeroinitializer, %0
# |   %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %0
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = xor <16 x i8> %0, splat (i8 -1)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = xor <8 x i16> %0, splat (i16 -1)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = xor <4 x i32> %0, splat (i32 -1)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = xor <16 x i8> %0, splat (i8 -1)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = xor <8 x i16> %0, splat (i16 -1)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = xor <4 x i32> %0, splat (i32 -1)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = call <16 x i8> @llvm.arm.mve.mvn.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i1> %3, <16 x i8> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.mvn.predicated.v16i8.v16i1(<16 x i8>, <16 x i1>, <16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.mvn.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.mvn.predicated.v8i16.v8i1(<8 x i16>, <8 x i1>, <8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = call <4 x i32> @llvm.arm.mve.mvn.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i1> %3, <4 x i32> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.mvn.predicated.v4i32.v4i1(<4 x i32>, <4 x i1>, <4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_m_u8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = call <16 x i8> @llvm.arm.mve.mvn.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i1> %3, <16 x i8> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.mvn.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_m_u32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = call <4 x i32> @llvm.arm.mve.mvn.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i1> %3, <4 x i32> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_x_s8(<16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = al
# | ...
# `---data was truncated (10240/40137) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f6a8bd3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f6a8bd0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f6a8bd462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b0d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b0d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b0d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b0d431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f6a8b69bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f6a8b69a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f6a8b4e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f6a87fde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f6a87fdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5b0d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b0d4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b0d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f6a87fda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c (56 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vctz_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vctz_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vctz.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vctz.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vctz_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vctz.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vctz.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vctz_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vctz.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vctz.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vctz_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vctz.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vctz.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vctz_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vctz.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vctz.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vctz_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vctz.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vctz.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vctz_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vctz.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vctz.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vctz_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vctz.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vctz.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vctz_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vctz.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vctz.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i1
# | ...
# `---data was truncated (10240/95001) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa92e11eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fa92e0ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fa92e1262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc3ac333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc3ac38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc3ac333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc3ac31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa92da7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fa92da7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fa92d8c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fa92a3be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fa92a3bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc3ac31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc3ac31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc3ac31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa92a3ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c (57 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564875bc7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564875bc4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564875bc862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8bd5649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8bd56a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8bd5649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8bd5631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564875b5dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564875b5da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564875b428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005648757f1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005648757f1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8bd5632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8bd56330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8bd56330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005648757f1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c (58 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16mf4x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16mf2x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16m1x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b751838eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b751835e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b75183962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f076e21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f076e2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f076e21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f076e203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b7517cebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b7517cea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b7517b38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b751462e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b751462b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f076e204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f076e2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f076e2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b751462a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c (59 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f266ca2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f266c9fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f266ca362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2d82733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2d8278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2d82733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2d8271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f266c38bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f266c38a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f266c1d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f2668cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f2668ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2d8271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2d8271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2d8271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f2668cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGenCXX/thinlto_public_type_test_distributed.ll (60 of 27911)
******************** TEST 'Clang :: CodeGenCXX/thinlto_public_type_test_distributed.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenCXX/Output/thinlto_public_type_test_distributed.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/thinlto_public_type_test_distributed.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenCXX/Output/thinlto_public_type_test_distributed.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/thinlto_public_type_test_distributed.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenCXX/Output/thinlto_public_type_test_distributed.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/thinlto_public_type_test_distributed.ll
# |  #0 0x000055a17a261eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a17a25ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a17a26262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f25b0333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f25b038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f25b0333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f25b031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a17a1f7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a17a1f7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a17a1dc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a179e8be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a179e8bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f25b031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f25b031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f25b031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a179e8ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c (61 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4r_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4r.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4r.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4r_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4r_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4r_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm4r_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4r_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4r_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale 
# | ...
# `---data was truncated (10240/20131) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005624c56eceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005624c56e9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005624c56ed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f53f5333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f53f538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f53f5333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f53f531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005624c5682bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005624c5682a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005624c56678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005624c5316e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005624c5316b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f53f531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f53f531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f53f531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005624c5316a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c (62 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), pt
# | ...
# `---data was truncated (10240/19484) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560285a34eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560285a31e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560285a3562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f839ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f839ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f839ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f839ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005602859cabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005602859caa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005602859af8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056028565ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056028565eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f839ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f839ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f839ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056028565ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c (63 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_f16mf4x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_f16mf2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_f16m1x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_f16m2x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_f16m4x2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_i16mf4x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_i16mf2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_i16m1x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_i16m2x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.
# | ...
# `---data was truncated (10240/16654) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005628ad3f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005628ad3f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005628ad3f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd858533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd85858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd858533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd85851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005628ad389bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005628ad389a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005628ad36e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005628ad01de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005628ad01db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd85851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd85851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd85851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005628ad01da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c (64 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjn_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjn_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjn_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjn_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjn_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjn_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjn_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjn_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjn_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <v
# | ...
# `---data was truncated (10240/157769) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bb43048eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bb43045e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bb4304962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4171733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f417178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4171733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f417171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bb42fdebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bb42fdea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bb42fc38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bb42c72e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bb42c72b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f417171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f417171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f417171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bb42c72a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c (65 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_i32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_i32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_u32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_u32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055abcf674eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055abcf671e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055abcf67562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd2e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd2e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd2e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd2e031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055abcf60abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055abcf60aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055abcf5ef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055abcf29ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055abcf29eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbd2e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd2e0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd2e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055abcf29ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c (66 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsof_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsof_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsof_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsof_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsof_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsof_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsof_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsof_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1> poison, <vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsof_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1> poison, <vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsof_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1> poison, <vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsof_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1> poison, <vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsof_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1.i64(<vscale x 4 x i1> poison, <vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree no
# | ...
# `---data was truncated (10240/13023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559a83f8feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559a83f8ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559a83f9062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f009681bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f00968725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f009681ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0096803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a83f25bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559a83f25a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559a83f0a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559a83bb9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559a83bb9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0096804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f00968050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f00968050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a83bb9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c (67 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_vv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_vx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_wv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_wx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_vv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_vx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_wv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_wx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsubu_vv_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |  
# | ...
# `---data was truncated (10240/306627) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bbfacd8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bbfacd5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bbfacd962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fed1a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fed1a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fed1a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fed1a631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bbfac6ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bbfac6ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bbfac538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bbfa902e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bbfa902b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fed1a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fed1a6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fed1a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bbfa902a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c (68 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsif_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsif_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsif_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsif_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsif_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsif_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsif_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsif_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1> poison, <vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsif_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1> poison, <vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsif_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1> poison, <vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsif_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1> poison, <vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsif_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1.i64(<vscale x 4 x i1> poison, <vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree no
# | ...
# `---data was truncated (10240/13023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056136b3adeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056136b3aae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056136b3ae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0af7c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0af7ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0af7c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0af7c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056136b343bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056136b343a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056136b3288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056136afd7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056136afd7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0af7c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0af7c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0af7c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056136afd7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c (69 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmsb_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %4 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.msb.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %4, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.msb.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmsb_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %6 = call <vscale x 8 x i16> @llvm.aarch64.sve.msb.nxv8i16(<vscale x 8 x i1> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.msb.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmsb_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %6 = call <vscale x 4 x i32> @llvm.aarch64.sve.msb.nxv4i32(<vscale x 4 x i1> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3)
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.msb.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmsb_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   %op3.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x i64> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %6 = call <vscale x 2 x i64> @llvm.aarch64.sve.msb.nxv2i64(<vscale x 2 x i1> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3)
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.msb.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmsb_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %4 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.msb.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %4, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmsb_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %6 = call <vscale x 8 x i16> @llvm.aarch64.sve.msb.nxv8i16(<vscale x 8 x i1> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmsb_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %6 = call <vscale x 4 x i32> @llvm.aarch64.sve.msb.nxv4i32(<vscale x 4 x i1> %4, <vs
# | ...
# `---data was truncated (10240/86847) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e238cc5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e238cc2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e238cc662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c11533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c1158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c11533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c1151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e238c5bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e238c5ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e238c408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e2388efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e2388efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7c1151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c1151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c1151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2388efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c (70 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulh_vv_i64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulh_vx_i64m1(<vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulh_vv_i64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulh_vx_i64m2(<vscale x 2 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulh_vv_i64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 4 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulh_vx_i64m4(<vscale x 4 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulh_vv_i64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 8 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulh_vx_i64m8(<vscale x 8 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulh_vv_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulh_vx_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load i64, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulh.mask.nxv1i64.i64.i64(<vs
# | ...
# `---data was truncated (10240/18591) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560dc1456eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560dc1453e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560dc145762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f792bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f792bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f792bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f792bf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560dc13ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560dc13eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560dc13d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560dc1080e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560dc1080b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f792bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f792bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f792bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560dc1080a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c (71 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_v
# | ...
# `---data was truncated (10240/253156) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b3061e8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b3061e5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b3061e962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f262bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f262bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f262bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f262bb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b30617ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b30617ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b3061638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b305e12e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b305e12b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f262bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f262bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f262bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b305e12a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c (72 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmflt
# | ...
# `---data was truncated (10240/18668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563d8192aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563d81927e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563d8192b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f806db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f806db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f806db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f806db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d818c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563d818c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563d818a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563d81554e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563d81554b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f806db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f806db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f806db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d81554a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c (73 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_u64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_u64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tu
# | ...
# `---data was truncated (10240/16560) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005638bec5beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005638bec58e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005638bec5c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f25d0733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f25d078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f25d0733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f25d071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005638bebf1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005638bebf1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005638bebd68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005638be885e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005638be885b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f25d071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f25d071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f25d071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005638be885a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/arm_acle_swp.c (74 of 27911)
******************** TEST 'Clang :: CodeGen/arm_acle_swp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple thumbv7m-none-eabi -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c -check-prefix=ATOMIC
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple thumbv7m-none-eabi -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv7m-unknown-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_swp(i32 noundef %x, ptr noundef %p) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__p.addr.i = alloca ptr, align 4
# |   %__v.i = alloca i32, align 4
# |   %.atomictmp.i = alloca i32, align 4
# |   %atomic-temp.i = alloca i32, align 4
# |   %x.addr = alloca i32, align 4
# |   %p.addr = alloca ptr, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   store ptr %p, ptr %p.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %1 = load ptr, ptr %p.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store ptr %1, ptr %__p.addr.i, align 4
# |   %2 = load ptr, ptr %__p.addr.i, align 4
# |   %3 = load i32, ptr %__x.addr.i, align 4
# |   store i32 %3, ptr %.atomictmp.i, align 4
# |   %4 = load i32, ptr %.atomictmp.i, align 4
# |   %5 = atomicrmw volatile xchg ptr %2, i32 %4 monotonic, align 4
# |   store i32 %5, ptr %atomic-temp.i, align 4
# |   %6 = load i32, ptr %atomic-temp.i, align 4
# |   store i32 %6, ptr %__v.i, align 4
# |   %7 = load i32, ptr %__v.i, align 4
# |   ret i32 %7
# | }
# | 
# | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv7-m,+thumb-mode" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"aapcs"}
# | !1 = !{i32 1, !"min_enum_size", i32 4}
# | !2 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !3 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dbc7b3ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dbc7b39e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dbc7b3d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f62b0133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f62b018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f62b0133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f62b011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dbc7ad2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dbc7ad2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dbc7ab78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dbc7766e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dbc7766b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f62b011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f62b011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f62b011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dbc7766a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c -check-prefix=ATOMIC
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c -check-prefix=ATOMIC
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vshlc.c (75 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vshlc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlcq_s8(<16 x i8> noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca ptr, align 4
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <16 x i8>, ptr %a.addr, align 8
# |   %3 = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.v16i8(<16 x i8> %2, i32 %1, i32 18)
# |   %4 = extractvalue { i32, <16 x i8> } %3, 0
# |   store i32 %4, ptr %0, align 4
# |   %5 = extractvalue { i32, <16 x i8> } %3, 1
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, <16 x i8> } @llvm.arm.mve.vshlc.v16i8(<16 x i8>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlcq_s16(<8 x i16> noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca ptr, align 4
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <8 x i16>, ptr %a.addr, align 8
# |   %3 = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.v8i16(<8 x i16> %2, i32 %1, i32 16)
# |   %4 = extractvalue { i32, <8 x i16> } %3, 0
# |   store i32 %4, ptr %0, align 4
# |   %5 = extractvalue { i32, <8 x i16> } %3, 1
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, <8 x i16> } @llvm.arm.mve.vshlc.v8i16(<8 x i16>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlcq_s32(<4 x i32> noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca ptr, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <4 x i32>, ptr %a.addr, align 8
# |   %3 = call { i32, <4 x i32> } @llvm.arm.mve.vshlc.v4i32(<4 x i32> %2, i32 %1, i32 4)
# |   %4 = extractvalue { i32, <4 x i32> } %3, 0
# |   store i32 %4, ptr %0, align 4
# |   %5 = extractvalue { i32, <4 x i32> } %3, 1
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, <4 x i32> } @llvm.arm.mve.vshlc.v4i32(<4 x i32>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlcq_u8(<16 x i8> noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca ptr, align 4
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <16 x i8>, ptr %a.addr, align 8
# |   %3 = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.v16i8(<16 x i8> %2, i32 %1, i32 17)
# |   %4 = extractvalue { i32, <16 x i8> } %3, 0
# |   store i32 %4, ptr %0, align 4
# |   %5 = extractvalue { i32, <16 x i8> } %3, 1
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlcq_u16(<8 x i16> noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca ptr, align 4
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <8 x i16>, ptr %a.addr, align 8
# |   %3 = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.v8i16(<8 x i16> %2, i32 %1, i32 17)
# |   %4 = extractvalue { i32, <8 x i16> } %3, 0
# |   store i32 %4, ptr %0, align 4
# |   %5 = extractvalue { i32, <8 x i16> } %3, 1
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlcq_u32(<4 x i32> noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca ptr, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <4 x i32>, ptr %a.addr, align 8
# |   %3 = call { i32, <4 x i32> } @llvm.arm.mve.vshlc.v4i32(<4 x i32> %2, i32 %1, i32 20)
# |   %4 = extractvalue { i32, <4 x i32> } %3, 0
# |   store i32 %4, ptr %0, align 4
# |   %5 = extractvalue { i32, <4 x i32> } %3, 1
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlcq_m_s8(<16 x i8> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <16 x i8>, ptr %a.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4)
# |   %6 = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.predicated.v16i8.v16i1(<16 x i8> %2, i32 %1, i32 29, <16 x i1> %5)
# |   %7 = extractvalue { i32, <16 x i8> } %6, 0
# |   store i32 %7, ptr %0, align 4
# |   %8 = extractvalue { i32, <16 x i8> } %6, 1
# |   ret <16 x i8> %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, <16 x i8> } @llvm.arm.mve.vshlc.predicated.v16i8.v16i1(<16 x i8>, i32, i32, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlcq_m_s16(<8 x i16> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <8 x i16>, ptr %a.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
# |   %6 = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.predicated.v8i16.v8i1(<8 x i16> %2, i32 %1, i32 17, <8 x i1> %5)
# |   %7 = extractvalue { i32, <8 x i16> } %6, 0
# |   store i32 %7, ptr %0, align 4
# |   %8 = extractvalue { i32, <8 x i16> } %6, 1
# |   ret <8 x i16> %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, <8 x i16> } @llvm.arm.mve.vshlc.predicated.v8i16.v8i1(<8 x i16>, i32, i32, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlcq_m_s32(<4 x i32> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <4 x i32>, ptr %a.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call { i32, <4 x i32> } @llvm.arm.mve.vshlc.predicated.v4i32.v4i1(<4 x i32> %2, i32 %1, i32 9, <4 x i1> %5)
# |   %7 = extractvalue { i32, <4 x i32> } %6, 0
# |   store i32 %7, ptr %0, align 4
# |   %8 = extractvalue { i32, <4 x i32> } %6, 1
# |   ret <4 x i32> %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, <4 x i32> } @llvm.arm.mve.vshlc.predicated.v4i32.v4i1(<4 x i32>, i32, i32, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlcq_m_u8(<16 x i8> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <16 x i8>, ptr %a.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4)
# |   %6 = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.predicated.v16i8.v16i1(<16 x i8> %2, i32 %1, i32 21, <16 x i1> %5)
# |   %7 = extractvalue { i32, <16 x i8> } %6, 0
# |   store i32 %7, ptr %0, align 4
# |   %8 = extractvalue { i32, <16 x i8> } %6, 1
# |   ret <16 x i8> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlcq_m_u16(<8 x i16> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <8 x i16>, ptr %a.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
# |   %6 = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.predicated.v8i16.v8i1(<8 x i16> %2, i32 %1, i32 24, <8 x i1> %5)
# |   %7 = extractvalue { i32, <8 x i16> } %6, 0
# |   store i32 %7, ptr %0, align 4
# |   %8 = extractvalue { i32, <8 x i16> } %6, 1
# |   ret <8 x i16> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlcq_m_u32(<4 x i32> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# | 
# | ...
# `---data was truncated (10240/11454) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e683d0feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e683d0ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e683d1062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1226333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f122638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1226333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f122631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e683ca5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e683ca5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e683c8a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e683939e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e683939b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f122631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f122631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f122631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e683939a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c (76 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc  -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +lut -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +lut -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | %struct.mfloat8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.mfloat8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.mfloat8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.mfloat8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.mfloat8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.mfloat8x16x4_t = type { [4 x <16 x i8>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vcreate_mf8(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__promote = alloca i64, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   store i64 %0, ptr %__promote, align 8
# |   %1 = load <8 x i8>, ptr %__promote, align 8
# |   store <8 x i8> %1, ptr %__ret, align 8
# |   %2 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %2, ptr %tmp, align 8
# |   %3 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vdup_n_mf8(<1 x i8> %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i8>, align 1
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %.compoundliteral.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x i8>, align 1
# |   store <1 x i8> %a, ptr %a.addr, align 1
# |   %0 = load <1 x i8>, ptr %a.addr, align 1
# |   store <1 x i8> %0, ptr %__p0.addr.i, align 1
# |   %1 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext.i = shufflevector <1 x i8> %1, <1 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit.i = shufflevector <8 x i8> %vext.i, <8 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %2 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext1.i = shufflevector <1 x i8> %2, <1 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit2.i = shufflevector <8 x i8> %vecinit.i, <8 x i8> %vext1.i, <8 x i32> <i32 0, i32 8, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %3 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext3.i = shufflevector <1 x i8> %3, <1 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit4.i = shufflevector <8 x i8> %vecinit2.i, <8 x i8> %vext3.i, <8 x i32> <i32 0, i32 1, i32 8, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %4 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext5.i = shufflevector <1 x i8> %4, <1 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit6.i = shufflevector <8 x i8> %vecinit4.i, <8 x i8> %vext5.i, <8 x i32> <i32 0, i32 1, i32 2, i32 8, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %5 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext7.i = shufflevector <1 x i8> %5, <1 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit8.i = shufflevector <8 x i8> %vecinit6.i, <8 x i8> %vext7.i, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 poison, i32 poison, i32 poison>
# |   %6 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext9.i = shufflevector <1 x i8> %6, <1 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit10.i = shufflevector <8 x i8> %vecinit8.i, <8 x i8> %vext9.i, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 8, i32 poison, i32 poison>
# |   %7 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext11.i = shufflevector <1 x i8> %7, <1 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit12.i = shufflevector <8 x i8> %vecinit10.i, <8 x i8> %vext11.i, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 poison>
# |   %8 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext13.i = shufflevector <1 x i8> %8, <1 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit14.i = shufflevector <8 x i8> %vecinit12.i, <8 x i8> %vext13.i, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 8>
# |   store <8 x i8> %vecinit14.i, ptr %.compoundliteral.i, align 8
# |   %9 = load <8 x i8>, ptr %.compoundliteral.i, align 8
# |   store <8 x i8> %9, ptr %__ret.i, align 8
# |   %10 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vdupq_n_mf8(<1 x i8> %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i8>, align 1
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %.compoundliteral.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <1 x i8>, align 1
# |   store <1 x i8> %a, ptr %a.addr, align 1
# |   %0 = load <1 x i8>, ptr %a.addr, align 1
# |   store <1 x i8> %0, ptr %__p0.addr.i, align 1
# |   %1 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext.i = shufflevector <1 x i8> %1, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit.i = shufflevector <16 x i8> %vext.i, <16 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %2 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext1.i = shufflevector <1 x i8> %2, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit2.i = shufflevector <16 x i8> %vecinit.i, <16 x i8> %vext1.i, <16 x i32> <i32 0, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %3 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext3.i = shufflevector <1 x i8> %3, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit4.i = shufflevector <16 x i8> %vecinit2.i, <16 x i8> %vext3.i, <16 x i32> <i32 0, i32 1, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %4 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext5.i = shufflevector <1 x i8> %4, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit6.i = shufflevector <16 x i8> %vecinit4.i, <16 x i8> %vext5.i, <16 x i32> <i32 0, i32 1, i32 2, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %5 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext7.i = shufflevector <1 x i8> %5, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit8.i = shufflevector <16 x i8> %vecinit6.i, <16 x i8> %vext7.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %6 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext9.i = shufflevector <1 x i8> %6, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit10.i = shufflevector <16 x i8> %vecinit8.i, <16 x i8> %vext9.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %7 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext11.i = shufflevector <1 x i8> %7, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit12.i = shufflevector <16 x i8> %vecinit10.i, <16 x i8> %vext11.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %8 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext13.i = shufflevector <1 x i8> %8, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit14.i = shufflevector <16 x i8> %vecinit12.i, <16 x i8> %vext13.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %9 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext15.i = shufflevector <1 x i8> %9, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit16.i = shufflevector <16 x i8> %vecinit14.i, <16 x i8> %vext15.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison
# | ...
# `---data was truncated (10240/101594) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# |  #0 0x0000557784cbaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557784cb7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557784cbb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc5ae133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5ae18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc5ae133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc5ae11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557784c50bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557784c50a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557784c358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005577848e4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005577848e4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc5ae11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5ae11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5ae11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005577848e4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c (77 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f16m1x3(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_f16m2x3(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f32m1x3(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_f32m2x3(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f64m1x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.
# | ...
# `---data was truncated (10240/87884) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555da034deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555da034ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555da034e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f248a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f248a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f248a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f248a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555da02e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555da02e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555da02c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555d9ff77e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555d9ff77b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f248a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f248a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f248a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555d9ff77a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c (78 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmseq_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmseq_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmseq_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmseq_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmseq_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmseq_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmseq_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i
# | ...
# `---data was truncated (10240/116267) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055634fd18eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055634fd15e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055634fd1962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f50e2849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f50e28a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f50e2849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f50e2831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055634fcaebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055634fcaea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055634fc938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055634f942e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055634f942b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f50e2832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f50e28330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f50e28330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055634f942a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c (79 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintp_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintp.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frintp.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintp_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintp.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frintp.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintp_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintp.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frintp.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintp_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.frintp.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintp_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frintp.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintp_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frintp.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintp_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintp.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintp_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintp.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintp_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintp.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000558b8322aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558b83227e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558b8322b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7061b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7061b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7061b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7061b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558b831c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558b831c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558b831a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558b82e54e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558b82e54b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7061b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7061b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7061b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558b82e54a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c (80 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_f16m1x2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_f16m2x2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_f32m1x2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_f32m2x2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei64_v_f32m4x2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple
# | ...
# `---data was truncated (10240/96919) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056080e7f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056080e7f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056080e7f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c9f41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c9f4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c9f41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c9f403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056080e789bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056080e789a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056080e76e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056080e41de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056080e41db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1c9f404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c9f4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c9f4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056080e41da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c (81 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_i8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_i8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8_v_i8m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_u8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_u8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_u8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8_v_u8m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_i8mf8x7_tum(<vscale x 1 x i1> %mas
# | ...
# `---data was truncated (10240/43111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055560a154eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055560a151e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055560a15562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b32e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b32ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b32e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b32e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055560a0eabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055560a0eaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055560a0cf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555609d7ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555609d7eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4b32e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b32e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b32e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555609d7ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c (82 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562fa8c16eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562fa8c13e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562fa8c1762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff826905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff82695c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff826905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff8268ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562fa8bacbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562fa8baca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562fa8b918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562fa8840e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562fa8840b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff8268eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff8268ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff8268ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562fa8840a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/arm-neon-shifts.c (83 of 27911)
******************** TEST 'Clang :: CodeGen/arm-neon-shifts.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-apple-darwin    -disable-O0-optnone    -target-cpu cortex-a8    -ffreestanding    -emit-llvm -w -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-apple-darwin -disable-O0-optnone -target-cpu cortex-a8 -ffreestanding -emit-llvm -w -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c"
# | target datalayout = "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
# | target triple = "thumbv7-apple-darwin"
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @test_shift_vshr(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vshr_n = lshr <8 x i8> %1, splat (i8 5)
# |   store <8 x i8> %vshr_n, ptr %ref.tmp, align 8
# |   %2 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %2, ptr %__ret, align 8
# |   %3 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %3, ptr %tmp, align 8
# |   %4 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @test_shift_vshr_smax(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vshr_n = ashr <8 x i8> %1, splat (i8 7)
# |   store <8 x i8> %vshr_n, ptr %ref.tmp, align 8
# |   %2 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %2, ptr %__ret, align 8
# |   %3 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %3, ptr %tmp, align 8
# |   %4 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @test_shift_vshr_umax(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   store <8 x i8> zeroinitializer, ptr %ref.tmp, align 8
# |   %2 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %2, ptr %__ret, align 8
# |   %3 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %3, ptr %tmp, align 8
# |   %4 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @test_shift_vsra(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %vsra_n = lshr <8 x i8> %3, splat (i8 5)
# |   %4 = add <8 x i8> %2, %vsra_n
# |   store <8 x i8> %4, ptr %ref.tmp, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %5, ptr %__ret, align 8
# |   %6 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %6, ptr %tmp, align 8
# |   %7 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @test_shift_vsra_smax(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %vsra_n = ashr <8 x i8> %3, splat (i8 7)
# |   %4 = add <8 x i8> %2, %vsra_n
# |   store <8 x i8> %4, ptr %ref.tmp, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %5, ptr %__ret, align 8
# |   %6 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %6, ptr %tmp, align 8
# |   %7 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @test_shift_vsra_umax(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %4 = add <8 x i8> %2, zeroinitializer
# |   store <8 x i8> %4, ptr %ref.tmp, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %5, ptr %__ret, align 8
# |   %6 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %6, ptr %tmp, align 8
# |   %7 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %7
# | }
# | 
# | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a8" "target-features"="+armv7-a,+d32,+dsp,+fp64,+neon,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp" }
# | 
# | !llvm.module.flags = !{!0, !1}
# | !llvm.ident = !{!2}
# | 
# | !0 = !{i32 1, !"target-abi", !"apcs-gnu"}
# | !1 = !{i32 1, !"min_enum_size", i32 4}
# | !2 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559cb7705eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559cb7702e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559cb770662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4702b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4702b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4702b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4702b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559cb769bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559cb769ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559cb76808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559cb732fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559cb732fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4702b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4702b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4702b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559cb732fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c (84 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i8> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i8> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i8> %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> %2, ptr %0, <vscale x 32 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 4 x bfloat> %vs3,
# | ...
# `---data was truncated (10240/15512) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559c5311aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559c53117e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559c5311b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3fde049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3fde0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3fde049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3fde031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c530b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559c530b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559c530958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559c52d44e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559c52d44b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3fde032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3fde0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3fde0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c52d44a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c (85 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_tu(<vscale x 1
# | ...
# `---data was truncated (10240/295853) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ef31914eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ef31911e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ef3191562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0c23733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0c2378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0c23733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0c2371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ef318aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ef318aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ef3188f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ef3153ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ef3153eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0c2371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0c2371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0c2371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ef3153ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c (86 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16mf4(ptr noundef %rs1, i64 noundef %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16mf2(ptr noundef %rs1, i64 noundef %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m1(ptr noundef %rs1, i64 noundef %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m2(ptr noundef %rs1, i64 noundef %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m4(ptr noundef %rs1, i64 noundef %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv16bf16.p0.i64(<vscale x 16 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m8(ptr noundef %rs1, i64 noundef %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv32bf16.p0.i64(<vscale x 32 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, <vscale x 8 x bfloat> %vs3
# | ...
# `---data was truncated (10240/14330) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561004707eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561004704e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056100470862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb278933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb27898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb278933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb27891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056100469dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056100469da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005610046828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561004331e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561004331b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb27891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb27891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb27891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561004331a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c (87 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wf_bf16_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wf_bf16_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 
# | ...
# `---data was truncated (10240/199596) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564d6ef12eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564d6ef0fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564d6ef1362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8959533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f895958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8959533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f895951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d6eea8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564d6eea8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564d6ee8d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564d6eb3ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564d6eb3cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f895951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f895951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f895951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d6eb3ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c (88 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f16m1x6(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f32m1x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f64m1x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561c52704eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561c52701e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561c5270562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9f6e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9f6e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9f6e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9f6e91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561c5269abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561c5269aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561c5267f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561c5232ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561c5232eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9f6e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9f6e91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9f6e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561c5232ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c (89 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrec7_v_bf16mf4(<vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrec7_v_bf16mf2(<vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrec7_v_bf16m1(<vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrec7_v_bf16m2(<vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrec7_v_bf16m4(<vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrec7_v_bf16m8(<vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrec7_v_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrec7_v_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrec7_v_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrec7.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrec7.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrec7_v_bf16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrec7.mask.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrec7.mask.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrec7_v_bf16m4_m(<vscale x 16 x i1> %mask, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   s
# | ...
# `---data was truncated (10240/12680) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555db61f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555db61efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555db61f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2735f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2735f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2735f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2735eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555db6188bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555db6188a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555db616d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555db5e1ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555db5e1cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2735eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2735eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2735eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555db5e1ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGenCoroutines/pr65054.cpp (90 of 27911)
******************** TEST 'Clang :: CodeGenCoroutines/pr65054.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20       -O0 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp -o - -disable-O0-optnone       | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes='sroa,mem2reg,simplifycfg' -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp --check-prefix=CHECK-O0
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 -O0 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | %struct.MyTask = type { %"struct.std::coroutine_handle" }
# | %"struct.std::coroutine_handle" = type { ptr }
# | %"struct.std::suspend_always" = type { i8 }
# | %struct.Awaiter = type { ptr }
# | %"struct.std::coroutine_handle.0" = type { %"struct.std::coroutine_handle" }
# | 
# | $_ZN6MyTask12promise_type17get_return_objectEv = comdat any
# | 
# | $_ZN6MyTask12promise_type15initial_suspendEv = comdat any
# | 
# | $_ZNSt14suspend_always11await_readyEv = comdat any
# | 
# | $_ZNSt14suspend_always13await_suspendESt16coroutine_handleIvE = comdat any
# | 
# | $_ZNSt16coroutine_handleIN6MyTask12promise_typeEE12from_addressEPv = comdat any
# | 
# | $_ZNSt14suspend_always12await_resumeEv = comdat any
# | 
# | $_ZN6MyTask12promise_type15await_transformERKi = comdat any
# | 
# | $_ZN7Awaiter11await_readyEv = comdat any
# | 
# | $_ZNKSt16coroutine_handleIvE7addressEv = comdat any
# | 
# | $_ZN7Awaiter12await_resumeEv = comdat any
# | 
# | $_ZN6MyTask12promise_type13final_suspendEv = comdat any
# | 
# | $_ZNSt16coroutine_handleIN6MyTask12promise_typeEE12from_promiseERS1_ = comdat any
# | 
# | $_ZNSt16coroutine_handleIN6MyTask12promise_typeEEC1Ev = comdat any
# | 
# | $_ZNSt16coroutine_handleIN6MyTask12promise_typeEEC2Ev = comdat any
# | 
# | $_ZNSt16coroutine_handleIvEC2Ev = comdat any
# | 
# | @g_array = global [32 x i32] zeroinitializer, align 16
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local ptr @_Z6FooBarv() #0 {
# | entry:
# |   %retval = alloca %struct.MyTask, align 8
# |   %undef.agg.tmp = alloca %"struct.std::suspend_always", align 1
# |   %undef.agg.tmp19 = alloca %"struct.std::suspend_always", align 1
# |   %call = call noalias noundef nonnull ptr @_Znwm(i64 noundef 64) #6
# |   store ptr @_Z6FooBarv.resume, ptr %call, align 8
# |   %0 = select i1 true, ptr @_Z6FooBarv.destroy, ptr @_Z6FooBarv.cleanup
# |   %destroy.addr = getelementptr inbounds i8, ptr %call, i64 8
# |   store ptr %0, ptr %destroy.addr, align 8
# |   %ref.tmp.reload.addr = getelementptr inbounds i8, ptr %call, i64 18
# |   %__range1.reload.addr = getelementptr inbounds i8, ptr %call, i64 24
# |   %__begin1.reload.addr = getelementptr inbounds i8, ptr %call, i64 32
# |   %__end1.reload.addr = getelementptr inbounds i8, ptr %call, i64 40
# |   %x.reload.addr = getelementptr inbounds i8, ptr %call, i64 48
# |   %ref.tmp4.reload.addr = getelementptr inbounds i8, ptr %call, i64 56
# |   %ref.tmp18.reload.addr = getelementptr inbounds i8, ptr %call, i64 19
# |   %__promise.reload.addr = getelementptr inbounds i8, ptr %call, i64 16
# |   %call1 = call ptr @_ZN6MyTask12promise_type17get_return_objectEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise.reload.addr)
# |   %coerce.dive = getelementptr inbounds nuw %struct.MyTask, ptr %retval, i32 0, i32 0
# |   %coerce.dive2 = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %coerce.dive, i32 0, i32 0
# |   store ptr %call1, ptr %coerce.dive2, align 8
# |   call void @_ZN6MyTask12promise_type15initial_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise.reload.addr)
# |   %call3 = call noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp.reload.addr) #7
# |   br i1 %call3, label %init.ready, label %CoroSave
# | 
# | CoroSave:                                         ; preds = %entry
# |   %index.addr39 = getelementptr inbounds i8, ptr %call, i64 17
# |   store i8 0, ptr %index.addr39, align 1
# |   call void @_Z6FooBarv.__await_suspend_wrapper__init(ptr %ref.tmp.reload.addr, ptr %call) #7
# |   br label %AfterCoroEnd
# | 
# | init.ready:                                       ; preds = %entry
# |   call void @_ZNSt14suspend_always12await_resumeEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp.reload.addr) #7
# |   store ptr @g_array, ptr %__range1.reload.addr, align 8
# |   store ptr @g_array, ptr %__begin1.reload.addr, align 8
# |   store ptr getelementptr inbounds nuw (i8, ptr @g_array, i64 128), ptr %__end1.reload.addr, align 8
# |   br label %for.cond
# | 
# | for.cond:                                         ; preds = %for.inc, %init.ready
# |   %1 = load ptr, ptr %__begin1.reload.addr, align 8
# |   %2 = load ptr, ptr %__end1.reload.addr, align 8
# |   %cmp = icmp ne ptr %1, %2
# |   br i1 %cmp, label %for.body, label %coro.final
# | 
# | for.body:                                         ; preds = %for.cond
# |   %3 = load ptr, ptr %__begin1.reload.addr, align 8
# |   store ptr %3, ptr %x.reload.addr, align 8
# |   %4 = load ptr, ptr %x.reload.addr, align 8, !nonnull !1, !align !2
# |   %call5 = call ptr @_ZN6MyTask12promise_type15await_transformERKi(ptr noundef nonnull align 1 dereferenceable(1) %__promise.reload.addr, ptr noundef nonnull align 4 dereferenceable(4) %4)
# |   %coerce.dive6 = getelementptr inbounds nuw %struct.Awaiter, ptr %ref.tmp4.reload.addr, i32 0, i32 0
# |   store ptr %call5, ptr %coerce.dive6, align 8
# |   %call7 = call noundef zeroext i1 @_ZN7Awaiter11await_readyEv(ptr noundef nonnull align 8 dereferenceable(8) %ref.tmp4.reload.addr)
# |   br i1 %call7, label %await.ready, label %CoroSave27
# | 
# | CoroSave27:                                       ; preds = %for.body
# |   %index.addr40 = getelementptr inbounds i8, ptr %call, i64 17
# |   store i8 1, ptr %index.addr40, align 1
# |   %5 = call ptr @_Z6FooBarv.__await_suspend_wrapper__await(ptr %ref.tmp4.reload.addr, ptr %call)
# |   %6 = getelementptr inbounds { ptr, ptr }, ptr %5, i32 0, i32 0
# |   %7 = load ptr, ptr %6, align 8
# |   call void %7(ptr %5)
# |   br label %AfterCoroEnd
# | 
# | await.ready:                                      ; preds = %for.body
# |   call void @_ZN7Awaiter12await_resumeEv(ptr noundef nonnull align 8 dereferenceable(8) %ref.tmp4.reload.addr)
# |   %cond = icmp eq i32 0, 0
# |   %cond26 = icmp eq i32 0, 0
# |   br i1 %cond26, label %for.inc, label %coro.final
# | 
# | for.inc:                                          ; preds = %await.ready
# |   %8 = load ptr, ptr %__begin1.reload.addr, align 8
# |   %incdec.ptr = getelementptr inbounds nuw i32, ptr %8, i32 1
# |   store ptr %incdec.ptr, ptr %__begin1.reload.addr, align 8
# |   br label %for.cond
# | 
# | coro.final:                                       ; preds = %await.ready, %for.cond
# |   call void @_ZN6MyTask12promise_type13final_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise.reload.addr) #7
# |   %call20 = call noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp18.reload.addr) #7
# |   br i1 %call20, label %final.ready, label %CoroSave31
# | 
# | CoroSave31:                                       ; preds = %coro.final
# |   store ptr null, ptr %call, align 8
# |   call void @_Z6FooBarv.__await_suspend_wrapper__final(ptr %ref.tmp18.reload.addr, ptr %call) #7
# |   br label %AfterCoroEnd
# | 
# | final.ready:                                      ; preds = %coro.final
# |   call void @_ZNSt14suspend_always12await_resumeEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp18.reload.addr) #7
# |   %9 = icmp ne ptr %call, null
# |   br i1 %9, label %coro.free, label %AfterCoroEnd
# | 
# | coro.free:                                        ; preds = %final.ready
# |   call void @_ZdlPvm(ptr noundef %call, i64 noundef 64) #7
# |   br label %AfterCoroEnd
# | 
# | AfterCoroEnd:                                     ; preds = %coro.free, %final.ready, %CoroSave27, %CoroSave31, %CoroSave
# |   %coerce.dive24 = getelementptr inbounds nuw %struct.MyTask, ptr %retval, i32 0, i32 0
# |   %coerce.dive25 = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %coerce.dive24, i32 0, i32 0
# |   %10 = load ptr, ptr %coerce.dive25, align 8
# |   ret ptr %10
# | }
# | 
# | ; Function Attrs: nobuiltin allocsize(0)
# | declare noundef nonnull ptr @_Znwm(i64 noundef) #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define linkonce_odr ptr @_ZN6MyTask12promise_type17get_return_objectEv(ptr noundef nonnull align 1 dereferenceable(1) %this) #0 comdat align 2 {
# | entry:
# |   %retval = alloca %struct.MyTask, align 8
# |   %this.addr = alloca ptr, align 8
# |   %ref.tmp = alloca %"struct.std::coroutine_handle.0", align 8
# |   store ptr %this, ptr %this.addr, align 8
# |   %this1 = load ptr, ptr %this.addr, align 8
# |   %h = getelementptr inbounds nuw %struct.MyTask, ptr %retval, i32 0, i32 0
# |   %call = call ptr @_ZNSt16coroutine_handleIN6MyTask12promise_typeEE12from_promiseERS1_(ptr noundef nonnull align 1 dereferenceable(1) %this1)
# |   %coerce.dive = getelementptr inbounds nuw %"struct.std::coroutine_handle.0", ptr %ref.tmp, i32 0, i32 0
# |   %coerce.dive2 = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %coerce.dive, i32 0, i32 0
# |   store ptr %call, ptr %coerce.dive2, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %h, ptr align 8 %ref.tmp, i64 8, i1 false)
# |   %coerce.dive3 = getelementptr inbounds nuw %struct.MyTask, ptr %retval, i32 0, i32 0
# |   %coerce.dive4 = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %coerce.dive3, i32 0, i32 0
# |   %0 = load ptr, ptr %coerce.dive4, align 8
# |   ret ptr %0
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define linkonce_odr void @_ZN6MyTask12promise_type15initial_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %this) #0 comdat align 2 {
# | entry:
# |   %this.addr = alloca ptr, align 8
# |   store ptr %this, ptr %this.addr, align 8
# |   %this1 = load ptr, ptr %this.addr, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define linkonce_odr noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %this) #0 comdat align 2 {
# | entry:
# |   %this.addr = alloca ptr, align 8
# |   store ptr %this, ptr %this.addr, align 8
# |   %this1 = load ptr, ptr %this.addr, align 8
# |   ret i1 false
# | }
# | 
# | ; Function Attrs: alwaysinline mustprogress nounwind
# | define internal void @_Z6FooBarv.__await_suspend_wrapper__init(ptr noundef nonnull %0, ptr noundef %1) #2 {
# | entry:
# |   %.addr = alloca ptr, align 8
# |   %.addr1 = alloca ptr, align 8
# |   %agg.tmp = alloca %"struct.std::coroutine_handle", align 8
# |   %ref.tmp = alloca %"struct.std::coroutine_handle.0", align 8
# |   store ptr %0, ptr %.addr, align 8
# |   store ptr %1, ptr %.addr1, align 8
# |   %2 = load ptr, ptr %.addr, align 8
# |   %3 = load ptr, ptr %.addr1, align 8
# |   %call = call ptr @_ZNSt16coroutine_handleIN6MyTask12promise_typeEE12from_addressEPv(ptr noundef %3) #7
# |   
# | ...
# `---data was truncated (10240/37953) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=sroa,mem2reg,simplifycfg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=sroa,mem2reg,simplifycfg -S
# |  #0 0x000055ea9f932eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ea9f92fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ea9f93362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2815733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f281578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2815733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f281571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ea9f8c8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ea9f8c8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ea9f8ad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ea9f55ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ea9f55cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f281571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f281571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f281571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ea9f55ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp --check-prefix=CHECK-O0
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp --check-prefix=CHECK-O0
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c (91 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f    -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_sf_vfexp_v_bf16mf4(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_sf_vfexp_v_bf16mf2(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_sf_vfexp_v_bf16m1(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_sf_vfexp_v_bf16m2(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_sf_vfexp_v_bf16m4(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_sf_vfexp_v_bf16m8(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_sf_vfexp_v_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_sf_vfexp_v_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_sf_vfexp_v_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_sf_vfexp_v_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_sf_vfexp_v_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, al
# | ...
# `---data was truncated (10240/12389) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005642f8704eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005642f8701e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005642f870562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8bc1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8bc178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8bc1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8bc171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005642f869abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005642f869aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005642f867f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005642f832ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005642f832eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8bc171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8bc171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8bc171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005642f832ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c (92 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svcreate2_b(<vscale x 16 x i1> %x0, <vscale x 16 x i1> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i1>, align 2
# |   %x1.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %x0, ptr %x0.addr, align 2
# |   store <vscale x 16 x i1> %x1, ptr %x1.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %x0.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %x1.addr, align 2
# |   %2 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %0, 0
# |   %3 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %1, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055bb073b2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bb073afe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bb073b362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f83ce333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83ce38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f83ce333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f83ce31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bb07348bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bb07348a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bb0732d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bb06fdce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bb06fdcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f83ce31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83ce31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83ce31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bb06fdca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c (93 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf4_f32m1(<vscale x 1 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float>, <vscale x 1 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf2_f32m1(<vscale x 2 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m1_f32m1(<vscale x 4 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float>, <vscale x 4 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m2_f32m1(<vscale x 8 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float>, <vscale x 8 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m4_f32m1(<vscale x 16 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float>, <vscale x 16 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m8_f32m1(<vscale x 32 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float>, <vscale x 32 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32mf2_f64m1(<vscale x 1 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m1_f64m1(<vscale x 2 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(<vscale x 1 x double>, <vscale x 2 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m2_f64m1(<vscale x 4 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret 
# | ...
# `---data was truncated (10240/50516) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005575c9595eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005575c9592e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005575c959662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9e70449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9e704a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9e70449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9e70431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005575c952bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005575c952ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005575c95108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005575c91bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005575c91bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9e70432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9e704330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9e704330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005575c91bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c (94 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzip1_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zip1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.zip1.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzip1_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zip1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.zip1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzip1_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zip1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.zip1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzip1_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zip1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.zip1.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzip1_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zip1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzip1_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zip1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzip1_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zip1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzip1_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zip1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svzip1_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.zip1.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.zip1.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svzip1_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.zip1.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.zip1.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svzip1_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.zip1.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.zip1.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svzip1_b8(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.zip1.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.zip1.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svzip1_b16(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.zip1.b16(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | ...
# `---data was truncated (10240/13404) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000556010ee1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556010edee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556010ee262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f104be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f104bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f104be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f104be31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556010e77bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556010e77a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556010e5c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556010b0be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556010b0bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f104be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f104be330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f104be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556010b0ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c (95 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056522def0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056522deede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056522def162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd544e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd544ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd544e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd544e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056522de86bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056522de86a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056522de6b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056522db1ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056522db1ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd544e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd544e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd544e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056522db1aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c (96 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtssel_f16(<vscale x 8 x half> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.ftssel.x.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ftssel.x.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtssel_f32(<vscale x 4 x float> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.ftssel.x.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ftssel.x.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtssel_f64(<vscale x 2 x double> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.ftssel.x.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ftssel.x.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i64>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560db98adeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560db98aae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560db98ae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0f96a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0f96aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0f96a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0f96a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560db9843bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560db9843a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560db98288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560db94d7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560db94d7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0f96a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0f96a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0f96a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560db94d7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c (97 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaaddu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaaddu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaaddu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaaddu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaaddu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaaddu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaaddu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaaddu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaaddu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaaddu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_lo
# | ...
# `---data was truncated (10240/99851) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561683760eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056168375de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056168376162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2534733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f253478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2534733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f253471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005616836f6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005616836f6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005616836db8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056168338ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056168338ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f253471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f253471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f253471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056168338aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c (98 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u8mf8(i8 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i32, align 4
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i8, ptr %rs1.addr, align 1
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 5, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 immarg, i32 immarg, i32 immarg, i8, i32 immarg, i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u8mf4(i8 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i32, align 4
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i8, ptr %rs1.addr, align 1
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 6, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u8mf2(i8 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i32, align 4
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i8, ptr %rs1.addr, align 1
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 7, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u8m1(i8 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i32, align 4
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i8, ptr %rs1.addr, align 1
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 0, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u8m2(i8 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i32, align 4
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i8, ptr %rs1.addr, align 1
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 1, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u8m4(i8 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i32, align 4
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i8, ptr %rs1.addr, align 1
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 2, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u8m8(i8 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i32, align 4
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i8, ptr %rs1.addr, align 1
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 3, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u16mf4(i16 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i16, align 2
# |   %vl.addr = alloca i32, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i16, ptr %rs1.addr, align 2
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 6, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 immarg, i32 immarg, i32 immarg, i16, i32 immarg, i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u16mf2(i16 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i16, align 2
# |   %vl.addr = alloca i32, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i16, ptr %rs1.addr, align 2
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 7, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u16m1(i16 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i16, align 2
# |   %vl.addr = alloca i32, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i16, ptr %rs1.addr, align 2
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 0, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u16m2(i16 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i16, align 2
# |   %vl.addr = alloca i32, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i16, ptr %rs1.addr, align 2
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 1, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u16m4(i16 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i16, align 2
# |   %vl.addr = alloca i32, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i16, ptr %rs1.addr, align 2
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 2, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u16m8(i16 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i16, align 2
# |   %vl.addr = alloca i32, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i16, ptr %rs1.addr, align 2
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 3, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u32mf2(i32 noundef %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 7, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 immarg, i32 immarg, i32 immarg, i32, i32 immarg, i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u32m1(i32 noundef %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 0, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u32m2(i32 noundef %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 1, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u32m4(i32 noundef %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 2, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u32m8(i32 noundef %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 3, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vc_v_x_se_u8mf8(i8 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i32, align 4
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i8, ptr %rs1.addr, align 1
# |   %1 = load i32, ptr %vl.addr, align 4
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.x.se.nxv1i8.i32.i8.i32(i32 3, i32 31, i8 %0, i32 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nounwind
# | ...
# `---data was truncated (10240/66298) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056184e8f6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056184e8f3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056184e8f762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd3af733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd3af78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd3af733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd3af71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056184e88cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056184e88ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056184e8718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056184e520e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056184e520b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd3af71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd3af71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd3af71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056184e520a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c (99 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabdu_vv_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabdu_vx_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabdu_vv_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabdu_vx_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabdu_vv_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabdu_vx_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabdu_vv_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabdu_vx_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabdu_vv_u8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale 
# | ...
# `---data was truncated (10240/215486) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a1319c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a1319bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a1319c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f50f7333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f50f738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f50f7333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f50f731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a131956bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a131956a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a13193b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a1315eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a1315eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f50f731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f50f731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f50f731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a1315eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c (100 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvpackfph -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadb_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadb_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadb_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadb_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half>, <vscale x 8 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_nds_vfpmadb_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half>, <vscale x 16 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_nds_vfpmadb_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half>, <vscale x 32 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadb_vf_f16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load float, ptr %op2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half> %1, <vscale x 1 x half> %2, float %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadb_vf_f16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load float, ptr %op2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64(<vscale x 2 x half> %1, <vscale x 2 x half> %2, float %3, <vsc
# | ...
# `---data was truncated (10240/59603) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a757850eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a75784de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a75785162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff2d9333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff2d938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff2d9333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff2d931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a7577e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a7577e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a7577cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a75747ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a75747ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff2d931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff2d931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff2d931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a75747aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c (101 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vget_v_u64m4x2_u64m4(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %src) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %src, ptr %src.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %src.addr, align 8
# |   %1 = call <vscale x 4 x i64> @llvm.riscv.tuple.extract.nxv4i64.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, i32 1)
# |   ret <vscale x 4 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.tuple.extract.nxv4i64.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vset_v_u64m4_u64m4x2(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %dest, <vscale x 4 x i64> %val) #0 {
# | entry:
# |   %dest.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %val.addr = alloca <vscale x 4 x i64>, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %dest, ptr %dest.addr, align 8
# |   store <vscale x 4 x i64> %val, ptr %val.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %dest.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %val.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv32i8_2t.nxv4i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, <vscale x 4 x i64> %1, i32 1)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv32i8_2t.nxv4i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), <vscale x 4 x i64>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056188561ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561885619e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056188561d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f95e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f95ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f95e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f95e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005618855b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005618855b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005618855978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561885246e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561885246b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1f95e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f95e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f95e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561885246a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c (102 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcvt1_bf16_mf8_fpm(<8 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %ref.tmp.i = alloca <8 x bfloat>, align 16
# |   %op.addr = alloca <8 x i8>, align 8
# |   %fpm.addr = alloca i64, align 8
# |   store <8 x i8> %op, ptr %op.addr, align 8
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <8 x i8>, ptr %op.addr, align 8
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt1.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl1.v8bf16.v8i8(<8 x i8> %2)
# |   store <8 x bfloat> %vbfcvt1.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x bfloat>, ptr %ref.tmp.i, align 16
# |   store <8 x bfloat> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcvt1_low_bf16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %ref.tmp.i = alloca <8 x bfloat>, align 16
# |   %op.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <16 x i8> %op, ptr %op.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <16 x i8>, ptr %op.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   %4 = call <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8> %2, i64 0)
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt1.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl1.v8bf16.v8i8(<8 x i8> %4)
# |   store <8 x bfloat> %vbfcvt1.i, ptr %ref.tmp.i, align 16
# |   %5 = load <8 x bfloat>, ptr %ref.tmp.i, align 16
# |   store <8 x bfloat> %5, ptr %__ret.i, align 16
# |   %6 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcvt2_bf16_mf8_fpm(<8 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %ref.tmp.i = alloca <8 x bfloat>, align 16
# |   %op.addr = alloca <8 x i8>, align 8
# |   %fpm.addr = alloca i64, align 8
# |   store <8 x i8> %op, ptr %op.addr, align 8
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <8 x i8>, ptr %op.addr, align 8
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt2.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl2.v8bf16.v8i8(<8 x i8> %2)
# |   store <8 x bfloat> %vbfcvt2.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x bfloat>, ptr %ref.tmp.i, align 16
# |   store <8 x bfloat> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcvt2_low_bf16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %ref.tmp.i = alloca <8 x bfloat>, align 16
# |   %op.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <16 x i8> %op, ptr %op.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <16 x i8>, ptr %op.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   %4 = call <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8> %2, i64 0)
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt2.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl2.v8bf16.v8i8(<8 x i8> %4)
# |   store <8 x bfloat> %vbfcvt2.i, ptr %ref.tmp.i, align 16
# |   %5 = load <8 x bfloat>, ptr %ref.tmp.i, align 16
# |   store <8 x bfloat> %5, ptr %__ret.i, align 16
# |   %6 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcvt1_high_bf16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %ref.tmp.i = alloca <8 x bfloat>, align 16
# |   %op.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <16 x i8> %op, ptr %op.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <16 x i8>, ptr %op.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt1.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl1.v8bf16.v16i8(<16 x i8> %2)
# |   store <8 x bfloat> %vbfcvt1.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x bfloat>, ptr %ref.tmp.i, align 16
# |   store <8 x bfloat> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcvt2_high_bf16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %ref.tmp.i = alloca <8 x bfloat>, align 16
# |   %op.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <16 x i8> %op, ptr %op.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <16 x i8>, ptr %op.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt2.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl2.v8bf16.v16i8(<16 x i8> %2)
# |   store <8 x bfloat> %vbfcvt2.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x bfloat>, ptr %ref.tmp.i, align 16
# |   store <8 x bfloat> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vcvt1_f16_mf8_fpm(<8 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <8 x half>, align 16
# |   %op.addr = alloca <8 x i8>, align 8
# |   %fpm.addr = alloca i64, align 8
# |   store <8 x i8> %op, ptr %op.addr, align 8
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <8 x i8>, ptr %op.addr, align 8
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt1.i = call <8 x half> @llvm.aarch64.neon.fp8.cvtl1.v8f16.v8i8(<8 x i8> %2)
# |   store <8 x half> %vbfcvt1.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vcvt1_low_f16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <8 x half>, align 16
# |   %op.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <16 x i8> %op, ptr %op.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <16 x i8>, ptr %op.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   %4 = call <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8> %2, i64 0)
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt1.i = call <8 x half> @llvm.aarch64.neon.fp8.cvtl1.v8f16.v8i8(<8 x i8> %4)
# |   store <8 x half> %vbfcvt1.i, ptr %ref.tmp.i, align 16
# |   %5 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %5, ptr %__ret.i, align 16
# |   %6 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vcvt2_f16_mf8_fpm(<8 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <8 x half>, align 16
# |   %op.addr = alloca <8 x i8>, align 8
# |   %fpm.addr = alloca i64, align 8
# |   store <8 x i8> %op, ptr %op.addr, align 8
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <8 x i8>, ptr %op.addr, align 8
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt2.i = call <8 x half> @llvm.aarch64.neon.fp8.cvtl2.v8f16.v8i8(<8 x i8> %2)
# |   store <8 x half> %vbfcvt2.i, ptr %ref.tmp.i
# | ...
# `---data was truncated (10240/23350) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# |  #0 0x000055bc37450eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bc3744de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bc3745162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd770a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd770aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd770a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd770a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bc373e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bc373e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bc373cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bc3707ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bc3707ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd770a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd770a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd770a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bc3707aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c (103 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563a33655eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563a33652e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563a3365662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1b87449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1b874a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1b87449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1b87431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a335ebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563a335eba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563a335d08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563a3327fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563a3327fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1b87432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1b874330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1b874330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a3327fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c (104 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsra_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsra_vx_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsra_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsra_vx_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsra_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsra_vx_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsra_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsra_vx_i8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsra_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsra_vx_i8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsra_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/98351) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555adfff1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555adffeee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555adfff262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0a90449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0a904a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0a90449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0a90431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555adff87bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555adff87a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555adff6c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555adfc1be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555adfc1bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0a90432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0a904330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0a904330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555adfc1ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c (105 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaeskf1_vi_u32mf2(<vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i64.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaeskf1_vi_u32m1(<vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i64.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaeskf1_vi_u32m2(<vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i64.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaeskf1_vi_u32m4(<vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i64.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaeskf1_vi_u32m8(<vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i64.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563bfb85eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563bfb85be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563bfb85f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f90fe049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f90fe0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f90fe049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f90fe031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563bfb7f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563bfb7f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563bfb7d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563bfb488e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563bfb488b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f90fe032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f90fe0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f90fe0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563bfb488a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vorrq.c (106 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vorrq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vorrq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = or <16 x i8> %0, %1
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = or <8 x i16> %0, %1
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = or <4 x i32> %0, %1
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vorrq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = or <4 x i32> %1, %3
# |   %5 = bitcast <4 x i32> %4 to <4 x float>
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vorrq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.orr.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.orr.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vorrq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <8 x i16>
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = bitcast <8 x half> %2 to <8 x i16>
# |   %4 = load i16, ptr %p.addr, align 2
# |   %5 = zext i16 %4 to i32
# |   %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5)
# |   %7 = load <8 x half>, ptr %inactive.addr, align 8
# |   %8 = bitcast <8 x half> %7 to <8 x i16>
# |   %9 = call <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8)
# |   %10 = bitcast <8 x i16> %9 to <8 x half>
# |   ret <8 x half> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vorrq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.orr.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vorrq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = load i16, ptr %p.addr, align 2
# |   %5 = zext i16 %4 to i32
# |   %6 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %5)
# |   %7 = call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32
# | ...
# `---data was truncated (10240/10897) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dd07eaceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dd07ea9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dd07ead62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf09d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf09d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf09d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf09ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd07e42bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dd07e42a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dd07e278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dd07ad6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dd07ad6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdf09ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf09cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf09cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd07ad6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c (107 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za32_s8_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smop4a.wide.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4a.wide.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x1_za32_s8_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smop4s.wide.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4s.wide.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za32_u8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umop4a.wide.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4a.wide.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x1_za32_u8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umop4s.wide.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4s.wide.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za32_s8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sumop4a.wide.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.sumop4a.wide.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x1_za32_s8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sumop4s.wide.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.sumop4s.wide.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za32_u8_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.usmop4a.wide.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.usmop4a.wide.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x1_za32_u8_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.usmop4s.wide.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.usmop4s.wide.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za32_s16_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smop4a.wide.1x1.nxv8i16(i32 1, <vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4a.wide.1x1.nxv8i16(i32 immarg, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x1_za32_s16_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smop4s.wide.1x1.nxv8i16(i32 1, <vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4s.wide.1x1.nxv8i16(i32 immarg, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za32_u16_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umop4a.wide.1x1.nxv8i16(i32 1, <vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4a.wide.1x1.nxv8i16(i32 immarg, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x1_za32_u16_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umop4s.wide.1x1.nxv8i16(i32 1, <vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4s.wide.1x1.nxv8i16(i32 immarg, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za32_f16_f16(
# | ...
# `---data was truncated (10240/27272) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055df4dac0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055df4dabde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055df4dac162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7a3f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7a3f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7a3f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7a3f11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055df4da56bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055df4da56a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055df4da3b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055df4d6eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055df4d6eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7a3f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7a3f11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7a3f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055df4d6eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c (108 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_f16m1x2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_f16m2x2(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei8_v_f16m4x2(ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_f32m1x2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_f32m2x2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x
# | ...
# `---data was truncated (10240/113019) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de365d2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055de365cfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055de365d362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f76d1105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f76d115c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f76d1105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f76d10ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de36568bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055de36568a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055de3654d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055de361fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055de361fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f76d10eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f76d10ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f76d10ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de361fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c (109 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8.p0.i64(<vscale x 16 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.p0.i64(<vscale x 32 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.p0.i64(<vscale x 64 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# | 
# | ...
# `---data was truncated (10240/54488) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b3f1118eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b3f1115e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b3f111962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f436f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f436f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f436f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f436f831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b3f10aebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b3f10aea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b3f10938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b3f0d42e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b3f0d42b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f436f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f436f8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f436f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b3f0d42a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c (110 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svmin_single_s8_x2(<vscale x 16 x i8> %zdn.coerce0, <vscale x 16 x i8> %zdn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zdn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zdn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.smin.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.smin.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svmin_single_s16_x2(<vscale x 8 x i16> %zdn.coerce0, <vscale x 8 x i16> %zdn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zdn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.smin.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.smin.single.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svmin_single_s32_x2(<vscale x 4 x i32> %zdn.coerce0, <vscale x 4 x i32> %zdn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zdn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zdn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zdn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.smin.single.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.smin.single.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svmin_single_s64_x2(<vscale x 2 x i64> %zdn.coerce0, <vscale x 2 x i64> %zdn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zdn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zdn.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zdn, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 0
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 1
# |   %5 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.smin.single.x2.nxv2i64(<vscale x 2 x i64> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.smin.single.x2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svmin_single_u8_x2(<vscale x 16 x i8> %zdn.coerce0, <vscale x 16 x i8> %zdn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zdn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zdn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.umin.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.umin.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svmin_single_u16_x2(<vscale x 8 x i16> %zdn.coerce0, <vscale x 8 x i16> %zdn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zdn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.umin.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.umin.single.x
# | ...
# `---data was truncated (10240/142195) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000558d6224ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558d62249e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558d6224d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5526733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f552678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5526733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f552671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d621e2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558d621e2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558d621c78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558d61e76e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558d61e76b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f552671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f552671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f552671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d61e76a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c (111 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzp2_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uzp2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzp2_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uzp2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzp2_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uzp2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzp2_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzp2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uzp2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzp2_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzp2_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzp2_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzp2_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzp2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svuzp2_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.uzp2.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.uzp2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svuzp2_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.uzp2.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.uzp2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svuzp2_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.uzp2.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.uzp2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svuzp2_b8(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.uzp2.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.uzp2.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svuzp2_b16(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.uzp2.b16(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | ...
# `---data was truncated (10240/13404) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000558519279eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558519276e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055851927a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1bfce1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1bfce725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1bfce1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1bfce03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055851920fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055851920fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005585191f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558518ea3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558518ea3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1bfce04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1bfce050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1bfce050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558518ea3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c (112 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadc_vvm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadc_vxm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadc_vvm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadc_vxm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadc_vvm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadc_vxm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadc_vvm_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 8 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | 
# | ...
# `---data was truncated (10240/116957) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555f2098ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555f20989e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555f2098d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba07d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba07d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba07d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba07ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f20922bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555f20922a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555f209078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555f205b6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555f205b6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fba07ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba07cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba07cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f205b6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c (113 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfwma -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vf_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vf_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vf_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vf_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x
# | ...
# `---data was truncated (10240/101475) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056507ae4beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056507ae48e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056507ae4c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb46049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb460a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb46049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb46031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056507ade1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056507ade1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056507adc68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056507aa75e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056507aa75b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffb46032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb460330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb460330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056507aa75a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c (114 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmadd_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmadd_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmadd_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmadd_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmadd_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmadd_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmadd_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmadd_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# | ...
# `---data was truncated (10240/34438) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557a04cd0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557a04ccde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557a04cd162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0ceef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0ceef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0ceef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0ceef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557a04c66bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557a04c66a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557a04c4b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557a048fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557a048fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0ceef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0ceef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0ceef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557a048faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c (115 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vv_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vf_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wv_bf16mf4_f32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wf_bf16_f32mf2(<vscale x 1 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vv_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vf_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wv_bf16mf2_f32m1(<vscale x 2 x float> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wf_bf16_f32m1(<vscale x 2 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwsub_vv_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwsub_vf_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.a
# | ...
# `---data was truncated (10240/86092) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564072837eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564072834e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056407283862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f648eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f648eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f648eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f648eb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005640727cdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005640727cda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005640727b28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564072461e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564072461b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f648eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f648eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f648eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564072461a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c (116 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_bf16mf4x4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_bf16mf2x4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_bf16m1x4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_bf16m2x4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i
# | ...
# `---data was truncated (10240/12756) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aca206ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aca2069e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aca206d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1074a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1074a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1074a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1074a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aca2002bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aca2002a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aca1fe78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aca1c96e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aca1c96b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1074a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1074a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1074a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aca1c96a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c (117 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16mf4x5(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16mf2x5(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16m1x5(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f13c4b9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f13c4b6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f13c4ba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8bf8049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8bf80a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8bf8049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8bf8031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f13c44fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f13c44fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f13c4348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f13c0e3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f13c0e3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8bf8032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8bf80330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8bf80330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f13c0e3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c (118 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>
# | ...
# `---data was truncated (10240/19492) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558b15a0ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558b15a09e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558b15a0d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f44ab933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f44ab98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f44ab933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f44ab91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558b159a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558b159a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558b159878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558b15636e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558b15636b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f44ab91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44ab91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44ab91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558b15636a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c (119 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmclr_m_b1(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 64 x i1> @llvm.riscv.vmclr.nxv64i1.i64(i64 %0)
# |   ret <vscale x 64 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmclr.nxv64i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmclr_m_b2(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 32 x i1> @llvm.riscv.vmclr.nxv32i1.i64(i64 %0)
# |   ret <vscale x 32 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmclr.nxv32i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmclr_m_b4(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 16 x i1> @llvm.riscv.vmclr.nxv16i1.i64(i64 %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmclr.nxv16i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmclr_m_b8(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 8 x i1> @llvm.riscv.vmclr.nxv8i1.i64(i64 %0)
# |   ret <vscale x 8 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmclr.nxv8i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmclr_m_b16(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 4 x i1> @llvm.riscv.vmclr.nxv4i1.i64(i64 %0)
# |   ret <vscale x 4 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmclr.nxv4i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmclr_m_b32(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 2 x i1> @llvm.riscv.vmclr.nxv2i1.i64(i64 %0)
# |   ret <vscale x 2 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmclr.nxv2i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmclr_m_b64(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 1 x i1> @llvm.riscv.vmclr.nxv1i1.i64(i64 %0)
# |   ret <vscale x 1 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmclr.nxv1i1.i64(i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d076522eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d07651fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d07652362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f61bf533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f61bf58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f61bf533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f61bf51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0764b8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d0764b8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d07649d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d07614ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d07614cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f61bf51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61bf51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61bf51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d07614ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c (120 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vbrev8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vbrev8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vbrev8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vbrev8_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vbrev8_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vbrev8_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vbrev8_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vbrev8_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vbrev8_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vbrev8_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwin
# | ...
# `---data was truncated (10240/95437) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561050c54eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561050c51e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561050c5562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc43d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc43d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc43d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc43d631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561050beabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561050beaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561050bcf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056105087ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056105087eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc43d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc43d6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc43d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056105087ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c (121 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2e
# | ...
# `---data was truncated (10240/253148) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec2a525eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ec2a522e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ec2a52662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd0f3249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd0f32a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd0f3249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd0f3231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec2a4bbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ec2a4bba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ec2a4a08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ec2a14fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ec2a14fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd0f3232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd0f32330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd0f32330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec2a14fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c (122 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_rod_f_f_w_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_rod_f_f_w_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfncvt_rod_f_f_w_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfncvt_rod_f_f_w_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfncvt_rod_f_f_w_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfncvt_rod_f_f_w_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> %0, <vscale x 1 x double> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfncvt_rod_f_f_w_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> %0, <vscale x 2 x double> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfncvt_rod_f_f_w_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> %0, <vscale x 4 x double> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfncvt_rod_f_f_w_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> %0, <vscale x 8 x double> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_rod_f_f_w_f16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x half> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, alig
# | ...
# `---data was truncated (10240/41926) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a2e88c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a2e88bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a2e88c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe4f4e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe4f4ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe4f4e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe4f4e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a2e8856bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a2e8856a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a2e883b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a2e84eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a2e84eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe4f4e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe4f4e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe4f4e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a2e84eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c (123 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i8> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i8> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i8> %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> %2, ptr %0, <vscale x 32 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs
# | ...
# `---data was truncated (10240/15504) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005567f66b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005567f66b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005567f66b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa45ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa45aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa45ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa45ac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005567f664bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005567f664ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005567f66308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005567f62dfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005567f62dfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa45ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa45ac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa45ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005567f62dfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c (124 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4k_vi_u32mf2(<vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i64.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4k_vi_u32m1(<vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i64.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4k_vi_u32m2(<vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i64.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4k_vi_u32m4(<vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i64.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm4k_vi_u32m8(<vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i64.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005583baf2aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005583baf27e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005583baf2b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fede6505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fede655c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fede6505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fede64ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005583baec0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005583baec0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005583baea58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005583bab54e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005583bab54b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fede64eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fede64ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fede64ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005583bab54a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c (125 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c  -check-prefix=RV32ZKND
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @aes32dsi(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   %2 = call i32 @llvm.riscv.aes32dsi(i32 %0, i32 %1, i32 3)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.aes32dsi(i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @aes32dsmi(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   %2 = call i32 @llvm.riscv.aes32dsmi(i32 %0, i32 %1, i32 3)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.aes32dsmi(i32, i32, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zknd" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zknd1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563cb9eb9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563cb9eb6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563cb9eba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f74d8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f74d898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f74d8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f74d891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563cb9e4fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563cb9e4fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563cb9e348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563cb9ae3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563cb9ae3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f74d891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f74d891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f74d891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563cb9ae3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c -check-prefix=RV32ZKND
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c -check-prefix=RV32ZKND
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c (126 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfdiv_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfdiv_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfdiv_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfdiv_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfdiv_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfdiv_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfdiv_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfdiv_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range
# | ...
# `---data was truncated (10240/302397) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556945e39eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556945e36e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556945e3a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2cb4249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2cb42a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2cb4249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2cb4231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556945dcfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556945dcfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556945db48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556945a63e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556945a63b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2cb4232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2cb42330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2cb42330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556945a63a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c (127 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfne_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfne_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfne_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 3
# | ...
# `---data was truncated (10240/27794) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a368d6ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a368d69e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a368d6d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f98cea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f98ceaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f98cea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f98cea31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a368d02bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a368d02a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a368ce78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a368996e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a368996b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f98cea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f98cea330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f98cea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a368996a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c (128 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f16m1x7(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f32m1x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f64m1x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei32_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561b552a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561b5529fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561b552a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb95f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb95f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb95f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb95f031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561b55238bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561b55238a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561b5521d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561b54ecce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561b54eccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb95f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb95f0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb95f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561b54ecca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c (129 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556e49551eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556e4954ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556e4955262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7894733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f789478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7894733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f789471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e494e7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556e494e7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556e494cc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556e4917be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556e4917bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f789471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f789471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f789471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e4917ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c (130 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zvfhmin -target-feature +zvfbfmin    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste16_bf16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.sf.vste16.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste16_f16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste16_i16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste16_u16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvfbfmin,+zvfhmin,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfhmin1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056141ab55eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056141ab52e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056141ab5662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5abd81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5abd8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5abd81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5abd803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056141aaebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056141aaeba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056141aad08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056141a77fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056141a77fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5abd804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5abd8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5abd8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056141a77fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c (131 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f16m1x3(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_f16m2x3(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f32m1x3(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_f32m2x3(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f64m1x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.
# | ...
# `---data was truncated (10240/87884) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cadd3b6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cadd3b3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cadd3b762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9844905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f984495c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9844905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f98448ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cadd34cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cadd34ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cadd3318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cadcfe0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cadcfe0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f98448eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f98448ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f98448ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cadcfe0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c (132 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsac_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsac_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsac_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsac_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsac_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsac_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsac_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsac_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <
# | ...
# `---data was truncated (10240/34430) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d03094feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d03094ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d03095062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbca7933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbca798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbca7933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbca791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0308e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d0308e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d0308ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d030579e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d030579b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbca791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbca791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbca791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d030579a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c (133 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b266a4aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b266a47e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b266a4b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f76ced33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f76ced8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f76ced33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f76ced1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b2669e0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b2669e0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b2669c58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b266674e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b266674b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f76ced1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f76ced1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f76ced1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b266674a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c (134 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei32_v_f16mf4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei32_v_f16mf2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei32_v_f16m1(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei32_v_f16m2(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei32_v_f16m4(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei32_v_f32mf2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei32_v_f32m1(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei32_v_f32m2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei32_v_f32m4(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vluxei32_v_f32m8(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.p0.nxv16i32.i64(<vscale x 16 x float> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.p0.nxv16i32.i64(<vscale x 16 x
# | ...
# `---data was truncated (10240/107864) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c03c319eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c03c316e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c03c31a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd240649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd2406a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd240649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd240631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c03c2afbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c03c2afa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c03c2948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c03bf43e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c03bf43b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd240632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd2406330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd2406330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c03bf43a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c (135 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_4x8x4_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_4x8x4_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_4x8x4_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_4x8x4_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f32aed6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f32aed3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f32aed762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff71de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff71dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff71de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff71de31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f32ae6cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f32ae6ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f32ae518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f32ab00e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f32ab00b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff71de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff71de330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff71de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f32ab00a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c (136 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei32_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005588e12c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005588e12c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005588e12c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf12849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf128a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf12849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf12831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005588e125abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005588e125aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005588e123f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005588e0eeee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005588e0eeeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdf12832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf128330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf128330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005588e0eeea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c (137 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf4_u32m1(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf4_u32m2(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vzext_vf4_u32m4(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vzext_vf4_u32m8(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf4_u64m1(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf4_u64m2(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf4_u64m4(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf4_u64m8(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vzext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf4_u32m1_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vzext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf4_u32m2_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vzext.mask.nxv4i32.nxv4i8.i64(<
# | ...
# `---data was truncated (10240/17495) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564aafc11eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564aafc0ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564aafc1262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f86ade49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f86adea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f86ade49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f86ade31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564aafba7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564aafba7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564aafb8c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564aaf83be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564aaf83bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f86ade32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f86ade330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f86ade330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564aaf83ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c (138 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_i8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e8_v_i8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e8_v_i8m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_u8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_u8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e8_v_u8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/48313) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559d696a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559d696a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559d696a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f760a505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f760a55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f760a505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f760a4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559d6963cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559d6963ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559d696218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559d692d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559d692d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f760a4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f760a4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f760a4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559d692d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c (139 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4au_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4au_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>
# | ...
# `---data was truncated (10240/26512) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560e7bf90eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560e7bf8de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560e7bf9162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb4f7b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb4f7b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb4f7b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb4f7b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e7bf26bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560e7bf26a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560e7bf0b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560e7bbbae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560e7bbbab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb4f7b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb4f7b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb4f7b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e7bbbaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c (140 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b1(ptr noundef %base, <vscale x 64 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 64 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 64 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv64i1.p0.i64(<vscale x 64 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv64i1.p0.i64(<vscale x 64 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b2(ptr noundef %base, <vscale x 32 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv32i1.p0.i64(<vscale x 32 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv32i1.p0.i64(<vscale x 32 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b4(ptr noundef %base, <vscale x 16 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv16i1.p0.i64(<vscale x 16 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv16i1.p0.i64(<vscale x 16 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b8(ptr noundef %base, <vscale x 8 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv8i1.p0.i64(<vscale x 8 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv8i1.p0.i64(<vscale x 8 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b16(ptr noundef %base, <vscale x 4 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv4i1.p0.i64(<vscale x 4 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv4i1.p0.i64(<vscale x 4 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b32(ptr noundef %base, <vscale x 2 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv2i1.p0.i64(<vscale x 2 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv2i1.p0.i64(<vscale x 2 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b64(ptr noundef %base, <vscale x 1 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv1i1.p0.i64(<vscale x 1 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv1i1.p0.i64(<vscale x 1 x i1>, ptr captures(none), i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f7bd198eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f7bd195e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f7bd19962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6991333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f699138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6991333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f699131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f7bd12ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f7bd12ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f7bd1138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f7bcdc2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f7bcdc2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f699131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f699131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f699131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f7bcdc2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c (141 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16
# | ...
# `---data was truncated (10240/295311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005642211bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005642211b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005642211bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca4c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca4c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca4c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca4c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564221151bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564221151a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005642211368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564220de5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564220de5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fca4c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca4c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca4c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564220de5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c (142 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclip_wv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclip_wx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclip_wv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclip_wx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclip_wv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclip_wx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclip_wv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclip_wx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclip_wv_i8m2_tu(<vscale x 16 x 
# | ...
# `---data was truncated (10240/156463) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560f57356eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560f57353e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560f5735762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fadb3133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fadb318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fadb3133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fadb311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f572ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560f572eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560f572d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560f56f80e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560f56f80b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fadb311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fadb311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fadb311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f56f80a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c (143 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_f16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_f16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_f16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_i16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_i16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_i16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_u16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_u16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_u16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale 
# | ...
# `---data was truncated (10240/23357) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a6c77b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a6c77b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a6c77b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc28df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc28df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc28df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc28df1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a6c7749bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a6c7749a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a6c772e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a6c73dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a6c73ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc28df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc28df1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc28df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a6c73dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c (144 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei32_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c24d7feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562c24d7ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562c24d8062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f987cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f987cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f987cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f987cf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c24d15bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562c24d15a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562c24cfa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562c249a9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562c249a9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f987cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f987cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f987cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c249a9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_max.c (145 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_max.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmax_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.smax.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.smax.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmax_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.smax.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.smax.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmax_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.smax.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.smax.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmax_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.smax.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.smax.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmax_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.umax.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.umax.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmax_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.umax.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.umax.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmax_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.umax.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.umax.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmax_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale
# | ...
# `---data was truncated (10240/74195) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055a60c19eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a60c19be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a60c19f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f851ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f851ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f851ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f851ad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a60c134bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a60c134a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a60c1198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a60bdc8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a60bdc8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f851ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f851ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f851ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a60bdc8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c (146 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvsintload -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vln8_v_i8mf8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.nds.vln.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vln.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vln8_v_i8mf4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.nds.vln.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vln.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vln8_v_i8mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.nds.vln.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vln.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vln8_v_i8m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.nds.vln.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vln.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vln8_v_i8m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.nds.vln.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.nds.vln.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i8> @test_nds_vln8_v_i8m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.nds.vln.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.nds.vln.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_nds_vln8_v_i8m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.nds.vln.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.nds.vln.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vln8_v_i8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vln8_v_i8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vln8_v_i8mf2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vln8_v_i8m1_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.nds.vln.mask.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vln.mask.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vln8_v_i8m2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.nds.vln.mask.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.ris
# | ...
# `---data was truncated (10240/12914) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fbd9a14eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fbd9a11e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fbd9a1562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f931b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f931b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f931b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f931b71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fbd99aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fbd99aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fbd998f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fbd963ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fbd963eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f931b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f931b71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f931b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fbd963ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c (147 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_ext_v_f16mf4_f16mf2(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.insert.nxv2f16.nxv1f16(<vscale x 2 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.insert.nxv2f16.nxv1f16(<vscale x 2 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_ext_v_f16mf4_f16m1(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv1f16(<vscale x 4 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv1f16(<vscale x 4 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_ext_v_f16mf4_f16m2(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv1f16(<vscale x 8 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv1f16(<vscale x 8 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16mf4_f16m4(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv1f16(<vscale x 16 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv1f16(<vscale x 16 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16mf4_f16m8(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv1f16(<vscale x 32 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv1f16(<vscale x 32 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_ext_v_f16mf2_f16m1(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv2f16(<vscale x 4 x half> poison, <vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv2f16(<vscale x 4 x half>, <vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_ext_v_f16mf2_f16m2(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv2f16(<vscale x 8 x half> poison, <vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv2f16(<vscale x 8 x half>, <vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16mf2_f16m4(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv2f16(<vscale x 16 x half> poison, <vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv2f16(<vscale x 16 x half>, <vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16mf2_f16m8(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv2f16(<vscale x 32 x half> poison, <vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv2f16(<vscale x 32 x half>, <vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_ext_v_f16m1_f16m2(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16m1_f16m4(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16m1_f16m8(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16m2_f16m4(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half> poison, <vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16m2_f16m8(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> poison, <vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind 
# | ...
# `---data was truncated (10240/83080) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056554089beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565540898e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056554089c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f11c5133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f11c518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f11c5133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f11c511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565540831bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565540831a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005655408168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005655404c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005655404c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f11c511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f11c511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f11c511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005655404c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c (148 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfneg_v_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfneg_v_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfneg_v_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1_tum(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store
# | ...
# `---data was truncated (10240/29296) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f0ab84eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559f0ab81e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559f0ab8562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa3b6a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa3b6aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa3b6a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa3b6a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f0ab1abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559f0ab1aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559f0aaff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559f0a7aee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559f0a7aeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa3b6a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa3b6a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa3b6a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f0a7aea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c (149 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssrl_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssrl_vx_u8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssrl_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssrl_vx_u8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssrl_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssrl_vx_u8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssrl_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssrl_vx_u8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssrl_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssrl_vx_u8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; 
# | ...
# `---data was truncated (10240/100289) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ea0aa57eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ea0aa54e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ea0aa5862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f64b4b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f64b4b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f64b4b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f64b4b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ea0a9edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ea0a9eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ea0a9d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ea0a681e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ea0a681b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f64b4b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f64b4b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f64b4b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ea0a681a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-vls-compare-ops.c (150 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-compare-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d  -target-feature +f -target-feature +d -disable-O0-optnone  -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c |  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @eq_i8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %cmp = icmp eq <32 x i8> %0, %1
# |   %sext = sext <32 x i1> %cmp to <32 x i8>
# |   store <32 x i8> %sext, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8>, <32 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @eq_i16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %cmp = icmp eq <16 x i16> %0, %1
# |   %sext = sext <16 x i1> %cmp to <16 x i16>
# |   store <16 x i16> %sext, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16>, <16 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @eq_i32(<vscale x 2 x i32> noundef %a.coerce, <vscale x 2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i32>, align 8
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca <8 x i32>, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %b.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i32>, ptr %b.addr, align 8
# |   %cmp = icmp eq <8 x i32> %0, %1
# |   %sext = sext <8 x i1> %cmp to <8 x i32>
# |   store <8 x i32> %sext, ptr %retval, align 8
# |   %2 = load <8 x i32>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> %2, i64 0)
# |   ret <vscale x 2 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32>, <8 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 1 x i64> @eq_i64(<vscale x 1 x i64> noundef %a.coerce, <vscale x 1 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <4 x i64>, align 8
# |   %a.addr = alloca <4 x i64>, align 8
# |   %b.addr = alloca <4 x i64>, align 8
# |   %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %a.coerce, i64 0)
# |   %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %b.coerce, i64 0)
# |   store <4 x i64> %a, ptr %a.addr, align 8
# |   store <4 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i64>, ptr %a.addr, align 8
# |   %1 = load <4 x i64>, ptr %b.addr, align 8
# |   %cmp = icmp eq <4 x i64> %0, %1
# |   %sext = sext <4 x i1> %cmp to <4 x i64>
# |   store <4 x i64> %sext, ptr %retval, align 8
# |   %2 = load <4 x i64>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64> poison, <4 x i64> %2, i64 0)
# |   ret <vscale x 1 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64>, <4 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @eq_u8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %cmp = icmp eq <32 x i8> %0, %1
# |   %sext = sext <32 x i1> %cmp to <32 x i8>
# |   store <32 x i8> %sext, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @eq_u16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %cmp = icmp eq <16 x i16> %0, %1
# |   %sext = sext <16 x i1> %cmp to <16 x i16>
# |   store <16 x i16> %sext, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @eq_u32(<vscale x 2 x i32> noundef %a.coerce, <vscale x 2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i32>, align 8
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca <8 x i32>, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %b.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i32>, ptr %b.addr, align 8
# |   %cmp = icmp eq <8 x i32> %0, %1
# |   %sext = sext <8 x i1> %cmp to <8 x i32>
# |   store <8 x i32> %sext, ptr %retval, align 8
# |   %2 = load <8 x i32>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> %2, i64 0)
# |   ret <vscale x 2 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 1 x i64> @eq_u64(<vscale x 1 x i64> noundef %a.coerce, <vscale x 1 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <4 x i64>, align 8
# |   %a.addr = alloca <4 x i64>, align 8
# |   %b.addr = alloca <4 x i64>, align 8
# |   %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %a.coerce, i64 0)
# |   %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %b.coerce, i64 0)
# |   store <4 x i64> %a, ptr %a.addr, align 8
# |   store <4 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i64>, ptr %a.addr, align 8
# |   %1 = load <4 x i64>, ptr %b.addr, align 8
# |   %cmp = icmp eq <4 x i64> %0, %1
# |   %sext = sext <4 x i1> %cmp to <4 x i64>
# |   store <4 x i64> %sext, ptr %retval, align 8
# |   %2 = load <4 x i64>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64> poison, <4 x i64> %2, i64 0)
# |   ret <vscale x 1 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @eq_f32(<vscale x 2 x float> noundef %a.coerce, <vscale x 2 x float> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i32>, align 8
# |   %a.addr = alloca <8 x float>, align 8
# |   %b.addr = alloca <8 x float>, align 8
# |   %a = call <8 x float> @llvm.vector.extract.v8f32.nxv2f32(<vscale x 2 x float> %a.coerce, i64 0)
# |   %b = call <8 x float> 
# | ...
# `---data was truncated (10240/63117) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x00005651dbbd4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005651dbbd1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005651dbbd562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f669b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f669b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f669b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f669b831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005651dbb6abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005651dbb6aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005651dbb4f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005651db7fee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005651db7feb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f669b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f669b8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f669b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005651db7fea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/neon-shifts.c (151 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-shifts.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon   -disable-O0-optnone -ffp-contract=fast -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -ffp-contract=fast -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_shift_vshr(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vshr_n = lshr <8 x i8> %1, splat (i8 5)
# |   store <8 x i8> %vshr_n, ptr %ref.tmp, align 8
# |   %2 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %2, ptr %__ret, align 8
# |   %3 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %3, ptr %tmp, align 8
# |   %4 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_shift_vshr_smax(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vshr_n = ashr <8 x i8> %1, splat (i8 7)
# |   store <8 x i8> %vshr_n, ptr %ref.tmp, align 8
# |   %2 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %2, ptr %__ret, align 8
# |   %3 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %3, ptr %tmp, align 8
# |   %4 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_shift_vshr_umax(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   store <8 x i8> zeroinitializer, ptr %ref.tmp, align 8
# |   %2 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %2, ptr %__ret, align 8
# |   %3 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %3, ptr %tmp, align 8
# |   %4 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_shift_vsra(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %vsra_n = lshr <8 x i8> %3, splat (i8 5)
# |   %4 = add <8 x i8> %2, %vsra_n
# |   store <8 x i8> %4, ptr %ref.tmp, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %5, ptr %__ret, align 8
# |   %6 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %6, ptr %tmp, align 8
# |   %7 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_shift_vsra_smax(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %vsra_n = ashr <8 x i8> %3, splat (i8 7)
# |   %4 = add <8 x i8> %2, %vsra_n
# |   store <8 x i8> %4, ptr %ref.tmp, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %5, ptr %__ret, align 8
# |   %6 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %6, ptr %tmp, align 8
# |   %7 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_shift_vsra_umax(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %4 = add <8 x i8> %2, zeroinitializer
# |   store <8 x i8> %4, ptr %ref.tmp, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %5, ptr %__ret, align 8
# |   %6 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %6, ptr %tmp, align 8
# |   %7 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %7
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055813f9fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055813f9f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055813f9fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fea66333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fea6638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fea66333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fea6631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055813f992bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055813f992a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055813f9778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055813f626e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055813f626b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fea6631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fea6631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fea6631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055813f626a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c (152 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560316089eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560316086e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056031608a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f094ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f094ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f094ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f094ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056031601fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056031601fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005603160048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560315cb3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560315cb3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f094ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f094ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f094ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560315cb3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c (153 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_f16mf4x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_f16mf2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_f16m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_f16m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_i16mf4x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_i16mf2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_i16m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_i16m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_u16mf4x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_u16mf2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_u16m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_u16m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_f16mf4x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = allo
# | ...
# `---data was truncated (10240/23031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005603cb68deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005603cb68ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005603cb68e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3beab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3beab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3beab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3beab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005603cb623bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005603cb623a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005603cb6088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005603cb2b7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005603cb2b7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3beab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3beab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3beab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005603cb2b7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c (154 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsub_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsub_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsub_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsub_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsub_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsub_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsub_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsub_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsub_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/424843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055da86be9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055da86be6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055da86bea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7165133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f716518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7165133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f716511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da86b7fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055da86b7fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055da86b648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055da86813e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055da86813b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f716511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f716511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f716511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da86813a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c (155 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vzip_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vzip_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vzip_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vzip_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vzip_vv_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vzip_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vzip_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vzip_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwi
# | ...
# `---data was truncated (10240/235604) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c6edddceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c6eddd9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c6edddd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7d47533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7d4758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7d47533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7d4751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c6edd72bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c6edd72a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c6edd578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c6eda06e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c6eda06b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7d4751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7d4751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7d4751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c6eda06a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c (156 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dots_vv_i32mf2(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dots_vv_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dots_vv_i32m2(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dots_vv_i32m4(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dots_vv_i32m8(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dots_vv_i64m1(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dots_vv_i64m2(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dots_vv_i64m4(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i6
# | ...
# `---data was truncated (10240/25511) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005633eb6d3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005633eb6d0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005633eb6d462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb06e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb06e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb06e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb06e631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005633eb669bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005633eb669a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005633eb64e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005633eb2fde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005633eb2fdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb06e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb06e6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb06e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005633eb2fda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c (157 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svbfmlalb_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalb(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlalb(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlalb_lane_0_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalb.lane.v2(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 0)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlalb.lane.v2(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlalb_lane_7_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalb.lane.v2(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 7)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlalb_n_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, bfloat noundef %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca bfloat, align 2
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store bfloat %z, ptr %z.addr, align 2
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load bfloat, ptr %z.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalb(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055debd6d3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055debd6d0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055debd6d462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f498ce1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f498ce725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f498ce1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f498ce03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055debd669bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055debd669a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055debd64e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055debd2fde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055debd2fdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f498ce04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f498ce050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f498ce050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055debd2fda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c (158 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005634a05e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005634a05e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005634a05e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5f67649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5f676a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5f67649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5f67631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005634a057abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005634a057aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005634a055f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005634a020ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005634a020eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5f67632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5f676330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5f676330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005634a020ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c (159 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_f64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_i64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_u64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c923f33eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c923f30e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c923f3462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5e79333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5e7938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5e79333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5e7931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c923ec9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c923ec9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c923eae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c923b5de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c923b5db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5e7931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5e7931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5e7931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c923b5da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c (160 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_s32(<vscale x 4 x i32> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sdot.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdot_s64(<vscale x 2 x i64> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.sdot.nxv2i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sdot.nxv2i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_u32(<vscale x 4 x i32> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.udot.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.udot.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdot_u64(<vscale x 2 x i64> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.udot.nxv2i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.udot.nxv2i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_n_s32(<vscale x 4 x i32> %op1, <vscale x 16 x i8> %op2, i8 noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca i8, align 1
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store i8 %op3, ptr %op3.addr, align 1
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load i8, ptr %op3.addr, align 1
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %2, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdot_n_s64(<vscale x 2 x i64> %op1, <vscale x 8 x i16> %op2, i16 noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca i16, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store i16 %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load i16, ptr %op3.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.sdot.nxv2i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_n_u32(<vscale x 4 x i32> %op1, <vscale x 16 x i8> %op2, i8 noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca i8, align 1
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store i8 %op3, ptr %op3.addr, align 1
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load i8, ptr %op3.addr, align 1
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %2, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.udot.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdot_n_u64(<vscale x 2 x i64> %op1, <vscale x 8 x i16> %op2, i16 noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca i16, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store i16 %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load i16, ptr %op3.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.udot.nxv2i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_lane_s32(<vscale x 4 x i32> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 0)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sdot.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_lane_s32_1(<vscale x 4 x i32> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 =
# | ...
# `---data was truncated (10240/15126) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055f899cbfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f899cbce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f899cc062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f76fa249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f76fa2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f76fa249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f76fa231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f899c55bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f899c55a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f899c3a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f8998e9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f8998e9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f76fa232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f76fa2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f76fa2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f8998e9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c (161 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssrl_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssrl_vx_u8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssrl_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssrl_vx_u8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssrl_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssrl_vx_u8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssrl_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssrl_vx_u8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssrl_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssrl_vx_u8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function
# | ...
# `---data was truncated (10240/100281) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005571fcc8feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005571fcc8ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005571fcc9062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb6a5e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb6a5ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb6a5e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb6a5e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005571fcc25bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005571fcc25a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005571fcc0a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005571fc8b9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005571fc8b9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb6a5e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb6a5e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb6a5e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005571fc8b9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c (162 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasubu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasubu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasubu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasubu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasubu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasubu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasubu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasubu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasubu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# | 
# | ...
# `---data was truncated (10240/225655) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee46c2feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ee46c2ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ee46c3062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9fc6933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9fc698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9fc6933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9fc691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee46bc5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ee46bc5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ee46baa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ee46859e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ee46859b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9fc691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9fc691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9fc691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee46859a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c (163 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincb_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincb.n32(i32 %0, i32 31, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqincb.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincb_n_s32_1(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincb.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincb_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqincb.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqincb.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincb_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqincb.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqincb.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincb_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqincb.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uqincb.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincb_pat_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincb.n32(i32 %0, i32 5, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincb_pat_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqincb.n64(i64 %0, i32 6, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincb_pat_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqincb.n32(i32 %0, i32 7, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincb_pat_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqincb.n64(i64 %0, i32 8, i32 1)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000559006c58eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559006c55e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559006c5962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd711733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd71178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd711733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd71171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559006beebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559006beea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559006bd38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559006882e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559006882b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd71171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd71171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd71171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559006882a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c (164 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_f32mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_f32m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_f32m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_i32mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_i32m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_i32m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_u32mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_u32m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_u32m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_f32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg
# | ...
# `---data was truncated (10240/20483) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c1da379eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c1da376e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c1da37a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe37d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe37d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe37d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe37d831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c1da30fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c1da30fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c1da2f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c1d9fa3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c1d9fa3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe37d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe37d8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe37d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c1d9fa3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c (165 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextw_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextw_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextw_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextw_u64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextw_s64_x(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextw_u64_x(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005605f5204eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005605f5201e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005605f520562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f97b9849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f97b98a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f97b9849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f97b9831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005605f519abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005605f519aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005605f517f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005605f4e2ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005605f4e2eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f97b9832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f97b98330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f97b98330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005605f4e2ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c (166 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svld4_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld4.sret.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld4.sret.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svld4_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld4.sret.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld4.sret.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svld4_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld4.sret.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld4.sret.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svld4_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld4.sret.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld4.sret.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svld4_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld4.sret.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svld4_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld4.sret.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svld4_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld4.sret.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svld4_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld4.sret.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svld4_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld4.sret.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld4.sret.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svld4_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.fr
# | ...
# `---data was truncated (10240/27970) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560963212eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056096320fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056096321362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f74dc133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f74dc18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f74dc133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f74dc11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005609631a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005609631a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056096318d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560962e3ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560962e3cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f74dc11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f74dc11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f74dc11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560962e3ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c (167 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmv_v_f_f16mf4_tu(<vscale x 1 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmv_v_f_f16mf2_tu(<vscale x 2 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmv_v_f_f16m1_tu(<vscale x 4 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmv_v_f_f16m2_tu(<vscale x 8 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmv_v_f_f16m4_tu(<vscale x 16 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfmv_v_f_f16m8_tu(<vscale x 32 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16.i64(<vscale x 32 x half> %0, half %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16.i64(<vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfmv_v_f_f32mf2_tu(<vscale x 1 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load float, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.i64(<vscale x 1 x float> %0, float %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.i64(<vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfmv_v_f_f32m1_tu(<vscale x 2 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load float, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.i64(<vscale x 2 x float> %0, float %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.i64(<vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfmv_v_f_f32m2_tu(<vscale x 4 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load float, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32.i64(<vscale x 4 x float> %0, float %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32.i64(<vscale x 4 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfmv_v_f_f32m4_tu(<vscale x 8 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load float, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32.i64(<vscale x 8 x float> %0, float %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32.i64(<vscale x 8 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfmv_v_f_f32m8_tu(<vscale x 16 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x flo
# | ...
# `---data was truncated (10240/29327) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b9a7eb3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b9a7eb0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b9a7eb462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f80b5705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f80b575c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f80b5705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f80b56ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b9a7e49bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b9a7e49a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b9a7e2e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b9a7adde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b9a7addb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f80b56eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f80b56ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f80b56ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b9a7adda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c (168 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadd_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadd_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadd_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadd_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadd_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadd_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadd_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadd_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vadd_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/424835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056092a12deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056092a12ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056092a12e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe90af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe90af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe90af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe90af1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056092a0c3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056092a0c3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056092a0a88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560929d57e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560929d57b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe90af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe90af1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe90af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560929d57a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c (169 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincw_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincw.n32(i32 %0, i32 31, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqincw.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincw_n_s32_1(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincw.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincw_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqincw.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqincw.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincw_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqincw.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqincw.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincw_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqincw.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uqincw.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincw_pat_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincw.n32(i32 %0, i32 4, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincw_pat_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqincw.n64(i64 %0, i32 5, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincw_pat_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqincw.n32(i32 %0, i32 6, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincw_pat_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqincw.n64(i64 %0, i32 7, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqincw_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.sqincw.nxv4i32(<vscale x 4 x i32> %0, i32 31, i32 16)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sqincw.nxv4i32(<vscale x 4 x i32>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqincw_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.uqincw.nxv4i32(<vscale x 4 x i32> %0, i32 31, i32 1)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uqincw.nxv4i32(<vscale x 4 x i32>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqincw_pat_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.sqincw.nxv4i32(<vscale x 4 x i32> %0, i32 8, i32 16)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqincw_pat_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.uqincw.nxv4i32(<vscale x 4 x i32> %0, i32 9, i32 1)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d92df2eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d92df2be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d92df2f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4aef505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4aef55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4aef505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4aef4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d92dec4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d92dec4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d92dea98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d92db58e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d92db58b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4aef4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4aef4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4aef4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d92db58a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c (170 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzpq2_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzpq2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uzpq2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzpq2_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzpq2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uzpq2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzpq2_u32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzpq2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uzpq2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzpq2_u64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzpq2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uzpq2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzpq2_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzpq2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzpq2_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzpq2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzpq2_s32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzpq2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzpq2_s64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzpq2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svuzpq2_f16(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.uzpq2.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.uzpq2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svuzpq2_f32(<vscale x 4 x float> %zn, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x float>, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.uzpq2.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.uzpq2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svuzpq2_f64(<vscale x 2 x double> %zn, <vscale x 2 x double> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x double>, align 16
# |   %zm.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x double> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.uzpq2.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.uzpq2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svuzpq2_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.uzpq2.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.uzpq2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzpq2_mf8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzpq2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %
# | ...
# `---data was truncated (10240/10910) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055c94ef3eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c94ef3be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c94ef3f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd7e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd7e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd7e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd7e31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c94eed4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c94eed4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c94eeb98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c94eb68e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c94eb68b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdd7e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd7e31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd7e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c94eb68a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c (171 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sh_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sh_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sh_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sh_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sh_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sh_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sh_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sh_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sh_gather_u32base_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1, i64 0)
# |   %4 = sext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sh_gather_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = sext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sh_gather_u32base_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.a
# | ...
# `---data was truncated (10240/36974) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x00005574c86b6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005574c86b3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005574c86b762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f6f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f6f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f6f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f6f31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005574c864cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005574c864ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005574c86318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005574c82e0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005574c82e0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2f6f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f6f31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f6f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005574c82e0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c (172 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_vv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_wv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_wx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_vv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_wv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_wx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsub_vv_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale
# | ...
# `---data was truncated (10240/306025) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f1153bdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f1153bae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f1153be62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f422d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f422d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f422d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f422d631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f115353bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f115353a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f1153388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f114fe7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f114fe7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f422d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f422d6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f422d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f114fe7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c (173 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svscale_single_f16_x2(<vscale x 8 x half> %op1.coerce0, <vscale x 8 x half> %op1.coerce1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %op1.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %op1.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %op1, align 16
# |   %op11 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %op1, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %op1.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %6 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.fp8.scale.single.x2.nxv8f16(<vscale x 8 x half> %3, <vscale x 8 x half> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.fp8.scale.single.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svscale_single_f32_x2(<vscale x 4 x float> %op1.coerce0, <vscale x 4 x float> %op1.coerce1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %op1.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %op1.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %op1, align 16
# |   %op11 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %op1, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %op1.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %6 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.fp8.scale.single.x2.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4, <vscale x 4 x i32> %5)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.fp8.scale.single.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double> } @test_svscale_single_f64_x2(<vscale x 2 x double> %op1.coerce0, <vscale x 2 x double> %op1.coerce1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %op1.addr = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } poison, <vscale x 2 x double> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } %0, <vscale x 2 x double> %op1.coerce1, 1
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %1, ptr %op1, align 16
# |   %op11 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %op1, align 16
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %2 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %op1.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %2, 0
# |   %4 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %2, 1
# |   %5 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %6 = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sme.fp8.scale.single.x2.nxv2f64(<vscale x 2 x double> %3, <vscale x 2 x double> %4, <vscale x 2 x i64> %5)
# |   ret { <vscale x 2 x double>, <vscale x 2 x double> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sme.fp8.scale.single.x2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svscale_single_f16_x4(<vscale x 8 x half> %op1.coerce0, <vscale x 8 x half> %op1.coerce1, <vscale x 8 x half> %op1.coerce2, <vscale x 8 x half> %op1.coerce3, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %op1.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %op1.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %1, <vscale x 8 x half> %op1.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %op1.coerce3, 3
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %op1, align 16
# |   %op11 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %op1, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %4 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %op1.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, 1
# |   %7 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, 2
# |   %8 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, 3
# |   %9 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %10 = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.fp8.scale.single.x4.nxv8f16(<vscale x 8 x half> %5, <vscale x 8 x half> %6, <vscale x 8 x half> %7, <vscale x 8 x half> %8, <vscale x 8 x i16> %9)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.fp8.scale.single.x4.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svscale_single_f32_x4(<vscale x 4 x float> %op1.coerce0, <vscale x 4 x float> %op1.coerce1, <vscale x 4 x float> %op1.coerce2, <vscale x 4 x float> %op1.coerce3, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %op1.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %op1.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, <vscale x 4 x float> %op1.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %op1.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %op1, align 16
# |   %op11 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %op1, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %op11, ptr 
# | ...
# `---data was truncated (10240/37349) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055daab06ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055daab069e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055daab06d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd2a2449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd2a24a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd2a2449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd2a2431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055daab002bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055daab002a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055daaafe78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055daaac96e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055daaac96b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd2a2432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd2a24330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd2a24330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055daaac96a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c (174 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtbxq_u8(<vscale x 16 x i8> %passthru, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 16 x i8>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.tbxq.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.tbxq.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtbxq_u16(<vscale x 8 x i16> %passthru, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 8 x i16>, align 16
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.tbxq.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.tbxq.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtbxq_u32(<vscale x 4 x i32> %passthru, <vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 4 x i32>, align 16
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.tbxq.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.tbxq.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtbxq_u64(<vscale x 2 x i64> %passthru, <vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 2 x i64>, align 16
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.tbxq.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.tbxq.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtbxq_s8(<vscale x 16 x i8> %passthru, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 16 x i8>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.tbxq.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtbxq_s16(<vscale x 8 x i16> %passthru, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 8 x i16>, align 16
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.tbxq.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtbxq_s32(<vscale x 4 x i32> %passthru, <vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 4 x i32>, align 16
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.tbxq.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtbxq_s64(<vscale x 2 x i64> %passthru, <vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 2 x i64>, align 16
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.tbxq.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtbxq_f16(<vscale x 8 x half> %passthru, <vscale x 8 x half> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x half> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.tbxq.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.tbxq.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtbxq_f32(<vscale x 4 x float> %passthru, <vscale x 4 x float> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 4 x float>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x float> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 4 x float> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.tbxq.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.
# | ...
# `---data was truncated (10240/14102) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055b79554deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b79554ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b79554e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc37a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc37a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc37a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc37a91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b7954e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b7954e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b7954c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b795177e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b795177b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc37a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc37a91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc37a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b795177a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c (175 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vf_f32mf2_tu(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vf_f32m1_tu(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vf_f32m2_tu(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vf_f32m4_tu(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(<vscale 
# | ...
# `---data was truncated (10240/179177) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005624bcf5aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005624bcf57e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005624bcf5b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1087d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1087d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1087d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1087d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005624bcef0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005624bcef0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005624bced58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005624bcb84e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005624bcb84b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1087d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1087d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1087d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005624bcb84a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c (176 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svget4_b_0(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1, <vscale x 16 x i1> %tuple.coerce2, <vscale x 16 x i1> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %1, <vscale x 16 x i1> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %tuple.coerce3, 3
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %3, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   %4 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %5 = extractvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %4, 0
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svget4_b_1(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1, <vscale x 16 x i1> %tuple.coerce2, <vscale x 16 x i1> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %1, <vscale x 16 x i1> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %tuple.coerce3, 3
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %3, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   %4 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %5 = extractvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %4, 1
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svget4_b_3(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1, <vscale x 16 x i1> %tuple.coerce2, <vscale x 16 x i1> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %1, <vscale x 16 x i1> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %tuple.coerce3, 3
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %3, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   %4 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %5 = extractvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %4, 3
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000561e6514beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561e65148e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561e6514c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6224333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f622438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6224333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f622431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561e650e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561e650e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561e650c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561e64d75e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561e64d75b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f622431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f622431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f622431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561e64d75a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c (177 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzipq1_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zipq1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.zipq1.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzipq1_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zipq1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.zipq1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzipq1_u32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zipq1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.zipq1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzipq1_u64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zipq1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.zipq1.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzipq1_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zipq1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzipq1_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zipq1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzipq1_s32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zipq1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzipq1_s64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zipq1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svzipq1_f16(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.zipq1.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.zipq1.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svzipq1_f32(<vscale x 4 x float> %zn, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x float>, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.zipq1.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.zipq1.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svzipq1_f64(<vscale x 2 x double> %zn, <vscale x 2 x double> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x double>, align 16
# |   %zm.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x double> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.zipq1.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.zipq1.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svzipq1_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.zipq1.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.zipq1.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzipq1_mf8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zipq1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %
# | ...
# `---data was truncated (10240/10910) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055789eba9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055789eba6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055789ebaa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f442b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f442b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f442b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f442b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055789eb3fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055789eb3fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055789eb248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055789e7d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055789e7d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f442b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f442b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f442b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055789e7d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c (178 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svsel_s8_x2(target("aarch64.svcount") %pn, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pn.addr = alloca target("aarch64.svcount"), align 2
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store target("aarch64.svcount") %pn, ptr %pn.addr, align 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   %4 = load target("aarch64.svcount"), ptr %pn.addr, align 2
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %8, 0
# |   %10 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %8, 1
# |   %11 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sel.x2.nxv16i8(target("aarch64.svcount") %4, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sel.x2.nxv16i8(target("aarch64.svcount"), <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svsel_u8_x2(target("aarch64.svcount") %pn, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pn.addr = alloca target("aarch64.svcount"), align 2
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store target("aarch64.svcount") %pn, ptr %pn.addr, align 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   %4 = load target("aarch64.svcount"), ptr %pn.addr, align 2
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %8, 0
# |   %10 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %8, 1
# |   %11 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sel.x2.nxv16i8(target("aarch64.svcount") %4, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %11
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svsel_mf8_x2(target("aarch64.svcount") %pn, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pn.addr = alloca target("aarch64.svcount"), align 2
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store target("aarch64.svcount") %pn, ptr %pn.addr, align 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   %4 = load target("aarch64.svcount"), ptr %pn.addr, align 2
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %8, 0
# |   %10 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %8, 1
# |   %11 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sel.x2.nxv16i8(target("aarch64.svcount") %4, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %11
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svsel_s16_x2(target("aarch64.svcount") %pn, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %pn.addr = alloca target("aarch64.svcount"), align 2
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zm.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm, align 16
# |   store target("aarch64.svcount") %pn, ptr %pn.addr, align 2
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zm2, ptr %zm.addr, align 16
# |   %4 = load target("aarch64.svcount"), ptr %pn.addr, align 2
# |   %5 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 1
# |   %8 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 1
# |   %11 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sel.x2.nxv8i16(target("aarch64.svcount") %4, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %9, <vscale x 8 x i16> %10)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sel.x2.nxv8i16(target("aarch64.svcount"), <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale 
# | ...
# `---data was truncated (10240/33971) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x00005567a0b81eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005567a0b7ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005567a0b8262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5e8c105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5e8c15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5e8c105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5e8c0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005567a0b17bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005567a0b17a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005567a0afc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005567a07abe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005567a07abb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5e8c0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5e8c0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5e8c0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005567a07aba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-vls-bitwise-ops.c (179 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-bitwise-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d  -target-feature +f -target-feature +d -disable-O0-optnone  -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c |  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @and_i8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %and = and <32 x i8> %0, %1
# |   store <32 x i8> %and, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8>, <32 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @and_i16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %and = and <16 x i16> %0, %1
# |   store <16 x i16> %and, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16>, <16 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @and_i32(<vscale x 2 x i32> noundef %a.coerce, <vscale x 2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i32>, align 8
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca <8 x i32>, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %b.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i32>, ptr %b.addr, align 8
# |   %and = and <8 x i32> %0, %1
# |   store <8 x i32> %and, ptr %retval, align 8
# |   %2 = load <8 x i32>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> %2, i64 0)
# |   ret <vscale x 2 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32>, <8 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 1 x i64> @and_i64(<vscale x 1 x i64> noundef %a.coerce, <vscale x 1 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <4 x i64>, align 8
# |   %a.addr = alloca <4 x i64>, align 8
# |   %b.addr = alloca <4 x i64>, align 8
# |   %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %a.coerce, i64 0)
# |   %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %b.coerce, i64 0)
# |   store <4 x i64> %a, ptr %a.addr, align 8
# |   store <4 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i64>, ptr %a.addr, align 8
# |   %1 = load <4 x i64>, ptr %b.addr, align 8
# |   %and = and <4 x i64> %0, %1
# |   store <4 x i64> %and, ptr %retval, align 8
# |   %2 = load <4 x i64>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64> poison, <4 x i64> %2, i64 0)
# |   ret <vscale x 1 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64>, <4 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @and_u8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %and = and <32 x i8> %0, %1
# |   store <32 x i8> %and, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @and_u16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %and = and <16 x i16> %0, %1
# |   store <16 x i16> %and, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @and_u32(<vscale x 2 x i32> noundef %a.coerce, <vscale x 2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i32>, align 8
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca <8 x i32>, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %b.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i32>, ptr %b.addr, align 8
# |   %and = and <8 x i32> %0, %1
# |   store <8 x i32> %and, ptr %retval, align 8
# |   %2 = load <8 x i32>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> %2, i64 0)
# |   ret <vscale x 2 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 1 x i64> @and_u64(<vscale x 1 x i64> noundef %a.coerce, <vscale x 1 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <4 x i64>, align 8
# |   %a.addr = alloca <4 x i64>, align 8
# |   %b.addr = alloca <4 x i64>, align 8
# |   %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %a.coerce, i64 0)
# |   %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %b.coerce, i64 0)
# |   store <4 x i64> %a, ptr %a.addr, align 8
# |   store <4 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i64>, ptr %a.addr, align 8
# |   %1 = load <4 x i64>, ptr %b.addr, align 8
# |   %and = and <4 x i64> %0, %1
# |   store <4 x i64> %and, ptr %retval, align 8
# |   %2 = load <4 x i64>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64> poison, <4 x i64> %2, i64 0)
# |   ret <vscale x 1 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @or_i8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %or = or <32 x i8> %0, %1
# |   store <32 x i8> %or, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 
# | ...
# `---data was truncated (10240/30877) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000056074d196eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056074d193e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056074d19762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7bd1133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7bd118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7bd1133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7bd111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056074d12cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056074d12ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056074d1118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056074cdc0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056074cdc0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7bd111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7bd111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7bd111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056074cdc0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c (180 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561ac4ba8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561ac4ba5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561ac4ba962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f50c4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f50c438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f50c4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f50c431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561ac4b3ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561ac4b3ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561ac4b238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561ac47d2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561ac47d2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f50c431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f50c431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f50c431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561ac47d2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/thinlto-funcattr-prop.ll (181 of 27911)
******************** TEST 'Clang :: CodeGen/thinlto-funcattr-prop.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 5
split-file /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-funcattr-prop.ll /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp
# executed command: split-file /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-funcattr-prop.ll /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp
# RUN: at line 6
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.bc
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.bc
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.bc
# |  #0 0x000055a60117feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a60117ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a60118062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e30049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e300a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e30049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e30031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a601115bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a601115a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a6010fa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a600da9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a600da9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6e30032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e300330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e300330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a600da9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing: 
FAIL: Clang :: CodeGen/arm_neon_intrinsics.c (182 of 27911)
******************** TEST 'Clang :: CodeGen/arm_neon_intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7s-apple-darwin -target-abi apcs-gnu  -target-cpu swift   -target-feature +fullfp16 -ffreestanding   -flax-vector-conversions=none   -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c   | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7s-apple-darwin -target-abi apcs-gnu -target-cpu swift -target-feature +fullfp16 -ffreestanding -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c"
# | target datalayout = "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
# | target triple = "thumbv7s-apple-darwin"
# | 
# | %struct.uint8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.uint16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.uint32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.int8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.int16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.int32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.float16x8x2_t = type { [2 x <8 x half>] }
# | %struct.float32x4x2_t = type { [2 x <4 x float>] }
# | %struct.poly8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.poly16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.uint8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.uint16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.uint32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.uint64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.int8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.int16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.int32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.int64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.float16x4x2_t = type { [2 x <4 x half>] }
# | %struct.float32x2x2_t = type { [2 x <2 x float>] }
# | %struct.poly8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.poly16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.uint8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.uint16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.uint32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.int8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.int16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.int32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.float16x8x3_t = type { [3 x <8 x half>] }
# | %struct.float32x4x3_t = type { [3 x <4 x float>] }
# | %struct.poly8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.poly16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.uint8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.uint16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.uint32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.uint64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.int8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.int16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.int32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.int64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.float16x4x3_t = type { [3 x <4 x half>] }
# | %struct.float32x2x3_t = type { [3 x <2 x float>] }
# | %struct.poly8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.poly16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.uint8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.uint16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.uint32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.int8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.int16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.int32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.float16x8x4_t = type { [4 x <8 x half>] }
# | %struct.float32x4x4_t = type { [4 x <4 x float>] }
# | %struct.poly8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.poly16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.uint8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.uint16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.uint32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.uint64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.int8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.int16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.int32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.int64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.float16x4x4_t = type { [4 x <4 x half>] }
# | %struct.float32x2x4_t = type { [4 x <2 x float>] }
# | %struct.poly8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.poly16x4x4_t = type { [4 x <4 x i16>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @test_vaba_s8(<8 x i8> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <8 x i8>, align 8
# |   %__p1.addr.i2 = alloca <8 x i8>, align 8
# |   %__ret.i3 = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   store <8 x i8> %4, ptr %__p0.addr.i1, align 8
# |   store <8 x i8> %5, ptr %__p1.addr.i2, align 8
# |   %6 = load <8 x i8>, ptr %__p0.addr.i1, align 8
# |   %7 = load <8 x i8>, ptr %__p1.addr.i2, align 8
# |   %vabd_v.i = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %6, <8 x i8> %7)
# |   store <8 x i8> %vabd_v.i, ptr %ref.tmp.i, align 8
# |   %8 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %8, ptr %__ret.i3, align 8
# |   %9 = load <8 x i8>, ptr %__ret.i3, align 8
# |   %add.i = add <8 x i8> %3, %9
# |   store <8 x i8> %add.i, ptr %__ret.i, align 8
# |   %10 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x i16> @test_vaba_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <4 x i16>, align 8
# |   %__p1.addr.i2 = alloca <4 x i16>, align 8
# |   %__ret.i3 = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__p2.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   %c.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   store <4 x i16> %c, ptr %c.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   %2 = load <4 x i16>, ptr %c.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   store <4 x i16> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %4 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %5 = load <4 x i16>, ptr %__p2.addr.i, align 8
# |   store <4 x i16> %4, ptr %__p0.addr.i1, align 8
# |   store <4 x i16> %5, ptr %__p1.addr.i2, align 8
# |   %6 = load <8 x i8>, ptr %__p0.addr.i1, align 8
# |   %7 = load <8 x i8>, ptr %__p1.addr.i2, align 8
# |   %vabd_v.i = bitcast <8 x i8> %6 to <4 x i16>
# |   %vabd_v1.i = bitcast <8 x i8> %7 to <4 x i16>
# |   %vabd_v2.i = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %vabd_v.i, <4 x i16> %vabd_v1.i)
# |   %vabd_v3.i = bitcast <4 x i16> %vabd_v2.i to <8 x i8>
# |   store <8 x i8> %vabd_v3.i, ptr %ref.tmp.i, align 8
# |   %8 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %8, ptr %__ret.i3, align 8
# |   %9 = load <4 x i16>, ptr %__ret.i3, align 8
# |   %add.i = add <4 x i16> %3, %9
# |   store <4 x i16> %add.i, ptr %__ret.i, align 8
# |   %10 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <2 x i32> @test_vaba_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <2 x i32> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <2 x i32>, align 8
# |   %__p1.addr.i2 = alloca <2 x i32>, align 8
# |   %__ret.i3 = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__p2.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   %c.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   store <2 x i32> %c, ptr %c.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   %2 = load <2 x i32>, ptr %c.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   store <2 x i32> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %4 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %5 = load <2 x i32>, ptr %__p2.addr.i, align 8
# |   store <2 x i32> %4, ptr %__p0.addr.i1, align 8
# |   store <2 x i32> %5, ptr %__p1.addr.i2, align 8
# |   %6 = load <8 x i8>, ptr %__p0.addr.i1, align 8
# |   %7 = load <8 x i8>, ptr %__p1.addr.i2, align 8
# |   %vabd_v.i = bitcast <8 x i8> %6 to <2 x i32>
# |   %vabd_v1.i = bitcast <8 x i8> %7 to <2 x i32>
# |   %vabd_v2.i = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %vabd_v.i, <2 x i32> %vabd_v1.i)
# |   %vabd_v3.i = bitcast <2 x i32> %vabd_v2.i to <8 x i8>
# |   store <8 x i8> %vabd_v3.i, ptr %ref.tmp.i, align 8
# |   %8 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %8, ptr %__ret.i3, align 8
# |   %9 = load <2 x i32>, ptr %__ret.i3, align 8
# |   %add.i = add <2 x i32> %3, %9
# |   store <2 x i32> %add.i, ptr %__ret.i, align 8
# |   %10 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @test_vaba_u8(<8 x i8> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <8 x i8>, align 8
# |   %__p1.addr.i2 = alloca <8 x i8>, align 8
# |   %__ret.i3 = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   store <8 x i8> %4, pt
# | ...
# `---data was truncated (10240/2159854) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005576b6e3beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005576b6e38e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005576b6e3c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7f50d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7f50d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7f50d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7f50d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005576b6dd1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005576b6dd1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005576b6db68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005576b6a65e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005576b6a65b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7f50d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7f50d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7f50d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005576b6a65a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c (183 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8ff_v_i8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8ff_v_i8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8ff_v_i8m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_u8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8ff_v_u8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8ff
# | ...
# `---data was truncated (10240/54702) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555d88f5beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555d88f58e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555d88f5c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c26333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c2638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c26333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c2631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555d88ef1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555d88ef1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555d88ed68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555d88b85e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555d88b85b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8c2631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c2631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c2631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555d88b85a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c (184 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsleu_vv_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsleu_vx_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsleu_vv_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsleu_vx_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsleu_vv_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsleu_vx_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsleu_vv_u8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vsca
# | ...
# `---data was truncated (10240/63705) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005648438dbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005648438d8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005648438dc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff40c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff40c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff40c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff40c91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564843871bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564843871a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005648438568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564843505e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564843505b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff40c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff40c91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff40c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564843505a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c (185 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_f32m2x4_tu(target("riscv.vector.tuple", <vs
# | ...
# `---data was truncated (10240/227771) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005629695ebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005629695e8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005629695ec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f84c0f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f84c0f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f84c0f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f84c0f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562969581bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562969581a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005629695668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562969215e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562969215b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f84c0f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f84c0f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f84c0f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562969215a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c (186 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgather_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgather_vx_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgather_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgather_vx_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgather_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgather_vx_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgather_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgather_vx_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgather_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x i16> %vs1, 
# | ...
# `---data was truncated (10240/62087) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560c5d0c5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560c5d0c2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560c5d0c662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7a1661bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7a166725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7a1661ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7a16603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c5d05bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560c5d05ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560c5d0408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560c5ccefe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560c5ccefb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7a16604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7a166050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7a166050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c5ccefa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c (187 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svluti4_lane_zt_u16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8i16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svluti4_lane_zt_f16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8f16(i32 0, <vscale x 16 x i8> %0, i32 1)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8f16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svluti4_lane_zt_bf16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8bf16(i32 0, <vscale x 16 x i8> %0, i32 1)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8bf16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svluti4_lane_zt_s16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svluti4_lane_zt_u32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4i32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svluti4_lane_zt_s32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svluti4_lane_zt_f32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4f32(i32 0, <vscale x 16 x i8> %0, i32 1)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4f32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000557fa8dfeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557fa8dfbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557fa8dff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4a63733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4a6378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4a63733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4a6371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557fa8d94bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557fa8d94a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557fa8d798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557fa8a28e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557fa8a28b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4a6371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4a6371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4a6371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557fa8a28a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c (188 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uh_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uh_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uh_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uh_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uh_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uh_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uh_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uh_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uh_gather_u32base_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1, i64 0)
# |   %4 = zext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uh_gather_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = zext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uh_gather_u32base_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.a
# | ...
# `---data was truncated (10240/36974) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055b1060edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b1060eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b1060ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f29e961bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f29e96725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f29e961ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f29e9603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b106083bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b106083a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b1060688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b105d17e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b105d17b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f29e9604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f29e96050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f29e96050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b105d17a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c (189 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.
# | ...
# `---data was truncated (10240/18498) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559fde654eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559fde651e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559fde65562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9d3cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9d3cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9d3cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9d3cc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559fde5eabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559fde5eaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559fde5cf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559fde27ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559fde27eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9d3cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9d3cc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9d3cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559fde27ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c (190 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d     -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vpairo_vv_f16mf4(<vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vpairo.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vpairo.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vpairo_vv_f16mf2(<vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vpairo.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vpairo.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vpairo_vv_f16m1(<vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vpairo.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vpairo.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vpairo_vv_f16m2(<vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vpairo.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vpairo.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vpairo_vv_f16m4(<vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vpairo.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vpairo.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vpairo_vv_f16m8(<vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vpairo.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vpairo.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vpairo_vv_f32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vpairo.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vpairo.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vpairo_vv_f32m1(<vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vpairo.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vpairo.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vpairo_vv_f32m2(<vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vpairo.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vpairo.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vpairo_vv_f32m4(<vscale x 8 x float> %vs2, <vscale x 8 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 =
# | ...
# `---data was truncated (10240/125488) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056063b330eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056063b32de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056063b33162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4825d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4825d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4825d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4825d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056063b2c6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056063b2c6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056063b2ab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056063af5ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056063af5ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4825d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4825d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4825d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056063af5aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c (191 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_4x8x4_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_4x8x4_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_4x8x4_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_4x8x4_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563e0912deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563e0912ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563e0912e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc073c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc073ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc073c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc073c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e090c3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563e090c3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563e090a88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563e08d57e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563e08d57b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc073c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc073c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc073c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e08d57a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/X86/avx-shuffle-builtins.c (192 of 27911)
******************** TEST 'Clang :: CodeGen/X86/avx-shuffle-builtins.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c -triple=x86_64-- -target-feature +avx -disable-O0-optnone -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c -triple=x86_64-- -target-feature +avx -disable-O0-optnone -emit-llvm -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-unknown"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x float> @x(<8 x float> noundef %a, <8 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x float>, align 32
# |   %b.addr = alloca <8 x float>, align 32
# |   store <8 x float> %a, ptr %a.addr, align 32
# |   store <8 x float> %b, ptr %b.addr, align 32
# |   %0 = load <8 x float>, ptr %a.addr, align 32
# |   %1 = load <8 x float>, ptr %b.addr, align 32
# |   %shufp = shufflevector <8 x float> %0, <8 x float> %1, <8 x i32> <i32 3, i32 2, i32 8, i32 11, i32 7, i32 6, i32 12, i32 15>
# |   ret <8 x float> %shufp
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_mm_permute_pd(<2 x double> noundef %a) #1 {
# | entry:
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   %permil = shufflevector <2 x double> %0, <2 x double> poison, <2 x i32> <i32 1, i32 0>
# |   ret <2 x double> %permil
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x double> @test_mm256_permute_pd(<4 x double> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x double>, align 32
# |   store <4 x double> %a, ptr %a.addr, align 32
# |   %0 = load <4 x double>, ptr %a.addr, align 32
# |   %permil = shufflevector <4 x double> %0, <4 x double> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
# |   ret <4 x double> %permil
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_mm_permute_ps(<4 x float> noundef %a) #1 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %permil = shufflevector <4 x float> %0, <4 x float> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
# |   ret <4 x float> %permil
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_mm_permute_ps2(<4 x float> noundef %a) #1 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %permil = shufflevector <4 x float> %0, <4 x float> poison, <4 x i32> <i32 2, i32 1, i32 2, i32 3>
# |   ret <4 x float> %permil
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x float> @test_mm256_permute_ps(<8 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x float>, align 32
# |   store <8 x float> %a, ptr %a.addr, align 32
# |   %0 = load <8 x float>, ptr %a.addr, align 32
# |   %permil = shufflevector <8 x float> %0, <8 x float> poison, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
# |   ret <8 x float> %permil
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x double> @test_mm256_permute2f128_pd(<4 x double> noundef %a, <4 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x double>, align 32
# |   %b.addr = alloca <4 x double>, align 32
# |   store <4 x double> %a, ptr %a.addr, align 32
# |   store <4 x double> %b, ptr %b.addr, align 32
# |   %0 = load <4 x double>, ptr %a.addr, align 32
# |   %1 = load <4 x double>, ptr %b.addr, align 32
# |   %vperm = shufflevector <4 x double> %0, <4 x double> %1, <4 x i32> <i32 2, i32 3, i32 6, i32 7>
# |   ret <4 x double> %vperm
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x float> @test_mm256_permute2f128_ps(<8 x float> noundef %a, <8 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x float>, align 32
# |   %b.addr = alloca <8 x float>, align 32
# |   store <8 x float> %a, ptr %a.addr, align 32
# |   store <8 x float> %b, ptr %b.addr, align 32
# |   %0 = load <8 x float>, ptr %a.addr, align 32
# |   %1 = load <8 x float>, ptr %b.addr, align 32
# |   %vperm = shufflevector <8 x float> %1, <8 x float> %0, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15>
# |   ret <8 x float> %vperm
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i64> @test_mm256_permute2f128_si256(<4 x i64> noundef %a, <4 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i64>, align 32
# |   %b.addr = alloca <4 x i64>, align 32
# |   store <4 x i64> %a, ptr %a.addr, align 32
# |   store <4 x i64> %b, ptr %b.addr, align 32
# |   %0 = load <4 x i64>, ptr %a.addr, align 32
# |   %1 = bitcast <4 x i64> %0 to <8 x i32>
# |   %2 = load <4 x i64>, ptr %b.addr, align 32
# |   %3 = bitcast <4 x i64> %2 to <8 x i32>
# |   %vperm = shufflevector <8 x i32> %1, <8 x i32> %3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
# |   %4 = bitcast <8 x i32> %vperm to <4 x i64>
# |   ret <4 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_mm_broadcast_ss(ptr noundef %__a) #1 {
# | entry:
# |   %__a.addr.i = alloca ptr, align 8
# |   %__f.i = alloca float, align 4
# |   %.compoundliteral.i = alloca <4 x float>, align 16
# |   %__a.addr = alloca ptr, align 8
# |   store ptr %__a, ptr %__a.addr, align 8
# |   %0 = load ptr, ptr %__a.addr, align 8
# |   store ptr %0, ptr %__a.addr.i, align 8
# |   %1 = load ptr, ptr %__a.addr.i, align 8
# |   %2 = load float, ptr %1, align 1
# |   store float %2, ptr %__f.i, align 4
# |   %3 = load float, ptr %__f.i, align 4
# |   %vecinit.i = insertelement <4 x float> poison, float %3, i32 0
# |   %4 = load float, ptr %__f.i, align 4
# |   %vecinit2.i = insertelement <4 x float> %vecinit.i, float %4, i32 1
# |   %5 = load float, ptr %__f.i, align 4
# |   %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %5, i32 2
# |   %6 = load float, ptr %__f.i, align 4
# |   %vecinit4.i = insertelement <4 x float> %vecinit3.i, float %6, i32 3
# |   store <4 x float> %vecinit4.i, ptr %.compoundliteral.i, align 16
# |   %7 = load <4 x float>, ptr %.compoundliteral.i, align 16
# |   ret <4 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x double> @test_mm256_broadcast_sd(ptr noundef %__a) #0 {
# | entry:
# |   %__a.addr.i = alloca ptr, align 8
# |   %__d.i = alloca double, align 8
# |   %.compoundliteral.i = alloca <4 x double>, align 32
# |   %__a.addr = alloca ptr, align 8
# |   store ptr %__a, ptr %__a.addr, align 8
# |   %0 = load ptr, ptr %__a.addr, align 8
# |   store ptr %0, ptr %__a.addr.i, align 8
# |   %1 = load ptr, ptr %__a.addr.i, align 8
# |   %2 = load double, ptr %1, align 1
# |   store double %2, ptr %__d.i, align 8
# |   %3 = load double, ptr %__d.i, align 8
# |   %vecinit.i = insertelement <4 x double> poison, double %3, i32 0
# |   %4 = load double, ptr %__d.i, align 8
# |   %vecinit2.i = insertelement <4 x double> %vecinit.i, double %4, i32 1
# |   %5 = load double, ptr %__d.i, align 8
# |   %vecinit3.i = insertelement <4 x double> %vecinit2.i, double %5, i32 2
# |   %6 = load double, ptr %__d.i, align 8
# |   %vecinit4.i = insertelement <4 x double> %vecinit3.i, double %6, i32 3
# |   store <4 x double> %vecinit4.i, ptr %.compoundliteral.i, align 32
# |   %7 = load <4 x double>, ptr %.compoundliteral.i, align 32
# |   ret <4 x double> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x float> @test_mm256_broadcast_ss(ptr noundef %__a) #0 {
# | entry:
# |   %__a.addr.i = alloca ptr, align 8
# |   %__f.i = alloca float, align 4
# |   %.compoundliteral.i = alloca <8 x float>, align 32
# |   %__a.addr = alloca ptr, align 8
# |   store ptr %__a, ptr %__a.addr, align 8
# |   %0 = load ptr, ptr %__a.addr, align 8
# |   store ptr %0, ptr %__a.addr.i, align 8
# |   %1 = load ptr, ptr %__a.addr.i, align 8
# |   %2 = load float, ptr %1, align 1
# |   store float %2, ptr %__f.i, align 4
# |   %3 = load float, ptr %__f.i, align 4
# |   %vecinit.i = insertelement <8 x float> poison, float %3, i32 0
# |   %4 = load float, ptr %__f.i, align 4
# |   %vecinit2.i = insertelement <8 x float> %vecinit.i, float %4, i32 1
# |   %5 = load float, ptr %__f.i, align 4
# |   %vecinit3.i = insertelement <8 x float> %vecinit2.i, float %5, i32 2
# |   %6 = load float, ptr %__f.i, align 4
# |   %vecinit4.i = insertelement <8 x float> %vecinit3.i, float %6, i32 3
# |   %7 = load float, ptr %__f.i, align 4
# |   %vecinit5.i = insertelement <8 x float> %vecinit4.i, float %7, i32 4
# |   %8 = load float, ptr %__f.i, align 4
# |   %vecinit6.i = insertelement <8 x float> %vecinit5.i, float %8, i32 5
# |   %9 = load float, ptr %__f.i, align 4
# |   %vecinit7.i = insertelement <8 x float> %vecinit6.i, float %9, i32 6
# |   %10 = load float, ptr %__f.i, align 4
# |   %vecinit8.i = insertelement <8 x float> %vecinit7.i, float %10, i32 7
# |   store <8 x float> %vecinit8.i, ptr %.compoundliteral.i, align 32
# |   %11 = load <8 x float>, ptr %.compoundliteral.i, align 32
# |   ret <8 x float> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x float> @test_mm256_insertf128_ps_0(<8 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x float>, align 32
# |   %b.addr = alloca <4 x float>, align 16
# |   store <8 x float> %a, ptr %a.addr, align 32
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <8 x float>, ptr %a.addr, align 32
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   %widen = shufflevector <4 x float> %1, <4 x float> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   %insert = shufflevector <8 x float> %0, <8 x float> %widen, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
# |   ret <8 x float> %insert
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x double> @test_mm256_insertf128_pd_0(<4 x double> noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x double>, align 32
# |   %b.addr = alloca <2 x double>, align 16
# |   store <4 x double> %a, ptr %a.addr, align 32
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <4 x double>, ptr %a.addr, align 32
# |   %1 = load <2 x double>, ptr %b.addr, align 16
# |   %widen = shufflevector <2 x double> %1, <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
# |   %insert = shufflevector <4 x double> %0, <4 x double> %widen, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
# |   ret <4 x double> %insert
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i64> @test_mm256_insertf128_si256_0(<4 x i64> noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i64>, align 32
# |   %b.addr = alloca <2 x i64>, align 16
# |   store <4 x i64> %a, ptr %a.addr, align 32
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <4 x i64>, ptr %a.addr, align 32
# |   %1 = bitcast <4 x i64> %0 to <8 x i32>
# |   %2 = load <2 x i64>, ptr
# | ...
# `---data was truncated (10240/21933) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005633f32bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005633f32b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005633f32bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0f72449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0f724a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0f72449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0f72431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005633f3251bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005633f3251a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005633f32368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005633f2ee5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005633f2ee5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0f72432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0f724330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0f724330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005633f2ee5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c (193 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmin_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmin_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmin_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmin_bf16_n_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmin_bf16_n_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmin_bf16_n_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005576e8891eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005576e888ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005576e889262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7a7e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7a7e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7a7e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7a7e31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005576e8827bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005576e8827a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005576e880c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005576e84bbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005576e84bbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7a7e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7a7e31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7a7e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005576e84bba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/neon-2velem.c (194 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-2velem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vmla_lane_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   %v.addr = alloca <4 x i16>, align 8
# |   %__ret_72 = alloca <4 x i16>, align 8
# |   %__s0_72 = alloca <4 x i16>, align 8
# |   %__s1_72 = alloca <4 x i16>, align 8
# |   %__s2_72 = alloca <4 x i16>, align 8
# |   %__ret = alloca <4 x i16>, align 8
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x i16>, align 8
# |   %tmp1 = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   store <4 x i16> %v, ptr %v.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__s0_72, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %1, ptr %__s1_72, align 8
# |   %2 = load <4 x i16>, ptr %v.addr, align 8
# |   store <4 x i16> %2, ptr %__s2_72, align 8
# |   %3 = load <4 x i16>, ptr %__s0_72, align 8
# |   %4 = load <4 x i16>, ptr %__s1_72, align 8
# |   %5 = load <4 x i16>, ptr %__s2_72, align 8
# |   store <4 x i16> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <4 x i16>
# |   %lane = shufflevector <4 x i16> %7, <4 x i16> %7, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
# |   store <4 x i16> %lane, ptr %ref.tmp, align 8
# |   %8 = load <4 x i16>, ptr %ref.tmp, align 8
# |   store <4 x i16> %8, ptr %__ret, align 8
# |   %9 = load <4 x i16>, ptr %__ret, align 8
# |   store <4 x i16> %9, ptr %tmp, align 8
# |   %10 = load <4 x i16>, ptr %tmp, align 8
# |   %mul = mul <4 x i16> %4, %10
# |   %add = add <4 x i16> %3, %mul
# |   store <4 x i16> %add, ptr %__ret_72, align 8
# |   %11 = load <4 x i16>, ptr %__ret_72, align 8
# |   store <4 x i16> %11, ptr %tmp1, align 8
# |   %12 = load <4 x i16>, ptr %tmp1, align 8
# |   ret <4 x i16> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vmlaq_lane_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, <4 x i16> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   %v.addr = alloca <4 x i16>, align 8
# |   %__ret_62 = alloca <8 x i16>, align 16
# |   %__s0_62 = alloca <8 x i16>, align 16
# |   %__s1_62 = alloca <8 x i16>, align 16
# |   %__s2_62 = alloca <4 x i16>, align 8
# |   %__ret = alloca <8 x i16>, align 16
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x i16>, align 16
# |   %tmp1 = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x i16> %b, ptr %b.addr, align 16
# |   store <4 x i16> %v, ptr %v.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__s0_62, align 16
# |   %1 = load <8 x i16>, ptr %b.addr, align 16
# |   store <8 x i16> %1, ptr %__s1_62, align 16
# |   %2 = load <4 x i16>, ptr %v.addr, align 8
# |   store <4 x i16> %2, ptr %__s2_62, align 8
# |   %3 = load <8 x i16>, ptr %__s0_62, align 16
# |   %4 = load <8 x i16>, ptr %__s1_62, align 16
# |   %5 = load <4 x i16>, ptr %__s2_62, align 8
# |   store <4 x i16> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <4 x i16>
# |   %lane = shufflevector <4 x i16> %7, <4 x i16> %7, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
# |   store <8 x i16> %lane, ptr %ref.tmp, align 16
# |   %8 = load <8 x i16>, ptr %ref.tmp, align 16
# |   store <8 x i16> %8, ptr %__ret, align 16
# |   %9 = load <8 x i16>, ptr %__ret, align 16
# |   store <8 x i16> %9, ptr %tmp, align 16
# |   %10 = load <8 x i16>, ptr %tmp, align 16
# |   %mul = mul <8 x i16> %4, %10
# |   %add = add <8 x i16> %3, %mul
# |   store <8 x i16> %add, ptr %__ret_62, align 16
# |   %11 = load <8 x i16>, ptr %__ret_62, align 16
# |   store <8 x i16> %11, ptr %tmp1, align 16
# |   %12 = load <8 x i16>, ptr %tmp1, align 16
# |   ret <8 x i16> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vmla_lane_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <2 x i32> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   %v.addr = alloca <2 x i32>, align 8
# |   %__ret_70 = alloca <2 x i32>, align 8
# |   %__s0_70 = alloca <2 x i32>, align 8
# |   %__s1_70 = alloca <2 x i32>, align 8
# |   %__s2_70 = alloca <2 x i32>, align 8
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   %tmp1 = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   store <2 x i32> %v, ptr %v.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0_70, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   store <2 x i32> %1, ptr %__s1_70, align 8
# |   %2 = load <2 x i32>, ptr %v.addr, align 8
# |   store <2 x i32> %2, ptr %__s2_70, align 8
# |   %3 = load <2 x i32>, ptr %__s0_70, align 8
# |   %4 = load <2 x i32>, ptr %__s1_70, align 8
# |   %5 = load <2 x i32>, ptr %__s2_70, align 8
# |   store <2 x i32> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x i32>
# |   %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> <i32 1, i32 1>
# |   store <2 x i32> %lane, ptr %ref.tmp, align 8
# |   %8 = load <2 x i32>, ptr %ref.tmp, align 8
# |   store <2 x i32> %8, ptr %__ret, align 8
# |   %9 = load <2 x i32>, ptr %__ret, align 8
# |   store <2 x i32> %9, ptr %tmp, align 8
# |   %10 = load <2 x i32>, ptr %tmp, align 8
# |   %mul = mul <2 x i32> %4, %10
# |   %add = add <2 x i32> %3, %mul
# |   store <2 x i32> %add, ptr %__ret_70, align 8
# |   %11 = load <2 x i32>, ptr %__ret_70, align 8
# |   store <2 x i32> %11, ptr %tmp1, align 8
# |   %12 = load <2 x i32>, ptr %tmp1, align 8
# |   ret <2 x i32> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmlaq_lane_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, <2 x i32> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <4 x i32>, align 16
# |   %v.addr = alloca <2 x i32>, align 8
# |   %__ret_60 = alloca <4 x i32>, align 16
# |   %__s0_60 = alloca <4 x i32>, align 16
# |   %__s1_60 = alloca <4 x i32>, align 16
# |   %__s2_60 = alloca <2 x i32>, align 8
# |   %__ret = alloca <4 x i32>, align 16
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x i32>, align 16
# |   %tmp1 = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <4 x i32> %b, ptr %b.addr, align 16
# |   store <2 x i32> %v, ptr %v.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__s0_60, align 16
# |   %1 = load <4 x i32>, ptr %b.addr, align 16
# |   store <4 x i32> %1, ptr %__s1_60, align 16
# |   %2 = load <2 x i32>, ptr %v.addr, align 8
# |   store <2 x i32> %2, ptr %__s2_60, align 8
# |   %3 = load <4 x i32>, ptr %__s0_60, align 16
# |   %4 = load <4 x i32>, ptr %__s1_60, align 16
# |   %5 = load <2 x i32>, ptr %__s2_60, align 8
# |   store <2 x i32> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x i32>
# |   %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
# |   store <4 x i32> %lane, ptr %ref.tmp, align 16
# |   %8 = load <4 x i32>, ptr %ref.tmp, align 16
# |   store <4 x i32> %8, ptr %__ret, align 16
# |   %9 = load <4 x i32>, ptr %__ret, align 16
# |   store <4 x i32> %9, ptr %tmp, align 16
# |   %10 = load <4 x i32>, ptr %tmp, align 16
# |   %mul = mul <4 x i32> %4, %10
# |   %add = add <4 x i32> %3, %mul
# |   store <4 x i32> %add, ptr %__ret_60, align 16
# |   %11 = load <4 x i32>, ptr %__ret_60, align 16
# |   store <4 x i32> %11, ptr %tmp1, align 16
# |   %12 = load <4 x i32>, ptr %tmp1, align 16
# |   ret <4 x i32> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vmla_laneq_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <8 x i16> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   %v.addr = alloca <8 x i16>, align 16
# |   %__ret_482 = alloca <4 x i16>, align 8
# |   %__s0_482 = alloca <4 x i16>, align 8
# |   %__s1_482 = alloca <4 x i16>, align 8
# |   %__s2_482 = alloca <8 x i16>, align 16
# |   %__ret = alloca <4 x i16>, align 8
# |   %__s0 = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x i16>, align 8
# |   %tmp1 = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %v, ptr %v.addr, align 16
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__s0_482, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %1, ptr %__s1_482, align 8
# |   %2 = load <8 x i16>, ptr %v.addr, align 16
# |   store <8 x i16> %2, ptr %__s2_482, align 16
# |   %3 = load <4 x i16>, ptr %__s0_482, align 8
# |   %4 = load <4 x i16>, ptr %__s1_482, align 8
# |   %5 = load <8 x i16>, ptr %__s2_482, align 16
# |   store <8 x i16> %5, ptr %__s0, align 16
# |   %6 = load <16 x i8>, ptr %__s0, align 16
# |   %7 = bitcast <16 x i8> %6 to <8 x i16>
# |   %lane = shufflevector <8 x i16> %7, <8 x i16> %7, <4 x i32> <i32 7, i32 7, i32 7, i32 7>
# |   store <4 x i16> %lane, ptr %ref.tmp, align 8
# |   %8 = load <4 x i16>, ptr %ref.tmp, align 8
# |   store <4 x i16> %8, ptr %__ret, align 8
# |   %9 = load <4 x i16>, ptr %__ret, align 8
# |   store <4 x i16> %9, ptr %tmp, align 8
# |   %10 = load <4 x i16>, ptr %tmp, align 8
# |   %mul = mul <4 x i16> %4, %10
# |   %add = add <4 x i16> %3, %mul
# |   store <4 x i16> %add, ptr %__ret_482, align 8
# |   %11 = load <4 x i16>, ptr %__ret_482, align 8
# |   store <4 x i16> %11, ptr %tmp1, align 8
# |   %12 = load <4 x i16>, ptr %tmp1, align 8
# |   ret <4 x i16> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vmlaq_laneq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   %v.addr = alloca <8 x i16>, align 16
# |   %__ret_472 = alloca <8 x i16>, align 16
# |   %__s0_472 = alloca <8 x i16>, align 16
# |   %__s1_472 = alloca <8
# | ...
# `---data was truncated (10240/857511) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055c57fcf3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c57fcf0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c57fcf462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa046933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa04698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa046933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa04691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c57fc89bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c57fc89a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c57fc6e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c57f91de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c57f91db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa04691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa04691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa04691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c57f91da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c (195 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svadd_write_single2_s32(i32 noundef %slice_base, <vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 1
# |   %6 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv4i32(i32 %2, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv4i32(i32, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svadd_write_single2_u32(i32 noundef %slice_base, <vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 1
# |   %6 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv4i32(i32 %2, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svadd_write_single2_s64(i32 noundef %slice_base, <vscale x 2 x i64> %zn.coerce0, <vscale x 2 x i64> %zn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zn.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 1
# |   %6 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv2i64(i32 %2, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv2i64(i32, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svadd_write_single2_u64(i32 noundef %slice_base, <vscale x 2 x i64> %zn.coerce0, <vscale x 2 x i64> %zn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zn.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 1
# |   %6 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv2i64(i32 %2, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svadd_write_single4_s32(i32 noundef %slice_base, <vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %zn.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 0
# |   %7 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 1
# |   %8 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 2
# |   %9 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 3
# |   %10 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.add.write.single.za.vg1x4.nxv4i32(i32 %4, <vscale x 4 x i32> %6, <vscale x 4 x i32> %7, <vscale x 4 x i32> %8, <vscale x 4 x i32> %9, <vscale x 4 x i32> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.add.write.single.za.vg1x4.nxv4i32(i32, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svadd_write_single4_u32(i32 noundef %slice_base, <vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i
# | ...
# `---data was truncated (10240/67892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055c48d3a0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c48d39de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c48d3a162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e8be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e8bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e8be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e8be31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c48d336bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c48d336a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c48d31b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c48cfcae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c48cfcab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0e8be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e8be330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e8be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c48cfcaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c (196 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_f32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_f32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_i32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_i32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_u32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_u32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounw
# | ...
# `---data was truncated (10240/15952) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055da304e8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055da304e5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055da304e962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efdf3705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efdf375c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efdf3705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efdf36ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da3047ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055da3047ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055da304638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055da30112e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055da30112b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efdf36eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efdf36ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efdf36ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da30112a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c (197 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svmul_single_bf16_x2(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 1
# |   %5 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmul.single.x2.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %5)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmul.single.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svmul_single_bf16_x4(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zdn.coerce2, <vscale x 8 x bfloat> %zdn.coerce3, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, <vscale x 8 x bfloat> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zdn.coerce3, 3
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 1
# |   %7 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 2
# |   %8 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 3
# |   %9 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %10 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmul.single.x4.nxv8bf16(<vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %6, <vscale x 8 x bfloat> %7, <vscale x 8 x bfloat> %8, <vscale x 8 x bfloat> %9)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmul.single.x4.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svmul_bf16_x2(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zm.coerce0, <vscale x 8 x bfloat> %zm.coerce1) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zm.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zm, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 1
# |   %7 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %7, 0
# |   %9 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %7, 1
# |   %10 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmul.x2.nxv8bf16(<vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %6, <vscale x 8 x bfloat> %8, <vscale x 8 x bfloat> %9)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmul.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svmul_bf16_x4(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zdn.coerce2, <vscale x 8 x bfloat> %zdn.coerce3, <vscale x 8 x bfloat> %zm.coerce0, <vscale x 8 x bfloat> %zm.coerce1, <vscale x 8 x bfloat> %zm.coerce2, <vscale x 8 x bfloat> %zm.coerce3) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, <vscale x 8 x bfloat> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zdn.coerce3, 3
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   %4 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zm.coerce0, 0
# |   %5 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, <vscale x 8 x bfloat> %zm.coerce1, 1
# |   %6 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %5, <vscale x 8 x bfloat> %zm.coerce2, 2
# |   %7 = insertvalue { <v
# | ...
# `---data was truncated (10240/13687) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000555eeee2eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555eeee2be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555eeee2f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcf3e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcf3e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcf3e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcf3e431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555eeedc4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555eeedc4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555eeeda98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555eeea58e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555eeea58b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcf3e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcf3e4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcf3e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555eeea58a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c (198 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svqdmulh_single_s8_x2(<vscale x 16 x i8> %zdn.coerce0, <vscale x 16 x i8> %zdn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zdn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zdn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svqdmulh_single_s16_x2(<vscale x 8 x i16> %zdn.coerce0, <vscale x 8 x i16> %zdn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zdn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svqdmulh_single_s32_x2(<vscale x 4 x i32> %zdn.coerce0, <vscale x 4 x i32> %zdn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zdn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zdn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zdn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svqdmulh_single_s64_x2(<vscale x 2 x i64> %zdn.coerce0, <vscale x 2 x i64> %zdn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zdn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zdn.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zdn, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 0
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 1
# |   %5 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv2i64(<vscale x 2 x i64> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svqdmulh_single_s8_x4(<vscale x 16 x i8> %zdn.coerce0, <vscale x 16 x i8> %zdn.coerce1, <vscale x 16 x i8> %zdn.coerce2, <vscale x 16 x i8> %zdn.coerce3, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zdn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zdn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 3
# |   %9 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %10 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sqdmulh.single.vgx4.nxv16i8(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sqdmulh.single.vgx4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svqdmulh_single_s16_x4(<vscale x 8 x i16> %zdn.coerce0, <vscale x 8 x i16> %zdn.coerce1, <vscale x 8 x i16> %zdn.coerce2, <vscale x 8
# | ...
# `---data was truncated (10240/47111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005579c2496eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005579c2493e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005579c249762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7636d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7636d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7636d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7636d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005579c242cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005579c242ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005579c24118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005579c20c0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005579c20c0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7636d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7636d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7636d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005579c20c0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c (199 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintn_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintn.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frintn.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintn_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintn.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frintn.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintn_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintn.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frintn.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintn_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.frintn.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintn_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frintn.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintn_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frintn.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintn_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintn.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintn_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintn.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintn_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintn.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005572aadebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005572aade8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005572aadec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe193333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe19338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe193333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe19331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005572aad81bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005572aad81a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005572aad668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005572aaa15e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005572aaa15b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe19331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe19331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe19331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005572aaa15a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c (200 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svmax_single_s8_x2(<vscale x 16 x i8> %zdn.coerce0, <vscale x 16 x i8> %zdn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zdn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zdn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.smax.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.smax.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svmax_single_s16_x2(<vscale x 8 x i16> %zdn.coerce0, <vscale x 8 x i16> %zdn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zdn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.smax.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.smax.single.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svmax_single_s32_x2(<vscale x 4 x i32> %zdn.coerce0, <vscale x 4 x i32> %zdn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zdn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zdn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zdn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.smax.single.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.smax.single.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svmax_single_s64_x2(<vscale x 2 x i64> %zdn.coerce0, <vscale x 2 x i64> %zdn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zdn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zdn.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zdn, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 0
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 1
# |   %5 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.smax.single.x2.nxv2i64(<vscale x 2 x i64> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.smax.single.x2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svmax_single_u8_x2(<vscale x 16 x i8> %zdn.coerce0, <vscale x 16 x i8> %zdn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zdn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zdn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.umax.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.umax.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svmax_single_u16_x2(<vscale x 8 x i16> %zdn.coerce0, <vscale x 8 x i16> %zdn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zdn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.umax.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.umax.single.x
# | ...
# `---data was truncated (10240/142195) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055bf7d0ddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bf7d0dae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bf7d0de62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb46d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb46d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb46d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb46d231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bf7d073bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bf7d073a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bf7d0588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bf7cd07e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bf7cd07b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb46d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb46d2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb46d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bf7cd07a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c (201 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls2_f32(i32 noundef %slice_base, <vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zm.coerce0, <vscale x 4 x float> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zm.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %5, 0
# |   %7 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %5, 1
# |   %8 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %8, 0
# |   %10 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %8, 1
# |   call void @llvm.aarch64.sme.fmls.vg1x2.nxv4f32(i32 %4, <vscale x 4 x float> %6, <vscale x 4 x float> %7, <vscale x 4 x float> %9, <vscale x 4 x float> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmls.vg1x2.nxv4f32(i32, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls4_f32(i32 noundef %slice_base, <vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zn.coerce2, <vscale x 4 x float> %zn.coerce3, <vscale x 4 x float> %zm.coerce0, <vscale x 4 x float> %zm.coerce1, <vscale x 4 x float> %zm.coerce2, <vscale x 4 x float> %zm.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, <vscale x 4 x float> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zn.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   %4 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zm.coerce0, 0
# |   %5 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, <vscale x 4 x float> %zm.coerce1, 1
# |   %6 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %5, <vscale x 4 x float> %zm.coerce2, 2
# |   %7 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %6, <vscale x 4 x float> %zm.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %7, ptr %zm, align 16
# |   %zm2 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %zm2, ptr %zm.addr, align 16
# |   %8 = load i32, ptr %slice_base.addr, align 4
# |   %9 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %10 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9, 0
# |   %11 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9, 1
# |   %12 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9, 2
# |   %13 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9, 3
# |   %14 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm.addr, align 16
# |   %15 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %14, 0
# |   %16 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %14, 1
# |   %17 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %14, 2
# |   %18 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %14, 3
# |   call void @llvm.aarch64.sme.fmls.vg1x4.nxv4f32(i32 %8, <vscale x 4 x float> %10, <vscale x 4 x float> %11, <vscale x 4 x float> %12, <vscale x 4 x float> %13, <vscale x 4 x float> %15, <vscale x 4 x float> %16, <vscale x 4 x float> %17, <vscale x 4 x float> %18)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmls.vg1x4.nxv4f32(i32, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls_single2_f32(i32 noundef %slice_base, <vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %3, 0
# |   %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %3, 1
# |   %6 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.fmls.single.vg1x2.nxv4f32(i32 %2, <vscale x 4 x float> %4, <vscale x 4 x float> %5, <vscale x 4 x float> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmls.single.vg1x2.nxv4f32(i32, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls_single4_f32(i32 noundef %slice_base, <vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zn.coerce2, <vscale x 4 x float> %zn.coerce3, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x flo
# | ...
# `---data was truncated (10240/34546) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005579838ceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005579838cbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005579838cf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f88ed733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f88ed78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f88ed733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f88ed71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557983864bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557983864a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005579838498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005579834f8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005579834f8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f88ed71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f88ed71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f88ed71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005579834f8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/X86/avx-cmp-builtins.c (202 of 27911)
******************** TEST 'Clang :: CodeGen/X86/avx-cmp-builtins.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -flax-vector-conversions=none -ffreestanding /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c -triple=x86_64-- -target-feature +avx -disable-O0-optnone -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -flax-vector-conversions=none -ffreestanding /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c -triple=x86_64-- -target-feature +avx -disable-O0-optnone -emit-llvm -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-unknown"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_cmp_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <2 x double>, align 16
# |   %b.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   %1 = load <2 x double>, ptr %b.addr, align 16
# |   %2 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %0, <2 x double> %1, i8 13)
# |   ret <2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double>, <2 x double>, i8 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_cmp_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   %2 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %0, <4 x float> %1, i8 13)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.x86.sse.cmp.ss(<4 x float>, <4 x float>, i8 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_cmpgt_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca <4 x float>, align 16
# |   %__b.addr.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x float> %0, ptr %__a.addr.i, align 16
# |   store <4 x float> %1, ptr %__b.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__a.addr.i, align 16
# |   %3 = load <4 x float>, ptr %__b.addr.i, align 16
# |   %4 = load <4 x float>, ptr %__a.addr.i, align 16
# |   %5 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %3, <4 x float> %4, i8 1)
# |   %shuffle.i = shufflevector <4 x float> %2, <4 x float> %5, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
# |   ret <4 x float> %shuffle.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_cmpge_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca <4 x float>, align 16
# |   %__b.addr.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x float> %0, ptr %__a.addr.i, align 16
# |   store <4 x float> %1, ptr %__b.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__a.addr.i, align 16
# |   %3 = load <4 x float>, ptr %__b.addr.i, align 16
# |   %4 = load <4 x float>, ptr %__a.addr.i, align 16
# |   %5 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %3, <4 x float> %4, i8 2)
# |   %shuffle.i = shufflevector <4 x float> %2, <4 x float> %5, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
# |   ret <4 x float> %shuffle.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_cmpngt_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca <4 x float>, align 16
# |   %__b.addr.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x float> %0, ptr %__a.addr.i, align 16
# |   store <4 x float> %1, ptr %__b.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__a.addr.i, align 16
# |   %3 = load <4 x float>, ptr %__b.addr.i, align 16
# |   %4 = load <4 x float>, ptr %__a.addr.i, align 16
# |   %5 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %3, <4 x float> %4, i8 5)
# |   %shuffle.i = shufflevector <4 x float> %2, <4 x float> %5, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
# |   ret <4 x float> %shuffle.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_cmpnge_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca <4 x float>, align 16
# |   %__b.addr.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x float> %0, ptr %__a.addr.i, align 16
# |   store <4 x float> %1, ptr %__b.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__a.addr.i, align 16
# |   %3 = load <4 x float>, ptr %__b.addr.i, align 16
# |   %4 = load <4 x float>, ptr %__a.addr.i, align 16
# |   %5 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %3, <4 x float> %4, i8 6)
# |   %shuffle.i = shufflevector <4 x float> %2, <4 x float> %5, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
# |   ret <4 x float> %shuffle.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_cmpgt_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca <2 x double>, align 16
# |   %__b.addr.i = alloca <2 x double>, align 16
# |   %__c.i = alloca <2 x double>, align 16
# |   %.compoundliteral.i = alloca <2 x double>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   %b.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   %1 = load <2 x double>, ptr %b.addr, align 16
# |   store <2 x double> %0, ptr %__a.addr.i, align 16
# |   store <2 x double> %1, ptr %__b.addr.i, align 16
# |   %2 = load <2 x double>, ptr %__b.addr.i, align 16
# |   %3 = load <2 x double>, ptr %__a.addr.i, align 16
# |   %4 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %2, <2 x double> %3, i8 1)
# |   store <2 x double> %4, ptr %__c.i, align 16
# |   %5 = load <2 x double>, ptr %__c.i, align 16
# |   %vecext.i = extractelement <2 x double> %5, i32 0
# |   %vecinit.i = insertelement <2 x double> poison, double %vecext.i, i32 0
# |   %6 = load <2 x double>, ptr %__a.addr.i, align 16
# |   %vecext1.i = extractelement <2 x double> %6, i32 1
# |   %vecinit2.i = insertelement <2 x double> %vecinit.i, double %vecext1.i, i32 1
# |   store <2 x double> %vecinit2.i, ptr %.compoundliteral.i, align 16
# |   %7 = load <2 x double>, ptr %.compoundliteral.i, align 16
# |   ret <2 x double> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_cmpge_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca <2 x double>, align 16
# |   %__b.addr.i = alloca <2 x double>, align 16
# |   %__c.i = alloca <2 x double>, align 16
# |   %.compoundliteral.i = alloca <2 x double>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   %b.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   %1 = load <2 x double>, ptr %b.addr, align 16
# |   store <2 x double> %0, ptr %__a.addr.i, align 16
# |   store <2 x double> %1, ptr %__b.addr.i, align 16
# |   %2 = load <2 x double>, ptr %__b.addr.i, align 16
# |   %3 = load <2 x double>, ptr %__a.addr.i, align 16
# |   %4 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %2, <2 x double> %3, i8 2)
# |   store <2 x double> %4, ptr %__c.i, align 16
# |   %5 = load <2 x double>, ptr %__c.i, align 16
# |   %vecext.i = extractelement <2 x double> %5, i32 0
# |   %vecinit.i = insertelement <2 x double> poison, double %vecext.i, i32 0
# |   %6 = load <2 x double>, ptr %__a.addr.i, align 16
# |   %vecext1.i = extractelement <2 x double> %6, i32 1
# |   %vecinit2.i = insertelement <2 x double> %vecinit.i, double %vecext1.i, i32 1
# |   store <2 x double> %vecinit2.i, ptr %.compoundliteral.i, align 16
# |   %7 = load <2 x double>, ptr %.compoundliteral.i, align 16
# |   ret <2 x double> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_cmpngt_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca <2 x double>, align 16
# |   %__b.addr.i = alloca <2 x double>, align 16
# |   %__c.i = alloca <2 x double>, align 16
# |   %.compoundliteral.i = alloca <2 x double>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   %b.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   %1 = load <2 x double>, ptr %b.addr, align 16
# |   store <2 x double> %0, ptr %__a.addr.i, align 16
# |   store <2 x double> %1, ptr %__b.addr.i, align 16
# |   %2 = load <2 x double>, ptr %__b.addr.i, align 16
# |   %3 = load <2 x double>, ptr %__a.addr.i, align 16
# |   %4 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %2, <2 x double> %3, i8 5)
# |   store <2 x double> %4, ptr %__c.i, align 16
# |   %5 = load <2 x double>, ptr %__c.i, align 16
# |   %vecext.i = extractelement <2 x double> %5, i32 0
# |   %vecinit.i = insertelement <2 x double> poison, double %vecext.i, i32 0
# |   %6 = load <2 x double>, ptr %__a.addr.i, align 16
# |   %vecext1.i = extractelement <2 x double> %6, i32 1
# |   %vecinit2.i = insertelement <2 x double> %vecinit.i, double %vecext1.i, i32 1
# |   store <2 x double> %vecinit2.i, ptr %.compoundliteral.i, align 16
# |   %7 = load <2 x double>, ptr %.compoundliteral.i, align 16
# |   ret <2 x double> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_cmpnge_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca <2 x double>, align 16
# |   %__b.addr.i = alloca <2 x double>, align 16
# |   %__c.i = alloca <2 x double>, align 16
# |   %.compoundlit
# | ...
# `---data was truncated (10240/11780) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564cd06b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564cd06b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564cd06b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f63a8905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f63a895c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f63a8905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f63a88ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564cd0649bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564cd0649a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564cd062e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564cd02dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564cd02ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f63a88eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f63a88ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f63a88ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564cd02dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c (203 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecw_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecw.n32(i32 %0, i32 31, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqdecw.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecw_n_s32_1(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecw.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecw_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqdecw.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqdecw.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecw_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqdecw.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqdecw.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecw_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqdecw.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uqdecw.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecw_pat_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecw.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecw_pat_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqdecw.n64(i64 %0, i32 0, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecw_pat_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqdecw.n32(i32 %0, i32 1, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecw_pat_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqdecw.n64(i64 %0, i32 2, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqdecw_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.sqdecw.nxv4i32(<vscale x 4 x i32> %0, i32 31, i32 16)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sqdecw.nxv4i32(<vscale x 4 x i32>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqdecw_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.uqdecw.nxv4i32(<vscale x 4 x i32> %0, i32 31, i32 1)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uqdecw.nxv4i32(<vscale x 4 x i32>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqdecw_pat_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.sqdecw.nxv4i32(<vscale x 4 x i32> %0, i32 3, i32 16)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqdecw_pat_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.uqdecw.nxv4i32(<vscale x 4 x i32> %0, i32 4, i32 1)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560d54fa6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560d54fa3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560d54fa762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9e14d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9e14d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9e14d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9e14d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560d54f3cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560d54f3ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560d54f218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560d54bd0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560d54bd0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9e14d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9e14d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9e14d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560d54bd0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c (204 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_svzero_zt() #0 {
# | entry:
# |   call void @llvm.aarch64.sme.zero.zt(i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write)
# | declare void @llvm.aarch64.sme.zero.zt(i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "aarch64_out_zt0" "aarch64_pstate_sm_compatible" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000557c85394eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557c85391e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557c8539562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5be3849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5be38a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5be3849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5be3831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557c8532abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557c8532aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557c8530f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557c84fbee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557c84fbeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5be3832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5be38330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5be38330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557c84fbea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c (205 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svset2_b_0(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1, <vscale x 16 x i1> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %x.addr = alloca <vscale x 16 x i1>, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1> } %1, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   store <vscale x 16 x i1> %x, ptr %x.addr, align 2
# |   %2 = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %3 = load <vscale x 16 x i1>, ptr %x.addr, align 2
# |   %4 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %3, 0
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svset2_b_1(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1, <vscale x 16 x i1> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %x.addr = alloca <vscale x 16 x i1>, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1> } %1, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   store <vscale x 16 x i1> %x, ptr %x.addr, align 2
# |   %2 = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %3 = load <vscale x 16 x i1>, ptr %x.addr, align 2
# |   %4 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %3, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000558b823f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558b823f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558b823f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f565a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f565a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f565a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f565a431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558b8238ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558b8238ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558b823738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558b82022e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558b82022b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f565a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f565a4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f565a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558b82022a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c (206 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svsub_write_single2_s32(i32 noundef %slice_base, <vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 1
# |   %6 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv4i32(i32 %2, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv4i32(i32, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svsub_write_single2_u32(i32 noundef %slice_base, <vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 1
# |   %6 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv4i32(i32 %2, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svsub_write_single2_s64(i32 noundef %slice_base, <vscale x 2 x i64> %zn.coerce0, <vscale x 2 x i64> %zn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zn.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 1
# |   %6 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv2i64(i32 %2, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv2i64(i32, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svsub_write_single2_u64(i32 noundef %slice_base, <vscale x 2 x i64> %zn.coerce0, <vscale x 2 x i64> %zn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zn.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 1
# |   %6 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv2i64(i32 %2, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svsub_write_single4_s32(i32 noundef %slice_base, <vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %zn.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 0
# |   %7 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 1
# |   %8 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 2
# |   %9 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 3
# |   %10 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sub.write.single.za.vg1x4.nxv4i32(i32 %4, <vscale x 4 x i32> %6, <vscale x 4 x i32> %7, <vscale x 4 x i32> %8, <vscale x 4 x i32> %9, <vscale x 4 x i32> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.sub.write.single.za.vg1x4.nxv4i32(i32, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svsub_write_single4_u32(i32 noundef %slice_base, <vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i
# | ...
# `---data was truncated (10240/67892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005622c9a86eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005622c9a83e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005622c9a8762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9118f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9118f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9118f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9118f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005622c9a1cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005622c9a1ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005622c9a018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005622c96b0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005622c96b0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9118f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9118f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9118f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005622c96b0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c (207 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @test_svadda_f16(<vscale x 16 x i1> %pg, half noundef %initial, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %initial.addr = alloca half, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store half %initial, ptr %initial.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load half, ptr %initial.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call half @llvm.aarch64.sve.fadda.nxv8f16(<vscale x 8 x i1> %3, half %1, <vscale x 8 x half> %2)
# |   ret half %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.sve.fadda.nxv8f16(<vscale x 8 x i1>, half, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @test_svadda_f32(<vscale x 16 x i1> %pg, float noundef %initial, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %initial.addr = alloca float, align 4
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store float %initial, ptr %initial.addr, align 4
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load float, ptr %initial.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call float @llvm.aarch64.sve.fadda.nxv4f32(<vscale x 4 x i1> %3, float %1, <vscale x 4 x float> %2)
# |   ret float %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.sve.fadda.nxv4f32(<vscale x 4 x i1>, float, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @test_svadda_f64(<vscale x 16 x i1> %pg, double noundef %initial, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %initial.addr = alloca double, align 8
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store double %initial, ptr %initial.addr, align 8
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load double, ptr %initial.addr, align 8
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call double @llvm.aarch64.sve.fadda.nxv2f64(<vscale x 2 x i1> %3, double %1, <vscale x 2 x double> %2)
# |   ret double %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.sve.fadda.nxv2f64(<vscale x 2 x i1>, double, <vscale x 2 x double>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e3346e6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e3346e3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e3346e762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f52d6c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f52d6ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f52d6c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f52d6c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e33467cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e33467ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e3346618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e334310e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e334310b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f52d6c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f52d6c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f52d6c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e334310a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c (208 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svextb_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.sxtb.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sxtb.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svextb_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sxtb.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sxtb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextb_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.sxtb.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sxtb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svextb_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.uxtb.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uxtb.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svextb_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.uxtb.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uxtb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextb_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtb.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uxtb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svextb_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.sxtb.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svextb_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.sxtb.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextb_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.sxtb.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svextb_u16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.ad
# | ...
# `---data was truncated (10240/17434) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005650fa489eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005650fa486e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005650fa48a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2dc6849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2dc68a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2dc6849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2dc6831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005650fa41fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005650fa41fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005650fa4048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005650fa0b3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005650fa0b3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2dc6832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2dc68330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2dc68330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005650fa0b3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c (209 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdech_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdech.n32(i32 %0, i32 31, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqdech.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdech_n_s32_1(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdech.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdech_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqdech.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqdech.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdech_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqdech.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqdech.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdech_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqdech.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uqdech.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdech_pat_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdech.n32(i32 %0, i32 10, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdech_pat_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqdech.n64(i64 %0, i32 11, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdech_pat_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqdech.n32(i32 %0, i32 12, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdech_pat_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqdech.n64(i64 %0, i32 13, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqdech_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqdech.nxv8i16(<vscale x 8 x i16> %0, i32 31, i32 16)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqdech.nxv8i16(<vscale x 8 x i16>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqdech_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16> %0, i32 31, i32 1)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqdech_pat_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqdech.nxv8i16(<vscale x 8 x i16> %0, i32 29, i32 16)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqdech_pat_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16> %0, i32 30, i32 1)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000562549c68eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562549c65e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562549c6962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f87d2b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87d2b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f87d2b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87d2aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562549bfebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562549bfea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562549be38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562549892e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562549892b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f87d2aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87d2aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87d2aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562549892a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c (210 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadrd_u32base_s32index(<vscale x 4 x i32> %bases, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.adrd.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.adrd.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadrd_u64base_s64index(<vscale x 2 x i64> %bases, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.adrd.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.adrd.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadrd_u32base_u32index(<vscale x 4 x i32> %bases, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.adrd.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadrd_u64base_u64index(<vscale x 2 x i64> %bases, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.adrd.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055f0c6221eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f0c621ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f0c622262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faefd705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faefd75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faefd705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faefd6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f0c61b7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f0c61b7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f0c619c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f0c5e4be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f0c5e4bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faefd6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faefd6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faefd6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f0c5e4ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c (211 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmaxnm_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmaxnm_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmaxnm_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmaxnm_bf16_n_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmaxnm_bf16_n_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmaxnm_bf16_n_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005607cba5aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005607cba57e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005607cba5b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f46b9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f46b9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f46b9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f46b9f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607cb9f0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005607cb9f0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005607cb9d58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005607cb684e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005607cb684b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f46b9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f46b9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f46b9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607cb684a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c (212 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrevb_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.revb.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.revb.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevb_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.revb.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.revb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevb_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revb.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.revb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrevb_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.revb.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevb_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.revb.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevb_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revb.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrevb_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.revb.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevb_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.revb.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevb_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.revb.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrevb_u16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.revb.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevb_u32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |  
# | ...
# `---data was truncated (10240/16804) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000555abe2a1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555abe29ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555abe2a262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb660649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb6606a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb660649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb660631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555abe237bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555abe237a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555abe21c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555abdecbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555abdecbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb660632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb6606330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb6606330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555abdecba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c (213 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmopa_za16_mf8_m(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %4 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %4)
# |   call void @llvm.aarch64.sme.fp8.fmopa.za16(i32 1, <vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmopa.za16(i32 immarg, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmopa_za32_mf8_m(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %4 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %4)
# |   call void @llvm.aarch64.sme.fp8.fmopa.za32(i32 3, <vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmopa.za32(i32 immarg, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme-f8f16,+sme-f8f32" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005570a8ddeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005570a8ddbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005570a8ddf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f27cff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f27cff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f27cff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f27cff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005570a8d74bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005570a8d74a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005570a8d598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005570a8a08e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005570a8a08b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f27cff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f27cff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f27cff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005570a8a08a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c (214 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1   -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svpmov_lane_u16_m(<vscale x 8 x i16> %zn, <vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %2, i32 1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svpmov_lane_s16_m(<vscale x 8 x i16> %zn, <vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %2, i32 1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svpmov_lane_u32_m(<vscale x 4 x i32> %zn, <vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %2, i32 1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svpmov_lane_s32_m(<vscale x 4 x i32> %zn, <vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %2, i32 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svpmov_lane_u64_m(<vscale x 2 x i64> %zn, <vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %2, i32 1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svpmov_lane_s64_m(<vscale x 2 x i64> %zn, <vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %2, i32 7)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svpmov_lane_u8_z(<vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv16i8(<vscale x 16 x i1> %0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv16i8(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svpmov_lane_s8_z(<vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv16i8(<vscale x 16 x i1> %0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svpmov_lane_u16_z(<vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv8i16(<vscale x 8 x i1> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv8i16(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svpmov_lane_s16_z(<vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv8i16(<vscale x 8 x i1> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svpmov_lane_u32_z(<vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv4i32(<vscale x 4 x i1> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv4i32(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svpmov_lane_s32_z(<vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv4i32(<vscale x 4 x i1> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svpmov_lane_u64_z(<vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# | ...
# `---data was truncated (10240/11780) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000564e84279eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564e84276e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564e8427a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4928733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f492878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4928733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f492871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564e8420fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564e8420fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564e841f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564e83ea3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564e83ea3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f492871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f492871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f492871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564e83ea3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c (215 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4asu_vv_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4asu_vv_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale
# | ...
# `---data was truncated (10240/14485) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560e9ce01eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560e9cdfee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560e9ce0262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f52ace49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f52acea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f52ace49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f52ace31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e9cd97bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560e9cd97a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560e9cd7c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560e9ca2be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560e9ca2bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f52ace32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f52ace330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f52ace330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e9ca2ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-vls-subscript-ops.c (216 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-subscript-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone -mvscale-min=4 -mvscale-max=4   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local i16 @subscript_int16(<vscale x 8 x i16> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <32 x i16> %0, i64 %1
# |   ret i16 %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local i16 @subscript_uint16(<vscale x 8 x i16> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <32 x i16> %0, i64 %1
# |   ret i16 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local i32 @subscript_int32(<vscale x 4 x i32> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <16 x i32> %0, i64 %1
# |   ret i32 %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local i32 @subscript_uint32(<vscale x 4 x i32> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <16 x i32> %0, i64 %1
# |   ret i32 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local i64 @subscript_int64(<vscale x 2 x i64> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i64>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %a.coerce, i64 0)
# |   store <8 x i64> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <8 x i64>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <8 x i64> %0, i64 %1
# |   ret i64 %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local i64 @subscript_uint64(<vscale x 2 x i64> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i64>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %a.coerce, i64 0)
# |   store <8 x i64> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <8 x i64>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <8 x i64> %0, i64 %1
# |   ret i64 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local half @subscript_float16(<vscale x 8 x half> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <32 x half>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> %a.coerce, i64 0)
# |   store <32 x half> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <32 x half>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <32 x half> %0, i64 %1
# |   ret half %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local float @subscript_float32(<vscale x 4 x float> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x float>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> %a.coerce, i64 0)
# |   store <16 x float> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <16 x float>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <16 x float> %0, i64 %1
# |   ret float %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local double @subscript_float64(<vscale x 2 x double> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x double>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> %a.coerce, i64 0)
# |   store <8 x double> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <8 x double>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <8 x double> %0, i64 %1
# |   ret double %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double>, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,4) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x0000557cec932eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557cec92fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557cec93362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd5e1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd5e178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd5e1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd5e171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557cec8c8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557cec8c8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557cec8ad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557cec55ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557cec55cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd5e171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd5e171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd5e171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557cec55ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c (217 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclasta_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %fallback, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 16 x i8>, align 16
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.clasta.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.clasta.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclasta_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %fallback, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 8 x i16>, align 16
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.clasta.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.clasta.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclasta_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %fallback, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 4 x i32>, align 16
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.clasta.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.clasta.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svclasta_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %fallback, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.clasta.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.clasta.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclasta_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %fallback, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 16 x i8>, align 16
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.clasta.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclasta_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %fallback, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 8 x i16>, align 16
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.clasta.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclasta_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %fallback, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 4 x i32>, align 16
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.clasta.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svclasta_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %fallback, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.clasta.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svclasta_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %fallback, <vscale x 8 x half> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 8 x half>, align 16
# |   %data.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 8 x half> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.clasta.nxv8f16(<vscale x 8 x i
# | ...
# `---data was truncated (10240/26390) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x0000556a4e813eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556a4e810e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556a4e81462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f72dad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f72dad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f72dad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f72dad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556a4e7a9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556a4e7a9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556a4e78e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556a4e43de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556a4e43db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f72dad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f72dad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f72dad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556a4e43da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/poly128.c (218 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/poly128.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon  -disable-O0-optnone -ffp-contract=fast -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa   | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -ffp-contract=fast -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vldrq_p128(ptr noundef %ptr) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %__ret = alloca i128, align 16
# |   %ref.tmp = alloca i128, align 16
# |   %tmp = alloca i128, align 16
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i128, ptr %0, align 16
# |   store i128 %1, ptr %ref.tmp, align 16
# |   %2 = load i128, ptr %ref.tmp, align 16
# |   store i128 %2, ptr %__ret, align 16
# |   %3 = load i128, ptr %__ret, align 16
# |   store i128 %3, ptr %tmp, align 16
# |   %4 = load i128, ptr %tmp, align 16
# |   ret i128 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_ld_st_p128(ptr noundef %ptr) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %__s1 = alloca i128, align 16
# |   %__ret = alloca i128, align 16
# |   %ref.tmp = alloca i128, align 16
# |   %tmp = alloca i128, align 16
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i128, ptr %0, align 16
# |   store i128 %1, ptr %ref.tmp, align 16
# |   %2 = load i128, ptr %ref.tmp, align 16
# |   store i128 %2, ptr %__ret, align 16
# |   %3 = load i128, ptr %__ret, align 16
# |   store i128 %3, ptr %tmp, align 16
# |   %4 = load i128, ptr %tmp, align 16
# |   store i128 %4, ptr %__s1, align 16
# |   %5 = load ptr, ptr %ptr.addr, align 8
# |   %add.ptr = getelementptr inbounds i128, ptr %5, i64 1
# |   %6 = load i128, ptr %__s1, align 16
# |   store i128 %6, ptr %add.ptr, align 16
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vmull_p64(i64 noundef %a, i64 noundef %b) #1 {
# | entry:
# |   %__p0.addr.i = alloca i64, align 8
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca i128, align 16
# |   %ref.tmp.i = alloca i128, align 16
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   store i64 %0, ptr %__p0.addr.i, align 8
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load i64, ptr %__p0.addr.i, align 8
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   %vmull_p64.i = call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %2, i64 %3)
# |   %vmull_p641.i = bitcast <16 x i8> %vmull_p64.i to i128
# |   store i128 %vmull_p641.i, ptr %ref.tmp.i, align 16
# |   %4 = load i128, ptr %ref.tmp.i, align 16
# |   store i128 %4, ptr %__ret.i, align 16
# |   %5 = load i128, ptr %__ret.i, align 16
# |   ret i128 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vmull_high_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 {
# | entry:
# |   %__p0.addr.i3 = alloca <2 x i64>, align 16
# |   %__ret.i4 = alloca <1 x i64>, align 8
# |   %__p0.addr.i1 = alloca <2 x i64>, align 16
# |   %__ret.i2 = alloca <1 x i64>, align 8
# |   %__p0.addr.i.i = alloca i64, align 8
# |   %__p1.addr.i.i = alloca i64, align 8
# |   %__ret.i.i = alloca i128, align 16
# |   %ref.tmp.i.i = alloca i128, align 16
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__p1.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %ref.tmp.i = alloca <1 x i64>, align 8
# |   %ref.tmp1.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <2 x i64>, align 16
# |   %b.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %2, ptr %__p0.addr.i3, align 16
# |   %3 = load <2 x i64>, ptr %__p0.addr.i3, align 16
# |   %4 = load <2 x i64>, ptr %__p0.addr.i3, align 16
# |   %shuffle.i5 = shufflevector <2 x i64> %3, <2 x i64> %4, <1 x i32> <i32 1>
# |   store <1 x i64> %shuffle.i5, ptr %__ret.i4, align 8
# |   %5 = load <1 x i64>, ptr %__ret.i4, align 8
# |   store <1 x i64> %5, ptr %ref.tmp.i, align 8
# |   %6 = load i64, ptr %ref.tmp.i, align 8
# |   %7 = load <2 x i64>, ptr %__p1.addr.i, align 16
# |   store <2 x i64> %7, ptr %__p0.addr.i1, align 16
# |   %8 = load <2 x i64>, ptr %__p0.addr.i1, align 16
# |   %9 = load <2 x i64>, ptr %__p0.addr.i1, align 16
# |   %shuffle.i = shufflevector <2 x i64> %8, <2 x i64> %9, <1 x i32> <i32 1>
# |   store <1 x i64> %shuffle.i, ptr %__ret.i2, align 8
# |   %10 = load <1 x i64>, ptr %__ret.i2, align 8
# |   store <1 x i64> %10, ptr %ref.tmp1.i, align 8
# |   %11 = load i64, ptr %ref.tmp1.i, align 8
# |   store i64 %6, ptr %__p0.addr.i.i, align 8
# |   store i64 %11, ptr %__p1.addr.i.i, align 8
# |   %12 = load i64, ptr %__p0.addr.i.i, align 8
# |   %13 = load i64, ptr %__p1.addr.i.i, align 8
# |   %vmull_p64.i.i = call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %12, i64 %13)
# |   %vmull_p641.i.i = bitcast <16 x i8> %vmull_p64.i.i to i128
# |   store i128 %vmull_p641.i.i, ptr %ref.tmp.i.i, align 16
# |   %14 = load i128, ptr %ref.tmp.i.i, align 16
# |   store i128 %14, ptr %__ret.i.i, align 16
# |   %15 = load i128, ptr %__ret.i.i, align 16
# |   store i128 %15, ptr %__ret.i, align 16
# |   %16 = load i128, ptr %__ret.i, align 16
# |   ret i128 %16
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_s64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_u64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.ad
# | ...
# `---data was truncated (10240/19795) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000056248b426eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056248b423e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056248b42762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdecc849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdecc8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdecc849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdecc831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056248b3bcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056248b3bca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056248b3a18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056248b050e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056248b050b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdecc832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdecc8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdecc8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056248b050a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/andv.c (219 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/andv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svandv_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.andv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.andv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svandv_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.andv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.andv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svandv_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.andv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.andv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svandv_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.andv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.andv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svandv_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.andv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svandv_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.andv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svandv_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.andv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svandv_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.andv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S
# |  #0 0x000055f535eb7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f535eb4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f535eb862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f754501bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f75450725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f754501ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7545003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f535e4dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f535e4da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f535e328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f535ae1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f535ae1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7545004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f75450050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f75450050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f535ae1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c (220 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x1_za32_s8_s8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smop4a.wide.2x1.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4a.wide.2x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_2x1_za32_s8_s8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smop4s.wide.2x1.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4s.wide.2x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x1_za32_u8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umop4a.wide.2x1.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4a.wide.2x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_2x1_za32_u8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umop4s.wide.2x1.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4s.wide.2x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x1_za32_s8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sumop4a.wide.2x1.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.sumop4a.wide.2x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_2x1_za32_s8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sumop4s.wide.2x1.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.sumop4s.wide.2x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x1_za32_u8_s8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <
# | ...
# `---data was truncated (10240/50499) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005564cd004eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005564cd001e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005564cd00562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f196101bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f19610725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f196101ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1961003507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005564ccf9abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005564ccf9aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005564ccf7f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005564ccc2ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005564ccc2eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1961004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f19610050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f19610050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005564ccc2ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/nand.c (221 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/nand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svnand_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.nand.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.nand.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x00005583e7509eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005583e7506e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005583e750a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7f14a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7f14aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7f14a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7f14a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005583e749fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005583e749fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005583e74848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005583e7133e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005583e7133b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7f14a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7f14a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7f14a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005583e7133a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/arm-vector_type-params-returns.c (222 of 27911)
******************** TEST 'Clang :: CodeGen/arm-vector_type-params-returns.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -DSVE_HEADER -triple aarch64 -target-feature +sve -emit-llvm -O2 -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -DSVE_HEADER -triple aarch64 -target-feature +sve -emit-llvm -O2 -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <8 x half> @test_ret_v8f16(<8 x half> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <8 x half> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <4 x float> @test_ret_v4f32(<4 x float> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <4 x float> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <2 x double> @test_ret_v2f64(<2 x double> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <2 x double> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <8 x bfloat> @test_ret_v8bf16(<8 x bfloat> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <8 x bfloat> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <16 x i8> @test_ret_v16s8(<16 x i8> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <16 x i8> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <8 x i16> @test_ret_v8s16(<8 x i16> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <8 x i16> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <4 x i32> @test_ret_v32s4(<4 x i32> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <4 x i32> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <2 x i64> @test_ret_v64s2(<2 x i64> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <2 x i64> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <16 x i8> @test_ret_v16u8(<16 x i8> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <16 x i8> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <8 x i16> @test_ret_v8u16(<8 x i16> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <8 x i16> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <4 x i32> @test_ret_v32u4(<4 x i32> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <4 x i32> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <2 x i64> @test_ret_v64u2(<2 x i64> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <2 x i64> %v
# | }
# | 
# | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | !llvm.errno.tbaa = !{!4}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# | !4 = !{!5, !6, i64 0}
# | !5 = !{!"__libc_errno", !6, i64 0}
# | !6 = !{!"int", !7, i64 0}
# | !7 = !{!"omnipotent char", !8, i64 0}
# | !8 = !{!"Simple C/C++ TBAA"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055f0dc81beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f0dc818e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f0dc81c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7bf0049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7bf00a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7bf0049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7bf0031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f0dc7b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f0dc7b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f0dc7968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f0dc445e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f0dc445b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7bf0032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7bf00330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7bf00330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f0dc445a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/pfalse.c (223 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/pfalse.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o -        /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpfalse_b() #0 {
# | entry:
# |   ret <vscale x 16 x i1> zeroinitializer
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x0000561288e8aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561288e87e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561288e8b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0556e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0556ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0556e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0556e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561288e20bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561288e20a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561288e058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561288ab4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561288ab4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0556e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0556e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0556e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561288ab4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c (224 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcvt_s16_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcvt_s16_f16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcvt_s16_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16(<vscale x 8 x i16> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcvt_u16_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcvt_u16_f16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcvt_u16_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16(<vscale x 8 x i16> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcvt_s32_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f16(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f16(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcvt_s32_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.nxv4i32.nxv4f32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.nxv4i32.nxv4f32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcvt_s32_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f64(<vscale x 4 x i32> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f64(<vscale x 4 x i32>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcvt_s32_f16_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f16(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 8 x half
# | ...
# `---data was truncated (10240/88476) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d898d5deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d898d5ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d898d5e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f807b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f807b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f807b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f807b31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d898cf3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d898cf3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d898cd88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d898987e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d898987b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f807b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f807b31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f807b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d898987a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c (225 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_multi_za32_vg1x2_u16(i32 noundef %slice_base, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zm.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 1
# |   %8 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 1
# |   call void @llvm.aarch64.sme.udot.za32.vg1x2.nxv8i16(i32 %4, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %9, <vscale x 8 x i16> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.udot.za32.vg1x2.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_multi_za32_vg1x4_u16(i32 noundef %slice_base, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zn.coerce2, <vscale x 8 x i16> %zn.coerce3, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1, <vscale x 8 x i16> %zm.coerce2, <vscale x 8 x i16> %zm.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zn.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   %4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %5 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, <vscale x 8 x i16> %zm.coerce1, 1
# |   %6 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5, <vscale x 8 x i16> %zm.coerce2, 2
# |   %7 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6, <vscale x 8 x i16> %zm.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %7, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %zm2, ptr %zm.addr, align 16
# |   %8 = load i32, ptr %slice_base.addr, align 4
# |   %9 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %10 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %9, 0
# |   %11 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %9, 1
# |   %12 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %9, 2
# |   %13 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %9, 3
# |   %14 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm.addr, align 16
# |   %15 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %14, 0
# |   %16 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %14, 1
# |   %17 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %14, 2
# |   %18 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %14, 3
# |   call void @llvm.aarch64.sme.udot.za32.vg1x4.nxv8i16(i32 %8, <vscale x 8 x i16> %10, <vscale x 8 x i16> %11, <vscale x 8 x i16> %12, <vscale x 8 x i16> %13, <vscale x 8 x i16> %15, <vscale x 8 x i16> %16, <vscale x 8 x i16> %17, <vscale x 8 x i16> %18)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.udot.za32.vg1x4.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_multi_za32_vg1x2_u8(i32 noundef %slice_base, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %8, 0
# |   %10 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %8, 1
# |   call void @llvm.aarch64.sme.udot.za32.vg1x2.nxv16i8(i32 %4, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.udot.za32.vg1x2.nxv16i8(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_multi_za32_vg1x4_u8(i32 noundef %slice_base, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1, <vscale x 16 x i8> %zm.coerce2, <vscale x 16 x i8> %zm.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align
# | ...
# `---data was truncated (10240/127452) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055edb93aeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055edb93abe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055edb93af62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd9ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd9ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd9ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd9ff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055edb9344bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055edb9344a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055edb93298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055edb8fd8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055edb8fd8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdd9ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd9ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd9ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055edb8fd8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c (226 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrecpx_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frecpx.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frecpx.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrecpx_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frecpx.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frecpx.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrecpx_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frecpx.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frecpx.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrecpx_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.frecpx.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrecpx_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frecpx.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrecpx_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frecpx.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrecpx_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frecpx.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrecpx_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frecpx.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrecpx_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frecpx.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000556f361eaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556f361e7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556f361eb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f42d1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42d1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f42d1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f42d1d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556f36180bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556f36180a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556f361658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556f35e14e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556f35e14b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f42d1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42d1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42d1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556f35e14a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c (227 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vset_v_f16m1_f16m2(<vscale x 8 x half> %dest, i64 noundef %index, <vscale x 4 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 8 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 0)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vset_v_f16m1_f16m4(<vscale x 16 x half> %dest, i64 noundef %index, <vscale x 4 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 16 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 0)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vset_v_f16m2_f16m4(<vscale x 16 x half> %dest, i64 noundef %index, <vscale x 8 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 16 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half> %0, <vscale x 8 x half> %1, i64 0)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vset_v_f16m1_f16m8(<vscale x 32 x half> %dest, i64 noundef %index, <vscale x 4 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 0)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vset_v_f16m2_f16m8(<vscale x 32 x half> %dest, i64 noundef %index, <vscale x 8 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> %0, <vscale x 8 x half> %1, i64 0)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vset_v_f16m4_f16m8(<vscale x 32 x half> %dest, i64 noundef %index, <vscale x 16 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 16 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half> %0, <vscale x 16 x half> %1, i64 0)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half>, <vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vset_v_f32m1_f32m2(<vscale x 4 x float> %dest, i64 noundef %index, <vscale x 2 x float> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 4 x float> %dest, ptr %dest.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 2 x float> %val, ptr %val.addr, align 4
# |   %0 = load <vscale x 4 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %val.addr, align 4
# |   %2 = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 0)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float>, <vscale x 2 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vset_v_f32m1_f32m4(<vscale x 8 x float> %dest, i64 noundef %index, <vscale x 2 x float> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 8 x float> %dest, ptr %dest.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 2 x float> %val, ptr %val.addr, align 4
# |   %0 = load <vscale x 8 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %val.addr, align 4
# |   %2 = call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv2f32(<vscale x 8 x float> %0, <vscale x 2 x float> %1, i64 0)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv2f32(<vscale x 8 x float>, <vscale x 2 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vset_v_f32m2_f32m4(<vscale x 8 x float> %dest, i64 noundef %index, <vscale x 4 x float> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 4 x float>, align 4
# |   store <vscale x 8 x float> %dest, ptr %dest.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x float> %val, ptr %val.addr, align 4
# |   %0 = load <vscale x 8 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %val.addr, align 4
# |   %2 = call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv4f32(<vscale x 8 x float> %0, <vscale x 4 x float> %1, i64 0)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv4f32(<vscale x 8 x float>, <vscale x 4 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vset_v_f32m1_f32m8(<vscale x 16 x float> %dest, i64 noundef %index, <vscale x 2 x float> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 16 x float> %dest, ptr %dest.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 2 x float> %val, ptr %val.addr, align 4
# |   %0 = load <vscale x 16 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %val.addr, align 4
# |   %2 = call <vscale x 16 x float> @llvm.vector.insert.nxv16f32.nxv2f32(<vscale x 16 x float> %0, <vscale x 2 x float> %1, i64 0)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x float
# | ...
# `---data was truncated (10240/338684) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b7dcceceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b7dcce9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b7dcced62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faa06333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faa0638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faa06333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faa0631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b7dcc82bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b7dcc82a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b7dcc678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b7dc916e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b7dc916b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faa0631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faa0631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faa0631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b7dc916a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c (228 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclastb_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %fallback, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 16 x i8>, align 16
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.clastb.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.clastb.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclastb_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %fallback, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 8 x i16>, align 16
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.clastb.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.clastb.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclastb_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %fallback, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 4 x i32>, align 16
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.clastb.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.clastb.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svclastb_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %fallback, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.clastb.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.clastb.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclastb_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %fallback, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 16 x i8>, align 16
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.clastb.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclastb_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %fallback, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 8 x i16>, align 16
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.clastb.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclastb_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %fallback, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 4 x i32>, align 16
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.clastb.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svclastb_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %fallback, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.clastb.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svclastb_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %fallback, <vscale x 8 x half> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 8 x half>, align 16
# |   %data.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 8 x half> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.clastb.nxv8f16(<vscale x 8 x i
# | ...
# `---data was truncated (10240/26390) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055a8725e6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a8725e3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a8725e762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc20c41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc20c4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc20c41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc20c403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a87257cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a87257ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a8725618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a872210e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a872210b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc20c404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc20c4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc20c4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a872210a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem.c (229 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vmuls_lane_f32(float noundef %a, <2 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca float, align 4
# |   %b.addr = alloca <2 x float>, align 8
# |   %__ret_571 = alloca float, align 4
# |   %__s0_571 = alloca float, align 4
# |   %__s1_571 = alloca <2 x float>, align 8
# |   %__ret = alloca float, align 4
# |   %__s0 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca float, align 4
# |   %tmp = alloca float, align 4
# |   %tmp1 = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__s0_571, align 4
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %1, ptr %__s1_571, align 8
# |   %2 = load float, ptr %__s0_571, align 4
# |   %3 = load <2 x float>, ptr %__s1_571, align 8
# |   store <2 x float> %3, ptr %__s0, align 8
# |   %4 = load <2 x float>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x float> %4, i32 1
# |   store float %vget_lane, ptr %ref.tmp, align 4
# |   %5 = load float, ptr %ref.tmp, align 4
# |   store float %5, ptr %__ret, align 4
# |   %6 = load float, ptr %__ret, align 4
# |   store float %6, ptr %tmp, align 4
# |   %7 = load float, ptr %tmp, align 4
# |   %mul = fmul float %2, %7
# |   store float %mul, ptr %__ret_571, align 4
# |   %8 = load float, ptr %__ret_571, align 4
# |   store float %8, ptr %tmp1, align 4
# |   %9 = load float, ptr %tmp1, align 4
# |   ret float %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_vmuld_lane_f64(double noundef %a, <1 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca double, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %__ret_570 = alloca double, align 8
# |   %__s0_570 = alloca double, align 8
# |   %__s1_570 = alloca <1 x double>, align 8
# |   %__ret = alloca double, align 8
# |   %__s0 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca double, align 8
# |   %tmp = alloca double, align 8
# |   %tmp1 = alloca double, align 8
# |   store double %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   %0 = load double, ptr %a.addr, align 8
# |   store double %0, ptr %__s0_570, align 8
# |   %1 = load <1 x double>, ptr %b.addr, align 8
# |   store <1 x double> %1, ptr %__s1_570, align 8
# |   %2 = load double, ptr %__s0_570, align 8
# |   %3 = load <1 x double>, ptr %__s1_570, align 8
# |   store <1 x double> %3, ptr %__s0, align 8
# |   %4 = load <1 x double>, ptr %__s0, align 8
# |   %vget_lane = extractelement <1 x double> %4, i32 0
# |   store double %vget_lane, ptr %ref.tmp, align 8
# |   %5 = load double, ptr %ref.tmp, align 8
# |   store double %5, ptr %__ret, align 8
# |   %6 = load double, ptr %__ret, align 8
# |   store double %6, ptr %tmp, align 8
# |   %7 = load double, ptr %tmp, align 8
# |   %mul = fmul double %2, %7
# |   store double %mul, ptr %__ret_570, align 8
# |   %8 = load double, ptr %__ret_570, align 8
# |   store double %8, ptr %tmp1, align 8
# |   %9 = load double, ptr %tmp1, align 8
# |   ret double %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vmuls_laneq_f32(float noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca float, align 4
# |   %b.addr = alloca <4 x float>, align 16
# |   %__ret_577 = alloca float, align 4
# |   %__s0_577 = alloca float, align 4
# |   %__s1_577 = alloca <4 x float>, align 16
# |   %__ret = alloca float, align 4
# |   %__s0 = alloca <4 x float>, align 16
# |   %ref.tmp = alloca float, align 4
# |   %tmp = alloca float, align 4
# |   %tmp1 = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__s0_577, align 4
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x float> %1, ptr %__s1_577, align 16
# |   %2 = load float, ptr %__s0_577, align 4
# |   %3 = load <4 x float>, ptr %__s1_577, align 16
# |   store <4 x float> %3, ptr %__s0, align 16
# |   %4 = load <4 x float>, ptr %__s0, align 16
# |   %vgetq_lane = extractelement <4 x float> %4, i32 3
# |   store float %vgetq_lane, ptr %ref.tmp, align 4
# |   %5 = load float, ptr %ref.tmp, align 4
# |   store float %5, ptr %__ret, align 4
# |   %6 = load float, ptr %__ret, align 4
# |   store float %6, ptr %tmp, align 4
# |   %7 = load float, ptr %tmp, align 4
# |   %mul = fmul float %2, %7
# |   store float %mul, ptr %__ret_577, align 4
# |   %8 = load float, ptr %__ret_577, align 4
# |   store float %8, ptr %tmp1, align 4
# |   %9 = load float, ptr %tmp1, align 4
# |   ret float %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_vmuld_laneq_f64(double noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca double, align 8
# |   %b.addr = alloca <2 x double>, align 16
# |   %__ret_575 = alloca double, align 8
# |   %__s0_575 = alloca double, align 8
# |   %__s1_575 = alloca <2 x double>, align 16
# |   %__ret = alloca double, align 8
# |   %__s0 = alloca <2 x double>, align 16
# |   %ref.tmp = alloca double, align 8
# |   %tmp = alloca double, align 8
# |   %tmp1 = alloca double, align 8
# |   store double %a, ptr %a.addr, align 8
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   %0 = load double, ptr %a.addr, align 8
# |   store double %0, ptr %__s0_575, align 8
# |   %1 = load <2 x double>, ptr %b.addr, align 16
# |   store <2 x double> %1, ptr %__s1_575, align 16
# |   %2 = load double, ptr %__s0_575, align 8
# |   %3 = load <2 x double>, ptr %__s1_575, align 16
# |   store <2 x double> %3, ptr %__s0, align 16
# |   %4 = load <2 x double>, ptr %__s0, align 16
# |   %vgetq_lane = extractelement <2 x double> %4, i32 1
# |   store double %vgetq_lane, ptr %ref.tmp, align 8
# |   %5 = load double, ptr %ref.tmp, align 8
# |   store double %5, ptr %__ret, align 8
# |   %6 = load double, ptr %__ret, align 8
# |   store double %6, ptr %tmp, align 8
# |   %7 = load double, ptr %tmp, align 8
# |   %mul = fmul double %2, %7
# |   store double %mul, ptr %__ret_575, align 8
# |   %8 = load double, ptr %__ret_575, align 8
# |   store double %8, ptr %tmp1, align 8
# |   %9 = load double, ptr %tmp1, align 8
# |   ret double %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vmul_n_f64(<1 x double> noundef %a, double noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__p1.addr.i = alloca double, align 8
# |   %__ret.i = alloca <1 x double>, align 8
# |   %ref.tmp.i = alloca <1 x double>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   %b.addr = alloca double, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   store double %b, ptr %b.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   %1 = load double, ptr %b.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   store double %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x double>, ptr %__p0.addr.i, align 8
# |   %3 = load double, ptr %__p1.addr.i, align 8
# |   %4 = bitcast <1 x double> %2 to double
# |   %5 = fmul double %4, %3
# |   store double %5, ptr %ref.tmp.i, align 8
# |   %6 = load <1 x double>, ptr %ref.tmp.i, align 8
# |   store <1 x double> %6, ptr %__ret.i, align 8
# |   %7 = load <1 x double>, ptr %__ret.i, align 8
# |   ret <1 x double> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vmulxs_lane_f32(float noundef %a, <2 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca float, align 4
# |   %__p1.addr.i = alloca float, align 4
# |   %__ret.i = alloca float, align 4
# |   %ref.tmp.i = alloca float, align 4
# |   %a.addr = alloca float, align 4
# |   %b.addr = alloca <2 x float>, align 8
# |   %__ret_626 = alloca float, align 4
# |   %__s0_626 = alloca float, align 4
# |   %__s1_626 = alloca <2 x float>, align 8
# |   %__ret = alloca float, align 4
# |   %__s0 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca float, align 4
# |   %tmp = alloca float, align 4
# |   %tmp1 = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__s0_626, align 4
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %1, ptr %__s1_626, align 8
# |   %2 = load float, ptr %__s0_626, align 4
# |   %3 = load <2 x float>, ptr %__s1_626, align 8
# |   store <2 x float> %3, ptr %__s0, align 8
# |   %4 = load <2 x float>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x float> %4, i32 1
# |   store float %vget_lane, ptr %ref.tmp, align 4
# |   %5 = load float, ptr %ref.tmp, align 4
# |   store float %5, ptr %__ret, align 4
# |   %6 = load float, ptr %__ret, align 4
# |   store float %6, ptr %tmp, align 4
# |   %7 = load float, ptr %tmp, align 4
# |   store float %2, ptr %__p0.addr.i, align 4
# |   store float %7, ptr %__p1.addr.i, align 4
# |   %8 = load float, ptr %__p0.addr.i, align 4
# |   %9 = load float, ptr %__p1.addr.i, align 4
# |   %vmulxs_f32.i = call float @llvm.aarch64.neon.fmulx.f32(float %8, float %9)
# |   store float %vmulxs_f32.i, ptr %ref.tmp.i, align 4
# |   %10 = load float, ptr %ref.tmp.i, align 4
# |   store float %10, ptr %__ret.i, align 4
# |   %11 = load float, ptr %__ret.i, align 4
# |   store float %11, ptr %__ret_626, align 4
# |   %12 = load float, ptr %__ret_626, align 4
# |   store float %12, ptr %tmp1, align 4
# |   %13 = load float, ptr %tmp1, align 4
# |   ret float %13
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vmulxs_laneq_f32(float noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca float, align 4
# |   %__p1.addr.i = alloca float, align 4
# |   %__ret.i = alloca float, align 4
# |   %ref.tmp.i = alloca float, align 4
# |   %a.addr = alloca float, align 4
# |   %b.addr = alloca <4 x float>, align 16
# |   %__ret_636 = alloca float, align 4
# |   %__s0_636 = alloca float, align 4
# |   %__s1_636 = alloca <4 x float>, align 16
# |   %__ret = alloca float, align 4
# |   %__s0 = alloca <4 x float>, align 16
# |   %ref.tmp = alloca float, align 4
# |   %tmp = alloca float, align 4
# |   %tmp1 = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__s0_636, align 4
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x float> %1, ptr %__s1_636, align 16
# |   %2 = load float, ptr %__s0_636, align 4
# |   %3 = load <4 x float>, ptr %__s1_636, align 16
# |   store <4 x float> %3, ptr %
# | ...
# `---data was truncated (10240/74804) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000556497d47eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556497d44e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556497d4862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9f68849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9f688a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9f68849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9f68831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556497cddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556497cdda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556497cc28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556497971e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556497971b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9f68832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9f688330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9f688330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556497971a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c (230 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcnot_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.cnot.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.cnot.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcnot_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.cnot.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.cnot.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcnot_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.cnot.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.cnot.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcnot_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.cnot.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.cnot.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcnot_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.cnot.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcnot_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.cnot.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcnot_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.cnot.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcnot_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.cnot.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcnot_s8_m(<vscale x 16 x i8> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i8>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.cnot.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcnot_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.cnot.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcnot_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x
# | ...
# `---data was truncated (10240/21349) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005635fdf0aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005635fdf07e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005635fdf0b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f99b7c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f99b7ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f99b7c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f99b7c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005635fdea0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005635fdea0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005635fde858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005635fdb34e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005635fdb34b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f99b7c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f99b7c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f99b7c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005635fdb34a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c (231 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svext_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ext.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 0)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.ext.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svext_s8_1(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ext.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 255)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svext_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.ext.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 0)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.ext.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svext_s16_1(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.ext.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 127)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svext_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.ext.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 0)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ext.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svext_s32_1(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.ext.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 63)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svext_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.ext.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 0)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ext.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svext_s64_1(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.ext.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 31)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svext_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ext.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 255)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svext_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.ext.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 127)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svext_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.ext.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 63)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svext_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.ext.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 31)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svext_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.ext.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 127)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ext.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svext_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr 
# | ...
# `---data was truncated (10240/12880) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005610c797ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005610c7979e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005610c797d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3505649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f35056a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3505649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3505631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005610c7912bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005610c7912a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005610c78f78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005610c75a6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005610c75a6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3505632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f35056330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f35056330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005610c75a6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c (232 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x2_za32_s8_s8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 0
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 1
# |   call void @llvm.aarch64.sme.smop4a.wide.2x2.nxv16i8(i32 1, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4a.wide.2x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_2x2_za32_s8_s8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 0
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 1
# |   call void @llvm.aarch64.sme.smop4s.wide.2x2.nxv16i8(i32 1, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4s.wide.2x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x2_za32_u8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 0
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 1
# |   call void @llvm.aarch64.sme.umop4a.wide.2x2.nxv16i8(i32 1, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4a.wide.2x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_2x2_za32_u8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 0
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 1
# |   call void @llvm.aarch64.sme.umop4s.wide.2x2.nxv16i8(i32 1, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4s.wide.2x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x2_za32_s8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %
# | ...
# `---data was truncated (10240/74176) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055bb8bb6eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bb8bb6be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bb8bb6f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f588d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f588d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f588d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f588d91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bb8bb04bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bb8bb04a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bb8bae98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bb8b798e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bb8b798b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f588d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f588d91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f588d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bb8b798a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c (233 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svrbit_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.rbit.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.rbit.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrbit_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.rbit.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.rbit.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrbit_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.rbit.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.rbit.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrbit_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.rbit.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.rbit.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svrbit_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.rbit.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrbit_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.rbit.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrbit_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.rbit.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrbit_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.rbit.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svrbit_s8_m(<vscale x 16 x i8> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i8>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.rbit.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrbit_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.rbit.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrbit_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x
# | ...
# `---data was truncated (10240/21349) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005589c5ac9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005589c5ac6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005589c5aca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6468449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f64684a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6468449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6468431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589c5a5fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005589c5a5fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005589c5a448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005589c56f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005589c56f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6468432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f64684330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f64684330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005589c56f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c (234 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e7109d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e7109d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e7109d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcb9b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcb9b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcb9b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcb9b71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e71096cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e71096ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e7109518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e710600e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e710600b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcb9b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcb9b71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcb9b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e710600a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c (235 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_f64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_i64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_u64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cc8d8a9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cc8d8a6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cc8d8aa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f425a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f425a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f425a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f425a431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc8d83fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cc8d83fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cc8d8248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cc8d4d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cc8d4d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f425a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f425a4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f425a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc8d4d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/recps.c (236 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/recps.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrecps_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.frecps.x.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frecps.x.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrecps_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.frecps.x.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frecps.x.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrecps_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.frecps.x.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frecps.x.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x0000559043459eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559043456e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055904345a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8588133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f858818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8588133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f858811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005590433efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005590433efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005590433d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559043083e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559043083b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f858811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f858811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f858811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559043083a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c (237 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_bf16mf2x5(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_bf16m1x5(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005604e4856eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005604e4853e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005604e485762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa537649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa5376a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa537649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa537631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005604e47ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005604e47eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005604e47d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005604e4480e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005604e4480b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa537632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa5376330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa5376330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005604e4480a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGenCXX/aarch64-sve-vector-conditional-op.cpp (238 of 27911)
******************** TEST 'Clang :: CodeGenCXX/aarch64-sve-vector-conditional-op.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @_Z9cond_boolu10__SVBool_tS_(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i1>, align 2
# |   %b.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %a, ptr %a.addr, align 2
# |   store <vscale x 16 x i1> %b, ptr %b.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %a.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %b.addr, align 2
# |   %cmp = icmp ult <vscale x 16 x i1> %0, %1
# |   %2 = load <vscale x 16 x i1>, ptr %a.addr, align 2
# |   %3 = load <vscale x 16 x i1>, ptr %b.addr, align 2
# |   %vector_select = select <vscale x 16 x i1> %cmp, <vscale x 16 x i1> %2, <vscale x 16 x i1> %3
# |   ret <vscale x 16 x i1> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @_Z7cond_i8u10__SVInt8_tS_(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %cmp = icmp slt <vscale x 16 x i8> %0, %1
# |   %sext = sext <vscale x 16 x i1> %cmp to <vscale x 16 x i8>
# |   %2 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 16 x i8> %sext, zeroinitializer
# |   %vector_select = select <vscale x 16 x i1> %vector_cond, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3
# |   ret <vscale x 16 x i8> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @_Z7cond_u8u11__SVUint8_tS_(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %cmp = icmp ult <vscale x 16 x i8> %0, %1
# |   %sext = sext <vscale x 16 x i1> %cmp to <vscale x 16 x i8>
# |   %2 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 16 x i8> %sext, zeroinitializer
# |   %vector_select = select <vscale x 16 x i1> %vector_cond, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3
# |   ret <vscale x 16 x i8> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @_Z8cond_i16u11__SVInt16_tS_(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %cmp = icmp slt <vscale x 8 x i16> %0, %1
# |   %sext = sext <vscale x 8 x i1> %cmp to <vscale x 8 x i16>
# |   %2 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 8 x i16> %sext, zeroinitializer
# |   %vector_select = select <vscale x 8 x i1> %vector_cond, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3
# |   ret <vscale x 8 x i16> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @_Z8cond_u16u12__SVUint16_tS_(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %cmp = icmp ult <vscale x 8 x i16> %0, %1
# |   %sext = sext <vscale x 8 x i1> %cmp to <vscale x 8 x i16>
# |   %2 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 8 x i16> %sext, zeroinitializer
# |   %vector_select = select <vscale x 8 x i1> %vector_cond, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3
# |   ret <vscale x 8 x i16> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @_Z8cond_i32u11__SVInt32_tS_(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %cmp = icmp slt <vscale x 4 x i32> %0, %1
# |   %sext = sext <vscale x 4 x i1> %cmp to <vscale x 4 x i32>
# |   %2 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 4 x i32> %sext, zeroinitializer
# |   %vector_select = select <vscale x 4 x i1> %vector_cond, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3
# |   ret <vscale x 4 x i32> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @_Z8cond_u32u12__SVUint32_tS_(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %cmp = icmp ult <vscale x 4 x i32> %0, %1
# |   %sext = sext <vscale x 4 x i1> %cmp to <vscale x 4 x i32>
# |   %2 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 4 x i32> %sext, zeroinitializer
# |   %vector_select = select <vscale x 4 x i1> %vector_cond, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3
# |   ret <vscale x 4 x i32> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @_Z8cond_i64u11__SVInt64_tS_(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %cmp = icmp slt <vscale x 2 x i64> %0, %1
# |   %sext = sext <vscale x 2 x i1> %cmp to <vscale x 2 x i64>
# |   %2 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 2 x i64> %sext, zeroinitializer
# |   %vector_select = select <vscale x 2 x i1> %vector_cond, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3
# |   ret <vscale x 2 x i64> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @_Z8cond_u64u12__SVUint64_tS_(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %cmp = icmp ult <vscale x 2 x i64> %0, %1
# |   %sext = sext <vscale x 2 x i1> %cmp to <vscale x 2 x i64>
# |   %2 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 2 x i64> %sext, zeroinitializer
# |   %vector_select = select <vscale x 2 x i1> %vector_cond, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3
# |   ret <vscale x 2 x i64> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @_Z8cond_f16u13__SVFloat16_tS_(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x half>, align 16
# |   %b.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %b.addr, align 16
# |   %cmp = fcmp olt <vscale x 8 x half> %0, %1
# |   %sext = sext <vscale x 8 x i1> %cmp to <vscale x 8 x i16>
# |   %2 = load <vscale x 8 x half>, ptr %a.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 8 x i16> %sext, zeroinitializer
# |   %vector_select = select <vscale x 8 x i1> %vector_cond, <vscale x 8 x half> %2, <vscale x 8 x half> %3
# |   ret <vscale x 8 x half> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @_Z8cond_f32u13__SVFloat32_tS_(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x float>, align 16
# |   %b.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %b.addr, align 16
# |   %cmp = fcmp olt <vscale x 4 x float> %0, %1
# |   %sext = sext <vscale x 4 x i1> %cmp to <vscale x 4 x i32>
# |   %2 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   %3 = load <vs
# | ...
# `---data was truncated (10240/16444) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055e1a80ddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e1a80dae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e1a80de62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6dbb733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6dbb78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6dbb733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6dbb71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e1a8073bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e1a8073a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e1a80588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e1a7d07e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e1a7d07b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6dbb71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6dbb71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6dbb71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e1a7d07a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c (239 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svadd_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svadd_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svadd_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svadd_bf16_n_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svadd_bf16_n_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svadd_bf16_n_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005641b5a40eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005641b5a3de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005641b5a4162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1b0eb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1b0eb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1b0eb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1b0eaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005641b59d6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005641b59d6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005641b59bb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005641b566ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005641b566ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1b0eaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1b0eaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1b0eaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005641b566aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c (240 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1wq_u32(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 4 x i32> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1wq.nxv4i32.p0(<vscale x 4 x i32> %2, <vscale x 1 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.aarch64.sve.st1wq.nxv4i32.p0(<vscale x 4 x i32>, <vscale x 1 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1wq_vnum_u32(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 4 x i32> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 1 x i32>, ptr %1, i64 1
# |   call void @llvm.aarch64.sve.st1wq.nxv4i32.p0(<vscale x 4 x i32> %2, <vscale x 1 x i1> %3, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1wq_s32(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 4 x i32> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1wq.nxv4i32.p0(<vscale x 4 x i32> %2, <vscale x 1 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1wq_vnum_s32(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 4 x i32> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 1 x i32>, ptr %1, i64 1
# |   call void @llvm.aarch64.sve.st1wq.nxv4i32.p0(<vscale x 4 x i32> %2, <vscale x 1 x i1> %3, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1wq_f32(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 4 x float> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x float> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1wq.nxv4f32.p0(<vscale x 4 x float> %2, <vscale x 1 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.aarch64.sve.st1wq.nxv4f32.p0(<vscale x 4 x float>, <vscale x 1 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1wq_vnum_f32(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 4 x float> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x float> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 1 x float>, ptr %1, i64 1
# |   call void @llvm.aarch64.sve.st1wq.nxv4f32.p0(<vscale x 4 x float> %2, <vscale x 1 x i1> %3, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1dq_u64(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 2 x i64> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1dq.nxv2i64.p0(<vscale x 2 x i64> %2, <vscale x 1 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.aarch64.sve.st1dq.nxv2i64.p0(<vscale x 2 x i64>, <vscale x 1 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1dq_vnum_u64(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 2 x i64> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 1 x i64>, ptr %1, i64 -8
# |   call void @llvm.aarch64.sve.st1dq.nxv2i64.p0(<vscale x 2 x i64> %2, <vscale x 1 x i1> %3, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1dq_s64(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 2 x i64> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1dq.nxv2i64.p0(<vscale x 2 x i64> %2, <vscale x 1 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1dq_vnum_s64(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 2 x i64> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 1 x i64>, ptr %1, i64 -8
# |   call void @llvm.aarch64.sve.st1dq.nxv2i64.p0(<vscale x 2 x i64> %2, <vscale x 1 x i1> %3, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1dq_f64(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 2 x double> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x double> %zt, ptr %zt.addr
# | ...
# `---data was truncated (10240/12466) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055c983222eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c98321fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c98322362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1501b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1501b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1501b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1501b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9831b8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c9831b8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c98319d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c982e4ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c982e4cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1501b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1501b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1501b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c982e4ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c (241 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16   -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svclamp_single_s8_x2(<vscale x 16 x i8> %op1.coerce0, <vscale x 16 x i8> %op1.coerce1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %op1.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %op1.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %op1, align 16
# |   %op11 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %op1, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %op1.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %6 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %7 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sclamp.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sclamp.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svclamp_single_s16_x2(<vscale x 8 x i16> %op1.coerce0, <vscale x 8 x i16> %op1.coerce1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %op1.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %op1.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %op1, align 16
# |   %op11 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %op1, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %op1.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %6 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %7 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sclamp.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %6)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sclamp.single.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svclamp_single_s32_x2(<vscale x 4 x i32> %op1.coerce0, <vscale x 4 x i32> %op1.coerce1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %op1.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %op1.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %op1, align 16
# |   %op11 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %op1, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %op1.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %6 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %7 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sclamp.single.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %6)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sclamp.single.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svclamp_single_s64_x2(<vscale x 2 x i64> %op1.coerce0, <vscale x 2 x i64> %op1.coerce1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %op1.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   %op3.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %op1.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %op1, align 16
# |   %op11 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %op1, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x i64> %op3, ptr %op3.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %op1.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 0
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 1
# |   %5 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %6 = load <vscale x 2 x i64>, ptr %op3.addr, align 16
# |   %7 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sclamp.single.x2.nxv2i64(<vscale x 2 x i64> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %6)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sclamp.single.x2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svclamp_single_s8_x4(<vscale x 16 x i8> %op1.coerce0, <vscale x 16 x i8> %op1.coerce1, <vscale x 16 x i8> %op1.coerce2, <vscale x 16 x i8> %op1.coerce3, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %op1.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %op1.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %op1.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %op1.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %op1, align 16
# |   %op11 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %op1, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %op1.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vsc
# | ...
# `---data was truncated (10240/62547) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055b45b4b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b45b4b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b45b4b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5067b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5067b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5067b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5067b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b45b44dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b45b44da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b45b4328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b45b0e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b45b0e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5067b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5067b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5067b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b45b0e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c (242 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacgt_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.facgt.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.facgt.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacgt_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.facgt.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.facgt.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacgt_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.facgt.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.facgt.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacgt_n_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, float noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca float, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store float %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 4 x float> poison, float %2, i64 0
# |   %.splat = shufflevector <vscale x 4 x float> %.splatinsert, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.facgt.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %.splat)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacgt_n_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, double noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca double, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store double %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load double, ptr %op2.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 2 x double> poison, double %2, i64 0
# |   %.splat = shufflevector <vscale x 2 x double> %.splatinsert, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.facgt.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %.splat)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055efe4a43eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055efe4a40e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055efe4a4462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0a5c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0a5c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0a5c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0a5c031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055efe49d9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055efe49d9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055efe49be8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055efe466de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055efe466db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0a5c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0a5c0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0a5c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055efe466da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c (243 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_rtz_x_f_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_rtz_x_f_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_rtz_x_f_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_rtz_x_f_v_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_rtz_x_f_v_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_rtz_x_f_v_i16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_rtz_xu_f_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_rtz_xu_f_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_rtz_xu_f_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_rtz_xu_f_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64
# | ...
# `---data was truncated (10240/135345) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005634d6761eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005634d675ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005634d676262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee8d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee8d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee8d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee8d91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005634d66f7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005634d66f7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005634d66dc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005634d638be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005634d638bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fee8d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee8d91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee8d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005634d638ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c (244 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_svldr_zt(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sme.ldr.zt.p0(i32 0, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.ldr.zt.p0(i32, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_svstr_zt(ptr noundef %base) #2 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sme.str.zt.p0(i32 0, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write, target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.str.zt.p0(i32, ptr) #3
# | 
# | attributes #0 = { noinline nounwind "aarch64_out_zt0" "aarch64_pstate_sm_compatible" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, target_mem0: readwrite) }
# | attributes #2 = { noinline nounwind "aarch64_in_zt0" "aarch64_pstate_sm_compatible" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #3 = { nocallback nofree nosync nounwind willreturn memory(argmem: write, target_mem0: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055d07369ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d073699e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d07369d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0832a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0832a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0832a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0832a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d073632bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d073632a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d0736178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d0732c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d0732c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0832a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0832a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0832a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d0732c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c (245 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzip1_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zip1q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.zip1q.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzip1_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zip1q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.zip1q.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzip1_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zip1q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.zip1q.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzip1_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zip1q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.zip1q.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzip1_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zip1q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzip1_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zip1q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzip1_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zip1q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzip1_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zip1q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svzip1_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.zip1q.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.zip1q.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svzip1_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.zip1q.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.zip1q.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svzip1_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.zip1q.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.zip1q.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svzip1_bf16(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.zip1q.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.zip1q.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055824d4baeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055824d4b7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055824d4bb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd5bf01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd5bf0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd5bf01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd5bf003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055824d450bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055824d450a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055824d4358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055824d0e4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055824d0e4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd5bf004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd5bf0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd5bf0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055824d0e4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c (246 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p2    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p2 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrint32x_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frint32x.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frint32x.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrint32x_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frint32x.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frint32x.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrint32x_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frint32x.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrint32x_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frint32x.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrint32x_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frint32x.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrint32x_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frint32x.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrint32z_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frint32z.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frint32z.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrint32z_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frint32z.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frint32z.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrint32z_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frint32z.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrint32z_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frint32z.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# | 
# | ...
# `---data was truncated (10240/23662) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055a64e512eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a64e50fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a64e51362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007effe7249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007effe72a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007effe7249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007effe7231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a64e4a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a64e4a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a64e48d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a64e13ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a64e13cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007effe7232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007effe72330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007effe72330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a64e13ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c (247 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtrn2_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.trn2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.trn2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtrn2_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.trn2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.trn2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtrn2_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.trn2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.trn2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtrn2_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.trn2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.trn2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtrn2_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.trn2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtrn2_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.trn2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtrn2_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.trn2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtrn2_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.trn2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtrn2_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.trn2.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.trn2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtrn2_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.trn2.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.trn2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtrn2_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.trn2.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.trn2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svtrn2_b8(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.trn2.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.trn2.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svtrn2_b16(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.trn2.b16(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | ...
# `---data was truncated (10240/13404) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055baf8845eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055baf8842e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055baf884662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1393b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1393b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1393b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1393b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055baf87dbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055baf87dba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055baf87c08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055baf846fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055baf846fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1393b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1393b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1393b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055baf846fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/maxv.c (248 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/maxv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svmaxv_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.smaxv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.smaxv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svmaxv_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.smaxv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.smaxv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svmaxv_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.smaxv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.smaxv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svmaxv_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.smaxv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.smaxv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svmaxv_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.umaxv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.umaxv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svmaxv_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.umaxv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.umaxv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svmaxv_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.umaxv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.umaxv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svmaxv_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.umaxv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.umaxv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @test_svmaxv_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call half @llvm.aarch64.sve.fmaxv.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret half %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.sve.fmaxv.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @test_svmaxv_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call float @llvm.aarch64.sve.fmaxv.nxv4f32(<vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret float %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.sve.fmaxv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @test_svmaxv_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call double @llvm.aarch64.sve.fmaxv.nxv2f64(<vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret double %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.sve.fmaxv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attribute
# | ...
# `---data was truncated (10240/10818) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x000055de3dc0deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055de3dc0ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055de3dc0e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f922b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f922b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f922b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f922b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de3dba3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055de3dba3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055de3db888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055de3d837e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055de3d837b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f922b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f922b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f922b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de3d837a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c (249 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svget2_b_0(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1> } %1, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   %2 = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %3 = extractvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %2, 0
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svget2_b_1(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1> } %1, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   %2 = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %3 = extractvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %2, 1
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000564b94befeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564b94bece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564b94bf062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3c5b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3c5b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3c5b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3c5b231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564b94b85bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564b94b85a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564b94b6a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564b94819e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564b94819b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3c5b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3c5b2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3c5b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564b94819a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c (250 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdivr_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdivr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sdivr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdivr_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.sdivr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sdivr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdivr_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.udivr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.udivr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdivr_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.udivr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.udivr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdivr_s32_m(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdivr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdivr_s64_m(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.sdivr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdivr_u32_m(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.udivr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdivr_u64_m(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.udivr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdivr_s32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 1
# | ...
# `---data was truncated (10240/48782) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000555bb1abeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555bb1abbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555bb1abf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffa51c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffa51ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffa51c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffa51c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555bb1a54bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555bb1a54a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555bb1a398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555bb16e8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555bb16e8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffa51c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffa51c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffa51c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555bb16e8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c (251 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmlalb_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalb.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalb.nxv8f16(<vscale x 8 x half>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmlalb_n_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <1 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <1 x i8>, align 1
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <1 x i8> %zm, ptr %zm.addr, align 1
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <1 x i8>, ptr %zm.addr, align 1
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = extractelement <1 x i8> %2, i64 0
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %4, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalb.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmlalt_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalt.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalt.nxv8f16(<vscale x 8 x half>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmlalt_n_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <1 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <1 x i8>, align 1
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <1 x i8> %zm, ptr %zm.addr, align 1
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <1 x i8>, ptr %zm.addr, align 1
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = extractelement <1 x i8> %2, i64 0
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %4, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalt.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmlalb_lane_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalb.lane.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 7)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalb.lane.nxv8f16(<vscale x 8 x half>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmlalt_lane_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalt.lane.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 7)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalt.lane.nxv8f16(<vscale x 8 x half>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmlallbb_f32_mf8(<vscale x 4 x float> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fmlallbb.nxv4f32(<vscale x 4 x float> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fp8.fmlallbb.nxv4f32(<vscale x 4 x float>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmlallbb_n_f32_mf8(<vscale x 4 x float> %zda, <vscale x 16 x i8> %zn, <1 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <1 x i8>, align 1
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <1 x i8> %zm, ptr %zm.addr, align 1
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <1 x i8>, ptr %zm.addr, align 1
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = extractelement <1 x i8> %2, i64 0
# |   %.splat
# | ...
# `---data was truncated (10240/24132) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055a202cb6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a202cb3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a202cb762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd24b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd24b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd24b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd24b91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a202c4cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a202c4ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a202c318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a2028e0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a2028e0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd24b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd24b91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd24b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a2028e0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/riscv-xcvalu.c (252 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/riscv-xcvalu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xcvalu -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xcvalu -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_abs(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call i32 @llvm.abs.i32(i32 %0, i1 true)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.abs.i32(i32, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_sle(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = icmp sle i32 %0, %1
# |   %sle = zext i1 %2 to i32
# |   ret i32 %sle
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_sleu(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = icmp ule i32 %0, %1
# |   %sleu = zext i1 %2 to i32
# |   ret i32 %sleu
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_exths(i16 noundef signext %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   %conv = sext i16 %0 to i32
# |   %1 = trunc i32 %conv to i16
# |   %exths = sext i16 %1 to i32
# |   ret i32 %exths
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_exthz(i16 noundef zeroext %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   %conv = zext i16 %0 to i32
# |   %1 = trunc i32 %conv to i16
# |   %exthz = zext i16 %1 to i32
# |   ret i32 %exthz
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_extbs(i8 noundef signext %a) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   store i8 %a, ptr %a.addr, align 1
# |   %0 = load i8, ptr %a.addr, align 1
# |   %conv = sext i8 %0 to i32
# |   %1 = trunc i32 %conv to i8
# |   %extbs = sext i8 %1 to i32
# |   ret i32 %extbs
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_extbz(i8 noundef zeroext %a) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   store i8 %a, ptr %a.addr, align 1
# |   %0 = load i8, ptr %a.addr, align 1
# |   %conv = zext i8 %0 to i32
# |   %1 = trunc i32 %conv to i8
# |   %extbz = zext i8 %1 to i32
# |   ret i32 %extbz
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_clip(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call i32 @llvm.riscv.cv.alu.clip(i32 %0, i32 15)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.clip(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_clipu(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call i32 @llvm.riscv.cv.alu.clipu(i32 %0, i32 15)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.clipu(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_addN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.cv.alu.addN(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.addN(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_adduN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.cv.alu.adduN(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.adduN(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_addRN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.cv.alu.addRN(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.addRN(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_adduRN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.cv.alu.adduRN(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.adduRN(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_subN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.cv.alu.subN(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.subN(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_subuN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.cv.alu.subuN(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.subuN(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_subRN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.cv.alu.subRN(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.subRN(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_subuRN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.cv.alu.subuRN(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.subuRN(i32, i32, i32) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+xcvalu" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_xcvalu1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ad5b0e0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ad5b0dde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ad5b0e162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f672a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f672a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f672a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f672a831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad5b076bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ad5b076a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ad5b05b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ad5ad0ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ad5ad0ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f672a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f672a8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f672a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad5ad0aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c (253 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svvdot_lane_za16_mf8_vg1x2(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load i32, ptr %slice.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %7 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   call void @llvm.aarch64.sme.fp8.fvdot.lane.za16.vg1x2(i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 7)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fvdot.lane.za16.vg1x2(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svvdotb_lane_za32_mf8_vg1x4(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load i32, ptr %slice.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %7 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   call void @llvm.aarch64.sme.fp8.fvdotb.lane.za32.vg1x4(i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fvdotb.lane.za32.vg1x4(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svvdott_lane_za32_mf8_vg1x4(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load i32, ptr %slice.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %7 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   call void @llvm.aarch64.sme.fp8.fvdott.lane.za32.vg1x4(i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fvdott.lane.za32.vg1x4(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme-f8f16,+sme-f8f32" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim
# |  #0 0x0000557828120eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055782811de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055782812162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3c68249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3c682a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3c68249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3c68231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005578280b6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005578280b6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055782809b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557827d4ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557827d4ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3c68232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3c682330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3c682330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557827d4aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c (254 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_s8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   call void @llvm.aarch64.sve.st1.nxv16i8.p0(<vscale x 16 x i8> %2, <vscale x 16 x i1> %0, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv16i8.p0(<vscale x 16 x i8>, <vscale x 16 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_s16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.nxv8i16.p0(<vscale x 8 x i16> %2, <vscale x 8 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv8i16.p0(<vscale x 8 x i16>, <vscale x 8 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_s32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.nxv4i32.p0(<vscale x 4 x i32> %2, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv4i32.p0(<vscale x 4 x i32>, <vscale x 4 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.nxv2i64.p0(<vscale x 2 x i64> %2, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv2i64.p0(<vscale x 2 x i64>, <vscale x 2 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_u8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   call void @llvm.aarch64.sve.st1.nxv16i8.p0(<vscale x 16 x i8> %2, <vscale x 16 x i1> %0, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_u16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.nxv8i16.p0(<vscale x 8 x i16> %2, <vscale x 8 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_u32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.nxv4i32.p0(<vscale x 4 x i32> %2, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.nxv2i64.p0(<vscale x 2 x i64> %2, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_f16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x half> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x half> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x half>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.nxv8f16.p0(<vscale x 8 x half> %2, <vscale x 8 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv8f16.p0(<vscale x 8 x half>, <vscale x 8 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_f32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x float> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x float> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.nxv4f32.p0(<vscale x 4 x float> %2, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv4f32.p0(<vscale x 4 x float>, <vscale x 4 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind
# | ...
# `---data was truncated (10240/75656) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x0000561d39033eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561d39030e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561d3903462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9bf6c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9bf6c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9bf6c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9bf6c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561d38fc9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561d38fc9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561d38fae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561d38c5de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561d38c5db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9bf6c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9bf6c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9bf6c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561d38c5da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c (255 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svcreate4_b(<vscale x 16 x i1> %x0, <vscale x 16 x i1> %x1, <vscale x 16 x i1> %x2, <vscale x 16 x i1> %x4) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i1>, align 2
# |   %x1.addr = alloca <vscale x 16 x i1>, align 2
# |   %x2.addr = alloca <vscale x 16 x i1>, align 2
# |   %x4.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %x0, ptr %x0.addr, align 2
# |   store <vscale x 16 x i1> %x1, ptr %x1.addr, align 2
# |   store <vscale x 16 x i1> %x2, ptr %x2.addr, align 2
# |   store <vscale x 16 x i1> %x4, ptr %x4.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %x0.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %x1.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %x2.addr, align 2
# |   %3 = load <vscale x 16 x i1>, ptr %x4.addr, align 2
# |   %4 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %0, 0
# |   %5 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %4, <vscale x 16 x i1> %1, 1
# |   %6 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %5, <vscale x 16 x i1> %2, 2
# |   %7 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %6, <vscale x 16 x i1> %3, 3
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %7
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000557fdd6a8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557fdd6a5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557fdd6a962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa1bfd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa1bfd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa1bfd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa1bfd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557fdd63ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557fdd63ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557fdd6238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557fdd2d2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557fdd2d2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa1bfd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa1bfd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa1bfd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557fdd2d2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c (256 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_b8() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_b16() #0 {
# | entry:
# |   %0 = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_b32() #0 {
# | entry:
# |   %0 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_b64() #0 {
# | entry:
# |   %0 = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 0)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_1() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 1)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_2() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 2)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_3() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 3)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_4() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 4)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_5() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 5)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_6() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 6)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_7() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 7)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_8() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 8)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_9() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 9)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_10() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 10)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_11() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 11)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_12() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 12)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_13() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 13)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_14() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 29)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_15() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 30)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_16() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b16() #0 {
# | entry:
# |   %0 = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 0)
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b32() #0 {
# | entry:
# |   %0 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 1)
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b64() #0 {
# | entry:
# |   %0 = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 2)
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560865fcaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560865fc7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560865fcb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe085d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe085d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe085d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe085d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560865f60bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560865f60a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560865f458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560865bf4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560865bf4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe085d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe085d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe085d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560865bf4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c (257 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls2_f16(i32 noundef %slice_base, <vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1, <vscale x 8 x half> %zm.coerce0, <vscale x 8 x half> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zm.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %5, 1
# |   %8 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %8, 1
# |   call void @llvm.aarch64.sme.fmlsl.vg2x2.nxv8f16(i32 %4, <vscale x 8 x half> %6, <vscale x 8 x half> %7, <vscale x 8 x half> %9, <vscale x 8 x half> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmlsl.vg2x2.nxv8f16(i32, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls2_bf16(i32 noundef %slice_base, <vscale x 8 x bfloat> %zn.coerce0, <vscale x 8 x bfloat> %zn.coerce1, <vscale x 8 x bfloat> %zm.coerce0, <vscale x 8 x bfloat> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zm.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %5, 1
# |   %8 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %8, 1
# |   call void @llvm.aarch64.sme.fmlsl.vg2x2.nxv8bf16(i32 %4, <vscale x 8 x bfloat> %6, <vscale x 8 x bfloat> %7, <vscale x 8 x bfloat> %9, <vscale x 8 x bfloat> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmlsl.vg2x2.nxv8bf16(i32, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls2_u16(i32 noundef %slice_base, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zm.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 1
# |   %8 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 1
# |   call void @llvm.aarch64.sme.umlsl.vg2x2.nxv8i16(i32 %4, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %9, <vscale x 8 x i16> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umlsl.vg2x2.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls2_s16(i32 noundef %slice_base, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zm.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 1
# |   %8 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 1
# |   call void @llvm.aarch64.sme.smlsl.vg2x2.nxv8i16(i32 %4, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %9, <vscale x 8 x i16> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smlsl.vg2x2.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls4
# | ...
# `---data was truncated (10240/73614) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005591423a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005591423a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005591423a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f18c3b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f18c3b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f18c3b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f18c3b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055914233bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055914233ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005591423208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559141fcfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559141fcfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f18c3b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f18c3b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f18c3b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559141fcfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_and.c (258 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_and.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svand_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.and.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.and.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svand_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.and.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.and.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svand_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.and.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.and.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svand_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.and.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.and.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svand_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.and.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svand_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.and.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svand_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.and.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svand_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.and.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svand_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, pt
# | ...
# `---data was truncated (10240/52880) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ce9d32beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ce9d328e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ce9d32c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff58b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff58b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff58b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff58b31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ce9d2c1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ce9d2c1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ce9d2a68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ce9cf55e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ce9cf55b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff58b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff58b31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff58b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ce9cf55a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c (259 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svexth_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sxth.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sxth.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svexth_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.sxth.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sxth.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svexth_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.uxth.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uxth.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svexth_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.uxth.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uxth.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svexth_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.sxth.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svexth_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.sxth.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svexth_u32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.uxth.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svexth_u64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.uxth.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svexth_s32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sxth.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svexth_s64_x(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.sxth.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svexth_u32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg,
# | ...
# `---data was truncated (10240/11908) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000558bb5a25eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558bb5a22e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558bb5a2662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f51c4133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f51c418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f51c4133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f51c411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558bb59bbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558bb59bba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558bb59a08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558bb564fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558bb564fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f51c411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51c411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51c411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558bb564fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c (260 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %3)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %6 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %3)
# |   ret <vscale x 8 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.u.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %3)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_n_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, bfloat noundef %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store bfloat %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load bfloat, ptr %op3.addr, align 2
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %3, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_n_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, bfloat noundef %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store bfloat %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load bfloat, ptr %op3.addr, align 2
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %3, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %6 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_n_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, bfloat noundef %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store bfloat %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load bfloat, ptr %op3.addr, align 2
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %3, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.u.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055e5e50c5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e5e50c2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e5e50c662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f59ee133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f59ee18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f59ee133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f59ee11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e5e505bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e5e505ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e5e50408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e5e4cefe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e5e4cefb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f59ee11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f59ee11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f59ee11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e5e4cefa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_not.c (261 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_not.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svnot_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.not.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.not.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svnot_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.not.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.not.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svnot_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.not.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.not.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svnot_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.not.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.not.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svnot_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.not.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svnot_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.not.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svnot_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.not.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svnot_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.not.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svnot_s8_m(<vscale x 16 x i8> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i8>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.not.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svnot_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.not.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svnot_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscal
# | ...
# `---data was truncated (10240/22149) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055f9e6444eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f9e6441e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f9e644562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f377ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f377cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f377ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f377ce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f9e63dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f9e63daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f9e63bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f9e606ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f9e606eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f377ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f377ce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f377ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f9e606ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c (262 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2q_u8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %zt.coerce0, <vscale x 16 x i8> %zt.coerce1) #0 {
# | entry:
# |   %zt = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zt.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zt.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zt, align 16
# |   %zt1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zt, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zt1, ptr %zt.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zt.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   call void @llvm.aarch64.sve.st2q.nxv16i8.p0(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i1> %2, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st2q.nxv16i8.p0(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2q_s8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %zt.coerce0, <vscale x 16 x i8> %zt.coerce1) #0 {
# | entry:
# |   %zt = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zt.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zt.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zt, align 16
# |   %zt1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zt, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zt1, ptr %zt.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zt.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   call void @llvm.aarch64.sve.st2q.nxv16i8.p0(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i1> %2, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2q_u16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %zt.coerce0, <vscale x 8 x i16> %zt.coerce1) #0 {
# | entry:
# |   %zt = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zt.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zt.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zt, align 16
# |   %zt1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zt, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zt1, ptr %zt.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zt.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 1
# |   %7 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %2)
# |   call void @llvm.aarch64.sve.st2q.nxv8i16.p0(<vscale x 8 x i16> %5, <vscale x 8 x i16> %6, <vscale x 8 x i1> %7, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st2q.nxv8i16.p0(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2q_s16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %zt.coerce0, <vscale x 8 x i16> %zt.coerce1) #0 {
# | entry:
# |   %zt = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zt.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zt.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zt, align 16
# |   %zt1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zt, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zt1, ptr %zt.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zt.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 1
# |   %7 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %2)
# |   call void @llvm.aarch64.sve.st2q.nxv8i16.p0(<vscale x 8 x i16> %5, <vscale x 8 x i16> %6, <vscale x 8 x i1> %7, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2q_u32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %zt.coerce0, <vscale x 4 x i32> %zt.coerce1) #0 {
# | entry:
# |   %zt = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zt.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zt.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zt, align 16
# |   %zt1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zt, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zt1, ptr %zt.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zt.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 1
# |   %7 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %2)
# |   call void @llvm.aarch64.sve.st2q.nxv4i32.p0(<vscale x 4 x i32> %5, <vscale x 4 x i32> %6, <vscale x 4 x i1> %7, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st2q.nxv4i32.p0(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2q_s32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %zt.coerce0, <vscale x 4 x i32> %zt.coerce1) #0 {
# | entry:
# |   %zt = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zt.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zt.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zt, align 16
# |   %zt1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zt, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zt1, ptr %zt.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zt.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 1
# |   %7 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %2)
# |   call void @llvm.aarch64.sve.st2q.nxv4i32.p0(<vscale x 
# | ...
# `---data was truncated (10240/172384) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055dcaa232eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dcaa22fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dcaa23362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee70649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee706a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee70649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee70631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dcaa1c8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dcaa1c8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dcaa1ad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dca9e5ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dca9e5cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fee70632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee706330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee706330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dca9e5ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c (263 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f16f16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f16f16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_cvtl_f32_x2(<vscale x 8 x half> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fcvtl.widen.x2.nxv4f32(<vscale x 8 x half> %0)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fcvtl.widen.x2.nxv4f32(<vscale x 8 x half>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme-f16f16" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005644f4c2eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005644f4c2be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005644f4c2f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb2ac249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb2ac2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb2ac249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb2ac231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005644f4bc4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005644f4bc4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005644f4ba98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005644f4858e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005644f4858b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb2ac232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb2ac2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb2ac2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005644f4858a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-vector-shift-ops.c (264 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-shift-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @lshift_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %shl = shl <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @rshift_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %shr = ashr <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %shr
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @lshift_u8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %shl = shl <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @rshift_u8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %shr = lshr <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %shr
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @lshift_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %shl = shl <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @rshift_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %shr = ashr <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %shr
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @lshift_u16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %shl = shl <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @rshift_u16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %shr = lshr <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %shr
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @lshift_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %shl = shl <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @rshift_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %shr = ashr <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %shr
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @lshift_u32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %shl = shl <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @rshift_u32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %shr = lshr <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %shr
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @lshift_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %shl = shl <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @rshift_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %shr = ashr <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %shr
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @lshift_u64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %shl = shl <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @rshift_u64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %shr = lshr <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %shr
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @lshift_i8_rsplat(<vscale x 16 x i8> %a, i8 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca i8, align 1
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load i8, ptr %b.addr, align 1
# |   %splat.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %1, i64 0
# |   %splat.splat = shufflevector <vscale x 16 x i8> %splat.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %shl = shl <vscale x 16 x i8> %0, %splat.splat
# |   ret <vscale x 16 x i8> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @lshift_i8_lsplat(<vscale x 16 x i8> %a, i8 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca i8, align 1
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load i8, ptr %b.addr, align 1
# |   %splat.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %0, i64 0
# |   %splat.splat
# | ...
# `---data was truncated (10240/32491) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055902f24beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055902f248e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055902f24c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faf60049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faf600a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faf60049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faf60031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055902f1e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055902f1e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055902f1c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055902ee75e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055902ee75b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faf60032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faf600330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faf600330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055902ee75a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c (265 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1>, ptr, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_1(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_2(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_3(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_4(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_5(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_6(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 8)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_7(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 9)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 10)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_9(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 11)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_10(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 12)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_11(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 13)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_vnum(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = getelementptr <vscale x 16 x i8>, ptr %1, i64 %2
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %3, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_gather_u32base(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prfb.gather.scalar.offset.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1, i64 0, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.aarch64.sve.prfb.gather.scalar.offset.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64, i32 immarg) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_gather_u64base(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prfb.gather.scalar.offset.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.aarch64.sve.prfb.gather.scalar.offset.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64, i32 immarg) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_gather_s32offset(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, ali
# | ...
# `---data was truncated (10240/16554) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000557387c00eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557387bfde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557387c0162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe780133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe78018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe780133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe78011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557387b96bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557387b96a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557387b7b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055738782ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055738782ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe78011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe78011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe78011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055738782aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c (266 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti2_lane_zt_u8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti2_lane_zt_s8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti2_lane_zt_mf8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svluti2_lane_zt_u16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8i16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svluti2_lane_zt_s16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svluti2_lane_zt_f16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8f16(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8f16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svluti2_lane_zt_bf16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8bf16(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8bf16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svluti2_lane_zt_u32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4i32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svluti2_lane_zt_s32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svluti2_lane_zt_f32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4f32(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4f32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005582e131beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005582e1318e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005582e131c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f346db05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f346db5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f346db05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f346daed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005582e12b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005582e12b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005582e12968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005582e0f45e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005582e0f45b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f346daeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f346daef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f346daef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005582e0f45a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c (267 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svvdot_lane_za32_bf16_vg1x2(i32 noundef %slice_base, <vscale x 8 x bfloat> %zn.coerce0, <vscale x 8 x bfloat> %zn.coerce1, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, 0
# |   %5 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, 1
# |   %6 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.fvdot.lane.za32.vg1x2.nxv8bf16(i32 %2, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fvdot.lane.za32.vg1x2.nxv8bf16(i32, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svvdot_lane_za32_f16_vg1x2(i32 noundef %slice_base, <vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %3, 0
# |   %5 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %3, 1
# |   %6 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.fvdot.lane.za32.vg1x2.nxv8f16(i32 %2, <vscale x 8 x half> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fvdot.lane.za32.vg1x2.nxv8f16(i32, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svvdot_lane_za32_s16_vg1x2(i32 noundef %slice_base, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, 0
# |   %5 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, 1
# |   %6 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.svdot.lane.za32.vg1x2.nxv8i16(i32 %2, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.svdot.lane.za32.vg1x2.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svvdot_lane_za32_u16_vg1x2(i32 noundef %slice_base, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, 0
# |   %5 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, 1
# |   %6 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.uvdot.lane.za32.vg1x2.nxv8i16(i32 %2, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.uvdot.lane.za32.vg1x2.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svvdot_lane_za32_s8_vg1x4(i32 noundef %slice_base, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 2
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 3
# |   %10 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.svdot.lane.za32.vg1x4.nxv16i8(i32 %4, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.svdot.lane.za32.vg1x4.nxv16i8(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | ...
# `---data was truncated (10240/24605) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055648f6d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055648f6d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055648f6d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8276a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8276a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8276a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8276a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055648f66cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055648f66ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055648f6518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055648f300e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055648f300b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8276a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8276a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8276a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055648f300a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c (268 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtrn1_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.trn1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.trn1.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtrn1_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.trn1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.trn1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtrn1_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.trn1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.trn1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtrn1_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.trn1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.trn1.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtrn1_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.trn1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtrn1_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.trn1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtrn1_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.trn1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtrn1_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.trn1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtrn1_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.trn1.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.trn1.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtrn1_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.trn1.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.trn1.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtrn1_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.trn1.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.trn1.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svtrn1_b8(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.trn1.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.trn1.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svtrn1_b16(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.trn1.b16(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | ...
# `---data was truncated (10240/13404) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055db329eaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055db329e7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055db329eb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd845f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd845f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd845f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd845f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055db32980bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055db32980a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055db329658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055db32614e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055db32614b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd845f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd845f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd845f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055db32614a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c (269 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f16m1x5(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f32m1x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f64m1x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei32_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005648934d4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005648934d1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005648934d562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0a1d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0a1d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0a1d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0a1d11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056489346abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056489346aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056489344f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005648930fee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005648930feb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0a1d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0a1d11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0a1d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005648930fea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c (270 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcompact_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.compact.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.compact.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcompact_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.compact.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.compact.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcompact_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.compact.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcompact_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.compact.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svcompact_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.compact.nxv4f32(<vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.compact.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svcompact_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.compact.nxv2f64(<vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.compact.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ee250e2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ee250dfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ee250e362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdea2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdea2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdea2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdea2f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee25078bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ee25078a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ee2505d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ee24d0ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ee24d0cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdea2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdea2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdea2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee24d0ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c (271 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svscale_single_bf16_x2(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fscale.single.x2.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fscale.single.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svscale_single_bf16_x4(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zdn.coerce2, <vscale x 8 x bfloat> %zdn.coerce3, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, <vscale x 8 x bfloat> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zdn.coerce3, 3
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 1
# |   %7 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 2
# |   %8 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 3
# |   %9 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %10 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fscale.single.x4.nxv8bf16(<vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %6, <vscale x 8 x bfloat> %7, <vscale x 8 x bfloat> %8, <vscale x 8 x i16> %9)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fscale.single.x4.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svscale_bf16_x2(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zm.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 1
# |   %7 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %7, 0
# |   %9 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %7, 1
# |   %10 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fscale.x2.nxv8bf16(<vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %6, <vscale x 8 x i16> %8, <vscale x 8 x i16> %9)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fscale.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svscale_bf16_x4(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zdn.coerce2, <vscale x 8 x bfloat> %zdn.coerce3, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1, <vscale x 8 x i16> %zm.coerce2, <vscale x 8 x i16> %zm.coerce3) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, <vscale x 8 x bfloat> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zdn.coerce3, 3
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   %4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %5 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, <vscale x 8 x i16> %zm.coerce1, 1
# |   %6 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5, <vscale x 8 x i16> %zm.coerce2, 2
# |   %7 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6, <vscale x 8 x i16> %zm.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 
# | ...
# `---data was truncated (10240/13379) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055ac3acf1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ac3aceee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ac3acf262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa619733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa61978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa619733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa61971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac3ac87bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ac3ac87a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ac3ac6c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ac3a91be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ac3a91bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa61971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa61971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa61971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac3a91ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c (272 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsrl_wv_u8mf8(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsrl_wx_u8mf8(<vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsrl_wv_u8mf4(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsrl_wx_u8mf4(<vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsrl_wv_u8mf2(<vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsrl_wx_u8mf2(<vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsrl_wv_u8m1(<vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsrl_wx_u8m1(<vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsrl_wv_u8m2(<vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsrl_wx_u8m2(<vscale x 16 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8>, <vscale x 1
# | ...
# `---data was truncated (10240/68509) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562bc1dedeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562bc1deae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562bc1dee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8074c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8074ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8074c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8074c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562bc1d83bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562bc1d83a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562bc1d688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562bc1a17e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562bc1a17b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8074c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8074c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8074c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562bc1a17a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c (273 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_i16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_i16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tupl
# | ...
# `---data was truncated (10240/88444) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c22161ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c221619e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c22161d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6b45849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6b458a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6b45849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6b45831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c2215b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c2215b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c2215978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c221246e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c221246b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6b45832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6b458330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6b458330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c221246a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c (274 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmulh_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.smulh.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.smulh.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmulh_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.smulh.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.smulh.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmulh_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.smulh.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.smulh.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmulh_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.smulh.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.smulh.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmulh_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.umulh.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.umulh.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmulh_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.umulh.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.umulh.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmulh_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.umulh.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.umulh.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmulh_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vsca
# | ...
# `---data was truncated (10240/53696) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c525536eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c525533e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c52553762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fceaab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fceaab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fceaab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fceaab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c5254ccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c5254cca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c5254b18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c525160e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c525160b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fceaab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fceaab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fceaab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c525160a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c (275 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svunpk_s16_x4(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sunpk.x4.nxv8i16(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sunpk.x4.nxv8i16(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svunpk_u16_x4(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uunpk.x4.nxv8i16(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uunpk.x4.nxv8i16(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svunpk_s32_x4(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sunpk.x4.nxv4i32(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sunpk.x4.nxv4i32(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svunpk_u32_x4(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.uunpk.x4.nxv4i32(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.uunpk.x4.nxv4i32(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svunpk_s64_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sunpk.x4.nxv2i64(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sunpk.x4.nxv2i64(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svunpk_u64_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.uunpk.x4.nxv2i64(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.uunpk.x4.nxv2i64(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000564c7c5e7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564c7c5e4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564c7c5e862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e89933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e8998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e89933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e8991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c7c57dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564c7c57da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564c7c5628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564c7c211e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564c7c211b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4e8991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e8991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e8991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c7c211a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c (276 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svzip_s8_x2(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svzip_u8_x2(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svzip_mf8_x2(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svzip_s16_x2(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.zip.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.zip.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svzip_u16_x2(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.zip.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svzip_f16_x2(<vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 1
# |   %5 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.zip.x2.nxv8f16(<vscale x 8 x half> %3, <vscale x 8 x half> %4)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.zip.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svzip_bf16_x2(<vscale x 8 x bfloat> %zn.coerce0, <vscale x 8 x bfloat> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 1
# |   %5 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.zip.x2.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %4)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.zip.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svzip_s32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.c
# | ...
# `---data was truncated (10240/35785) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005593b003ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005593b0039e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005593b003d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7d60933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7d6098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7d60933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7d6091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005593affd2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005593affd2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005593affb78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005593afc66e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005593afc66b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7d6091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7d6091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7d6091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005593afc66a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c (277 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svuzp_s8_x2(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svuzp_u8_x2(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svuzp_mf8_x2(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svuzp_s16_x2(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uzp.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uzp.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svuzp_u16_x2(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uzp.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svuzp_f16_x2(<vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 1
# |   %5 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.uzp.x2.nxv8f16(<vscale x 8 x half> %3, <vscale x 8 x half> %4)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.uzp.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svuzp_bf16_x2(<vscale x 8 x bfloat> %zn.coerce0, <vscale x 8 x bfloat> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 1
# |   %5 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.uzp.x2.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %4)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.uzp.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svuzp_s32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.c
# | ...
# `---data was truncated (10240/35785) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000559268ab5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559268ab2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559268ab662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa5bc705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa5bc75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa5bc705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa5bc6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559268a4bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559268a4ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559268a308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005592686dfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005592686dfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa5bc6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa5bc6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa5bc6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005592686dfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c (278 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmin_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmin_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmin_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmin_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmin_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmin_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmin_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmin_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmin_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmin_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmin.
# | ...
# `---data was truncated (10240/69313) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ed5ee4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564ed5ee1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564ed5ee562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f46dc333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f46dc38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f46dc333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f46dc31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ed5e7abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564ed5e7aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564ed5e5f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564ed5b0ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564ed5b0eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f46dc31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f46dc31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f46dc31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ed5b0ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c (279 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_lane_za16_vg2x1(i32 noundef %slice, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x1(i32 %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x1(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_lane_za16_vg2x2(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %2 = load i32, ptr %slice.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %7 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x2(i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 15)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x2(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_lane_za16_vg2x4(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %4 = load i32, ptr %slice.addr, align 4
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 2
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 3
# |   %10 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %11 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %11)
# |   call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x4(i32 %4, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10, i32 7)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x4(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_lane_za32_vg4x1(i32 noundef %slice, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   call void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x1(i32 %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x1(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_lane_za32_vg4x2(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %2 = load i32, ptr %slice.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %7 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   call void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x2(i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 15)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x2(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_lane_za32_vg4x4(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   %0
# | ...
# `---data was truncated (10240/39820) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000056365d764eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056365d761e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056365d76562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff7e7c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff7e7ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff7e7c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff7e7c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056365d6fabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056365d6faa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056365d6df8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056365d38ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056365d38eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff7e7c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff7e7c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff7e7c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056365d38ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c (280 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svunpklo_s16(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.sunpklo.nxv8i16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sunpklo.nxv8i16(<vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svunpklo_s32(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.sunpklo.nxv4i32(<vscale x 8 x i16> %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sunpklo.nxv4i32(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svunpklo_s64(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.sunpklo.nxv2i64(<vscale x 4 x i32> %0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sunpklo.nxv2i64(<vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svunpklo_u16(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.uunpklo.nxv8i16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uunpklo.nxv8i16(<vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svunpklo_u32(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.uunpklo.nxv4i32(<vscale x 8 x i16> %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uunpklo.nxv4i32(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svunpklo_u64(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.uunpklo.nxv2i64(<vscale x 4 x i32> %0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uunpklo.nxv2i64(<vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svunpklo_b(<vscale x 16 x i1> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.punpklo.nxv16i1(<vscale x 16 x i1> %0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.punpklo.nxv16i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d14fd37eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d14fd34e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d14fd3862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f37b3849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f37b38a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f37b3849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f37b3831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d14fccdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d14fccda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d14fcb28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d14f961e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d14f961b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f37b3832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f37b38330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f37b38330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d14f961a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c (281 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %3)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %6 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %3)
# |   ret <vscale x 8 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.u.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %3)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_n_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, bfloat noundef %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store bfloat %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load bfloat, ptr %op3.addr, align 2
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %3, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_n_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, bfloat noundef %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store bfloat %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load bfloat, ptr %op3.addr, align 2
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %3, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %6 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_n_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, bfloat noundef %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store bfloat %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load bfloat, ptr %op3.addr, align 2
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %3, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.u.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000558aba266eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558aba263e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558aba26762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f87e7905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87e795c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f87e7905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87e78ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558aba1fcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558aba1fca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558aba1e18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558ab9e90e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558ab9e90b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f87e78eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87e78ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87e78ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558ab9e90a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c (282 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_v
# | ...
# `---data was truncated (10240/228865) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559fdefdaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559fdefd7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559fdefdb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe15ae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe15aea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe15ae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe15ae31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559fdef70bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559fdef70a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559fdef558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559fdec04e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559fdec04b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe15ae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe15ae330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe15ae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559fdec04a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c (283 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclz_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.clz.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.clz.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclz_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.clz.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.clz.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclz_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.clz.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.clz.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svclz_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.clz.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.clz.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclz_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.clz.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclz_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.clz.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclz_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.clz.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svclz_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.clz.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclz_s8_m(<vscale x 16 x i8> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i8>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.clz.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclz_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.clz.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclz_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscal
# | ...
# `---data was truncated (10240/21295) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000561f02798eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561f02795e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561f0279962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb7a1533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb7a158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb7a1533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb7a151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f0272ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561f0272ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561f027138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561f023c2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561f023c2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb7a151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb7a151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb7a151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f023c2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c (284 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +f8f32mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +f8f32mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_f32mf8(<vscale x 4 x float> %acc, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i64 noundef %fpmr) #0 {
# | entry:
# |   %acc.addr = alloca <vscale x 4 x float>, align 16
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %acc, ptr %acc.addr, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %acc.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %3 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fmmla.nxv4f32(<vscale x 4 x float> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fp8.fmmla.nxv4f32(<vscale x 4 x float>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f8f32mm,+sve,+sve2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000555bcf5c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555bcf5bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555bcf5c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f51b1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f51b178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f51b1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f51b171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555bcf556bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555bcf556a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555bcf53b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555bcf1eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555bcf1eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f51b171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51b171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51b171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555bcf1eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c (285 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svmmla_f64(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 2 x double>, align 16
# |   %y.addr = alloca <vscale x 2 x double>, align 16
# |   %z.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %x, ptr %x.addr, align 16
# |   store <vscale x 2 x double> %y, ptr %y.addr, align 16
# |   store <vscale x 2 x double> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %x.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %y.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %z.addr, align 16
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.fmmla.nxv2f64.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fmmla.nxv2f64.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005595a6a5feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005595a6a5ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005595a6a6062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbde4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbde478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbde4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbde471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005595a69f5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005595a69f5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005595a69da8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005595a6689e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005595a6689b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbde471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbde471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbde471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005595a6689a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c (286 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sw_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sw_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sw_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sw_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055796e85beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055796e858e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055796e85c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff64f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff64f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff64f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff64f51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055796e7f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055796e7f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055796e7d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055796e485e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055796e485b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff64f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff64f51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff64f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055796e485a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c (287 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_cvt_f16_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fcvt.x2.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fcvt.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_cvt_bf16_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.bfcvt.x2(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.bfcvt.x2(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svcvt_f32_u32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ucvtf.x2.nxv4f32.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ucvtf.x2.nxv4f32.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svcvt_f32_s32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.scvtf.x2.nxv4f32.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.scvtf.x2.nxv4f32.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svcvt_u32_f32_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.fcvtzu.x2.nxv4i32.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.fcvtzu.x2.nxv4i32.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svcvt_s32_f32_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.fcvtzs.x2.nxv4i32.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.fcvtzs.x2.nxv4i32.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svcvt_f32_u32_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %zn.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, p
# | ...
# `---data was truncated (10240/39207) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000555606dbaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555606db7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555606dbb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f89cbf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f89cbf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f89cbf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f89cbf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555606d50bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555606d50a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555606d358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005556069e4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005556069e4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f89cbf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f89cbf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f89cbf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005556069e4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c (288 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svsqrt_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.fsqrt.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fsqrt.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svsqrt_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fsqrt.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fsqrt.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svsqrt_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.fsqrt.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fsqrt.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svsqrt_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fsqrt.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svsqrt_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fsqrt.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svsqrt_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.fsqrt.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svsqrt_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.fsqrt.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svsqrt_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fsqrt.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svsqrt_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.fsqrt.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000558dd5433eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558dd5430e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558dd543462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f00f9133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f00f918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f00f9133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f00f911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558dd53c9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558dd53c9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558dd53ae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558dd505de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558dd505db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f00f911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f00f911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f00f911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558dd505da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c (289 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst4_s8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data.coerce0, <vscale x 16 x i8> %data.coerce1, <vscale x 16 x i8> %data.coerce2, <vscale x 16 x i8> %data.coerce3) #0 {
# | entry:
# |   %data = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %data.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %data.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %data.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %data, align 16
# |   %data1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %data1, ptr %data.addr, align 16
# |   %4 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %5 = load ptr, ptr %base.addr, align 8
# |   %6 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %data.addr, align 16
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6, 0
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6, 1
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6, 2
# |   %10 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6, 3
# |   call void @llvm.aarch64.sve.st4.nxv16i8.p0(<vscale x 16 x i8> %7, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10, <vscale x 16 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st4.nxv16i8.p0(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst4_s16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data.coerce0, <vscale x 8 x i16> %data.coerce1, <vscale x 8 x i16> %data.coerce2, <vscale x 8 x i16> %data.coerce3) #0 {
# | entry:
# |   %data = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %data.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %data.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %data.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %data, align 16
# |   %data1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %data1, ptr %data.addr, align 16
# |   %4 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %5 = load ptr, ptr %base.addr, align 8
# |   %6 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %data.addr, align 16
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6, 0
# |   %8 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6, 1
# |   %9 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6, 2
# |   %10 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6, 3
# |   %11 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %4)
# |   call void @llvm.aarch64.sve.st4.nxv8i16.p0(<vscale x 8 x i16> %7, <vscale x 8 x i16> %8, <vscale x 8 x i16> %9, <vscale x 8 x i16> %10, <vscale x 8 x i1> %11, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st4.nxv8i16.p0(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst4_s32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data.coerce0, <vscale x 4 x i32> %data.coerce1, <vscale x 4 x i32> %data.coerce2, <vscale x 4 x i32> %data.coerce3) #0 {
# | entry:
# |   %data = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %data.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %data.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %data.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %data, align 16
# |   %data1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %data1, ptr %data.addr, align 16
# |   %4 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %5 = load ptr, ptr %base.addr, align 8
# |   %6 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %data.addr, align 16
# |   %7 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %6, 0
# |   %8 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %6, 1
# |   %9 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %6, 2
# |   %10 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %6, 3
# |   %11 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %4)
# |   call void @llvm.aarch64.sve.st4.nxv4i32.p0(<vscale x 4 x i32> %7, <vscale x 4 x i32> %8, <vscale x 4 x i32> %9, <vscale x 4 x i32> %10, <vscale x 4 x i1> %11, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st4.nxv4i32.p0(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst4_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data.coerce0, <vscale x 2 x i64> %data.coerce1, <vscale x 2 x i64> %data.coerce2, <vscale x 2 x i64> %data.coerce3) #0 {
# | entry:
# |   %data = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %data.coerce1, 1
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, <vscale x 2 x i64> %data.coerce2, 2
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %da
# | ...
# `---data was truncated (10240/73307) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056056c352eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056056c34fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056056c35362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb76849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb768a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb76849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb76831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056056c2e8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056056c2e8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056056c2cd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056056bf7ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056056bf7cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffb76832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb768330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb768330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056056bf7ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c (290 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svuzp_s8_x4(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 3
# |   %9 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x4.nxv16i8(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svuzp_u8_x4(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 3
# |   %9 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x4.nxv16i8(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svuzp_mf8_x4(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 3
# |   %9 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x4.nxv16i8(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svuzp_s16_x4(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zn.coerce2, <vscale x 8 x i16> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zn.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 1
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 2
# |   %8 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 3
# |   %9 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uzp.x4.nxv8i16(<vscale x 8 x i16> %5, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %8)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uzp.x4.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | ...
# `---data was truncated (10240/67329) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055f635361eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f63535ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f63536262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0ac6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0ac6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0ac6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0ac6b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f6352f7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f6352f7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f6352dc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f634f8be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f634f8bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0ac6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0ac6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0ac6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f634f8ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c (291 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintz_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintz.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frintz.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintz_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintz.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frintz.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintz_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintz.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frintz.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintz_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.frintz.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintz_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frintz.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintz_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frintz.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintz_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintz.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintz_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintz.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintz_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintz.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560f037e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560f037e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560f037e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5e9b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5e9b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5e9b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5e9b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f0377bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560f0377ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560f037608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560f0340fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560f0340fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5e9b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5e9b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5e9b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f0340fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c (292 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmul_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.mul.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.mul.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmul_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.mul.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.mul.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmul_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.mul.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmul_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.mul.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.mul.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmul_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.mul.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmul_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.mul.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmul_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmul_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.mul.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmul_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, pt
# | ...
# `---data was truncated (10240/77120) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055a536741eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a53673ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a53674262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc987049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc9870a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc987049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc987031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a5366d7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a5366d7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a5366bc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a53636be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a53636bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc987032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc9870330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc9870330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a53636ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c (293 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vminu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vminu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vminu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vminu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vminu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vminu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vminu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vminu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vminu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x
# | ...
# `---data was truncated (10240/222925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005601ef02aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005601ef027e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005601ef02b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2970105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f297015c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2970105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f29700ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005601eefc0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005601eefc0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005601eefa58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005601eec54e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005601eec54b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f29700eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f29700ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f29700ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005601eec54a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-vector-subscript-ops.c (294 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-subscript-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @subscript_int16(<vscale x 8 x i16> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 8 x i16> %0, i64 %1
# |   ret i16 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @subscript_uint16(<vscale x 8 x i16> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 8 x i16> %0, i64 %1
# |   ret i16 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @subscript_int32(<vscale x 4 x i32> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 4 x i32> %0, i64 %1
# |   ret i32 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @subscript_uint32(<vscale x 4 x i32> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 4 x i32> %0, i64 %1
# |   ret i32 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @subscript_int64(<vscale x 2 x i64> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 2 x i64> %0, i64 %1
# |   ret i64 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @subscript_uint64(<vscale x 2 x i64> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 2 x i64> %0, i64 %1
# |   ret i64 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @subscript_float16(<vscale x 8 x half> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x half>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 8 x half> %0, i64 %1
# |   ret half %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @subscript_float32(<vscale x 4 x float> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x float>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 4 x float> %0, i64 %1
# |   ret float %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @subscript_float64(<vscale x 2 x double> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x double>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 2 x double> %0, i64 %1
# |   ret double %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @subscript_write_float32(<vscale x 4 x float> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x float>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %b.addr, align 8
# |   %1 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   %vecins = insertelement <vscale x 4 x float> %1, float 1.000000e+00, i64 %0
# |   store <vscale x 4 x float> %vecins, ptr %a.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @subscript_read_write_float32(<vscale x 4 x float> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x float>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %b.addr, align 8
# |   %1 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   %vecext = extractelement <vscale x 4 x float> %1, i64 %0
# |   %add = fadd float %vecext, 1.000000e+00
# |   %2 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   %vecins = insertelement <vscale x 4 x float> %2, float %add, i64 %0
# |   store <vscale x 4 x float> %vecins, ptr %a.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x0000561007ee5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561007ee2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561007ee662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4166533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f416658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4166533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f416651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561007e7bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561007e7ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561007e608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561007b0fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561007b0fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f416651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f416651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f416651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561007b0fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c (295 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecp_n_s32_b8(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv16i1(i32 %0, <vscale x 16 x i1> %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqdecp.n32.nxv16i1(i32, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecp_n_s32_b16(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv8i1(i32 %0, <vscale x 8 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqdecp.n32.nxv8i1(i32, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecp_n_s32_b32(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv4i1(i32 %0, <vscale x 4 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqdecp.n32.nxv4i1(i32, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecp_n_s32_b64(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv2i1(i32 %0, <vscale x 2 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqdecp.n32.nxv2i1(i32, <vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecp_n_s64_b8(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i64 %op, ptr %op.addr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call i64 @llvm.aarch64.sve.sqdecp.n64.nxv16i1(i64 %0, <vscale x 16 x i1> %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqdecp.n64.nxv16i1(i64, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecp_n_s64_b16(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i64 %op, ptr %op.addr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %3 = call i64 @llvm.aarch64.sve.sqdecp.n64.nxv8i1(i64 %0, <vscale x 8 x i1> %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqdecp.n64.nxv8i1(i64, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecp_n_s64_b32(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i64 %op, ptr %op.addr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %3 = call i64 @llvm.aarch64.sve.sqdecp.n64.nxv4i1(i64 %0, <vscale x 4 x i1> %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqdecp.n64.nxv4i1(i64, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecp_n_s64_b64(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i64 %op, ptr %op.addr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %3 = call i64 @llvm.aarch64.sve.sqdecp.n64.nxv2i1(i64 %0, <vscale x 2 x i1> %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqdecp.n64.nxv2i1(i64, <vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecp_n_u32_b8(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv16i1(i32 %0, <vscale x 16 x i1> %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv16i1(i32, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecp_n_u32_b16(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv8i1(i32 %0, <vscale x 8 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv8i1(i32, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecp_n_u32_b32(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv4i1(i32 %0, <vscale x 4 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv4i1(i32, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecp_n_u32_b64(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv2i1(i32 %0, <vscale x 2 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv2i1(i32, <vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecp_n_u64_b8(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/19010) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055f32cd92eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f32cd8fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f32cd9362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa4b801bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa4b80725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa4b801ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa4b8003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f32cd28bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f32cd28a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f32cd0d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f32c9bce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f32c9bcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa4b8004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4b80050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4b80050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f32c9bca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c (296 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpeq_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpeq_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpeq.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpeq.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpeq_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpeq.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpeq.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpeq_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpeq.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpeq.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpeq_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpeq_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpeq.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpeq_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpeq.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpeq_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpeq.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_r
# | ...
# `---data was truncated (10240/34127) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055806e03feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055806e03ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055806e04062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6a03e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6a03e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6a03e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6a03e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055806dfd5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055806dfd5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055806dfba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055806dc69e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055806dc69b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6a03e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6a03e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6a03e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055806dc69a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c (297 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpge_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpge_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpge.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpge.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpge_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpge.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpge.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpge_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpge.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpge.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpge_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmphs.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmphs.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpge_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmphs.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmphs.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpge_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmphs.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmphs.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpge_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr,
# | ...
# `---data was truncated (10240/41923) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055eb3ab0deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eb3ab0ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eb3ab0e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7d8cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7d8cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7d8cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7d8cb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb3aaa3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eb3aaa3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eb3aa888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eb3a737e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eb3a737b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7d8cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7d8cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7d8cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb3a737a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c (298 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmple_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %2, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmple_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpge.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %2, <vscale x 8 x i16> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpge.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmple_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpge.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %2, <vscale x 4 x i32> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpge.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmple_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpge.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %2, <vscale x 2 x i64> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpge.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmple_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmphs.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %2, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmphs.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmple_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmphs.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %2, <vscale x 8 x i16> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmphs.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmple_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmphs.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %2, <vscale x 4 x i32> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmphs.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmple_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr,
# | ...
# `---data was truncated (10240/41923) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055873cb80eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055873cb7de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055873cb8162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1885b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1885b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1885b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1885b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055873cb16bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055873cb16a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055873cafb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055873c7aae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055873c7aab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1885b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1885b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1885b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055873c7aaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c (299 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsudot_s32(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %2, <vscale x 16 x i8> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.usdot.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsudot_n_s32(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, i8 noundef %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca i8, align 1
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store i8 %z, ptr %z.addr, align 1
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load i8, ptr %z.addr, align 1
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %2, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %.splat, <vscale x 16 x i8> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsudot_lane_s32_0(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sudot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 0)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sudot.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsudot_lane_s32_1(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sudot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsudot_lane_s32_2(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sudot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsudot_lane_s32_3(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sudot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+i8mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055a28a2d1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a28a2cee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a28a2d262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff968249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff9682a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff968249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff968231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a28a267bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a28a267a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a28a24c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a289efbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a289efbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff968232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff9682330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff9682330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a289efba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c (300 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svundef2_b() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svundef4_b() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } undef
# | }
# | 
# | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | !llvm.errno.tbaa = !{!4}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# | !4 = !{!5, !6, i64 0}
# | !5 = !{!"__libc_errno", !6, i64 0}
# | !6 = !{!"int", !7, i64 0}
# | !7 = !{!"omnipotent char", !8, i64 0}
# | !8 = !{!"Simple C/C++ TBAA"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000565166ae3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565166ae0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000565166ae462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f29cf849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f29cf8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f29cf849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f29cf831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565166a79bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565166a79a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000565166a5e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056516670de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056516670db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f29cf832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f29cf8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f29cf8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056516670da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c (301 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svorr_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.orr.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.orr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svorr_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.orr.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.orr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svorr_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svorr_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.orr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.orr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svorr_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.orr.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svorr_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.orr.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svorr_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svorr_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.orr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svorr_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, pt
# | ...
# `---data was truncated (10240/52880) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055897d486eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055897d483e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055897d48762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff0c2049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff0c20a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff0c2049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff0c2031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055897d41cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055897d41ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055897d4018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055897d0b0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055897d0b0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff0c2032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff0c20330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff0c20330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055897d0b0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c (302 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsub_vv_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsub_vx_i8mf8_tu(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsub_vv_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsub_vx_i8mf4_tu(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsub_vv_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsub_vx_i8mf2_tu(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsub_vv_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsub_vx_i8m1_tu(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnmsub_vv_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = loa
# | ...
# `---data was truncated (10240/415311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee38113eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ee38110e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ee3811462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc9f8533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc9f858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc9f8533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc9f851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee380a9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ee380a9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ee3808e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ee37d3de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ee37d3db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc9f851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc9f851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc9f851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee37d3da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_div.c (303 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_div.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdiv_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdiv_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.sdiv.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sdiv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdiv_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.udiv.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.udiv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdiv_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.udiv.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.udiv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdiv_s32_m(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdiv_s64_m(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.sdiv.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdiv_u32_m(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.udiv.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdiv_u64_m(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.udiv.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdiv_s32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call
# | ...
# `---data was truncated (10240/48703) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055816c50eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055816c50be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055816c50f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa22ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa22ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa22ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa22ad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055816c4a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055816c4a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055816c4898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055816c138e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055816c138b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa22ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa22ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa22ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055816c138a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c (304 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svlasta_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.lasta.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.lasta.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svlasta_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.lasta.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.lasta.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svlasta_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.lasta.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.lasta.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlasta_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.lasta.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.lasta.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svlasta_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.lasta.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svlasta_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.lasta.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svlasta_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.lasta.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlasta_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.lasta.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @test_svlasta_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call half @llvm.aarch64.sve.lasta.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret half %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare half @llvm.aarch64.sve.lasta.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @test_svlasta_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call float @llvm.aarch64.sve.lasta.nxv4f32(<vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret float %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare float @llvm.aarch64.sve.lasta.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @test_svlasta_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call double @llvm.aarch64.sve.lasta.nxv2f64(<vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret double %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare double @llvm.aarch64.sve.lasta.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local bfloat @test_svlasta_bf16(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call bfloat @llvm.aarch64.sve.lasta.nxv8bf16(<vscale x 8 x i1> %2, <vscale x 8 x bfloat> %1)
# |   ret bfloat %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willretur
# | ...
# `---data was truncated (10240/10821) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000563746edbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563746ed8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563746edc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc054133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc05418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc054133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc05411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563746e71bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563746e71a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563746e568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563746b05e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563746b05b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc05411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc05411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc05411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563746b05a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-vector-arith-ops.c (305 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-arith-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @add_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %add = add <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @add_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %add = add <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @add_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %add = add <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @add_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %add = add <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @add_u8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %add = add <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @add_u16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %add = add <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @add_u32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %add = add <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @add_u64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %add = add <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @add_f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x half>, align 16
# |   %b.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %b.addr, align 16
# |   %add = fadd <vscale x 8 x half> %0, %1
# |   ret <vscale x 8 x half> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @add_f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x float>, align 16
# |   %b.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %b.addr, align 16
# |   %add = fadd <vscale x 4 x float> %0, %1
# |   ret <vscale x 4 x float> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @add_f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x double>, align 16
# |   %b.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %b.addr, align 16
# |   %add = fadd <vscale x 2 x double> %0, %1
# |   ret <vscale x 2 x double> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @add_inplace_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %add = add <vscale x 16 x i8> %1, %0
# |   store <vscale x 16 x i8> %add, ptr %a.addr, align 16
# |   ret <vscale x 16 x i8> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @add_inplace_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %add = add <vscale x 8 x i16> %1, %0
# |   store <vscale x 8 x i16> %add, ptr %a.addr, align 16
# |   ret <vscale x 8 x i16> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @add_inplace_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %add = add <vscale x 4 x i32> %1, %0
# |   store <vscale x 4 x i32> %add, ptr %a.addr, align 16
# |   ret <vscale x 4 x i32> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @add_inplace_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %add = add <vscale x 2 x i64> %1, %0
# |   store <vscale x 2 x i64> %add, ptr %a.addr, align 16
# |   ret <vscale x 2 x i64> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @add_inplace_u8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %add = add <vscale x 16 x i8> %1, %0
# |   store <vscale x 16 x i8> %add, ptr %a.addr, align 16
# |   ret <vscale x 16 x i8> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @add_inplace_u16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %add = add <vscale x 8 x i16> %1, %0
# |   store <vscale x 8 x i16> %add, ptr %a.addr, align 16
# |   ret <vscale x 8 x i16> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @add_inplace_u32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <
# | ...
# `---data was truncated (10240/107144) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055e8f125eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e8f125be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e8f125f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d57f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d57f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d57f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d57f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e8f11f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e8f11f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e8f11d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e8f0e88e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e8f0e88b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8d57f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d57f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d57f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e8f0e88a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c (306 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svusdot_s32(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.usdot.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svusdot_n_s32(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, i8 noundef %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca i8, align 1
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store i8 %z, ptr %z.addr, align 1
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load i8, ptr %z.addr, align 1
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %2, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svusdot_lane_s32_0(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 0)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svusdot_lane_s32_1(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svusdot_lane_s32_2(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svusdot_lane_s32_3(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+i8mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055973a89ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055973a899e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055973a89d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f0a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f0a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f0a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f0a31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055973a832bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055973a832a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055973a8178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055973a4c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055973a4c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6f0a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f0a31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f0a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055973a4c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c (307 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_vv_u16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_vx_u16mf4(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_wv_u16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_wx_u16mf4(<vscale x 1 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_vv_u16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_vx_u16mf2(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_wv_u16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_wx_u16mf2(<vscale x 2 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwaddu_vv_u16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwaddu_vx_u16m1(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x 
# | ...
# `---data was truncated (10240/134919) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d95c6adeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d95c6aae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d95c6ae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac44e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac44ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac44e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac44e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d95c643bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d95c643a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d95c6288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d95c2d7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d95c2d7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fac44e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac44e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac44e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d95c2d7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c (308 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svasr_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svasr_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svasr_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svasr_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svasr_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svasr_s16_m(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svasr_s32_m(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svasr_s64_m(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svasr_s8_x(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.u.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# | 
# | ...
# `---data was truncated (10240/46416) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005615867afeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005615867ace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005615867b062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f50a9c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f50a9ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f50a9c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f50a9c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561586745bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561586745a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056158672a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005615863d9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005615863d9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f50a9c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f50a9c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f50a9c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615863d9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c (309 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svbrkn_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.brkn.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.brkn.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c6cef80eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c6cef7de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c6cef8162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8a2b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8a2b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8a2b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8a2b631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c6cef16bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c6cef16a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c6ceefb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c6cebaae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c6cebaab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8a2b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8a2b6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8a2b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c6cebaaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c (310 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sme2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sme2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svzero_za64_vg1x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   call void @llvm.aarch64.sme.zero.za64.vg1x2(i32 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.zero.za64.vg1x2(i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svzero_za64_vg1x4(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   call void @llvm.aarch64.sme.zero.za64.vg1x4(i32 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.zero.za64.vg1x4(i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svzero_za64_vg2x1(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   call void @llvm.aarch64.sme.zero.za64.vg2x1(i32 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.zero.za64.vg2x1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svzero_za64_vg2x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   call void @llvm.aarch64.sme.zero.za64.vg2x2(i32 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.zero.za64.vg2x2(i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svzero_za64_vg2x4(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   call void @llvm.aarch64.sme.zero.za64.vg2x4(i32 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.zero.za64.vg2x4(i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svzero_za64_vg4x1(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   call void @llvm.aarch64.sme.zero.za64.vg4x1(i32 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.zero.za64.vg4x1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svzero_za64_vg4x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   call void @llvm.aarch64.sme.zero.za64.vg4x2(i32 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.zero.za64.vg4x2(i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svzero_za64_vg4x4(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   call void @llvm.aarch64.sme.zero.za64.vg4x4(i32 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.zero.za64.vg4x4(i32) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sme2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem1: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000561ccad8deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561ccad8ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561ccad8e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f26649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f266a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f26649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f26631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561ccad23bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561ccad23a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561ccad088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561cca9b7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561cca9b7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1f26632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f266330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f266330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561cca9b7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c (311 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svclamp_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.fclamp.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fclamp.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svclamp_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fclamp.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fclamp.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svclamp_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.fclamp.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fclamp.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055ac6cb08eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ac6cb05e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ac6cb0962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7fa0f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7fa0f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7fa0f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7fa0f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac6ca9ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ac6ca9ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ac6ca838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ac6c732e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ac6c732b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7fa0f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7fa0f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7fa0f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac6c732a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c (312 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f16m1x3(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f16m2x3(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f32m1x3(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f32m2x3(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f64m1x3(ptr noundef %base, <vscale x 1 x i64
# | ...
# `---data was truncated (10240/94235) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562495a91eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562495a8ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562495a9262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc1c9d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc1c9d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc1c9d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc1c9d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562495a27bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562495a27a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562495a0c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005624956bbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005624956bbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc1c9d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc1c9d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc1c9d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005624956bba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c (313 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4e
# | ...
# `---data was truncated (10240/228857) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056472cee7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056472cee4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056472cee862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f35fa133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f35fa18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f35fa133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f35fa11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056472ce7dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056472ce7da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056472ce628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056472cb11e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056472cb11b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f35fa11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f35fa11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f35fa11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056472cb11a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c (314 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilege_b8_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call { <vscale x 16 x i1>, <vscale x 16 x i1> } @llvm.aarch64.sve.whilege.x2.nxv16i1(i64 %0, i64 %1)
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i1>, <vscale x 16 x i1> } @llvm.aarch64.sve.whilege.x2.nxv16i1(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilege_b8_u64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call { <vscale x 16 x i1>, <vscale x 16 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv16i1(i64 %0, i64 %1)
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i1>, <vscale x 16 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv16i1(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilege_b16_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call { <vscale x 8 x i1>, <vscale x 8 x i1> } @llvm.aarch64.sve.whilege.x2.nxv8i1(i64 %0, i64 %1)
# |   %3 = extractvalue { <vscale x 8 x i1>, <vscale x 8 x i1> } %2, 0
# |   %4 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %3)
# |   %5 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %4, 0
# |   %6 = extractvalue { <vscale x 8 x i1>, <vscale x 8 x i1> } %2, 1
# |   %7 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %6)
# |   %8 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %5, <vscale x 16 x i1> %7, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i1>, <vscale x 8 x i1> } @llvm.aarch64.sve.whilege.x2.nxv8i1(i64, i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilege_b16_u64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call { <vscale x 8 x i1>, <vscale x 8 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv8i1(i64 %0, i64 %1)
# |   %3 = extractvalue { <vscale x 8 x i1>, <vscale x 8 x i1> } %2, 0
# |   %4 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %3)
# |   %5 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %4, 0
# |   %6 = extractvalue { <vscale x 8 x i1>, <vscale x 8 x i1> } %2, 1
# |   %7 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %6)
# |   %8 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %5, <vscale x 16 x i1> %7, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i1>, <vscale x 8 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv8i1(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilege_b32_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.whilege.x2.nxv4i1(i64 %0, i64 %1)
# |   %3 = extractvalue { <vscale x 4 x i1>, <vscale x 4 x i1> } %2, 0
# |   %4 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %3)
# |   %5 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %4, 0
# |   %6 = extractvalue { <vscale x 4 x i1>, <vscale x 4 x i1> } %2, 1
# |   %7 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %6)
# |   %8 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %5, <vscale x 16 x i1> %7, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.whilege.x2.nxv4i1(i64, i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilege_b32_u64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv4i1(i64 %0, i64 %1)
# |   %3 = extractvalue { <vscale x 4 x i1>, <vscale x 4 x i1> } %2, 0
# |   %4 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %3)
# |   %5 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %4, 0
# |   %6 = extractvalue { <vscale x 4 x i1>, <vscale x 4 x i1> } %2, 1
# |   %7 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %6)
# |   %8 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %5, <vscale x 16 x i1> %7, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv4i1(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilege_b64_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call { <vscale x 2 x i1>, <vscale x 2 x i1> } @llvm.aarch64.sve.whilege.x2.nxv2i1(i64 %0, i64 %1)
# |   %3 = extractvalue { <vscale x 2 x i1>, <vscale x 2 x i1> } %2, 0
# |   %4 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %3)
# |   %5 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %4, 0
# |   %6 = extractvalue { <vscale x 2 x i1>, <vscale x 2 x i1> } %2, 1
# |   %7 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %6)
# |   %8 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %5, <vscale x 16 x i1> %7, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i1>, <vscale x 2 x i1> } @llvm.aarch64.sve.whilege.x2.nxv2i1(i64, i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilege_b64_u64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call { <vscale x 2 x i1>, <vscale x 2 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv2i1(i64 %0, i64 %1)
# |   %3 = extractvalue { <vscale x 2 x i1>, <vscale x 2 x i1> } %2, 0
# |   %4 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %3)
# |   %5 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %4, 0
# |   %6 = extractvalue { <vscale x 2 x i1>, <vscale x 2 x i1> } %2, 1
# |   %7 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %6)
# |   %8 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %5, <vscale x 16 x i1> %7, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i1>, <vscale x 2 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv2i1(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilegt_b8_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1
# | ...
# `---data was truncated (10240/37926) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000561a0a767eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561a0a764e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561a0a76862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe2da049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe2da0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe2da049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe2da031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a0a6fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561a0a6fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561a0a6e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561a0a391e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561a0a391b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe2da032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe2da0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe2da0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a0a391a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c (315 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svminnm_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svminnm_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svminnm_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svminnm_bf16_n_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svminnm_bf16_n_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svminnm_bf16_n_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000555c1c3f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555c1c3eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555c1c3f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3776333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f377638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3776333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f377631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555c1c387bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555c1c387a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555c1c36c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555c1c01be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555c1c01bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f377631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f377631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f377631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555c1c01ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c (316 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svclamp_bf16(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fclamp.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fclamp.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16b16,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000564a49e2feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564a49e2ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564a49e3062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff2e7049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff2e70a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff2e7049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff2e7031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564a49dc5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564a49dc5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564a49daa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564a49a59e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564a49a59b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff2e7032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff2e70330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff2e70330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564a49a59a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/minnmv.c (317 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/minnmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @test_svminnmv_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call half @llvm.aarch64.sve.fminnmv.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret half %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.sve.fminnmv.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @test_svminnmv_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call float @llvm.aarch64.sve.fminnmv.nxv4f32(<vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret float %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.sve.fminnmv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @test_svminnmv_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call double @llvm.aarch64.sve.fminnmv.nxv2f64(<vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret double %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.sve.fminnmv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x00005583d11e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005583d11e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005583d11e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f72d1f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f72d1f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f72d1f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f72d1f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005583d117abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005583d117aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005583d115f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005583d0e0ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005583d0e0eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f72d1f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f72d1f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f72d1f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005583d0e0ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon/widen.c (318 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/widen.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c --check-prefixes=LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vmovl_s8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vmovl.i = sext <8 x i8> %1 to <8 x i16>
# |   store <8 x i16> %vmovl.i, ptr %ref.tmp.i, align 16
# |   %2 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %2, ptr %__ret.i, align 16
# |   %3 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmovl_s16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x i16>
# |   %vmovl.i = sext <4 x i16> %2 to <4 x i32>
# |   store <4 x i32> %vmovl.i, ptr %ref.tmp.i, align 16
# |   %3 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %3, ptr %__ret.i, align 16
# |   %4 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vmovl_s32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <2 x i32>
# |   %vmovl.i = sext <2 x i32> %2 to <2 x i64>
# |   store <2 x i64> %vmovl.i, ptr %ref.tmp.i, align 16
# |   %3 = load <2 x i64>, ptr %ref.tmp.i, align 16
# |   store <2 x i64> %3, ptr %__ret.i, align 16
# |   %4 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vmovl_u8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vmovl.i = zext <8 x i8> %1 to <8 x i16>
# |   store <8 x i16> %vmovl.i, ptr %ref.tmp.i, align 16
# |   %2 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %2, ptr %__ret.i, align 16
# |   %3 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmovl_u16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x i16>
# |   %vmovl.i = zext <4 x i16> %2 to <4 x i32>
# |   store <4 x i32> %vmovl.i, ptr %ref.tmp.i, align 16
# |   %3 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %3, ptr %__ret.i, align 16
# |   %4 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vmovl_u32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <2 x i32>
# |   %vmovl.i = zext <2 x i32> %2 to <2 x i64>
# |   store <2 x i64> %vmovl.i, ptr %ref.tmp.i, align 16
# |   %3 = load <2 x i64>, ptr %ref.tmp.i, align 16
# |   store <2 x i64> %3, ptr %__ret.i, align 16
# |   %4 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vmovl_high_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i1 = alloca <8 x i8>, align 8
# |   %__p0_561.addr.i = alloca <16 x i8>, align 16
# |   %__ret_561.i = alloca <8 x i16>, align 16
# |   %__a1_561.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %__s0.i = alloca <8 x i8>, align 8
# |   %ref.tmp1.i = alloca <16 x i8>, align 16
# |   %tmp.i = alloca <8 x i16>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0_561.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0_561.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %2, <16 x i8> %3, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i1, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i1, align 8
# |   store <8 x i8> %4, ptr %__a1_561.i, align 8
# |   %5 = load <8 x i8>, ptr %__a1_561.i, align 8
# |   store <8 x i8> %5, ptr %__s0.i, align 8
# |   %6 = load <8 x i8>, ptr %__s0.i, align 8
# |   %7 = sext <8 x i8> %6 to <8 x i16>
# |   store <8 x i16> %7, ptr %ref.tmp1.i, align 16
# |   %8 = load <8 x i16>, ptr %ref.tmp1.i, align 16
# |   store <8 x i16> %8, ptr %__ret.i, align 16
# |   %9 = load <8 x i16>, ptr %__ret.i, align 16
# |   store <8 x i16> %9, ptr %tmp.i, align 16
# |   %10 = load <8 x i16>, ptr %tmp.i, align 16
# |   store <8 x i16> %10, ptr %ref.tmp.i, align 16
# |   %11 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %11, ptr %__ret_561.i, align 16
# |   %12 = load <8 x i16>, ptr %__ret_561.i, align 16
# |   ret <8 x i16> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmovl_high_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i1 = alloca <4 x i16>, align 8
# |   %__p0_567.addr.i = alloca <8 x i16>, align 16
# |   %__ret_567.i = alloca <4 x i32>, align 16
# |   %__a1_567.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %__s0.i = alloca <4 x i16>, align 8
# |   %ref.tmp1.i = alloca <16 x i8>, align 16
# |   %tmp.i = alloca <4 x i32>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0_567.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0_567.addr.i, align 16
# |   store <8 x i16> %1, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %3 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %2, <8 x i16> %3, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i1, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i1, align 8
# |   store <4 x i16> %4, ptr %__a1_567.i, align 8
# |   %5 = load <4 x i16>, ptr %__a1_567.i, align 8
# |   store <4 x i16> %5, ptr %__s0.i, align 8
# |   %6 = load <8 x i8>, ptr %__s0.i, align 8
# |   %7 = bitcast <8 x i8> %6 to <4 x i16>
# |   %8 = sext <4 x i16> %7 to <4 x i32>
# |   store <4 x i32> %8, ptr %ref.tmp1.i, align 16
# |   %9 = load <4 x i32>, ptr %ref.tmp1.i, align 16
# |   store <4 x i32> %9, ptr %__ret.i, align 16
# |   %10 = load <4 x i32>, ptr %__ret.i, align 16
# |   store <4 x i32> %10, ptr %tmp.i, align 16
# |   %11 = load <4 x i32>, ptr %tmp.i, align 16
# |   store <4 x i32> %11, ptr %ref.tmp.i, align 16
# |   %12 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %12, ptr %__ret_567.i, align 16
# |   %13 = load <4 x i32>, ptr %__ret_567.i, align 16
# |   ret <4 x i32> %13
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vmovl_high_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i1 = alloca <2 x i32>, align 8
# |   %__p0_564.addr.i = alloca <4 x i32>, align 16
# |   %__ret_564.i = alloca <2 x i64>, align 16
# |   %__a1_564.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %__s0.i = alloca <2 x i32>, align 8
# |   %ref.tmp1.i = alloca <16 x i8>, align 16
# |   %tmp.i = alloca <2 x i64>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0_564.addr.i, align 16
# |   %1 = load <4 x i32>, ptr %__p0_564.addr.i, align 16
# |   store <4 x i32> %1, ptr %__p0.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %3 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <4 x i32> %2, <4 x i32> %3, <2 x i32> <i32 2, i32 3>
# |   store <2 x i32> %shuffle.i, ptr %__ret.i1, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i1, align 8
# |   store <2 x i32> %4, ptr %__a1_564.i, align 8
# |   %5 = load <2 x i32>, ptr %__a1_564.i, align 8
# |   store <2 x i32> %5, ptr %__s0.i, align 8
# |   %6 = load <8 x i8>, ptr %__s0.i, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x i32>
# |   %8 = sext <2 x i32> %7 to <2 x i64>
# |   store <2 x i64> %8, ptr %ref.tmp1.i, align 16
# |   %9 = load <2 x i64>, ptr %ref.tmp1.i, align 16
# |   store <2 x i64> %9, ptr %__ret.i, align 16
# |   %10 = load <2 x i64>, ptr %__ret.i, align 16
# |   store <2 x i64> %10, ptr %tmp.i, align 16
# |   %11 = load <2 x i64>, ptr %tmp.i, align 16
# |   store <2 x i64> %11, ptr %ref.tmp.i, align 16
# |   %12 = load <2 
# | ...
# `---data was truncated (10240/16529) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000558c26d39eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558c26d36e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558c26d3a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fea4d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fea4d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fea4d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fea4d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c26ccfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558c26ccfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558c26cb48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558c26963e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558c26963b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fea4d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fea4d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fea4d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c26963a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c --check-prefixes=LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c --check-prefixes=LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c (319 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64ff_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(<vscale x 1 x double> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(<vscale x 1 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64ff_v_f64m2_tu(<vscale x 2 x double> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(<vscale x 2 x double> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(<vscale x 2 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vle64ff_v_f64m4_tu(<vscale x 4 x double> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(<vscale x 4 x double> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(<vscale x 4 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vle64ff_v_f64m8_tu(<vscale x 8 x double> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(<vscale x 8 x double> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(<vscale x 8 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64ff_v_i64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(<vscale x 1 x i64> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(<vscale x 1 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64ff_v_i64m2_tu(<vscale x 2 x i64> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(<vscale x 2 x i64> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(<vscale x 2 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64ff_v_i64m4_tu(<vscale x 4 x i64> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(<vscale x 4 x i64> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(<vscale x 4 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64ff_v_i64m8_tu(<vscale x 8 x i64> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x i64>, i64 } @llvm.riscv.vleff.nxv8i64.i64.p0(<vscale x 8 x i64> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x i64>, i64 } @llvm.risc
# | ...
# `---data was truncated (10240/62752) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005582b47ebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005582b47e8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005582b47ec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6c19333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6c1938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6c19333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6c1931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005582b4781bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005582b4781a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005582b47668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005582b4415e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005582b4415b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6c1931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6c1931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6c1931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005582b4415a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c (320 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f16m1x6(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f32m1x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f64m1x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560b73f03eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560b73f00e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560b73f0462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffae3249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffae32a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffae3249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffae3231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b73e99bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560b73e99a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560b73e7e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560b73b2de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560b73b2db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffae3232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffae32330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffae32330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b73b2da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c (321 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f32mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f32mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmmla_f32(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 4 x float>, align 16
# |   %z.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 4 x float> %y, ptr %y.addr, align 16
# |   store <vscale x 4 x float> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %y.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fmmla.nxv4f32.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fmmla.nxv4f32.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f32mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000559571693eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559571690e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055957169462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1647a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1647aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1647a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1647a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559571629bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559571629a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055957160e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005595712bde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005595712bdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1647a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1647a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1647a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005595712bda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c (322 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vle32ff_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(<vscale x 1 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 1 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(<vscale x 1 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vle32ff_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(<vscale x 2 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 2 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(<vscale x 2 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vle32ff_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(<vscale x 4 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(<vscale x 4 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vle32ff_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(<vscale x 8 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 8 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(<vscale x 8 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vle32ff_v_f32m8_tu(<vscale x 16 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(<vscale x 16 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 16 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 16 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(<vscale x 16 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32ff_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(<vscale x 1 x i32> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i32>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i32>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(<vscale x 1 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32ff_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(<vscale x 2 x i32> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x i32>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i32>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(<vscale x 2 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32ff_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.nxv4i32.i64.p0(<vscale x 4 x i32> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x i32>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i32>, i64 } @llvm.risc
# | ...
# `---data was truncated (10240/78164) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005641d9979eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005641d9976e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005641d997a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f06a7a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f06a7aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f06a7a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f06a7a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005641d990fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005641d990fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005641d98f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005641d95a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005641d95a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f06a7a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f06a7a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f06a7a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005641d95a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c (323 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svsel_s8_x4(target("aarch64.svcount") %pn, <vscale x 16 x i8> %zn1.coerce0, <vscale x 16 x i8> %zn1.coerce1, <vscale x 16 x i8> %zn1.coerce2, <vscale x 16 x i8> %zn1.coerce3, <vscale x 16 x i8> %zn2.coerce0, <vscale x 16 x i8> %zn2.coerce1, <vscale x 16 x i8> %zn2.coerce2, <vscale x 16 x i8> %zn2.coerce3) #0 {
# | entry:
# |   %zn1 = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn2 = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pn.addr = alloca target("aarch64.svcount"), align 2
# |   %zn1.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn2.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn1.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn1.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn1.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn1.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn1, align 16
# |   %zn11 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn1, align 16
# |   %4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn2.coerce0, 0
# |   %5 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, <vscale x 16 x i8> %zn2.coerce1, 1
# |   %6 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, <vscale x 16 x i8> %zn2.coerce2, 2
# |   %7 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6, <vscale x 16 x i8> %zn2.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %7, ptr %zn2, align 16
# |   %zn22 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn2, align 16
# |   store target("aarch64.svcount") %pn, ptr %pn.addr, align 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn11, ptr %zn1.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn22, ptr %zn2.addr, align 16
# |   %8 = load target("aarch64.svcount"), ptr %pn.addr, align 2
# |   %9 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn1.addr, align 16
# |   %10 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9, 0
# |   %11 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9, 1
# |   %12 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9, 2
# |   %13 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9, 3
# |   %14 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn2.addr, align 16
# |   %15 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %14, 0
# |   %16 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %14, 1
# |   %17 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %14, 2
# |   %18 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %14, 3
# |   %19 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sel.x4.nxv16i8(target("aarch64.svcount") %8, <vscale x 16 x i8> %10, <vscale x 16 x i8> %11, <vscale x 16 x i8> %12, <vscale x 16 x i8> %13, <vscale x 16 x i8> %15, <vscale x 16 x i8> %16, <vscale x 16 x i8> %17, <vscale x 16 x i8> %18)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %19
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sel.x4.nxv16i8(target("aarch64.svcount"), <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svsel_u8_x4(target("aarch64.svcount") %pn, <vscale x 16 x i8> %zn1.coerce0, <vscale x 16 x i8> %zn1.coerce1, <vscale x 16 x i8> %zn1.coerce2, <vscale x 16 x i8> %zn1.coerce3, <vscale x 16 x i8> %zn2.coerce0, <vscale x 16 x i8> %zn2.coerce1, <vscale x 16 x i8> %zn2.coerce2, <vscale x 16 x i8> %zn2.coerce3, ptr nofreeobj noundef align 16 dead_on_return %0, ptr nofreeobj noundef align 16 dead_on_return %1) #0 {
# | entry:
# |   %zn1 = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn2 = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pn.addr = alloca target("aarch64.svcount"), align 2
# |   %zn1.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn2.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn3.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn4.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn1.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn1.coerce1, 1
# |   %4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, <vscale x 16 x i8> %zn1.coerce2, 2
# |   %5 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, <vscale x 16 x i8> %zn1.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, ptr %zn1, align 16
# |   %zn11 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn1, align 16
# |   %6 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn2.coerce0, 0
# |   %7 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6, <vscale x 16 x i8> %zn2.coerce1, 1
# |   %8 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %7, <vscale x 16 x i8> %zn2.coerce2, 2
# |   %9 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %8, <vscale x 16 x i8> %zn2.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9, ptr %zn2, align 16
# |   %zn22 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn2, align 16
# |   %zn3 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %0, align 16
# |   %zn4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %1, align 16
# |   store target("aarch64.svcount") %pn, ptr %pn.addr, align 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn11, ptr %zn1.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn22, ptr %zn2.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn3, ptr %zn3.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn4, ptr %zn4.addr, align 16
# |   %10 = load target("aarch64.svcount"), ptr %pn.addr, align 2
# |   %11 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn1.addr, align 16
# |   %12 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %11, 0
# |   %13 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %11, 1
# |   %14 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %11, 2
# |   %15 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %11, 3
# |   %16 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn2.addr, align 16
# |   %17 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %16, 0
# |   %18 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %16, 1
# |   %19 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %16, 2
# |   %20 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %16, 3
# |   %21 = call { <vscale x 16 x i8>, <vscale x 16 
# | ...
# `---data was truncated (10240/73319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim
# |  #0 0x000055da0f009eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055da0f006e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055da0f00a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5e48e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5e48e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5e48e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5e48e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da0ef9fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055da0ef9fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055da0ef848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055da0ec33e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055da0ec33b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5e48e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5e48e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5e48e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da0ec33a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c (324 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsel_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsel_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsel_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svsel_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsel_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsel_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsel_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svsel_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svsel_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.sel.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.sel.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_
# | ...
# `---data was truncated (10240/15264) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055a3fa824eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a3fa821e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a3fa82562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe9bb333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe9bb38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe9bb333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe9bb31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a3fa7babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a3fa7baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a3fa79f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a3fa44ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a3fa44eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe9bb31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe9bb31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe9bb31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a3fa44ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c (325 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svqsub_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.sqsub.x.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.sqsub.x.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqsub_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqsub.x.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqsub.x.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqsub_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.sqsub.x.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sqsub.x.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqsub_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.sqsub.x.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sqsub.x.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svqsub_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uqsub.x.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uqsub.x.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqsub_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqsub.x.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqsub.x.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqsub_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uqsub.x.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uqsub.x.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqsub_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uqsub.x.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uqsub.x.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svqsub_n_s8(<vscale x 16 x i8> %op1, i8 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca i8, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store i8 %op2, ptr %op2.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.sqsub.x.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqsub_n_s16(<vscale x 8 x i16> %op1, i16 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca i16, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store i16 %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqsub.x.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqsub_n_s32(<vscale x 4 x i32> %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca i32, align 4
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %.splatinsert = insertelement <vscale x 4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <vscale x 4 x i32> %.splatinsert, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.sqsub.x.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %.splat)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqsub_n_s64(<vscale x 2 x i64> %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %.splatinsert = insertelement <vscale x 2 x i64> poison, i64 %1, i64 0
# |   %.splat = shufflevector <vscale x 2 x i64> %.splatinsert, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.sqsub.x.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %.splat)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_l
# | ...
# `---data was truncated (10240/13780) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560b2224eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560b2224be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560b2224f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3302e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3302ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3302e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3302e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b221e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560b221e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560b221c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560b21e78e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560b21e78b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3302e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3302e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3302e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b21e78a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c (326 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmsb_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %6 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmsb.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fnmsb.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svnmsb_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %6 = call <vscale x 4 x float> @llvm.aarch64.sve.fnmsb.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %5, <vscale x 4 x float> %2, <vscale x 4 x float> %3)
# |   ret <vscale x 4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fnmsb.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svnmsb_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %6 = call <vscale x 2 x double> @llvm.aarch64.sve.fnmsb.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %5, <vscale x 2 x double> %2, <vscale x 2 x double> %3)
# |   ret <vscale x 2 x double> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fnmsb.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmsb_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmsb.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svnmsb_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fnmsb.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svnmsb_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fnmsb.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmsb_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmls.u.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %3, <vscale x 8 x half> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind w
# | ...
# `---data was truncated (10240/26173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000556ed937feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556ed937ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556ed938062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff251733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff25178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff251733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff25171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ed9315bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556ed9315a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556ed92fa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556ed8fa9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556ed8fa9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff25171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff25171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff25171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556ed8fa9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c (327 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcmla_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %6 = call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 0)
# |   ret <vscale x 8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcmla_f16_z_1(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %6 = call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 90)
# |   ret <vscale x 8 x half> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcmla_f16_z_2(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %6 = call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 180)
# |   ret <vscale x 8 x half> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcmla_f16_z_3(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %6 = call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 270)
# |   ret <vscale x 8 x half> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svcmla_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %6 = call <vscale x 4 x float> @llvm.aarch64.sve.fcmla.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %5, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i32 0)
# |   ret <vscale x 4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fcmla.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svcmla_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %6 = call <vscale x 2 x double> @llvm.aarch64.sve.fcmla.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %5, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i32 90)
# |   ret <vscale x 2 x double> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fcmla.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcmla_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale
# | ...
# `---data was truncated (10240/21122) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005629795fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005629795f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005629795fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fae52d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fae52d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fae52d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fae52d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562979592bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562979592a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005629795778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562979226e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562979226b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fae52d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fae52d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fae52d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562979226a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vbrsrq.c (328 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vbrsrq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbrsrq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call <4 x i32> @llvm.arm.mve.vbrsr.v4i32(<4 x i32> %0, i32 %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vbrsr.v4i32(<4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vbrsrq_n_f16(<8 x half> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call <8 x half> @llvm.arm.mve.vbrsr.v8f16(<8 x half> %0, i32 %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vbrsr.v8f16(<8 x half>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vbrsrq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load i32, ptr %b.addr, align 4
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4)
# |   %6 = call <16 x i8> @llvm.arm.mve.vbrsr.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 %2, <16 x i1> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vbrsr.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vbrsrq_m_n_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %inactive.addr, align 8
# |   %1 = load <4 x float>, ptr %a.addr, align 8
# |   %2 = load i32, ptr %b.addr, align 4
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call <4 x float> @llvm.arm.mve.vbrsr.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 %2, <4 x i1> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vbrsr.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbrsrq_x_n_u16(<8 x i16> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vbrsr.predicated.v8i16.v8i1(<8 x i16> undef, <8 x i16> %0, i32 %1, <8 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vbrsr.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vbrsrq_x_n_f16(<8 x half> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x half> @llvm.arm.mve.vbrsr.predicated.v8f16.v8i1(<8 x half> undef, <8 x half> %0, i32 %1, <8 x i1> %4)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vbrsr.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560dec664eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560dec661e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560dec66562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e5cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e5cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e5cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e5cd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560dec5fabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560dec5faa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560dec5df8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560dec28ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560dec28eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0e5cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e5cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e5cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560dec28ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c (329 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svrshl_single_s8_x2(<vscale x 16 x i8> %zdn.coerce0, <vscale x 16 x i8> %zdn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zdn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zdn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.srshl.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.srshl.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svrshl_single_s16_x2(<vscale x 8 x i16> %zdn.coerce0, <vscale x 8 x i16> %zdn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zdn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.srshl.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.srshl.single.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svrshl_single_s32_x2(<vscale x 4 x i32> %zdn.coerce0, <vscale x 4 x i32> %zdn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zdn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zdn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zdn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.srshl.single.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.srshl.single.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svrshl_single_s64_x2(<vscale x 2 x i64> %zdn.coerce0, <vscale x 2 x i64> %zdn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zdn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zdn.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zdn, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 0
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 1
# |   %5 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.srshl.single.x2.nxv2i64(<vscale x 2 x i64> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.srshl.single.x2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svrshl_single_u8_x2(<vscale x 16 x i8> %zdn.coerce0, <vscale x 16 x i8> %zdn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zdn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zdn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.urshl.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.urshl.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svrshl_single_u16_x2(<vscale x 8 x i16> %zdn.coerce0, <vscale x 8 x i16> %zdn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zdn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.urshl.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> 
# | ...
# `---data was truncated (10240/93119) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055c9d000ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c9d0009e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c9d000d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6beaf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6beaf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6beaf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6beaeed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9cffa2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c9cffa2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c9cff878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c9cfc36e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c9cfc36b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6beaeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6beaeef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6beaeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c9cfc36a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c (330 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_x_f_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_x_f_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_x_f_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_x_f_v_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_x_f_v_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_x_f_v_i16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> %0, <vscale x 32 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_xu_f_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_xu_f_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_xu_f_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_xu_f_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x
# | ...
# `---data was truncated (10240/514173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a055482eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a05547fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a05548362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2fc4a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2fc4aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2fc4a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2fc4a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a055418bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a055418a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a0553fd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a0550ace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a0550acb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2fc4a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2fc4a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2fc4a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a0550aca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c (331 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vv_f32mf2(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vf_f32mf2(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wv_f32mf2(<vscale x 1 x float> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wf_f32mf2(<vscale x 1 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vv_f32m1(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vf_f32m1(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wv_f32m1(<vscale x 2 x float> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wf_f32m1(<vscale x 2 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwsub_vv_f32m2(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwsub_vf_f32m2(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/151903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558501c8deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558501c8ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558501c8e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f739ba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f739baa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f739ba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f739ba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558501c23bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558501c23a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558501c088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005585018b7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005585018b7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f739ba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f739ba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f739ba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005585018b7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-vls-compare-ops.c (332 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-compare-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone -mvscale-min=4 -mvscale-max=4   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i1> @eq_bool(<vscale x 16 x i1> noundef %0, <vscale x 16 x i1> noundef %1) #0 {
# | entry:
# |   %retval = alloca <8 x i8>, align 2
# |   %a.addr = alloca <8 x i8>, align 2
# |   %b.addr = alloca <8 x i8>, align 2
# |   %a.coerce = bitcast <vscale x 16 x i1> %0 to <vscale x 2 x i8>
# |   %a = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> %a.coerce, i64 0)
# |   %b.coerce = bitcast <vscale x 16 x i1> %1 to <vscale x 2 x i8>
# |   %b = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> %b.coerce, i64 0)
# |   store <8 x i8> %a, ptr %a.addr, align 2
# |   store <8 x i8> %b, ptr %b.addr, align 2
# |   %2 = load <8 x i8>, ptr %a.addr, align 2
# |   %3 = load <8 x i8>, ptr %b.addr, align 2
# |   %cmp = icmp eq <8 x i8> %2, %3
# |   %sext = sext <8 x i1> %cmp to <8 x i8>
# |   store <8 x i8> %sext, ptr %retval, align 2
# |   %4 = load <8 x i8>, ptr %retval, align 2
# |   %cast.scalable = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> poison, <8 x i8> %4, i64 0)
# |   %5 = bitcast <vscale x 2 x i8> %cast.scalable to <vscale x 16 x i1>
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8>, <8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @eq_i8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %cmp = icmp eq <64 x i8> %0, %1
# |   %sext = sext <64 x i1> %cmp to <64 x i8>
# |   store <64 x i8> %sext, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8>, <64 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @eq_i16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %cmp = icmp eq <32 x i16> %0, %1
# |   %sext = sext <32 x i1> %cmp to <32 x i16>
# |   store <32 x i16> %sext, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16>, <32 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i32> @eq_i32(<vscale x 4 x i32> noundef %a.coerce, <vscale x 4 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i32>, align 16
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca <16 x i32>, align 16
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %b.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i32>, ptr %b.addr, align 16
# |   %cmp = icmp eq <16 x i32> %0, %1
# |   %sext = sext <16 x i1> %cmp to <16 x i32>
# |   store <16 x i32> %sext, ptr %retval, align 16
# |   %2 = load <16 x i32>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> poison, <16 x i32> %2, i64 0)
# |   ret <vscale x 4 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32>, <16 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i64> @eq_i64(<vscale x 2 x i64> noundef %a.coerce, <vscale x 2 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i64>, align 16
# |   %a.addr = alloca <8 x i64>, align 16
# |   %b.addr = alloca <8 x i64>, align 16
# |   %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %a.coerce, i64 0)
# |   %b = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %b.coerce, i64 0)
# |   store <8 x i64> %a, ptr %a.addr, align 16
# |   store <8 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i64>, ptr %a.addr, align 16
# |   %1 = load <8 x i64>, ptr %b.addr, align 16
# |   %cmp = icmp eq <8 x i64> %0, %1
# |   %sext = sext <8 x i1> %cmp to <8 x i64>
# |   store <8 x i64> %sext, ptr %retval, align 16
# |   %2 = load <8 x i64>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> poison, <8 x i64> %2, i64 0)
# |   ret <vscale x 2 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64>, <8 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @eq_u8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %cmp = icmp eq <64 x i8> %0, %1
# |   %sext = sext <64 x i1> %cmp to <64 x i8>
# |   store <64 x i8> %sext, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @eq_u16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %cmp = icmp eq <32 x i16> %0, %1
# |   %sext = sext <32 x i1> %cmp to <32 x i16>
# |   store <32 x i16> %sext, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i32> @eq_u32(<vscale x 4 x i32> noundef %a.coerce, <vscale x 4 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i32>, align 16
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca <16 x i32>, align 16
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %b.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i32>, ptr %b.addr, align 16
# |   %cmp = icmp eq <16 x i32> %0, %1
# |   %sext = sext <16 x i1> %cmp to <16 x 
# | ...
# `---data was truncated (10240/78785) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055a573e73eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a573e70e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a573e7462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f18ffa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f18ffaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f18ffa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f18ffa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a573e09bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a573e09a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a573dee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a573a9de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a573a9db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f18ffa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f18ffa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f18ffa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a573a9da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c (333 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 31)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.cntd(i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_1() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_2() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_3() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_4() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 4)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_5() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 5)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_6() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 6)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_7() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_8() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 8)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_9() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 9)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_10() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 10)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_11() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 11)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_12() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 12)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_13() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 13)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_14() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 29)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_15() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 30)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_16() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 31)
# |   ret i64 %0
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055a1e5508eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a1e5505e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a1e550962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f79a3049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f79a30a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f79a3049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f79a3031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a1e549ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a1e549ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a1e54838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a1e5132e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a1e5132b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f79a3032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f79a30330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f79a30330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a1e5132a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c (334 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_luti4_zt_u8_x4(<vscale x 16 x i8> %op.coerce0, <vscale x 16 x i8> %op.coerce1) #0 {
# | entry:
# |   %op = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %op.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %op.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %op.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %op, align 16
# |   %op1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %op, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %op1, ptr %op.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %op.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti4.zt.x4.nxv16i8(i32 0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti4.zt.x4.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_luti4_zt_s8_x4(<vscale x 16 x i8> %op.coerce0, <vscale x 16 x i8> %op.coerce1) #0 {
# | entry:
# |   %op = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %op.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %op.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %op.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %op, align 16
# |   %op1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %op, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %op1, ptr %op.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %op.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti4.zt.x4.nxv16i8(i32 0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme-lutv2,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055679e039eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055679e036e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055679e03a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff63d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff63d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff63d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff63d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055679dfcfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055679dfcfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055679dfb48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055679dc63e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055679dc63b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff63d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff63d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff63d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055679dc63a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c (335 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_sveor_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.eor.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.eor.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_sveor_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.eor.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.eor.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_sveor_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.eor.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.eor.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_sveor_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.eor.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.eor.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_sveor_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.eor.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_sveor_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.eor.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_sveor_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.eor.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_sveor_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.eor.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_sveor_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, pt
# | ...
# `---data was truncated (10240/52880) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000564e850e1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564e850dee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564e850e262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efe79649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efe796a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efe79649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efe79631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564e85077bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564e85077a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564e8505c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564e84d0be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564e84d0bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efe79632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efe796330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efe796330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564e84d0ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c (336 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfdot_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfdot(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfdot(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfdot_lane_0_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfdot.lane.v2(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 0)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfdot.lane.v2(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfdot_lane_3_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfdot.lane.v2(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfdot_n_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, bfloat noundef %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca bfloat, align 2
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store bfloat %z, ptr %z.addr, align 2
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load bfloat, ptr %z.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfdot(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055fe41381eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fe4137ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fe4138262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc167533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc16758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc167533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc16751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fe41317bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fe41317a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fe412fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fe40fabe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fe40fabb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc16751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc16751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc16751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fe40faba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c (337 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntp_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call i64 @llvm.aarch64.sve.cntp.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.cntp.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntp_b16(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.cntp.nxv8i1(<vscale x 8 x i1> %2, <vscale x 8 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.cntp.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntp_b32(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.cntp.nxv4i1(<vscale x 4 x i1> %2, <vscale x 4 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.cntp.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntp_b64(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.cntp.nxv2i1(<vscale x 2 x i1> %2, <vscale x 2 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.cntp.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055b370d95eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b370d92e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b370d9662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb05d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb05d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb05d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb05d031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b370d2bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b370d2ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b370d108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b3709bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b3709bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb05d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb05d0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb05d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b3709bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon/intrinsics.c (338 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vmaxnmv_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca float, align 4
# |   %ref.tmp.i = alloca float, align 4
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %vmaxnmv_f32.i = call float @llvm.aarch64.neon.fmaxnmv.f32.v2f32(<2 x float> %1)
# |   store float %vmaxnmv_f32.i, ptr %ref.tmp.i, align 4
# |   %2 = load float, ptr %ref.tmp.i, align 4
# |   store float %2, ptr %__ret.i, align 4
# |   %3 = load float, ptr %__ret.i, align 4
# |   ret float %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vmaxnmvq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca float, align 4
# |   %ref.tmp.i = alloca float, align 4
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %vmaxnmvq_f32.i = call float @llvm.aarch64.neon.fmaxnmv.f32.v4f32(<4 x float> %1)
# |   store float %vmaxnmvq_f32.i, ptr %ref.tmp.i, align 4
# |   %2 = load float, ptr %ref.tmp.i, align 4
# |   store float %2, ptr %__ret.i, align 4
# |   %3 = load float, ptr %__ret.i, align 4
# |   ret float %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_vmaxnmvq_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca double, align 8
# |   %ref.tmp.i = alloca double, align 8
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x double>, ptr %__p0.addr.i, align 16
# |   %vmaxnmvq_f64.i = call double @llvm.aarch64.neon.fmaxnmv.f64.v2f64(<2 x double> %1)
# |   store double %vmaxnmvq_f64.i, ptr %ref.tmp.i, align 8
# |   %2 = load double, ptr %ref.tmp.i, align 8
# |   store double %2, ptr %__ret.i, align 8
# |   %3 = load double, ptr %__ret.i, align 8
# |   ret double %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i8 @test_vqrshrunh_n_s16(i16 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca i16, align 2
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %__s0, align 2
# |   %1 = load i16, ptr %__s0, align 2
# |   %2 = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %vqrshrunh_n_s16 = call <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16> %2, i32 8)
# |   %3 = extractelement <8 x i8> %vqrshrunh_n_s16, i64 0
# |   store i8 %3, ptr %ref.tmp, align 1
# |   %4 = load i8, ptr %ref.tmp, align 1
# |   store i8 %4, ptr %__ret, align 1
# |   %5 = load i8, ptr %__ret, align 1
# |   store i8 %5, ptr %tmp, align 1
# |   %6 = load i8, ptr %tmp, align 1
# |   ret i8 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vqrshruns_n_s32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca i32, align 4
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__s0, align 4
# |   %1 = load i32, ptr %__s0, align 4
# |   %2 = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %vqrshruns_n_s32 = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> %2, i32 16)
# |   %3 = extractelement <4 x i16> %vqrshruns_n_s32, i64 0
# |   store i16 %3, ptr %ref.tmp, align 2
# |   %4 = load i16, ptr %ref.tmp, align 2
# |   store i16 %4, ptr %__ret, align 2
# |   %5 = load i16, ptr %__ret, align 2
# |   store i16 %5, ptr %tmp, align 2
# |   %6 = load i16, ptr %tmp, align 2
# |   ret i16 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i8 @test_vqrshrnh_n_s16(i16 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca i16, align 2
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %__s0, align 2
# |   %1 = load i16, ptr %__s0, align 2
# |   %2 = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %vqrshrnh_n_s16 = call <8 x i8> @llvm.aarch64.neon.sqrshrn.v8i8(<8 x i16> %2, i32 8)
# |   %3 = extractelement <8 x i8> %vqrshrnh_n_s16, i64 0
# |   store i8 %3, ptr %ref.tmp, align 1
# |   %4 = load i8, ptr %ref.tmp, align 1
# |   store i8 %4, ptr %__ret, align 1
# |   %5 = load i8, ptr %__ret, align 1
# |   store i8 %5, ptr %tmp, align 1
# |   %6 = load i8, ptr %tmp, align 1
# |   ret i8 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i8> @llvm.aarch64.neon.sqrshrn.v8i8(<8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vqrshrns_n_s32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca i32, align 4
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__s0, align 4
# |   %1 = load i32, ptr %__s0, align 4
# |   %2 = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %vqrshrns_n_s32 = call <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32> %2, i32 16)
# |   %3 = extractelement <4 x i16> %vqrshrns_n_s32, i64 0
# |   store i16 %3, ptr %ref.tmp, align 2
# |   %4 = load i16, ptr %ref.tmp, align 2
# |   store i16 %4, ptr %__ret, align 2
# |   %5 = load i16, ptr %__ret, align 2
# |   store i16 %5, ptr %tmp, align 2
# |   %6 = load i16, ptr %tmp, align 2
# |   ret i16 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i8 @test_vqrshrnh_n_u16(i16 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca i16, align 2
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %__s0, align 2
# |   %1 = load i16, ptr %__s0, align 2
# |   %2 = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %vqrshrnh_n_u16 = call <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16> %2, i32 8)
# |   %3 = extractelement <8 x i8> %vqrshrnh_n_u16, i64 0
# |   store i8 %3, ptr %ref.tmp, align 1
# |   %4 = load i8, ptr %ref.tmp, align 1
# |   store i8 %4, ptr %__ret, align 1
# |   %5 = load i8, ptr %__ret, align 1
# |   store i8 %5, ptr %tmp, align 1
# |   %6 = load i8, ptr %tmp, align 1
# |   ret i8 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vqrshrns_n_u32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca i32, align 4
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__s0, align 4
# |   %1 = load i32, ptr %__s0, align 4
# |   %2 = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %vqrshrns_n_u32 = call <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32> %2, i32 16)
# |   %3 = extractelement <4 x i16> %vqrshrns_n_u32, i64 0
# |   store i16 %3, ptr %ref.tmp, align 2
# |   %4 = load i16, ptr %ref.tmp, align 2
# |   store i16 %4, ptr %__ret, align 2
# |   %5 = load i16, ptr %__ret, align 2
# |   store i16 %5, ptr %tmp, align 2
# |   %6 = load i16, ptr %tmp, align 2
# |   ret i16 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vqrshrun_n_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 16
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__s0, align 16
# |   %1 = load <16 x i8>, ptr %__s0, align 16
# |   %vqrshrun_n = bitcast <16 x i8> %1 to <8 x i16>
# |   %vqrshrun_n1 = call <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16> %vqrshrun_n, i32 3)
# |   store <8 x i8> %vqrshrun_n1, ptr %ref.tmp, align 8
# |   %2 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %2, ptr %__ret, align 8
# |   %3 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %3, ptr %tmp, align 8
# |   %4 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vqrshrun_n_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 16
# |   %__ret = alloca <4 x i16>, align 8
# |   %__s0 = alloca <4 x i32>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x i16>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__s0, align 16
# |   %1 = load <16 x i8>, ptr %__s0, align 16
# |   %vqrshrun_n = bitcast <16 x i8> %1 to <4 x i32>
# |   %vqrshrun_n1 = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> %vqrshrun_n, i32 9)
# |   store <4 x i16> %vqrshrun_n1, ptr %ref.tmp, align 8
# |   %2 = load <4 x i16>, ptr %ref.tmp, align 8
# |   store <4 x i16> %2, ptr %__ret, align 8
# |   %3 = load <4 x i16>, p
# | ...
# `---data was truncated (10240/770739) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000560b79fa8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560b79fa5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560b79fa962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efd90049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efd900a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efd90049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efd90031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b79f3ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560b79f3ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560b79f238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560b79bd2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560b79bd2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efd90032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efd900330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efd900330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b79bd2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c (339 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1   -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_lane_u8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv16i8(<vscale x 16 x i8> %0, i32 0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv16i8(<vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_lane_s8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv16i8(<vscale x 16 x i8> %0, i32 0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_lane_u16(<vscale x 8 x i16> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv8i16(<vscale x 8 x i16> %0, i32 0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv8i16(<vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_lane_s16(<vscale x 8 x i16> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv8i16(<vscale x 8 x i16> %0, i32 1)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_lane_u32(<vscale x 4 x i32> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv4i32(<vscale x 4 x i32> %0, i32 0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv4i32(<vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_lane_s32(<vscale x 4 x i32> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv4i32(<vscale x 4 x i32> %0, i32 3)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_lane_u64(<vscale x 2 x i64> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv2i64(<vscale x 2 x i64> %0, i32 0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv2i64(<vscale x 2 x i64>, i32 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_lane_s64(<vscale x 2 x i64> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv2i64(<vscale x 2 x i64> %0, i32 7)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_u8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv16i8(<vscale x 16 x i8> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv16i8(<vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_s8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv16i8(<vscale x 16 x i8> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_u16(<vscale x 8 x i16> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv8i16(<vscale x 8 x i16> %0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv8i16(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_s16(<vscale x 8 x i16> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv8i16(<vscale x 8 x i16> %0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_u32(<vscale x 4 x i32> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv4i32(<vscale x 4 x i32> %0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv4i32(<vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_s32(<vscale x 4 x i32> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv4i32(<vscale x 4 x i32> %0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_u64(<vscale x 2 x i64> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv2i64(<vscale x 2 x i64> %0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv2i64(<vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x
# | ...
# `---data was truncated (10240/11356) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000565434268eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565434265e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056543426962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fda26f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fda26f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fda26f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fda26eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005654341febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005654341fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005654341e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565433e92e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565433e92b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fda26eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fda26eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fda26eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565433e92a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c (340 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_lane_bf16_idx1(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 1)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.lane.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_lane_bf16_idx3(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_lane_bf16_idx7(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 7)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16b16,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000555833d7eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555833d7be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555833d7f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3839649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f38396a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3839649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3839631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555833d14bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555833d14a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555833cf98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005558339a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005558339a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3839632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f38396330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f38396330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005558339a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c (341 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdup_laneq_s8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.laneq.nxv16i8(<vscale x 16 x i8> %0, i32 0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.dup.laneq.nxv16i8(<vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdup_laneq_u8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.laneq.nxv16i8(<vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdup_laneq_s16(<vscale x 8 x i16> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.laneq.nxv8i16(<vscale x 8 x i16> %0, i32 1)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.dup.laneq.nxv8i16(<vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdup_laneq_u16(<vscale x 8 x i16> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.laneq.nxv8i16(<vscale x 8 x i16> %0, i32 7)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdup_laneq_s32(<vscale x 4 x i32> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.laneq.nxv4i32(<vscale x 4 x i32> %0, i32 2)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.dup.laneq.nxv4i32(<vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdup_laneq_u32(<vscale x 4 x i32> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.laneq.nxv4i32(<vscale x 4 x i32> %0, i32 3)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdup_laneq_s64(<vscale x 2 x i64> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.laneq.nxv2i64(<vscale x 2 x i64> %0, i32 0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.dup.laneq.nxv2i64(<vscale x 2 x i64>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdup_laneq_u64(<vscale x 2 x i64> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.laneq.nxv2i64(<vscale x 2 x i64> %0, i32 1)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svdup_laneq_f16(<vscale x 8 x half> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x half> @llvm.aarch64.sve.dup.laneq.nxv8f16(<vscale x 8 x half> %0, i32 4)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.dup.laneq.nxv8f16(<vscale x 8 x half>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdup_laneq_f32(<vscale x 4 x float> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x float> @llvm.aarch64.sve.dup.laneq.nxv4f32(<vscale x 4 x float> %0, i32 1)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.dup.laneq.nxv4f32(<vscale x 4 x float>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svdup_laneq_f64(<vscale x 2 x double> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 2 x double> @llvm.aarch64.sve.dup.laneq.nxv2f64(<vscale x 2 x double> %0, i32 1)
# |   ret <vscale x 2 x double> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.dup.laneq.nxv2f64(<vscale x 2 x double>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svdup_laneq_bf16(<vscale x 8 x bfloat> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.dup.laneq.nxv8bf16(<vscale x 8 x bfloat> %0, i32 3)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.dup.laneq.nxv8bf16(<vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdup_laneq_mf8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.laneq.nxv16i8(<vscale x 16 x i8> %0, i32 1)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000056292edc5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056292edc2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056292edc662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb2a0649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb2a06a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb2a0649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb2a0631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056292ed5bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056292ed5ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056292ed408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056292e9efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056292e9efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb2a0632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb2a06330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb2a06330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056292e9efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c (342 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtblq_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.tblq.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.tblq.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtblq_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.tblq.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.tblq.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtblq_u32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.tblq.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.tblq.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtblq_u64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.tblq.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.tblq.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtblq_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.tblq.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtblq_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.tblq.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtblq_s32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.tblq.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtblq_s64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.tblq.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtblq_f16(<vscale x 8 x half> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.tblq.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.tblq.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtblq_f32(<vscale x 4 x float> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x float>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x float> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.tblq.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.tblq.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtblq_f64(<vscale x 2 x double> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x double>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x double> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.tblq.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.tblq.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svtblq_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.tblq.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.tblq.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtblq_mf8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.tblq.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "sta
# | ...
# `---data was truncated (10240/10820) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005589fdfbfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005589fdfbce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005589fdfc062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6a44a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6a44a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6a44a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6a44a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589fdf55bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005589fdf55a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005589fdf3a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005589fdbe9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005589fdbe9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6a44a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6a44a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6a44a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005589fdbe9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c (343 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 2 x i64> %2 to <vscale x 2 x i32>
# |   call void @llvm.aarch64.sve.st1.nxv2i32.p0(<vscale x 2 x i32> %4, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv2i32.p0(<vscale x 2 x i32>, <vscale x 2 x i1>, ptr captures(none)) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 2 x i64> %2 to <vscale x 2 x i32>
# |   call void @llvm.aarch64.sve.st1.nxv2i32.p0(<vscale x 2 x i32> %4, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 2 x i64> %3 to <vscale x 2 x i32>
# |   call void @llvm.aarch64.sve.st1.nxv2i32.p0(<vscale x 2 x i32> %6, <vscale x 2 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 2 x i64> %3 to <vscale x 2 x i32>
# |   call void @llvm.aarch64.sve.st1.nxv2i32.p0(<vscale x 2 x i32> %6, <vscale x 2 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_scatter_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = trunc <vscale x 2 x i64> %2 to <vscale x 2 x i32>
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i32> %3, <vscale x 2 x i1> %4, <vscale x 2 x i64> %1, i64 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i32>, <vscale x 2 x i1>, <vscale x 2 x i64>, i64) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_scatter_u64base_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = trunc <vscale x 2 x i64> %2 to <vscale x 2 x i32>
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i32> %3, <vscale x 2 x i1> %4, <vscale x 2 x i64> %1, i64 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_scatter_s64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = trunc <vscale x 2 x i64> %3 to <vscale x 2 x i32>
# |   %5 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.scatter.nxv2i32.p0(<vscale x 2 x i32> %4, <vscale x 2 x i1> %5, ptr %1, <vscale x 2 x i64> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.aarch64.sve.st1.scatter.nxv2i32.p0(<vscale x 2 x i32>, <vscale x 2 x i1>, ptr, <vscale x 2 x i64>) #4
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_scatter_s64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = trunc <vscale x 2 x i64> %3 to <vscale x 2 x i32>
# |   %5 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.scatter.nxv2i32.p0(<vscale x 2 x i32> %4, <vscale x 2 x i1> %5, ptr %1, <vscale x 2 x i64> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_scatter_u64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = load <vscale x 2 x i64
# | ...
# `---data was truncated (10240/21923) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x0000563c164a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563c1649fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563c164a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f17d8b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f17d8b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f17d8b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f17d8aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c16438bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563c16438a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563c1641d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563c160cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563c160ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f17d8aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f17d8aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f17d8aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c160cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c (344 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1sb_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sb_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sb_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1sb_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sb_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sb_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1sb_vnum_s16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sb_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i8> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sb_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i8> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1sb_vnum_u16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sb_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4
# | ...
# `---data was truncated (10240/27977) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x00005640c7f26eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005640c7f23e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005640c7f2762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0a21d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0a21d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0a21d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0a21d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005640c7ebcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005640c7ebca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005640c7ea18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005640c7b50e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005640c7b50b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0a21d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0a21d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0a21d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005640c7b50a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c (345 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_i64m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_u64m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055db15942eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055db1593fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055db1594362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8cdd81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8cdd8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8cdd81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8cdd803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055db158d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055db158d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055db158bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055db1556ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055db1556cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8cdd804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8cdd8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8cdd8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055db1556ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c (346 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local target("aarch64.svcount") @test_svpfalse_c() #0 {
# | entry:
# |   ret target("aarch64.svcount") zeroinitializer
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000555b88893eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555b88890e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555b8889462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbac3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbac338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbac3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbac331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b88829bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555b88829a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555b8880e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555b884bde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555b884bdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbac331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbac331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbac331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b884bda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c (347 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte32_f32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vlte32.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte32_i32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte32_u32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555e302eaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555e302e7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555e302eb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9e0c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9e0c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9e0c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9e0c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555e30280bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555e30280a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555e302658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555e2ff14e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555e2ff14b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9e0c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9e0c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9e0c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555e2ff14a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c (348 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svminnm_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fminnm.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %4, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fminnm.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svminnm_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fminnm.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %4, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fminnm.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svminnm_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fminnm.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %4, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fminnm.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svminnm_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fminnm.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svminnm_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fminnm.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svminnm_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.fminnm.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svminnm_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fminnm.u.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fminnm.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svminnm_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fminnm.u.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fminnm.u.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svminnm_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.ad
# | ...
# `---data was truncated (10240/22107) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c6eafa8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c6eafa5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c6eafa962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f460a01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f460a0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f460a01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f460a003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c6eaf3ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c6eaf3ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c6eaf238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c6eabd2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c6eabd2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f460a004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f460a0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f460a0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c6eabd2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c (349 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfwcvt_f_x_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfwcvt_f_x_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfwcvt_f_x_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfwcvt_f_x_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfwcvt_f_x_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfwcvt_f_x_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfwcvt_f_xu_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfwcvt_f_xu_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfwcvt_f_xu_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfwcvt_f_xu_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, 
# | ...
# `---data was truncated (10240/288103) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f02416ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f024169e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f02416d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f59b2c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f59b2ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f59b2c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f59b2c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f024102bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f024102a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f0240e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f023d96e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f023d96b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f59b2c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f59b2c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f59b2c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f023d96a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c (350 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmv_v_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmv_v_x_i8mf8_tu(<vscale x 1 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmv_v_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmv_v_x_i8mf4_tu(<vscale x 2 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmv_v_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmv_v_x_i8mf2_tu(<vscale x 4 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmv_v_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmv_v_x_i8m1_tu(<vscale x 8 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmv_v_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmv_v_x_i8m2_tu(<vscale x 16 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmv_v_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# | 
# | ...
# `---data was truncated (10240/134744) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b5357bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b5357b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b5357bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f16dd533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f16dd58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f16dd533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f16dd51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b535752bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b535752a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b5357378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b5353e6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b5353e6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f16dd51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f16dd51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f16dd51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b5353e6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c (351 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svcreate3_s8(<vscale x 16 x i8> %x0, <vscale x 16 x i8> %x1, <vscale x 16 x i8> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i8>, align 16
# |   %x1.addr = alloca <vscale x 16 x i8>, align 16
# |   %x2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %x0, ptr %x0.addr, align 16
# |   store <vscale x 16 x i8> %x1, ptr %x1.addr, align 16
# |   store <vscale x 16 x i8> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %0, 0
# |   %4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, <vscale x 16 x i8> %1, 1
# |   %5 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, <vscale x 16 x i8> %2, 2
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svcreate3_s16(<vscale x 8 x i16> %x0, <vscale x 8 x i16> %x1, <vscale x 8 x i16> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x i16>, align 16
# |   %x1.addr = alloca <vscale x 8 x i16>, align 16
# |   %x2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x i16> %x1, ptr %x1.addr, align 16
# |   store <vscale x 8 x i16> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %0, 0
# |   %4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, <vscale x 8 x i16> %1, 1
# |   %5 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, <vscale x 8 x i16> %2, 2
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svcreate3_s32(<vscale x 4 x i32> %x0, <vscale x 4 x i32> %x1, <vscale x 4 x i32> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 4 x i32>, align 16
# |   %x1.addr = alloca <vscale x 4 x i32>, align 16
# |   %x2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %x0, ptr %x0.addr, align 16
# |   store <vscale x 4 x i32> %x1, ptr %x1.addr, align 16
# |   store <vscale x 4 x i32> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %0, 0
# |   %4 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, <vscale x 4 x i32> %1, 1
# |   %5 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, <vscale x 4 x i32> %2, 2
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svcreate3_s64(<vscale x 2 x i64> %x0, <vscale x 2 x i64> %x1, <vscale x 2 x i64> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 2 x i64>, align 16
# |   %x1.addr = alloca <vscale x 2 x i64>, align 16
# |   %x2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %x0, ptr %x0.addr, align 16
# |   store <vscale x 2 x i64> %x1, ptr %x1.addr, align 16
# |   store <vscale x 2 x i64> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %0, 0
# |   %4 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3, <vscale x 2 x i64> %1, 1
# |   %5 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, <vscale x 2 x i64> %2, 2
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svcreate3_u8(<vscale x 16 x i8> %x0, <vscale x 16 x i8> %x1, <vscale x 16 x i8> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i8>, align 16
# |   %x1.addr = alloca <vscale x 16 x i8>, align 16
# |   %x2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %x0, ptr %x0.addr, align 16
# |   store <vscale x 16 x i8> %x1, ptr %x1.addr, align 16
# |   store <vscale x 16 x i8> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %0, 0
# |   %4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, <vscale x 16 x i8> %1, 1
# |   %5 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, <vscale x 16 x i8> %2, 2
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svcreate3_u16(<vscale x 8 x i16> %x0, <vscale x 8 x i16> %x1, <vscale x 8 x i16> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x i16>, align 16
# |   %x1.addr = alloca <vscale x 8 x i16>, align 16
# |   %x2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x i16> %x1, ptr %x1.addr, align 16
# |   store <vscale x 8 x i16> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %0, 0
# |   %4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, <vscale x 8 x i16> %1, 1
# |   %5 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, <vscale x 8 x i16> %2, 2
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svcreate3_u32(<vscale x 4 x i32> %x0, <vscale x 4 x i32> %x1, <vscale x 4 x i32> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 4 x i32>, align 16
# |   %x1.addr = alloca <vscale x 4 x i32>, align 16
# |   %x2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %x0, ptr %x0.addr, align 16
# |   store <vscale x 4 x i32> %x1, ptr %x1.addr, align 16
# |   store <vscale x 4 x i32> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %0, 0
# |   %4 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, <vscale x 4 x i32> %1, 1
# |   %5 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, <vscale x 4 x i32> %2, 2
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svcreate3_u64(<vscale x 2 x i64> %x0, <vscale x 2 x i64> %x1, <vscale x 2 x i64> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 2 x i64>, align 16
# |   %x1.addr = alloca <vscale x 2 x i64>, align 16
# |   %x2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %x0, ptr %x0.addr, align 16
# |   store <vscale x 2 x i64> %x1, ptr %x1.addr, align 16
# |   store <vscale x 2 x i64> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %0, 0
# |   %4 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3, <vscale x 2 x i64> %1, 1
# |   %5 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, <vscale x 2 x i64> %2, 2
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svcreate3_f16(<vscale x 8 x half> %x0, <vscale x 8 x half> %x1, <vscale x 8 x half> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x half>, align 16
# |   %x1.addr = alloca <vscale x 8 x half>, align 16
# |   %x2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x half> %x1, ptr %x1.addr, align 16
# |   store <vscale x 8 x half> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vsc
# | ...
# `---data was truncated (10240/15704) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005613845feeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005613845fbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005613845ff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb050449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb0504a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb050449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb050431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561384594bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561384594a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005613845798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561384228e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561384228b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb050432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb0504330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb0504330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561384228a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c (352 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vget_v_bf16m2_bf16m1(<vscale x 8 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vget_v_bf16m4_bf16m1(<vscale x 16 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vget_v_bf16m8_bf16m1(<vscale x 32 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vget_v_bf16m4_bf16m2(<vscale x 16 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vget_v_bf16m8_bf16m2(<vscale x 32 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vget_v_bf16m8_bf16m4(<vscale x 32 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.extract.nxv16bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.extract.nxv16bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x2_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x3_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x4_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x5_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x6_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x7_bf16mf4(target("riscv.vector.tuple", <vscal
# | ...
# `---data was truncated (10240/30690) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556ede156eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556ede153e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556ede15762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6958249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f69582a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6958249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6958231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ede0ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556ede0eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556ede0d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556eddd80e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556eddd80b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6958232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f69582330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f69582330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556eddd80a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c (353 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmls_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %4 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.mls.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %4, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.mls.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmls_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %6 = call <vscale x 8 x i16> @llvm.aarch64.sve.mls.nxv8i16(<vscale x 8 x i1> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.mls.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmls_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %6 = call <vscale x 4 x i32> @llvm.aarch64.sve.mls.nxv4i32(<vscale x 4 x i1> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3)
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.mls.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmls_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   %op3.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x i64> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %6 = call <vscale x 2 x i64> @llvm.aarch64.sve.mls.nxv2i64(<vscale x 2 x i1> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3)
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.mls.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmls_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %4 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.mls.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %4, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmls_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %6 = call <vscale x 8 x i16> @llvm.aarch64.sve.mls.nxv8i16(<vscale x 8 x i1> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmls_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %6 = call <vscale x 4 x i32> @llvm.aarch64.sve.mls.nxv4i32(<vscale x 4 x i1> %4, <vs
# | ...
# `---data was truncated (10240/92910) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ec95ae6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ec95ae3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ec95ae762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0d98249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0d982a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0d98249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0d98231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec95a7cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ec95a7ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ec95a618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ec95710e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ec95710b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0d98232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0d982330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0d982330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec95710a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c (354 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svlsr_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svlsr_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.lsr.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.lsr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svlsr_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svlsr_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.lsr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.lsr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svlsr_u8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svlsr_u16_m(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.lsr.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svlsr_u32_m(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svlsr_u64_m(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.lsr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svlsr_u8_x(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.u.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# | 
# | ...
# `---data was truncated (10240/33353) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000557bd68dbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557bd68d8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557bd68dc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3f1b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3f1b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3f1b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3f1b91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557bd6871bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557bd6871a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557bd68568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557bd6505e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557bd6505b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3f1b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3f1b91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3f1b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557bd6505a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c (355 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_xv_se_u64m1(<vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.xv.se.i64.nxv1i64.i64.i64(i64 3, i64 31, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.xv.se.i64.nxv1i64.i64.i64(i64 immarg, i64 immarg, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_xv_se_u64m2(<vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.xv.se.i64.nxv2i64.i64.i64(i64 3, i64 31, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.xv.se.i64.nxv2i64.i64.i64(i64 immarg, i64 immarg, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_xv_se_u64m4(<vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.xv.se.i64.nxv4i64.i64.i64(i64 3, i64 31, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.xv.se.i64.nxv4i64.i64.i64(i64 immarg, i64 immarg, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_xv_se_u64m8(<vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.xv.se.i64.nxv8i64.i64.i64(i64 3, i64 31, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.xv.se.i64.nxv8i64.i64.i64(i64 immarg, i64 immarg, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_sf_vc_v_xv_se_u64m1(<vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv1i64.i64.nxv1i64.i64.i64(i64 3, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv1i64.i64.nxv1i64.i64.i64(i64 immarg, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_sf_vc_v_xv_se_u64m2(<vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv2i64.i64.nxv2i64.i64.i64(i64 3, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 2 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv2i64.i64.nxv2i64.i64.i64(i64 immarg, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_sf_vc_v_xv_se_u64m4(<vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv4i64.i64.nxv4i64.i64.i64(i64 3, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 4 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv4i64.i64.nxv4i64.i64.i64(i64 immarg, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_sf_vc_v_xv_se_u64m8(<vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv8i64.i64.nxv8i64.i64.i64(i64 3, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 8 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv8i64.i64.nxv8i64.i64.i64(i64 immarg, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_sf_vc_v_xv_u64m1(<vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xv.nxv1i64.i64.nxv1i64.i64.i64(i64 3, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xv.nxv1i64.i64.nxv1i64.i64.i64(i64 immarg, <vscale x 1 x i64>, i64, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_sf_vc_v_xv_u64m2(<vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.xv.nxv2i64.i64.nxv2i64.i64.i64(i64 3, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.sf.vc.v.xv.nxv2i64.i64.nxv2i64.i64.i64(i64 immarg, <vscale x 2 x i64>, i64, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_sf_vc_v_xv_u64m4(<vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.xv.nxv4i64.i64.nxv4i64.i64.i64(i64 3, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.sf.vc.v.xv.nxv4i64.i64.nxv4i64.i64.i64(i64 immarg, <vscale x 4 x i64>, i64, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_sf_vc_v_xv_u64m8(<vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.
# | ...
# `---data was truncated (10240/11504) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ef7b50eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557ef7b4de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557ef7b5162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f66c2133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f66c218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f66c2133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f66c211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ef7ae6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557ef7ae6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557ef7acb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557ef777ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557ef777ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f66c211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f66c211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f66c211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ef777aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c (356 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla2_f32(i32 noundef %slice_base, <vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zm.coerce0, <vscale x 4 x float> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zm.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %5, 0
# |   %7 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %5, 1
# |   %8 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %8, 0
# |   %10 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %8, 1
# |   call void @llvm.aarch64.sme.fmla.vg1x2.nxv4f32(i32 %4, <vscale x 4 x float> %6, <vscale x 4 x float> %7, <vscale x 4 x float> %9, <vscale x 4 x float> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmla.vg1x2.nxv4f32(i32, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla4_f32(i32 noundef %slice_base, <vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zn.coerce2, <vscale x 4 x float> %zn.coerce3, <vscale x 4 x float> %zm.coerce0, <vscale x 4 x float> %zm.coerce1, <vscale x 4 x float> %zm.coerce2, <vscale x 4 x float> %zm.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, <vscale x 4 x float> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zn.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   %4 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zm.coerce0, 0
# |   %5 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, <vscale x 4 x float> %zm.coerce1, 1
# |   %6 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %5, <vscale x 4 x float> %zm.coerce2, 2
# |   %7 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %6, <vscale x 4 x float> %zm.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %7, ptr %zm, align 16
# |   %zm2 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %zm2, ptr %zm.addr, align 16
# |   %8 = load i32, ptr %slice_base.addr, align 4
# |   %9 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %10 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9, 0
# |   %11 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9, 1
# |   %12 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9, 2
# |   %13 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9, 3
# |   %14 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm.addr, align 16
# |   %15 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %14, 0
# |   %16 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %14, 1
# |   %17 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %14, 2
# |   %18 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %14, 3
# |   call void @llvm.aarch64.sme.fmla.vg1x4.nxv4f32(i32 %8, <vscale x 4 x float> %10, <vscale x 4 x float> %11, <vscale x 4 x float> %12, <vscale x 4 x float> %13, <vscale x 4 x float> %15, <vscale x 4 x float> %16, <vscale x 4 x float> %17, <vscale x 4 x float> %18)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmla.vg1x4.nxv4f32(i32, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_single2_f32(i32 noundef %slice_base, <vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %3, 0
# |   %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %3, 1
# |   %6 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.fmla.single.vg1x2.nxv4f32(i32 %2, <vscale x 4 x float> %4, <vscale x 4 x float> %5, <vscale x 4 x float> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmla.single.vg1x2.nxv4f32(i32, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_single4_f32(i32 noundef %slice_base, <vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zn.coerce2, <vscale x 4 x float> %zn.coerce3, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x flo
# | ...
# `---data was truncated (10240/34546) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000562b908f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562b908efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562b908f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f625ec1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f625ec725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f625ec1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f625ec03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b90888bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562b90888a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562b9086d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562b9051ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562b9051cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f625ec04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f625ec050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f625ec050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b9051ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/rsqrte.c (357 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/rsqrte.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrsqrte_f16(<vscale x 8 x half> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x half> @llvm.aarch64.sve.frsqrte.x.nxv8f16(<vscale x 8 x half> %0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frsqrte.x.nxv8f16(<vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrsqrte_f32(<vscale x 4 x float> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x float> @llvm.aarch64.sve.frsqrte.x.nxv4f32(<vscale x 4 x float> %0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frsqrte.x.nxv4f32(<vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrsqrte_f64(<vscale x 2 x double> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x double> @llvm.aarch64.sve.frsqrte.x.nxv2f64(<vscale x 2 x double> %0)
# |   ret <vscale x 2 x double> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frsqrte.x.nxv2f64(<vscale x 2 x double>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x0000556186da0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556186d9de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556186da162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcae5f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcae5f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcae5f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcae5f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556186d36bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556186d36a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556186d1b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005561869cae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005561869cab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcae5f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcae5f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcae5f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005561869caa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c (358 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdivu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdivu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdivu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdivu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdivu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdivu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdivu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdivu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdivu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vdivu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vdivu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdivu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vdivu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vdivu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vdivu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr
# | ...
# `---data was truncated (10240/97905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aa2a8d7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aa2a8d4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aa2a8d862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6a28b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6a28b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6a28b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6a28b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa2a86dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aa2a86da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aa2a8528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aa2a501e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aa2a501b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6a28b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6a28b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6a28b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa2a501a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c (359 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_u8_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_s8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_u8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x i32> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x i32> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x i64> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x i64> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_f16(<vscale x 8 x half> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x half> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_bf16(<vscale x 8 x bfloat> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x bfloat> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_f32(<vscale x 4 x float> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x float> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_f64(<vscale x 2 x double> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x double> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_u16_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svreinterpret_s32_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svreinterpret_u32_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svreinterpret_s64_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svreinterpret_u64_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svreinterpret_f16_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 8 x half>
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svreinterpret_bf16_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 8 x bfloat>
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svreinterpret_f32_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 4 x float>
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svreinterpret_f64_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 t
# | ...
# `---data was truncated (10240/168193) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg
# |  #0 0x000055e9c90a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e9c90a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e9c90a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6cc0449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6cc04a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6cc0449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6cc0431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e9c903cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e9c903ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e9c90218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e9c8cd0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e9c8cd0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6cc0432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6cc04330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6cc04330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e9c8cd0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c (360 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p3 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p3 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdot_s16_x2(<vscale x 8 x i16> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.sdot.x2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sdot.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdot_u16_x2(<vscale x 8 x i16> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.udot.x2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.udot.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdot_n_s16_x2(<vscale x 8 x i16> %op1, <vscale x 16 x i8> %op2, i8 noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca i8, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store i8 %op3, ptr %op3.addr, align 1
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load i8, ptr %op3.addr, align 1
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %2, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.sdot.x2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdot_n_u16_x2(<vscale x 8 x i16> %op1, <vscale x 16 x i8> %op2, i8 noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca i8, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store i8 %op3, ptr %op3.addr, align 1
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load i8, ptr %op3.addr, align 1
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %2, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.udot.x2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdot_lane_s16_x2(<vscale x 8 x i16> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.sdot.lane.x2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 7)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sdot.lane.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdot_lane_u16_x2(<vscale x 8 x i16> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.udot.lane.x2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 7)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.udot.lane.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2p3" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055fb0e7d1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fb0e7cee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fb0e7d262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd73b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd73b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd73b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd73b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb0e767bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fb0e767a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fb0e74c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fb0e3fbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fb0e3fbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd73b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd73b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd73b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb0e3fba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c (361 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1ub_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1ub_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1ub_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1ub_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1ub_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1ub_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1ub_vnum_s16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1ub_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i8> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1ub_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i8> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1ub_vnum_u16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1ub_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x
# | ...
# `---data was truncated (10240/28299) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c23b763eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c23b760e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c23b76462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f971c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f971c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f971c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f971c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c23b6f9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c23b6f9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c23b6de8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c23b38de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c23b38db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f971c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f971c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f971c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c23b38da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c (362 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmad_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %6 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmad.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fnmad.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svnmad_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %6 = call <vscale x 4 x float> @llvm.aarch64.sve.fnmad.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %5, <vscale x 4 x float> %2, <vscale x 4 x float> %3)
# |   ret <vscale x 4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fnmad.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svnmad_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %6 = call <vscale x 2 x double> @llvm.aarch64.sve.fnmad.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %5, <vscale x 2 x double> %2, <vscale x 2 x double> %3)
# |   ret <vscale x 2 x double> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fnmad.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmad_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmad.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svnmad_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fnmad.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svnmad_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fnmad.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmad_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmla.u.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %3, <vscale x 8 x half> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind w
# | ...
# `---data was truncated (10240/26173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005652be403eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005652be400e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005652be40462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa3dbd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa3dbd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa3dbd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa3dbd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005652be399bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005652be399a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005652be37e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005652be02de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005652be02db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa3dbd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa3dbd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa3dbd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005652be02da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c (363 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlslb(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlslb(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlslb(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlslb_lane(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlslb.lane(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 7)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlslb.lane(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlslt(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlslt(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlslt(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlslt_lane(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlslt.lane(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 7)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlslt.lane(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000557f9e4bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557f9e4b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557f9e4bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff26c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff26c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff26c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff26c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f9e452bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557f9e452a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557f9e4378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557f9e0e6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557f9e0e6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff26c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff26c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff26c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f9e0e6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c (364 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmul_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmul_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmul_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmul_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmul_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmul_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmul_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmul_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmul_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/424835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b561c96eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b561c93e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b561c9762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7a2b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7a2b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7a2b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7a2b91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b561c2cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b561c2ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b561c118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b5618c0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b5618c0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7a2b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7a2b91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7a2b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b5618c0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c (365 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadrb_u32base_s32offset(<vscale x 4 x i32> %bases, <vscale x 4 x i32> %offsets) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %offsets.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %offsets.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.adrb.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.adrb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadrb_u64base_s64offset(<vscale x 2 x i64> %bases, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.adrb.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.adrb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadrb_u32base_u32offset(<vscale x 4 x i32> %bases, <vscale x 4 x i32> %offsets) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %offsets.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %offsets.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.adrb.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadrb_u64base_u64offset(<vscale x 2 x i64> %bases, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.adrb.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000564553c2ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564553c29e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564553c2d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f86bf733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f86bf78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f86bf733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f86bf71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564553bc2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564553bc2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564553ba78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564553856e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564553856b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f86bf71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f86bf71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f86bf71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564553856a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c (366 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svwrite_ver_za8_u8_vg2(i32 noundef %base, <vscale x 16 x i8> %val.coerce0, <vscale x 16 x i8> %val.coerce1) #0 {
# | entry:
# |   %val = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %base.addr = alloca i32, align 4
# |   %val.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %val.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %val.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %val, align 16
# |   %val1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val, align 16
# |   store i32 %base, ptr %base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %val1, ptr %val.addr, align 16
# |   %2 = load i32, ptr %base.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.write.ver.vg2.nxv16i8(i32 0, i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.write.ver.vg2.nxv16i8(i32 immarg, i32, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svwrite_ver_za8_s8_vg2(i32 noundef %base, <vscale x 16 x i8> %val.coerce0, <vscale x 16 x i8> %val.coerce1) #0 {
# | entry:
# |   %val = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %base.addr = alloca i32, align 4
# |   %val.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %val.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %val.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %val, align 16
# |   %val1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val, align 16
# |   store i32 %base, ptr %base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %val1, ptr %val.addr, align 16
# |   %2 = load i32, ptr %base.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.write.ver.vg2.nxv16i8(i32 0, i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svwrite_ver_za8_mf8_vg2(i32 noundef %base, <vscale x 16 x i8> %val.coerce0, <vscale x 16 x i8> %val.coerce1) #0 {
# | entry:
# |   %val = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %base.addr = alloca i32, align 4
# |   %val.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %val.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %val.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %val, align 16
# |   %val1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val, align 16
# |   store i32 %base, ptr %base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %val1, ptr %val.addr, align 16
# |   %2 = load i32, ptr %base.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.write.ver.vg2.nxv16i8(i32 0, i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svwrite_hor_za8_u8_vg2(i32 noundef %base, <vscale x 16 x i8> %val.coerce0, <vscale x 16 x i8> %val.coerce1) #0 {
# | entry:
# |   %val = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %base.addr = alloca i32, align 4
# |   %val.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %val.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %val.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %val, align 16
# |   %val1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val, align 16
# |   store i32 %base, ptr %base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %val1, ptr %val.addr, align 16
# |   %2 = load i32, ptr %base.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.write.hor.vg2.nxv16i8(i32 0, i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.write.hor.vg2.nxv16i8(i32 immarg, i32, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svwrite_hor_za8_s8_vg2(i32 noundef %base, <vscale x 16 x i8> %val.coerce0, <vscale x 16 x i8> %val.coerce1) #0 {
# | entry:
# |   %val = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %base.addr = alloca i32, align 4
# |   %val.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %val.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %val.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %val, align 16
# |   %val1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val, align 16
# |   store i32 %base, ptr %base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %val1, ptr %val.addr, align 16
# |   %2 = load i32, ptr %base.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.write.hor.vg2.nxv16i8(i32 0, i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svwrite_hor_za8_mf8_vg2(i32 noundef %base, <vscale x 16 x i8> %val.coerce0, <vscale x 16 x i8> %val.coerce1) #0 {
# | entry:
# |   %val = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %base.addr = alloca i32, align 4
# |   %val.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %val.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %val.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %val, align 16
# |   %val1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val, align 16
# |   store i32 %base, ptr %base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %val1, ptr %val.addr, align 16
# |   %2 = load i32, ptr %base.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.write.hor.vg2.nxv16i8(i32 0, i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svwrite_hor_za8_u8_vg4(i32 noundef %base, <vscale x 16 x i8> %val.coerce0, <vscale x 16 x i8> %val.coerce1, <vscale x 16 x i8> %val.coerce2, <vscale x 16 x i8> %val.coerce3) #0 {
# | entry:
# |   %val = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %base.addr = alloca i32, align 4
# |   %val.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %val.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %val.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %val.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %val.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %val, align 16
# |   %val1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val, align 16
# |   store i32 %base, ptr %base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %val1, ptr %val.addr, align 16
# |   %4 = load i32, ptr %base.addr, align 4
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale
# | ...
# `---data was truncated (10240/150970) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055d1a267aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d1a2677e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d1a267b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faa94133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faa9418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faa94133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faa9411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d1a2610bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d1a2610a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d1a25f58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d1a22a4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d1a22a4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faa9411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faa9411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faa9411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d1a22a4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c (367 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svluti2_lane_zt_u8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svluti2_lane_zt_s8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svluti2_lane_zt_u16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sme.luti2.lane.zt.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 8 x i16> @llvm.aarch64.sme.luti2.lane.zt.nxv8i16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svluti2_lane_zt_mf8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svluti2_lane_zt_s16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sme.luti2.lane.zt.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svluti2_lane_zt_f16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x half> @llvm.aarch64.sme.luti2.lane.zt.nxv8f16(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sme.luti2.lane.zt.nxv8f16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svluti2_lane_zt_bf16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x bfloat> @llvm.aarch64.sme.luti2.lane.zt.nxv8bf16(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sme.luti2.lane.zt.nxv8bf16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svluti2_lane_zt_u32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sme.luti2.lane.zt.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 4 x i32> @llvm.aarch64.sme.luti2.lane.zt.nxv4i32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svluti2_lane_zt_s32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sme.luti2.lane.zt.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svluti2_lane_zt_f32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x float> @llvm.aarch64.sme.luti2.lane.zt.nxv4f32(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sme.luti2.lane.zt.nxv4f32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000556763a48eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556763a45e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556763a4962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1019705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f101975c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1019705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f10196ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005567639debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005567639dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005567639c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556763672e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556763672b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f10196eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f10196ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f10196ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556763672a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c (368 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vget_v_f16m2_f16m1(<vscale x 8 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vget_v_f16m4_f16m1(<vscale x 16 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vget_v_f16m8_f16m1(<vscale x 32 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vget_v_f16m4_f16m2(<vscale x 16 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vget_v_f16m8_f16m2(<vscale x 32 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vget_v_f16m8_f16m4(<vscale x 32 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vget_v_f32m2_f32m1(<vscale x 4 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float> %0, i64 0)
# |   ret <vscale x 2 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vget_v_f32m4_f32m1(<vscale x 8 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv8f32(<vscale x 8 x float> %0, i64 0)
# |   ret <vscale x 2 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv8f32(<vscale x 8 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vget_v_f32m8_f32m1(<vscale x 16 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv16f32(<vscale x 16 x float> %0, i64 0)
# |   ret <vscale x 2 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv16f32(<vscale x 16 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vget_v_f32m4_f32m2(<vscale x 8 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv8f32(<vscale x 8 x float> %0, i64 0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv8f32(<vscale x 8 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vget_v_f32m8_f32m2(<vscale x 16 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv16f32(<vscale x 16 x float> %0, i64 0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv16f32(<vscale x 16 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vget_v_f32m8_f32m4(<vscale x 16 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 8 x float> @llvm.vector.extract.nxv8f32.nxv16f32(<vscale x 16 x float> %0, i64 0)
# |   ret <vscale x 8 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.vector.extract.nxv8f32.nxv16f32(<vscale x 16 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vget_v_f64m2_f64m1(<vscale x 2 x double> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %1 = call <vscale x 1 x double> @llvm.vector.extract.nxv1f64.nxv2f64(<vscale x 2 x double> %0, i64 0)
# |   ret <vscale x 1 x double> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.vector.extract.nxv1f64.nxv2f64(<vscale x 2 x double>, i64 immarg) #1
# | 
# | ; Function Attrs: noinli
# | ...
# `---data was truncated (10240/246614) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558c36a12eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558c36a0fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558c36a1362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6c50f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6c50f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6c50f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6c50f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c369a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558c369a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558c3698d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558c3663ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558c3663cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6c50f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6c50f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6c50f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c3663ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c (369 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclamp_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.sclamp.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.sclamp.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclamp_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.sclamp.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sclamp.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclamp_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sclamp.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sclamp.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svclamp_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   %op3.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x i64> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.sclamp.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sclamp.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000559d0f95eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559d0f95be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559d0f95f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f029321bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f02932725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f029321ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0293203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559d0f8f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559d0f8f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559d0f8d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559d0f588e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559d0f588b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0293204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f02932050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f02932050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559d0f588a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-vls-shift-ops.c (370 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-shift-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone -mvscale-min=4 -mvscale-max=4   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @lshift_i8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %shl = shl <64 x i8> %0, %1
# |   store <64 x i8> %shl, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8>, <64 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @rshift_i8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %shr = ashr <64 x i8> %0, %1
# |   store <64 x i8> %shr, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @lshift_u8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %shl = shl <64 x i8> %0, %1
# |   store <64 x i8> %shl, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @rshift_u8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %shr = lshr <64 x i8> %0, %1
# |   store <64 x i8> %shr, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @lshift_i16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %shl = shl <32 x i16> %0, %1
# |   store <32 x i16> %shl, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16>, <32 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @rshift_i16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %shr = ashr <32 x i16> %0, %1
# |   store <32 x i16> %shr, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @lshift_u16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %shl = shl <32 x i16> %0, %1
# |   store <32 x i16> %shl, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @rshift_u16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %shr = lshr <32 x i16> %0, %1
# |   store <32 x i16> %shr, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i32> @lshift_i32(<vscale x 4 x i32> noundef %a.coerce, <vscale x 4 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i32>, align 16
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca <16 x i32>, align 16
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %b.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i32>, ptr %b.addr, align 16
# |   %shl = shl <16 x i32> %0, %1
# |   store <16 x i32> %shl, ptr %retval, align 16
# |   %2 = load <16 x i32>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> poison, <16 x i32> %2, i64 0)
# |   ret <vscale x 4 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32>, <16 x i32>, i64 imma
# | ...
# `---data was truncated (10240/51475) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x0000564d60a9aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564d60a97e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564d60a9b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3764c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3764c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3764c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3764c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d60a30bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564d60a30a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564d60a158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564d606c4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564d606c4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3764c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3764c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3764c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d606c4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16.c (371 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vfma_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %6 = bitcast <8 x i8> %3 to <4 x half>
# |   %7 = bitcast <8 x i8> %4 to <4 x half>
# |   %8 = bitcast <8 x i8> %5 to <4 x half>
# |   %9 = call <4 x half> @llvm.fma.v4f16(<4 x half> %7, <4 x half> %8, <4 x half> %6)
# |   store <4 x half> %9, ptr %ref.tmp.i, align 8
# |   %10 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %10, ptr %__ret.i, align 8
# |   %11 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vfmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %6 = bitcast <16 x i8> %3 to <8 x half>
# |   %7 = bitcast <16 x i8> %4 to <8 x half>
# |   %8 = bitcast <16 x i8> %5 to <8 x half>
# |   %9 = call <8 x half> @llvm.fma.v8f16(<8 x half> %7, <8 x half> %8, <8 x half> %6)
# |   store <8 x half> %9, ptr %ref.tmp.i, align 16
# |   %10 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %10, ptr %__ret.i, align 16
# |   %11 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vfms_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i.i = alloca <4 x half>, align 8
# |   %__p1.addr.i.i = alloca <4 x half>, align 8
# |   %__p2.addr.i.i = alloca <4 x half>, align 8
# |   %__ret.i.i = alloca <4 x half>, align 8
# |   %ref.tmp.i.i = alloca <8 x i8>, align 8
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <4 x half>, ptr %__p0.addr.i, align 8
# |   %4 = load <4 x half>, ptr %__p1.addr.i, align 8
# |   %fneg.i = fneg <4 x half> %4
# |   %5 = load <4 x half>, ptr %__p2.addr.i, align 8
# |   store <4 x half> %3, ptr %__p0.addr.i.i, align 8
# |   store <4 x half> %fneg.i, ptr %__p1.addr.i.i, align 8
# |   store <4 x half> %5, ptr %__p2.addr.i.i, align 8
# |   %6 = load <8 x i8>, ptr %__p0.addr.i.i, align 8
# |   %7 = load <8 x i8>, ptr %__p1.addr.i.i, align 8
# |   %8 = load <8 x i8>, ptr %__p2.addr.i.i, align 8
# |   %9 = bitcast <8 x i8> %6 to <4 x half>
# |   %10 = bitcast <8 x i8> %7 to <4 x half>
# |   %11 = bitcast <8 x i8> %8 to <4 x half>
# |   %12 = call <4 x half> @llvm.fma.v4f16(<4 x half> %10, <4 x half> %11, <4 x half> %9)
# |   store <4 x half> %12, ptr %ref.tmp.i.i, align 8
# |   %13 = load <4 x half>, ptr %ref.tmp.i.i, align 8
# |   store <4 x half> %13, ptr %__ret.i.i, align 8
# |   %14 = load <4 x half>, ptr %__ret.i.i, align 8
# |   store <4 x half> %14, ptr %__ret.i, align 8
# |   %15 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %15
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vfmsq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i.i = alloca <8 x half>, align 16
# |   %__p1.addr.i.i = alloca <8 x half>, align 16
# |   %__p2.addr.i.i = alloca <8 x half>, align 16
# |   %__ret.i.i = alloca <8 x half>, align 16
# |   %ref.tmp.i.i = alloca <16 x i8>, align 16
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <8 x half>, ptr %__p0.addr.i, align 16
# |   %4 = load <8 x half>, ptr %__p1.addr.i, align 16
# |   %fneg.i = fneg <8 x half> %4
# |   %5 = load <8 x half>, ptr %__p2.addr.i, align 16
# |   store <8 x half> %3, ptr %__p0.addr.i.i, align 16
# |   store <8 x half> %fneg.i, ptr %__p1.addr.i.i, align 16
# |   store <8 x half> %5, ptr %__p2.addr.i.i, align 16
# |   %6 = load <16 x i8>, ptr %__p0.addr.i.i, align 16
# |   %7 = load <16 x i8>, ptr %__p1.addr.i.i, align 16
# |   %8 = load <16 x i8>, ptr %__p2.addr.i.i, align 16
# |   %9 = bitcast <16 x i8> %6 to <8 x half>
# |   %10 = bitcast <16 x i8> %7 to <8 x half>
# |   %11 = bitcast <16 x i8> %8 to <8 x half>
# |   %12 = call <8 x half> @llvm.fma.v8f16(<8 x half> %10, <8 x half> %11, <8 x half> %9)
# |   store <8 x half> %12, ptr %ref.tmp.i.i, align 16
# |   %13 = load <8 x half>, ptr %ref.tmp.i.i, align 16
# |   store <8 x half> %13, ptr %__ret.i.i, align 16
# |   %14 = load <8 x half>, ptr %__ret.i.i, align 16
# |   store <8 x half> %14, ptr %__ret.i, align 16
# |   %15 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %15
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vfma_lane_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca <4 x half>, align 8
# |   %__s1 = alloca <4 x half>, align 8
# |   %__s2 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__s0, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %1, ptr %__s1, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x half> %2, ptr %__s2, align 8
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <8 x i8>, ptr %__s2, align 8
# |   %6 = bitcast <8 x i8> %5 to <4 x half>
# |   %lane = shufflevector <4 x half> %6, <4 x half> %6, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
# |   %fmla = bitcast <8 x i8> %4 to <4 x half>
# |   %fmla1 = bitcast <8 x i8> %3 to <4 x half>
# |   %fmla2 = call <4 x half> @llvm.fma.v4f16(<4 x half> %fmla, <4 x half> %lane, <4 x half> %fmla1)
# |   store <4 x half> %fmla2, ptr %ref.tmp, align 8
# |   %7 = load <4 x half>, ptr %ref.tmp, align 8
# |   store <4 x half> %7, ptr %__ret, align 8
# |   %8 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %8, ptr %tmp, align 8
# |   %9 = load <4 x half>, ptr %tmp, align 8
# |   ret <4 x half> %9
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x half> @llvm.fma.v4f16(<4 x half>, <4 x half>, <4 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vfmaq_lane_f16(<8 x half> noundef %a, <8 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <4 x half>, align 8
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca <8 x half>, align 16
# |   %__s1 = alloca <8 x half>, align 16
# |   %__s2 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__s0, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %1, ptr %__s1
# | ...
# `---data was truncated (10240/42739) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000556831299eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556831296e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055683129a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe35d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe35d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe35d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe35d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055683122fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055683122fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005568312148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556830ec3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556830ec3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe35d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe35d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe35d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556830ec3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c (372 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1>, ptr, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_1(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_2(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_3(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_4(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_5(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_6(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 8)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_7(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 9)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 10)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_9(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 11)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_10(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 12)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_11(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 13)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_vnum(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i64>, ptr %1, i64 %2
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %3, ptr %4, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_gather_u32base(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prfd.gather.scalar.offset.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1, i64 0, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.aarch64.sve.prfd.gather.scalar.offset.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64, i32 immarg) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_gather_u64base(<vscale x 16 x i1> %pg, <vscale x 2 x i64
# | ...
# `---data was truncated (10240/17826) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000556d4df1aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556d4df17e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556d4df1b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f27ebf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f27ebf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f27ebf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f27ebf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556d4deb0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556d4deb0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556d4de958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556d4db44e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556d4db44b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f27ebf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f27ebf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f27ebf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556d4db44a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_min.c (373 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_min.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmin_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.smin.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.smin.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmin_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.smin.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.smin.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmin_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.smin.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.smin.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmin_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.smin.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.smin.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmin_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.umin.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.umin.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmin_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.umin.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.umin.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmin_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.umin.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.umin.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmin_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale
# | ...
# `---data was truncated (10240/74195) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005641e6b28eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005641e6b25e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005641e6b2962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa298049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa2980a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa298049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa298031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005641e6abebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005641e6abea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005641e6aa38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005641e6752e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005641e6752b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa298032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa2980330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa2980330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005641e6752a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c (374 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei64_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei64_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei64_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei64_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei64_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei64_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei64_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei64_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vluxei64_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, <vscale x 1 
# | ...
# `---data was truncated (10240/215949) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005622f58cfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005622f58cce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005622f58d062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f168ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f168cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f168ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f168ce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005622f5865bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005622f5865a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005622f584a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005622f54f9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005622f54f9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f168ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f168ce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f168ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005622f54f9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c (375 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei8_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei8_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei8_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei8_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei8_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i8> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vloxei8_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, <vscale x 32 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i8> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei8_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei8_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei8_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.
# | ...
# `---data was truncated (10240/288058) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556267114eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556267111e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055626711562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5cf3733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5cf378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5cf3733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5cf371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005562670aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005562670aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055626708f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556266d3ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556266d3eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5cf371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5cf371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5cf371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556266d3ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c (376 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.7a -target-feature +f16mm -target-feature +f16f32mm  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.7a -target-feature +f16mm -target-feature +f16f32mm -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <8 x half> @test_vmmlaq_f16(<8 x half> noundef %acc, <8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %acc.addr = alloca <8 x half>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   store <8 x half> %acc, ptr %acc.addr, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <8 x half>, ptr %acc.addr, align 16
# |   %1 = load <8 x half>, ptr %a.addr, align 16
# |   %2 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %fmmla.i = bitcast <16 x i8> %3 to <8 x half>
# |   %fmmla1.i = bitcast <16 x i8> %4 to <8 x half>
# |   %fmmla2.i = bitcast <16 x i8> %5 to <8 x half>
# |   %fmmla3.i = call <8 x half> @llvm.aarch64.neon.fmmla.v8f16.v8f16(<8 x half> %fmmla.i, <8 x half> %fmmla1.i, <8 x half> %fmmla2.i)
# |   store <8 x half> %fmmla3.i, ptr %ref.tmp.i, align 16
# |   %6 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %6, ptr %__ret.i, align 16
# |   %7 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <4 x float> @test_vmmlaq_f32_f16(<4 x float> noundef %acc, <8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %acc.addr = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   store <4 x float> %acc, ptr %acc.addr, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %acc.addr, align 16
# |   %1 = load <8 x half>, ptr %a.addr, align 16
# |   %2 = load <8 x half>, ptr %b.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %fmmla.i = bitcast <16 x i8> %3 to <4 x float>
# |   %fmmla1.i = bitcast <16 x i8> %4 to <8 x half>
# |   %fmmla2.i = bitcast <16 x i8> %5 to <8 x half>
# |   %fmmla3.i = call <4 x float> @llvm.aarch64.neon.fmmla.v4f32.v8f16(<4 x float> %fmmla.i, <8 x half> %fmmla1.i, <8 x half> %fmmla2.i)
# |   store <4 x float> %fmmla3.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.aarch64.neon.fmmla.v8f16.v8f16(<8 x half>, <8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.aarch64.neon.fmmla.v4f32.v8f16(<4 x float>, <8 x half>, <8 x half>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+cmpbr,+complxnum,+cpa,+crc,+cssc,+dit,+dotprod,+f16f32dot,+f16f32mm,+f16mm,+faminmax,+flagm,+fp-armv8,+fprcvt,+fullfp16,+hbc,+hinte,+i8mm,+jsconv,+lse,+lsui,+lut,+mec,+mops,+neon,+occmo,+pauth,+predres,+ras,+rasv2,+rcpc,+rdm,+rme,+sb,+spe-eef,+specres2,+ssbs,+sve,+sve2,+sve2p1,+sve2p3,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v8.9a,+v8a,+v9.1a,+v9.2a,+v9.3a,+v9.4a,+v9.5a,+v9.6a,+v9.7a,+v9a,+wfxt" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055d742adfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d742adce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d742ae062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f070d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f070d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f070d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f070d231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d742a75bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d742a75a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d742a5a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d742709e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d742709b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f070d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f070d2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f070d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d742709a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c (377 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvt_bf16_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fcvt.bf16f32.v2(<vscale x 8 x bfloat> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fcvt.bf16f32.v2(<vscale x 8 x bfloat>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvt_bf16_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fcvt.bf16f32.v2(<vscale x 8 x bfloat> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvt_bf16_f32_m(<vscale x 8 x bfloat> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 8 x bfloat> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fcvt.bf16f32.v2(<vscale x 8 x bfloat> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055fabe97ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fabe979e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fabe97d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd727505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd72755c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd727505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd7274ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fabe912bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fabe912a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fabe8f78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fabe5a6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fabe5a6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd7274eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd7274ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd7274ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fabe5a6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c (378 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svwrffr(<vscale x 16 x i1> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   call void @llvm.aarch64.sve.wrffr(<vscale x 16 x i1> %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.sve.wrffr(<vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000558ad21dceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558ad21d9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558ad21dd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f069fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f069fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f069fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f069fd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558ad2172bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558ad2172a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558ad21578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558ad1e06e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558ad1e06b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f069fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f069fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f069fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558ad1e06a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c (379 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmadd_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmadd_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmadd_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmadd_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmadd_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmadd_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmadd_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmadd_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <v
# | ...
# `---data was truncated (10240/64252) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559409764eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559409761e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055940976562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f65ca849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f65ca8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f65ca849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f65ca831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005594096fabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005594096faa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005594096df8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055940938ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055940938eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f65ca832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f65ca8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f65ca8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055940938ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c (380 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vpaire_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vpaire.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vpaire.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vpaire_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vpaire.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vpaire.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vpaire_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vpaire.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vpaire.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vpaire_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vpaire.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vpaire.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vpaire_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vpaire.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vpaire.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vpaire_vv_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vpaire.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vpaire.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vpaire_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vpaire.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vpaire.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vpaire_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vpaire.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vpaire.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vpaire_vv_f32m2_tu(<vscale
# | ...
# `---data was truncated (10240/288267) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056399bbe5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056399bbe2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056399bbe662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb78c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb78c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb78c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb78c91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056399bb7bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056399bb7ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056399bb608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056399b80fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056399b80fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb78c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb78c91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb78c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056399b80fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c (381 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563094547eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563094544e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056309454862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f84c6249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f84c62a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f84c6249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f84c6231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005630944ddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005630944dda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005630944c28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563094171e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563094171b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f84c6232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f84c62330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f84c62330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563094171a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c (382 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svundef_s8() #0 {
# | entry:
# |   ret <vscale x 16 x i8> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svundef_s16() #0 {
# | entry:
# |   ret <vscale x 8 x i16> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svundef_s32() #0 {
# | entry:
# |   ret <vscale x 4 x i32> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svundef_s64() #0 {
# | entry:
# |   ret <vscale x 2 x i64> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svundef_u8() #0 {
# | entry:
# |   ret <vscale x 16 x i8> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svundef_u16() #0 {
# | entry:
# |   ret <vscale x 8 x i16> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svundef_u32() #0 {
# | entry:
# |   ret <vscale x 4 x i32> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svundef_u64() #0 {
# | entry:
# |   ret <vscale x 2 x i64> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svundef_f16() #0 {
# | entry:
# |   ret <vscale x 8 x half> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svundef_f32() #0 {
# | entry:
# |   ret <vscale x 4 x float> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svundef_f64() #0 {
# | entry:
# |   ret <vscale x 2 x double> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svundef_mf8() #0 {
# | entry:
# |   ret <vscale x 16 x i8> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svundef_bf16() #0 {
# | entry:
# |   ret <vscale x 8 x bfloat> undef
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055b5fc604eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b5fc601e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b5fc60562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6a45133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6a4518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6a45133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6a4511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b5fc59abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b5fc59aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b5fc57f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b5fc22ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b5fc22eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6a4511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6a4511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6a4511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b5fc22ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c (383 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_ver_za8_u8_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.ver.vg2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.ver.vg2.nxv16i8(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_ver_za8_s8_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.ver.vg2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_ver_za8_mf8_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.ver.vg2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_hor_za8_u8_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.hor.vg2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.hor.vg2.nxv16i8(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_hor_za8_s8_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.hor.vg2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_hor_za8_mf8_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.hor.vg2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_hor_za8_u8_vg4(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.hor.vg4.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.hor.vg4.nxv16i8(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_hor_za8_s8_vg4(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.hor.vg4.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_hor_za8_mf8_vg4(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.hor.vg4.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_ver_za8_u8_vg4(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.ver.vg4.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.ver.vg4.nxv16i8(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_ver_za8_s8_vg4(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.ver.vg4.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_ver_za8_mf8_vg4(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.ver.vg4.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svread_hor_za16_u16_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.read.hor.vg2.nxv8i16(i32 1, i32 %0)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.read.hor.vg2.nxv8i16(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svread_hor_za16_bf16_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.read.hor.vg2.nxv8bf16(i32 1, i32 %0)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.read.hor.vg2.nxv8bf16(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svread_hor_za16_f16_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.read.hor.vg2.nxv8f16(i32 1, i32 %0)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.read.hor.vg2.nxv8f16(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svread_hor_za16_s16_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.read.hor.vg2.nxv8i16(i32 1, i32 %0)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svread_ver_za16_u16_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x
# | ...
# `---data was truncated (10240/51854) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000556badf8aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556badf87e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556badf8b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0955f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0955f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0955f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0955f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556badf20bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556badf20a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556badf058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556badbb4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556badbb4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0955f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0955f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0955f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556badbb4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/minv.c (384 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/minv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svminv_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.sminv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.sminv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svminv_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.sminv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.sminv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svminv_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.sminv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sminv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svminv_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.sminv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sminv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svminv_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.uminv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.uminv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svminv_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.uminv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.uminv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svminv_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.uminv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uminv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svminv_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @test_svminv_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call half @llvm.aarch64.sve.fminv.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret half %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.sve.fminv.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @test_svminv_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call float @llvm.aarch64.sve.fminv.nxv4f32(<vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret float %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.sve.fminv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @test_svminv_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call double @llvm.aarch64.sve.fminv.nxv2f64(<vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret double %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.sve.fminv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attribute
# | ...
# `---data was truncated (10240/10818) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x000055c1abf56eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c1abf53e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c1abf5762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb0d241bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb0d24725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb0d241ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb0d2403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c1abeecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c1abeeca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c1abed18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c1abb80e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c1abb80b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb0d2404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb0d24050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb0d24050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c1abb80a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c (385 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfeq_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfeq_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfeq_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64
# | ...
# `---data was truncated (10240/66565) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056349242aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563492427e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056349242b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f211f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f211f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f211f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f211f631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005634923c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005634923c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005634923a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563492054e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563492054b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f211f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f211f6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f211f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563492054a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c (386 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sh_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sh_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sh_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sh_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sh_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sh_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sh_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sh_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sh_gather_u32base_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1, i64 0)
# |   %4 = sext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sh_gather_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = sext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sh_gather_u32base_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg,
# | ...
# `---data was truncated (10240/37388) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005646cd7d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005646cd7d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005646cd7d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b31a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b31aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b31a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b31a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005646cd76ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005646cd76ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005646cd7538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005646cd402e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005646cd402b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2b31a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b31a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b31a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005646cd402a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c (387 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1rq_mf8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1rq.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.ld1rq.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1rq_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1rq.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1rq_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1rq.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.ld1rq.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1rq_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1rq.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1rq.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1rq_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1rq.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1rq.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1rq_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1rq.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1rq_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1rq.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1rq_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1rq.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1rq_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1rq.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svld1rq_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.ld1rq.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ld1rq.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svld1rq_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.ld1rq.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ld1rq.nxv4f32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svld1rq_f64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.ld1rq.nxv2f64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ld1rq.nxv2f64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svld1rq_bf16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr 
# | ...
# `---data was truncated (10240/11267) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005617ae6b0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005617ae6ade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005617ae6b162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007facfc449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007facfc4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007facfc449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007facfc431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005617ae646bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005617ae646a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005617ae62b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005617ae2dae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005617ae2dab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007facfc432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007facfc4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007facfc4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005617ae2daa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c (388 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_f64m1(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1f64.p0.i64(<vscale x 1 x double> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_f64m2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2f64.p0.i64(<vscale x 2 x double> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_f64m4(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4f64.p0.i64(<vscale x 4 x double> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_f64m8(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8f64.p0.i64(<vscale x 8 x double> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_i64m1(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i64.p0.i64(<vscale x 1 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_i64m2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i64.p0.i64(<vscale x 2 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_i64m4(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i64.p0.i64(<vscale x 4 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_i64m8(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8i64.p0.i64(<vscale x 8 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_u64m1(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i64.p0.i64(<vscale x 1 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_u64m2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i64.p0.i64(<vscale x 2 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1
# | ...
# `---data was truncated (10240/26772) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056054b7bdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056054b7bae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056054b7be62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d2a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d2a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d2a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d2a831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056054b753bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056054b753a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056054b7388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056054b3e7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056054b3e7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1d2a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d2a8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d2a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056054b3e7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c (389 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcadd_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fcadd.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %4, <vscale x 8 x half> %2, i32 90)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fcadd.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcadd_f16_z_1(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fcadd.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %4, <vscale x 8 x half> %2, i32 270)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svcadd_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fcadd.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %4, <vscale x 4 x float> %2, i32 90)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fcadd.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svcadd_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fcadd.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %4, <vscale x 2 x double> %2, i32 90)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fcadd.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcadd_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fcadd.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i32 90)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svcadd_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fcadd.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i32 90)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svcadd_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.fcadd.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %2, i32 90)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcadd_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fcadd.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i32 90)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svcadd_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.ad
# | ...
# `---data was truncated (10240/12234) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c7d086feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c7d086ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c7d087062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6af5d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6af5d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6af5d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6af5d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c7d0805bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c7d0805a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c7d07ea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c7d0499e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c7d0499b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6af5d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6af5d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6af5d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c7d0499a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/addv.c (390 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/addv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svaddv_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i64 @llvm.aarch64.sve.saddv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.saddv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svaddv_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.saddv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.saddv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svaddv_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.saddv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.saddv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svaddv_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.saddv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.saddv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svaddv_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i64 @llvm.aarch64.sve.uaddv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uaddv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svaddv_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.uaddv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uaddv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svaddv_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.uaddv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uaddv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svaddv_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.uaddv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uaddv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @test_svaddv_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call half @llvm.aarch64.sve.faddv.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret half %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.sve.faddv.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @test_svaddv_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call float @llvm.aarch64.sve.faddv.nxv4f32(<vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret float %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.sve.faddv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @test_svaddv_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call double @llvm.aarch64.sve.faddv.nxv2f64(<vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret double %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.sve.faddv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | a
# | ...
# `---data was truncated (10240/10826) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S
# |  #0 0x00005583fae07eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005583fae04e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005583fae0862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1b37049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1b370a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1b37049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1b37031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005583fad9dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005583fad9da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005583fad828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005583faa31e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005583faa31b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1b37032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1b370330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1b370330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005583faa31a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c (391 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei8_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei8_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei8_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei8_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei8_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i8> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vloxei8_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, <vscale x 32 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i8> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei8_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei8_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei8_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = a
# | ...
# `---data was truncated (10240/288050) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056401fb36eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056401fb33e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056401fb3762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9f5eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9f5eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9f5eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9f5eb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056401faccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056401facca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056401fab18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056401f760e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056401f760b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9f5eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9f5eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9f5eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056401f760a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c (392 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmaxu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmaxu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmaxu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmaxu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmaxu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmaxu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmaxu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmaxu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmaxu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmaxu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmaxu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/97913) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e4cddfeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e4cddfbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e4cddff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f058bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f058bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f058bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f058bd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e4cdd94bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e4cdd94a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e4cdd798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e4cda28e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e4cda28b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f058bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f058bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f058bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e4cda28a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c (393 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzp1_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp1q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uzp1q.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzp1_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp1q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uzp1q.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzp1_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp1q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uzp1q.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzp1_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzp1q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uzp1q.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzp1_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp1q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzp1_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp1q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzp1_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp1q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzp1_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzp1q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svuzp1_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.uzp1q.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.uzp1q.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svuzp1_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.uzp1q.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.uzp1q.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svuzp1_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.uzp1q.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.uzp1q.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svuzp1_bf16(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.uzp1q.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.uzp1q.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056133d6a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056133d6a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056133d6a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f03af333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03af38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f03af333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f03af31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056133d63cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056133d63ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056133d6218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056133d2d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056133d2d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f03af31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03af31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03af31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056133d2d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c (394 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_single_x1_s8(i32 noundef %slice_base, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smla.za32.single.vg4x1.nxv16i8(i32 %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smla.za32.single.vg4x1.nxv16i8(i32, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_single_x1_s16(i32 noundef %slice_base, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smla.za64.single.vg4x1.nxv8i16(i32 %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smla.za64.single.vg4x1.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_uvmlal_single_x1_u8(i32 noundef %slice_base, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umla.za32.single.vg4x1.nxv16i8(i32 %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umla.za32.single.vg4x1.nxv16i8(i32, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_uvmlal_single_x1_u16(i32 noundef %slice_base, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umla.za64.single.vg4x1.nxv8i16(i32 %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umla.za64.single.vg4x1.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls_single_x1_s8(i32 noundef %slice_base, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smls.za32.single.vg4x1.nxv16i8(i32 %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smls.za32.single.vg4x1.nxv16i8(i32, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls_single_x1_s16(i32 noundef %slice_base, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smls.za64.single.vg4x1.nxv8i16(i32 %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smls.za64.single.vg4x1.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_uvmlsl_single_x1_u8(i32 noundef %slice_base, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umls.za32.single.vg4x1.nxv16i8(i32 %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umls.za32.single.vg4x1.nxv16i8(i32, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_uvmlsl_single_x1_u16(i32 noundef %slice_base, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umls.za64.single.vg4x1.nxv8i16(i32 %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umls.za64.single.vg4x1.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_sumlall_single_x1_s8(i32 noundef %slice_base, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.usmla.za32.single.vg4x1.nxv16i8(i32 %0, <vscale x 16 x i8> %2, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.usmla.za32.single.vg4x1.nxv16i8(i32, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_usmlall_single_x1_u8(i32 noundef %slice_base, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.usmla.za32.single.vg4x1.nxv16i8(i32 %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_single_x2_s8(i32 noundef %slice_base, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | 
# | ...
# `---data was truncated (10240/178306) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000561f65d8deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561f65d8ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561f65d8e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1ca0505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1ca055c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1ca0505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1ca04ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f65d23bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561f65d23a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561f65d088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561f659b7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561f659b7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1ca04eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1ca04ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1ca04ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f659b7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c (395 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i1 @test_svptest_any(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret i1 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i1 @test_svptest_first(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call i1 @llvm.aarch64.sve.ptest.first.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret i1 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i1 @llvm.aarch64.sve.ptest.first.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i1 @test_svptest_last(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call i1 @llvm.aarch64.sve.ptest.last.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret i1 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i1 @llvm.aarch64.sve.ptest.last.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005625620e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005625620e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005625620ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b8a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b8a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b8a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b8a31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056256207fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056256207fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005625620648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562561d13e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562561d13b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8b8a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b8a31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b8a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562561d13a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c (396 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8mf8x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_u8mf8x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_u8mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_u8mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_u8m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   
# | ...
# `---data was truncated (10240/21558) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556b2314deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556b2314ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556b2314e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f57c801bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57c80725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f57c801ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f57c8003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b230e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556b230e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556b230c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556b22d77e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556b22d77b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f57c8004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57c80050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57c80050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b22d77a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c (397 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvtbf16_f_f_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvtbf16_f_f_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvtbf16_f_f_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvtbf16_f_f_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvtbf16_f_f_v_f32m8_tu(<vscale x 16 x float> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvtbf16_f_f_v_f32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvtbf16_f_f_v_f32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvtbf16_f_f_v_f32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvtbf16_f_f_v_f32m4_tum(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr,
# | ...
# `---data was truncated (10240/23056) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a10062eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a10062be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a10062f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f43e6649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f43e66a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f43e6649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f43e6631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a1005c4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a1005c4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a1005a98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a100258e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a100258b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f43e6632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f43e66330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f43e66330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a100258a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c (398 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1ub_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1ub_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1ub_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1ub_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1ub_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1ub_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1ub_vnum_s16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1ub_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i8> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1ub_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i8> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1ub_vnum_u16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1ub_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4
# | ...
# `---data was truncated (10240/27977) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055e4addd4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e4addd1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e4addd562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2834c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2834ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2834c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2834c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e4add6abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e4add6aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e4add4f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e4ad9fee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e4ad9feb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2834c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2834c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2834c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e4ad9fea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c (399 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svmaxnm_single_bf16_x2(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 1
# |   %5 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %5)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svmaxnm_single_f16_x2(<vscale x 8 x half> %zdn.coerce0, <vscale x 8 x half> %zdn.coerce1, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zdn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 1
# |   %5 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv8f16(<vscale x 8 x half> %3, <vscale x 8 x half> %4, <vscale x 8 x half> %5)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svmaxnm_single_f32_x2(<vscale x 4 x float> %zdn.coerce0, <vscale x 4 x float> %zdn.coerce1, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zdn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zdn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zdn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4, <vscale x 4 x float> %5)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double> } @test_svmaxnm_single_f64_x2(<vscale x 2 x double> %zdn.coerce0, <vscale x 2 x double> %zdn.coerce1, <vscale x 2 x double> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %zdn.addr = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %zm.addr = alloca <vscale x 2 x double>, align 16
# |   %0 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } poison, <vscale x 2 x double> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } %0, <vscale x 2 x double> %zdn.coerce1, 1
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %zdn, align 16
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 2 x double> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %2, 0
# |   %4 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %2, 1
# |   %5 = load <vscale x 2 x double>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv2f64(<vscale x 2 x double> %3, <vscale x 2 x double> %4, <vscale x 2 x double> %5)
# |   ret { <vscale x 2 x double>, <vscale x 2 x double> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svmaxnm_single_bf16_x4(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zdn.coerce2, <vscale x 8 x bfloat> %zdn.coerce3, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, <vscale x 8 x bfloat> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zdn.coerce3, 3
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 1
# |   %7 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 2
# |   %8 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 3
# |   %9 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %10 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmaxnm.single.x4.nxv8bf16(<vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %6, <vscale x 8 x bfloat> %7, <vscale x 8 x bfloat> %8, <vscale x 8 x bfloat> %9)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %10
# | }
# | 
# | ; Funct
# | ...
# `---data was truncated (10240/50311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055954ee1beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055954ee18e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055954ee1c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f38bef05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f38bef5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f38bef05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f38beeed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055954edb1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055954edb1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055954ed968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055954ea45e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055954ea45b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f38beeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f38beeef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f38beeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055954ea45a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c (400 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-tmop -target-feature +sme-f16f16 -target-feature +sme-f8f32 -target-feature +sme-b16b16 -target-feature +sme-f8f16 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-tmop -target-feature +sme-f16f16 -target-feature +sme-f8f32 -target-feature +sme-b16b16 -target-feature +sme-f8f16 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svtmopa_lane_za32_s8_s8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, <vscale x 16 x i8> %zk) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %zk.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store <vscale x 16 x i8> %zk, ptr %zk.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = load <vscale x 16 x i8>, ptr %zk.addr, align 16
# |   call void @llvm.aarch64.sme.stmopa.za32.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.stmopa.za32.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svtmopa_lane_za32_u8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, <vscale x 16 x i8> %zk) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %zk.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store <vscale x 16 x i8> %zk, ptr %zk.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = load <vscale x 16 x i8>, ptr %zk.addr, align 16
# |   call void @llvm.aarch64.sme.utmopa.za32.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.utmopa.za32.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svtmopa_lane_za32_s8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, <vscale x 16 x i8> %zk) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %zk.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store <vscale x 16 x i8> %zk, ptr %zk.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = load <vscale x 16 x i8>, ptr %zk.addr, align 16
# |   call void @llvm.aarch64.sme.sutmopa.za32.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.sutmopa.za32.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svtmopa_lane_za32_u8_s8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, <vscale x 16 x i8> %zk) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %zk.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store <vscale x 16 x i8> %zk, ptr %zk.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = load <vscale x 16 x i8>, ptr %zk.addr, align 16
# |   call void @llvm.aarch64.sme.ustmopa.za32.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.ustmopa.za32.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svtmopa_lane_za32_s16_s16(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm, <vscale x 16 x i8> %zk) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %zk.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   store <vscale x 16 x i8> %zk, ptr %zk.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = load <vscale x 16 x i8>, ptr %zk.addr, align 16
# |   call void @llvm.aarch64.sme.stmopa.za32.nxv8i16(i32 1, <vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.stmopa.za32.nxv8i16(i32 immarg, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svtmopa_lane_za32_u16_u16(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm, <vscale x 16 x i8> %zk) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %zk.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   store <vscale x 16 x i8> %zk, ptr %zk.addr, align 16
# |   %2 = load { <v
# | ...
# `---data was truncated (10240/25017) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000565015b2deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565015b2ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000565015b2e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe1fa249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe1fa2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe1fa249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe1fa231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565015ac3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565015ac3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000565015aa88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565015757e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565015757b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe1fa232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe1fa2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe1fa2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565015757a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c (401 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svbrkpa_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.brkpa.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.brkpa.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d99dd48eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d99dd45e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d99dd4962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb69821bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb6982725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb69821ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb698203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d99dcdebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d99dcdea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d99dcc38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d99d972e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d99d972b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb698204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb6982050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb6982050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d99d972a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c (402 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1uh_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uh_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1uh_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uh_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1uh_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uh_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1uh_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uh_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1uh_gather_u32base_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1, i64 0)
# |   %4 = zext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uh_gather_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = zext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1uh_gather_u32base_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg,
# | ...
# `---data was truncated (10240/37388) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055bdd8dc4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bdd8dc1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bdd8dc562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f776fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f776fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f776fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f776fd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bdd8d5abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bdd8d5aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bdd8d3f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bdd89eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bdd89eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f776fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f776fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f776fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bdd89eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c (403 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadrw_u32base_s32index(<vscale x 4 x i32> %bases, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.adrw.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.adrw.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadrw_u64base_s64index(<vscale x 2 x i64> %bases, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.adrw.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.adrw.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadrw_u32base_u32index(<vscale x 4 x i32> %bases, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.adrw.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadrw_u64base_u64index(<vscale x 2 x i64> %bases, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.adrw.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056376e66eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056376e66be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056376e66f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe5eca1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe5eca725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe5eca1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe5eca03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056376e604bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056376e604a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056376e5e98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056376e298e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056376e298b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe5eca04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe5eca050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe5eca050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056376e298a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c (404 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_i8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e8_v_i8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e8_v_i8m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_u8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_u8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e8_v_u8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/48305) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d53856beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d538568e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d53856c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab70a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab70aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab70a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab70a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d538501bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d538501a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d5384e68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d538195e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d538195b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fab70a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab70a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab70a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d538195a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c (405 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_bf16_n_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_bf16_n_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_bf16_n_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000562a1731ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562a17319e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562a1731d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6514f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6514f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6514f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6514f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562a172b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562a172b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562a172978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562a16f46e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562a16f46b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6514f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6514f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6514f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562a16f46a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c (406 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x2_za32_s8_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm1, ptr %zm.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.smop4a.wide.1x2.nxv16i8(i32 1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4a.wide.1x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x2_za32_s8_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm1, ptr %zm.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.smop4s.wide.1x2.nxv16i8(i32 1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4s.wide.1x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x2_za32_u8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm1, ptr %zm.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.umop4a.wide.1x2.nxv16i8(i32 1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4a.wide.1x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x2_za32_u8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm1, ptr %zm.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.umop4s.wide.1x2.nxv16i8(i32 1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4s.wide.1x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x2_za32_s8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm1, ptr %zm.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.sumop4a.wide.1x2.nxv16i8(i32 1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.sumop4a.wide.1x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x2_za32_s8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm1, ptr %zm.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.sumop4s.wide.1x2.nxv16i8(i32 1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.sumop4s.wide.1x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x2_za32_u8_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <
# | ...
# `---data was truncated (10240/50724) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055c7cc57beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c7cc578e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c7cc57c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a82049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a820a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a82049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a82031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c7cc511bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c7cc511a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c7cc4f68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c7cc1a5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c7cc1a5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2a82032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a820330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a820330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c7cc1a5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c (407 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16ff_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16ff_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_i16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# | 
# | ...
# `---data was truncated (10240/100521) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005629d154feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005629d154ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005629d155062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf3a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf3a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf3a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf3a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005629d14e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005629d14e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005629d14ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005629d1179e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005629d1179b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdf3a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf3a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf3a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005629d1179a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c (408 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf8_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> %0, <vscale x 1 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16>, <vscale x 1 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf4_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> %0, <vscale x 2 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16>, <vscale x 2 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf2_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m1_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> %0, <vscale x 8 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16>, <vscale x 8 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m2_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> %0, <vscale x 16 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16>, <vscale x 16 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m4_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> %0, <vscale x 32 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16>, <vscale x 32 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m8_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> %0, <vscale x 64 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16>, <vscale x 64 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsumu_vs_u16mf4_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv1i
# | ...
# `---data was truncated (10240/51295) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559a370f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559a370f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559a370fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3a78849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3a788a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3a78849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3a78831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a3708fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559a3708fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559a370748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559a36d23e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559a36d23b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3a78832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3a788330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3a788330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a36d23a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon/rounding-v8.5.c (409 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/rounding-v8.5.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +v8.5a           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c --check-prefixes=LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +v8.5a -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrnd32x_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrnd32x_f32.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrnd32x_f321.i = call <2 x float> @llvm.aarch64.neon.frint32x.v2f32(<2 x float> %vrnd32x_f32.i)
# |   %vrnd32x_f322.i = bitcast <2 x float> %vrnd32x_f321.i to <8 x i8>
# |   store <8 x i8> %vrnd32x_f322.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrnd32xq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrnd32xq_f32.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrnd32xq_f321.i = call <4 x float> @llvm.aarch64.neon.frint32x.v4f32(<4 x float> %vrnd32xq_f32.i)
# |   %vrnd32xq_f322.i = bitcast <4 x float> %vrnd32xq_f321.i to <16 x i8>
# |   store <16 x i8> %vrnd32xq_f322.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrnd32z_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrnd32z_f32.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrnd32z_f321.i = call <2 x float> @llvm.aarch64.neon.frint32z.v2f32(<2 x float> %vrnd32z_f32.i)
# |   %vrnd32z_f322.i = bitcast <2 x float> %vrnd32z_f321.i to <8 x i8>
# |   store <8 x i8> %vrnd32z_f322.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrnd32zq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrnd32zq_f32.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrnd32zq_f321.i = call <4 x float> @llvm.aarch64.neon.frint32z.v4f32(<4 x float> %vrnd32zq_f32.i)
# |   %vrnd32zq_f322.i = bitcast <4 x float> %vrnd32zq_f321.i to <16 x i8>
# |   store <16 x i8> %vrnd32zq_f322.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrnd64x_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrnd64x_f32.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrnd64x_f321.i = call <2 x float> @llvm.aarch64.neon.frint64x.v2f32(<2 x float> %vrnd64x_f32.i)
# |   %vrnd64x_f322.i = bitcast <2 x float> %vrnd64x_f321.i to <8 x i8>
# |   store <8 x i8> %vrnd64x_f322.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrnd64xq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrnd64xq_f32.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrnd64xq_f321.i = call <4 x float> @llvm.aarch64.neon.frint64x.v4f32(<4 x float> %vrnd64xq_f32.i)
# |   %vrnd64xq_f322.i = bitcast <4 x float> %vrnd64xq_f321.i to <16 x i8>
# |   store <16 x i8> %vrnd64xq_f322.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrnd64z_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrnd64z_f32.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrnd64z_f321.i = call <2 x float> @llvm.aarch64.neon.frint64z.v2f32(<2 x float> %vrnd64z_f32.i)
# |   %vrnd64z_f322.i = bitcast <2 x float> %vrnd64z_f321.i to <8 x i8>
# |   store <8 x i8> %vrnd64z_f322.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrnd64zq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrnd64zq_f32.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrnd64zq_f321.i = call <4 x float> @llvm.aarch64.neon.frint64z.v4f32(<4 x float> %vrnd64zq_f32.i)
# |   %vrnd64zq_f322.i = bitcast <4 x float> %vrnd64zq_f321.i to <16 x i8>
# |   store <16 x i8> %vrnd64zq_f322.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vrnd32x_f64(<1 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__ret.i = alloca <1 x double>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrnd32x_f64.i = bitcast <8 x i8> %1 to <1 x double>
# |   %vrnd32x_f641.i = call <1 x double> @llvm.aarch64.neon.frint32x.v1f64(<1 x double> %vrnd32x_f64.i)
# |   %vrnd32x_f642.i = bitcast <1 x double> %vrnd32x_f641.i to <8 x i8>
# |   store <8 x i8> %vrnd32x_f642.i, ptr %ref.tmp.i, align 8
# |   %2 = load <1 x double>, ptr %ref.tmp.i, align 8
# |   store <1 x double> %2, ptr %__ret.i, align 8
# |   %3 = load <1 x double>, ptr %__ret.i, align 8
# |   ret <1 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vrnd32xq_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrnd32xq_f64.i = bitcast <16 x i8> %1 to <2 x double>
# |   %vrnd32xq_f641.i = call <2 x double> @llvm.aarch64.neon.frint32x.v2f64(<2 x double> %vrnd32xq_f64.i)
# |   %vrnd32xq_f642.i = bitcast <2 x double> %vrnd32xq_f641.i to <16 x i8>
# |   store <16 x i8> %vrnd32xq_f642.i, ptr %ref.tmp.i, align 16
# |   %2 = load <2 x double>, ptr %ref.tmp.i, align 16
# |   store <2 x double> %2, ptr %__ret.i, align 16
# |   %3 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vrnd32z_f64(<1 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__ret.i = alloca <1 x double>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrnd32z_f64.i = bitcast <8 x i8> %1 
# | ...
# `---data was truncated (10240/18543) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055c8e6e8ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c8e6e89e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c8e6e8d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa8fa933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa8fa98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa8fa933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa8fa91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c8e6e22bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c8e6e22a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c8e6e078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c8e6ab6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c8e6ab6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa8fa91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa8fa91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa8fa91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c8e6ab6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c --check-prefixes=LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c --check-prefixes=LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c (410 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti2_lane_zt_u8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti2_lane_zt_s8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti2_lane_zt_mf8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svluti2_lane_zt_u16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8i16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svluti2_lane_zt_s16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svluti2_lane_zt_f16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8f16(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8f16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svluti2_lane_zt_bf16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8bf16(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8bf16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svluti2_lane_zt_u32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4i32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svluti2_lane_zt_s32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svluti2_lane_zt_f32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4f32(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4f32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000556299fa0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556299f9de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556299fa162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8990133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f899018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8990133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f899011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556299f36bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556299f36a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556299f1b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556299bcae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556299bcab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f899011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f899011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f899011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556299bcaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c (411 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svbic_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.bic.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.bic.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svbic_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.bic.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.bic.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svbic_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.bic.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.bic.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svbic_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.bic.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.bic.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svbic_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.bic.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svbic_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.bic.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svbic_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.bic.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svbic_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.bic.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svbic_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, pt
# | ...
# `---data was truncated (10240/52880) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055982cb36eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055982cb33e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055982cb3762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f433f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f433f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f433f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f433f031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055982caccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055982cacca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055982cab18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055982c760e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055982c760b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f433f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f433f0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f433f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055982c760a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c (412 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsub_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsub_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsub_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsub_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsub_vf_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrsub_vf_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsub_vf_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsub_vf_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.a
# | ...
# `---data was truncated (10240/32394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005628d36f0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005628d36ede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005628d36f162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f012dd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f012dd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f012dd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f012dced507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005628d3686bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005628d3686a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005628d366b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005628d331ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005628d331ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f012dceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f012dcef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f012dcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005628d331aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c (413 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f16m1x6(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f32m1x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f64m1x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/69980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005590d6dd5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005590d6dd2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005590d6dd662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2808333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f280838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2808333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f280831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005590d6d6bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005590d6d6ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005590d6d508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005590d69ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005590d69ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f280831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f280831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f280831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005590d69ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c (414 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssubu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssubu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssubu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssubu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssubu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssubu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssubu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssubu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssubu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   s
# | ...
# `---data was truncated (10240/223359) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055affe8eaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055affe8e7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055affe8eb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f23e7849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f23e78a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f23e7849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f23e7831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055affe880bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055affe880a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055affe8658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055affe514e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055affe514b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f23e7832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f23e78330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f23e78330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055affe514a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmaxaq.c (415 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmaxaq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxaq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %b.addr, align 8
# |   %1 = icmp slt <16 x i8> %0, zeroinitializer
# |   %2 = sub <16 x i8> zeroinitializer, %0
# |   %3 = select <16 x i1> %1, <16 x i8> %2, <16 x i8> %0
# |   %4 = load <16 x i8>, ptr %a.addr, align 8
# |   %5 = icmp uge <16 x i8> %4, %3
# |   %6 = select <16 x i1> %5, <16 x i8> %4, <16 x i8> %3
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxaq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = icmp slt <8 x i16> %0, zeroinitializer
# |   %2 = sub <8 x i16> zeroinitializer, %0
# |   %3 = select <8 x i1> %1, <8 x i16> %2, <8 x i16> %0
# |   %4 = load <8 x i16>, ptr %a.addr, align 8
# |   %5 = icmp uge <8 x i16> %4, %3
# |   %6 = select <8 x i1> %5, <8 x i16> %4, <8 x i16> %3
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxaq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = icmp slt <4 x i32> %0, zeroinitializer
# |   %2 = sub <4 x i32> zeroinitializer, %0
# |   %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %0
# |   %4 = load <4 x i32>, ptr %a.addr, align 8
# |   %5 = icmp uge <4 x i32> %4, %3
# |   %6 = select <4 x i1> %5, <4 x i32> %4, <4 x i32> %3
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxaq_m_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vmaxa.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vmaxa.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxaq_m_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vmaxa.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vmaxa.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxaq_m_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.vmaxa.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vmaxa.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563fa93d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563fa93d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563fa93d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b09249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b092a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b09249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b09231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563fa936bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563fa936ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563fa93508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563fa8fffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563fa8fffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4b09232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b092330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b092330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563fa8fffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c (416 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwcvtu_x_x_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwcvtu_x_x_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwcvtu_x_x_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwcvtu_x_x_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwcvtu_x_x_v_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwcvtu_x_x_v_u16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwcvtu_x_x_v_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwcvtu_x_x_v_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwcvtu_x_x_v_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vwcvtu_x_x_v_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %2 = load i6
# | ...
# `---data was truncated (10240/67158) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564b24240eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564b2423de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564b2424162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f0b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f0b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f0b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f0b831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564b241d6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564b241d6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564b241bb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564b23e6ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564b23e6ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1f0b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f0b8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f0b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564b23e6aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c (417 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16
# | ...
# `---data was truncated (10240/295311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564bd0b22eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564bd0b1fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564bd0b2362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd843a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd843aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd843a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd843a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564bd0ab8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564bd0ab8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564bd0a9d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564bd074ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564bd074cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd843a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd843a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd843a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564bd074ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c (418 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svcreate2_s8(<vscale x 16 x i8> %x0, <vscale x 16 x i8> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i8>, align 16
# |   %x1.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %x0, ptr %x0.addr, align 16
# |   store <vscale x 16 x i8> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %1, 1
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svcreate2_s16(<vscale x 8 x i16> %x0, <vscale x 8 x i16> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x i16>, align 16
# |   %x1.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x i16> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %1, 1
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svcreate2_s32(<vscale x 4 x i32> %x0, <vscale x 4 x i32> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 4 x i32>, align 16
# |   %x1.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %x0, ptr %x0.addr, align 16
# |   store <vscale x 4 x i32> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %0, 0
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %1, 1
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svcreate2_s64(<vscale x 2 x i64> %x0, <vscale x 2 x i64> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 2 x i64>, align 16
# |   %x1.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %x0, ptr %x0.addr, align 16
# |   store <vscale x 2 x i64> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %0, 0
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %1, 1
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svcreate2_u8(<vscale x 16 x i8> %x0, <vscale x 16 x i8> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i8>, align 16
# |   %x1.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %x0, ptr %x0.addr, align 16
# |   store <vscale x 16 x i8> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %1, 1
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svcreate2_u16(<vscale x 8 x i16> %x0, <vscale x 8 x i16> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x i16>, align 16
# |   %x1.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x i16> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %1, 1
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svcreate2_u32(<vscale x 4 x i32> %x0, <vscale x 4 x i32> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 4 x i32>, align 16
# |   %x1.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %x0, ptr %x0.addr, align 16
# |   store <vscale x 4 x i32> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %0, 0
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %1, 1
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svcreate2_u64(<vscale x 2 x i64> %x0, <vscale x 2 x i64> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 2 x i64>, align 16
# |   %x1.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %x0, ptr %x0.addr, align 16
# |   store <vscale x 2 x i64> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %0, 0
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %1, 1
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svcreate2_f16(<vscale x 8 x half> %x0, <vscale x 8 x half> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x half>, align 16
# |   %x1.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x half> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %0, 0
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %1, 1
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svcreate2_f32(<vscale x 4 x float> %x0, <vscale x 4 x float> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 4 x float>, align 16
# |   %x1.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %x0, ptr %x0.addr, align 16
# |   store <vscale x 4 x float> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %0, 0
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %1, 1
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double> } @test_svcreate2_f64(<vscale x 2 x double> %x0, <vscale x 2 x double> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 2 x double>, align 16
# |   %x1.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %x0, ptr %x0.addr, align 16
# |   store <vscale x 2 x double> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } poison, <vscale x 2 x double> %0, 0
# |   %3 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } %2, <vscale x 2 x double> %1, 1
# |   ret { <vscale x 2 x double>, <vscale x 2 x double> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svcreate2_mf8(<vscale x 16 x i8> %x0, <vscale x 16 x i8> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i8>, align 16
# |   %x1.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %x0, ptr %x0.addr, align 16
# |   store <vscale x 16 x i8> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %1, 1
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svcreate2_bf16(<vscale x 8 x bfloat> %x0, <vscale x 8 x bfloat> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %x1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x bfloat> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %0, 0
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vsc
# | ...
# `---data was truncated (10240/10734) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005579757b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005579757b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005579757b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f58f0f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f58f0f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f58f0f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f58f0f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055797574bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055797574ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005579757308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005579753dfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005579753dfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f58f0f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f58f0f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f58f0f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005579753dfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c (419 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1q_gather_u64base_offset_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2i64.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2i64.nxv2i64(<vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1q_gather_u64base_offset_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2i64.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1q_gather_u64base_offset_u32(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv4i32.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv4i32.nxv2i64(<vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1q_gather_u64base_offset_s32(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv4i32.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1q_gather_u64base_offset_u16(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv8i16.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv8i16.nxv2i64(<vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1q_gather_u64base_offset_s16(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv8i16.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1q_gather_u64base_offset_u8(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv16i8.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv16i8.nxv2i64(<vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1q_gather_u64base_offset_s8(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv16i8.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svld1q_gather_u64base_offset_f64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2f64.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2f64.nxv2i64(<vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svld1q_gather_u64base_offset_f32(<vscale x 16 x i1> %pg, <vscale x 2 x
# | ...
# `---data was truncated (10240/58824) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005645cd38eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005645cd38be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005645cd38f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff886b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff886b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff886b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff886b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005645cd324bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005645cd324a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005645cd3098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005645ccfb8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005645ccfb8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff886b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff886b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff886b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005645ccfb8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c (420 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfgt_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfgt_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfgt_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/66557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d36515eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d36515be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d36515f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6a17b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6a17b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6a17b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6a17b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d3650f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d3650f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d3650d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d364d88e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d364d88b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6a17b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6a17b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6a17b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d364d88a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c (421 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsge_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsge_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsge_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsge_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsge_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsge_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsge_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsge_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsge_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsge_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsge_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsge.nxv32i8.nxv32i8.i64(<vscale x 32 x 
# | ...
# `---data was truncated (10240/95089) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055770308eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055770308be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055770308f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff871133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff87118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff871133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff87111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557703024bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557703024a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005577030098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557702cb8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557702cb8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff87111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff87111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff87111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557702cb8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c (422 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f16m1x3(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f16m2x3(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f32m1x3(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f32m2x3(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f64m1x3(ptr noundef %base, <vscale x 1 x i32> %binde
# | ...
# `---data was truncated (10240/99754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055761696beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557616968e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055761696c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb743849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb7438a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb743849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb743831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557616901bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557616901a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005576168e68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557616595e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557616595b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb743832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb7438330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb7438330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557616595a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c (423 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmin_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmin_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmin_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   stor
# | ...
# `---data was truncated (10240/52599) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056281833deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056281833ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056281833e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f15a6f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f15a6f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f15a6f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f15a6f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005628182d3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005628182d3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005628182b88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562817f67e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562817f67b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f15a6f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15a6f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15a6f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562817f67a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c (424 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqrshrn_s16_s32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrn.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, i32 16)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrn.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqrshrn_u16_u32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqrshrn.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, i32 16)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqrshrn.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqrshrun_u16_s32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrun.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, i32 16)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrun.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x0000564153641eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056415363ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056415364262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab88f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab88f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab88f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab88f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005641535d7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005641535d7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005641535bc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056415326be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056415326bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fab88f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab88f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab88f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056415326ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c (425 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_multi_za32_vg1x2_f16(i32 noundef %slice_base, <vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1, <vscale x 8 x half> %zm.coerce0, <vscale x 8 x half> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zm.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %5, 1
# |   %8 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %8, 1
# |   call void @llvm.aarch64.sme.fdot.za32.vg1x2.nxv8f16(i32 %4, <vscale x 8 x half> %6, <vscale x 8 x half> %7, <vscale x 8 x half> %9, <vscale x 8 x half> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fdot.za32.vg1x2.nxv8f16(i32, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_multi_za32_vg1x4_f16(i32 noundef %slice_base, <vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1, <vscale x 8 x half> %zn.coerce2, <vscale x 8 x half> %zn.coerce3, <vscale x 8 x half> %zm.coerce0, <vscale x 8 x half> %zm.coerce1, <vscale x 8 x half> %zm.coerce2, <vscale x 8 x half> %zm.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %1, <vscale x 8 x half> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zn.coerce3, 3
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   %4 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zm.coerce0, 0
# |   %5 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, <vscale x 8 x half> %zm.coerce1, 1
# |   %6 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %5, <vscale x 8 x half> %zm.coerce2, 2
# |   %7 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %6, <vscale x 8 x half> %zm.coerce3, 3
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %7, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %zm2, ptr %zm.addr, align 16
# |   %8 = load i32, ptr %slice_base.addr, align 4
# |   %9 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %10 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %9, 0
# |   %11 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %9, 1
# |   %12 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %9, 2
# |   %13 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %9, 3
# |   %14 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm.addr, align 16
# |   %15 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %14, 0
# |   %16 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %14, 1
# |   %17 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %14, 2
# |   %18 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %14, 3
# |   call void @llvm.aarch64.sme.fdot.za32.vg1x4.nxv8f16(i32 %8, <vscale x 8 x half> %10, <vscale x 8 x half> %11, <vscale x 8 x half> %12, <vscale x 8 x half> %13, <vscale x 8 x half> %15, <vscale x 8 x half> %16, <vscale x 8 x half> %17, <vscale x 8 x half> %18)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fdot.za32.vg1x4.nxv8f16(i32, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_single_za32_vg1x2_f16(i32 noundef %slice_base, <vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %3, 0
# |   %5 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %3, 1
# |   %6 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.fdot.single.za32.vg1x2.nxv8f16(i32 %2, <vscale x 8 x half> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fdot.single.za32.vg1x2.nxv8f16(i32, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_single_za32_vg1x4_f16(i32 noundef %slice_base, <vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1, <vscale x 8 x half> %zn.coerce2, <vscale x 8 x half> %zn.coerce3, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x 
# | ...
# `---data was truncated (10240/34400) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005611eaf2deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005611eaf2ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005611eaf2e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1af1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1af1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1af1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1af1d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005611eaec3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005611eaec3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005611eaea88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005611eab57e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005611eab57b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1af1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1af1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1af1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005611eab57a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c (426 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmla_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %4 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.mla.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %4, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.mla.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmla_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %6 = call <vscale x 8 x i16> @llvm.aarch64.sve.mla.nxv8i16(<vscale x 8 x i1> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.mla.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmla_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %6 = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.nxv4i32(<vscale x 4 x i1> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3)
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.mla.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmla_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   %op3.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x i64> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %6 = call <vscale x 2 x i64> @llvm.aarch64.sve.mla.nxv2i64(<vscale x 2 x i1> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3)
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.mla.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmla_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %4 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.mla.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %4, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmla_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %6 = call <vscale x 8 x i16> @llvm.aarch64.sve.mla.nxv8i16(<vscale x 8 x i1> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmla_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %6 = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.nxv4i32(<vscale x 4 x i1> %4, <vs
# | ...
# `---data was truncated (10240/92910) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055dadb4f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dadb4f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dadb4f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f56e1649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56e16a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f56e1649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f56e1631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dadb48abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dadb48aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dadb46f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dadb11ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dadb11eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f56e1632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56e16330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56e16330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dadb11ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c (427 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgather_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgather_vx_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgather_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgather_vx_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgather_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgather_vx_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgather_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgather_vx_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgather_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x i16
# | ...
# `---data was truncated (10240/62095) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558f4482eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558f4482be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558f4482f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2ee6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2ee618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2ee6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2ee611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f447c4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558f447c4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558f447a98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558f44458e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558f44458b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2ee611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2ee611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2ee611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f44458a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c (428 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16mf4(ptr noundef %base, <vscale x 1 x i32> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16mf2(ptr noundef %base, <vscale x 2 x i32> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16m1(ptr noundef %base, <vscale x 4 x i32> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16m2(ptr noundef %base, <vscale x 8 x i32> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16m4(ptr noundef %base, <vscale x 16 x i32> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f32mf2(ptr noundef %base, <vscale x 1 x i32> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f32m1(ptr noundef %base, <vscale x 2 x i32> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f32m2(ptr noundef %base, <vscale x 4 x i32> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f32m4(ptr noundef %base, <vscale x 8 x i32> %bindex, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | ...
# `---data was truncated (10240/120907) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564143b9eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564143b9be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564143b9f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb3a1a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb3a1aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb3a1a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb3a1a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564143b34bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564143b34a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564143b198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005641437c8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005641437c8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb3a1a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb3a1a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb3a1a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005641437c8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c (429 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_qcvtn_s16_s32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtn.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtn.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_qcvtn_u16_u32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqcvtn.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqcvtn.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_qcvtn_u16_s32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtun.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtun.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005592205e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005592205e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005592205e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9d8ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9d8eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9d8ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9d8ec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055922057bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055922057ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005592205608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055922020fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055922020fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9d8ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9d8ec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9d8ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055922020fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c (430 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svluti4_lane_zt_u8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svluti4_lane_zt_s8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svluti4_lane_zt_mf8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svluti4_lane_zt_u16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sme.luti4.lane.zt.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 8 x i16> @llvm.aarch64.sme.luti4.lane.zt.nxv8i16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svluti4_lane_zt_s16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sme.luti4.lane.zt.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svluti4_lane_zt_f16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x half> @llvm.aarch64.sme.luti4.lane.zt.nxv8f16(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sme.luti4.lane.zt.nxv8f16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svluti4_lane_zt_bf16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x bfloat> @llvm.aarch64.sme.luti4.lane.zt.nxv8bf16(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sme.luti4.lane.zt.nxv8bf16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svluti4_lane_zt_u32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sme.luti4.lane.zt.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 4 x i32> @llvm.aarch64.sme.luti4.lane.zt.nxv4i32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svluti4_lane_zt_s32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sme.luti4.lane.zt.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svluti4_lane_zt_f32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x float> @llvm.aarch64.sme.luti4.lane.zt.nxv4f32(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sme.luti4.lane.zt.nxv4f32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005633c662feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005633c662ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005633c663062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fde3db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fde3db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fde3db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fde3db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005633c65c5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005633c65c5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005633c65aa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005633c6259e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005633c6259b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fde3db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fde3db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fde3db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005633c6259a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c (431 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svasrd_n_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %2, i32 1)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svasrd_n_s8_z_1(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %2, i32 8)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svasrd_n_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = select <vscale x 8 x i1> %2, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %3, i32 1)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svasrd_n_s16_z_1(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = select <vscale x 8 x i1> %2, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %3, i32 16)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svasrd_n_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = select <vscale x 4 x i1> %2, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %3, i32 1)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svasrd_n_s32_z_1(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = select <vscale x 4 x i1> %2, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %3, i32 32)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svasrd_n_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = select <vscale x 2 x i1> %2, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.asrd.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %3, i32 1)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.asrd.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svasrd_n_s64_z_1(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = select <vscale x 2 x i1> %2, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.asrd.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %3, i32 64)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svasrd_n_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i32 1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svasrd_n_s16_m(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1, i32 1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svasrd_n_s32_m(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1> %2, 
# | ...
# `---data was truncated (10240/14353) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d11bc8feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d11bc8ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d11bc9062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc3f8905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc3f895c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc3f8905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc3f88ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d11bc25bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d11bc25a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d11bc0a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d11b8b9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d11b8b9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc3f88eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc3f88ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc3f88ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d11b8b9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c (432 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmopa_s16(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   call void @llvm.aarch64.sme.smopa.za32.nxv8i16(i32 3, <vscale x 8 x i1> %4, <vscale x 8 x i1> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smopa.za32.nxv8i16(i32 immarg, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmopa_u16(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   call void @llvm.aarch64.sme.umopa.za32.nxv8i16(i32 3, <vscale x 8 x i1> %4, <vscale x 8 x i1> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umopa.za32.nxv8i16(i32 immarg, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmops_s16(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   call void @llvm.aarch64.sme.smops.za32.nxv8i16(i32 3, <vscale x 8 x i1> %4, <vscale x 8 x i1> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smops.za32.nxv8i16(i32 immarg, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmops_u16(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   call void @llvm.aarch64.sme.umops.za32.nxv8i16(i32 3, <vscale x 8 x i1> %4, <vscale x 8 x i1> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umops.za32.nxv8i16(i32 immarg, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055a12f0dbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a12f0d8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a12f0dc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5a42133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5a4218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5a42133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5a4211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a12f071bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a12f071a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a12f0568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a12ed05e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a12ed05b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5a4211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5a4211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5a4211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a12ed05a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c (433 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdupq_lane_s8(<vscale x 16 x i8> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdupq_lane_s16(<vscale x 8 x i16> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdupq_lane_s32(<vscale x 4 x i32> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdupq_lane_s64(<vscale x 2 x i64> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdupq_lane_u8(<vscale x 16 x i8> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdupq_lane_u16(<vscale x 8 x i16> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdupq_lane_u32(<vscale x 4 x i32> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdupq_lane_u64(<vscale x 2 x i64> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svdupq_lane_f16(<vscale x 8 x half> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 8 x half>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.dupq.lane.nxv8f16(<vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.dupq.lane.nxv8f16(<vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdupq_lane_f32(<vscale x 4 x float> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 4 x float>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.dupq.lane.nxv4f32(<vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.dupq.lane.nxv4f32(<vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svdupq_lane_f64(<vscale x 2 x double> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 2 x double>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.dupq.lane.nxv2f64(<vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.dupq.lane.nxv2f64(<vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdupq_n_s8(i8 noundef %x0, i8 noundef %x1, i8 noundef %x2, i8 noundef %x3, i8 noundef %x4, i8 noundef %x5, i8 noundef %x6, i8 noundef %x7, i8 noundef %x8, i8 noundef %x9, i8 noundef %x10, i8 noundef %x11, i8 noundef %x12, i8 noundef %x13, i8 noundef %x14, i8 noundef %x15) #0 {
# | entry:
# |   %x0.addr = alloca i8, align 1
# |   %x1.addr = alloca i8, align 1
# |   %x2.addr = alloca i8, align 1
# |   %x3.addr = alloca i8, align 1
# |   %x4.addr = alloca i8, align 1
# |   %x5.addr = alloca i8, align 1
# |   %x6.addr = alloca i8, align 1
# |   %x7.addr = alloca i8, align 1
# |   %x8.addr = alloca i8, align 1
# |   %x9.addr = alloca i8, align 1
# |   %x10.addr = alloca i8, align 1
# |   %x11.addr = alloca i8, align 1
# |   %x12.addr = alloca i8, align 1
# |   %x13.addr = alloca i8, align 1
# |   %x14.addr = alloca i8, align 1
# |   %x15.addr = alloca i8, align 1
# |   store i8 %x0, ptr %x0.addr, align 1
# |   store i8 %x1, ptr %x1.addr, align 1
# |   store i8 %x2, ptr %x2.addr, align 1
# |   store i8 %x3, ptr %x3.addr, align 1
# |   store i8 %x4, ptr %x4.addr, align 1
# |   store i8 %x5, ptr %x5.addr, align 1
# |   store i8 %x6, ptr %x6.addr, align 1
# |   store i8 %x7, ptr %x7.addr, align 1
# |   store i8 %x8, ptr %x8.addr, align 1
# |   store i8 %x9, ptr %x9.addr, align 1
# |   store i8 %x10, ptr %x10.addr, align 1
# |   store i8 %x11, ptr %x11.addr, align 1
# |   store i8 %x12, ptr %x12.addr, align 1
# |   store i8 %x13, ptr %x13.addr, align 1
# |   store i8 %x14, ptr %x14.addr, align 1
# |   store i8 %x15, ptr %x15.addr, align 1
# |   %0 = load i8, ptr %x0.addr, align 1
# |   %1 = load i8, ptr %x1.addr, align 1
# |   %2 = load i8, ptr %x2.addr, align 1
# |   %3 = load i8, ptr %x3.addr, align 1
# |   %4 = load i8, ptr %x4.addr, align 1
# |   %5 = load i8, ptr %x5.addr, align 1
# |   %6 = load i8, ptr %x6.addr, align 1
# |   %7 = load i8, ptr %x7.addr, align 1
# |   %8 = load i8, ptr %x8.addr, align 1
# |   %9 = load i8, ptr %x9.addr, align 1
# |   %10 = load i8, ptr %x10.addr, align 1
# |   %11 = load i8, ptr %x11.addr, align 1
# |   %12 = load i8, ptr %x12.addr, align 1
# |   %13 = load i8, ptr
# | ...
# `---data was truncated (10240/42600) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d341f1ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d341f19e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d341f1d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb1b4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb1b478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb1b4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb1b471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d341eb2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d341eb2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d341e978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d341b46e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d341b46b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb1b471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb1b471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb1b471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d341b46a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c (434 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 31)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.cntw(i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_1() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_2() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_3() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_4() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 4)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_5() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 5)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_6() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 6)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_7() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_8() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 8)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_9() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 9)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_10() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 10)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_11() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 11)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_12() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 12)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_13() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 13)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_14() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 29)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_15() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 30)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_16() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 31)
# |   ret i64 %0
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055d1d0840eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d1d083de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d1d084162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8def333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8def38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8def333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8def31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d1d07d6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d1d07d6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d1d07bb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d1d046ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d1d046ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8def31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8def31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8def31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d1d046aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c (435 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svfirstp_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call i64 @llvm.aarch64.sve.firstp.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.firstp.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svfirstp_b16(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.firstp.nxv8i1(<vscale x 8 x i1> %2, <vscale x 8 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.firstp.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svfirstp_b32(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.firstp.nxv4i1(<vscale x 4 x i1> %2, <vscale x 4 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.firstp.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svfirstp_b64(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.firstp.nxv2i1(<vscale x 2 x i1> %2, <vscale x 2 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.firstp.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2p2" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000557703779eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557703776e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055770377a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc114449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc1144a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc114449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc114431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055770370fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055770370fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005577036f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005577033a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005577033a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc114432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc1144330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc1144330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005577033a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c (436 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsll_vv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsll_vx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsll_vv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsll_vx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsll_vv_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsll_vx_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vwsll_vv_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vwsll_vx_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vwsll_vv_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/153813) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560fae897eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560fae894e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560fae89862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f14bf933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f14bf98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f14bf933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f14bf91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560fae82dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560fae82da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560fae8128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560fae4c1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560fae4c1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f14bf91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f14bf91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f14bf91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560fae4c1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c (437 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfadd_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfadd_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfadd_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfadd_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfadd_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfadd_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfadd_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfadd_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.r
# | ...
# `---data was truncated (10240/65582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fcec621eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fcec61ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fcec62262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b90a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b90aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b90a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b90a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fcec5b7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fcec5b7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fcec59c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fcec24be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fcec24bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5b90a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b90a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b90a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fcec24ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c (438 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svset4_s8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %tuple.coerce2, <vscale x 16 x i8> %tuple.coerce3, <vscale x 16 x i8> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %x.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %tuple.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 16 x i8> %x, ptr %x.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %5 = load <vscale x 16 x i8>, ptr %x.addr, align 16
# |   %6 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, <vscale x 16 x i8> %5, 1
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svset4_s16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %tuple.coerce2, <vscale x 8 x i16> %tuple.coerce3, <vscale x 8 x i16> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %x.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %tuple.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 8 x i16> %x, ptr %x.addr, align 16
# |   %4 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %5 = load <vscale x 8 x i16>, ptr %x.addr, align 16
# |   %6 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, <vscale x 8 x i16> %5, 3
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svset4_s32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1, <vscale x 4 x i32> %tuple.coerce2, <vscale x 4 x i32> %tuple.coerce3, <vscale x 4 x i32> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %tuple.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %5 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %6 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, <vscale x 4 x i32> %5, 1
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svset4_s64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1, <vscale x 2 x i64> %tuple.coerce2, <vscale x 2 x i64> %tuple.coerce3, <vscale x 2 x i64> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %x.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, <vscale x 2 x i64> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %tuple.coerce3, 3
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 2 x i64> %x, ptr %x.addr, align 16
# |   %4 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple.addr, align 16
# |   %5 = load <vscale x 2 x i64>, ptr %x.addr, align 16
# |   %6 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, <vscale x 2 x i64> %5, 1
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svset4_u8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %tuple.coerce2, <vscale x 16 x i8> %tuple.coerce3, <vscale x 16 x i8> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %x.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %tuple.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 16 x i8> %x, ptr %x.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %5 = load <vscale x 16 x i8>, ptr %x.addr, align 16
# | ...
# `---data was truncated (10240/34217) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055dc662c5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dc662c2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dc662c662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3fd061bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3fd06725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3fd061ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3fd0603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc6625bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dc6625ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dc662408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dc65eefe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dc65eefb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3fd0604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3fd06050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3fd06050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc65eefa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon-intrinsics.c (439 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vmul_s8(<8 x i8> noundef %v1, <8 x i8> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %v1.addr = alloca <8 x i8>, align 8
# |   %v2.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %v1, ptr %v1.addr, align 8
# |   store <8 x i8> %v2, ptr %v2.addr, align 8
# |   %0 = load <8 x i8>, ptr %v1.addr, align 8
# |   %1 = load <8 x i8>, ptr %v2.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %mul.i = mul <8 x i8> %2, %3
# |   store <8 x i8> %mul.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vmul_s16(<4 x i16> noundef %v1, <4 x i16> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %v1.addr = alloca <4 x i16>, align 8
# |   %v2.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %v1, ptr %v1.addr, align 8
# |   store <4 x i16> %v2, ptr %v2.addr, align 8
# |   %0 = load <4 x i16>, ptr %v1.addr, align 8
# |   %1 = load <4 x i16>, ptr %v2.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %mul.i = mul <4 x i16> %2, %3
# |   store <4 x i16> %mul.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vmul_s32(<2 x i32> noundef %v1, <2 x i32> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %v1.addr = alloca <2 x i32>, align 8
# |   %v2.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %v1, ptr %v1.addr, align 8
# |   store <2 x i32> %v2, ptr %v2.addr, align 8
# |   %0 = load <2 x i32>, ptr %v1.addr, align 8
# |   %1 = load <2 x i32>, ptr %v2.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %mul.i = mul <2 x i32> %2, %3
# |   store <2 x i32> %mul.i, ptr %__ret.i, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vmul_f32(<2 x float> noundef %v1, <2 x float> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %v1.addr = alloca <2 x float>, align 8
# |   %v2.addr = alloca <2 x float>, align 8
# |   store <2 x float> %v1, ptr %v1.addr, align 8
# |   store <2 x float> %v2, ptr %v2.addr, align 8
# |   %0 = load <2 x float>, ptr %v1.addr, align 8
# |   %1 = load <2 x float>, ptr %v2.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %mul.i = fmul <2 x float> %2, %3
# |   store <2 x float> %mul.i, ptr %__ret.i, align 8
# |   %4 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vmul_u8(<8 x i8> noundef %v1, <8 x i8> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %v1.addr = alloca <8 x i8>, align 8
# |   %v2.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %v1, ptr %v1.addr, align 8
# |   store <8 x i8> %v2, ptr %v2.addr, align 8
# |   %0 = load <8 x i8>, ptr %v1.addr, align 8
# |   %1 = load <8 x i8>, ptr %v2.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %mul.i = mul <8 x i8> %2, %3
# |   store <8 x i8> %mul.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vmul_u16(<4 x i16> noundef %v1, <4 x i16> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %v1.addr = alloca <4 x i16>, align 8
# |   %v2.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %v1, ptr %v1.addr, align 8
# |   store <4 x i16> %v2, ptr %v2.addr, align 8
# |   %0 = load <4 x i16>, ptr %v1.addr, align 8
# |   %1 = load <4 x i16>, ptr %v2.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %mul.i = mul <4 x i16> %2, %3
# |   store <4 x i16> %mul.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vmul_u32(<2 x i32> noundef %v1, <2 x i32> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %v1.addr = alloca <2 x i32>, align 8
# |   %v2.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %v1, ptr %v1.addr, align 8
# |   store <2 x i32> %v2, ptr %v2.addr, align 8
# |   %0 = load <2 x i32>, ptr %v1.addr, align 8
# |   %1 = load <2 x i32>, ptr %v2.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %mul.i = mul <2 x i32> %2, %3
# |   store <2 x i32> %mul.i, ptr %__ret.i, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vmulq_s8(<16 x i8> noundef %v1, <16 x i8> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %v1.addr = alloca <16 x i8>, align 16
# |   %v2.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v1, ptr %v1.addr, align 16
# |   store <16 x i8> %v2, ptr %v2.addr, align 16
# |   %0 = load <16 x i8>, ptr %v1.addr, align 16
# |   %1 = load <16 x i8>, ptr %v2.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %mul.i = mul <16 x i8> %2, %3
# |   store <16 x i8> %mul.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vmulq_s16(<8 x i16> noundef %v1, <8 x i16> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %v1.addr = alloca <8 x i16>, align 16
# |   %v2.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %v1, ptr %v1.addr, align 16
# |   store <8 x i16> %v2, ptr %v2.addr, align 16
# |   %0 = load <8 x i16>, ptr %v1.addr, align 16
# |   %1 = load <8 x i16>, ptr %v2.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %3 = load <8 x i16>, ptr %__p1.addr.i, align 16
# |   %mul.i = mul <8 x i16> %2, %3
# |   store <8 x i16> %mul.i, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmulq_s32(<4 x i32> noundef %v1, <4 x i32> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %v1.addr = alloca <4 x i32>, align 16
# |   %v2.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %v1, ptr %v1.addr, align 16
# |   store <4 x i32> %v2, ptr %v2.addr, align 16
# |   %0 = load <4 x i32>, ptr %v1.addr, align 16
# |   %1 = load <4 x i32>, ptr %v2.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <4 x i32> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %3 = load <4 x i32>, ptr %__p1.addr.i, align 16
# |   %mul.i = mul <4 x i32> %2, %3
# |   store <4 x i32> %mul.i, ptr %__ret.i, align 16
# |   %4 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vmulq_u8(<16 x i8> noundef %v1, <16 x i8> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %v1.addr = alloca <16 x i8>, align 16
# |   %v2.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v1, ptr %v1.addr, align 16
# |   store <16 x i8> %v2, ptr %v2.addr, align 16
# |   %0 = load <16 x i8>, ptr %v1.addr, align 16
# |   %1 = load <16 x i8>, ptr %v2.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %mul.i = mul <16 x i8> %2, %3
# |   store <16 x i8> %mul.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vmulq_u16(<8 x i16> noundef %v1, <8 x i16> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %v1.addr = alloca <8 x i16>, align 16
# |   %v2.addr = alloca <8 x i16>, align 16
# |   s
# | ...
# `---data was truncated (10240/798827) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055721f4f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055721f4f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055721f4f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff776733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff77678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff776733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff77671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055721f48abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055721f48aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055721f46f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055721f11ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055721f11eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff77671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff77671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff77671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055721f11ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c (440 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_f16m1x2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_f16m2x2(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei32_v_f16m4x2(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_f32m1x2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_f32m2x2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple
# | ...
# `---data was truncated (10240/108848) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a4d0c5deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a4d0c5ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a4d0c5e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff790c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff790ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff790c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff790c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a4d0bf3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a4d0bf3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a4d0bd88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a4d0887e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a4d0887b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff790c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff790c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff790c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a4d0887a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c (441 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +f8f16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +f8f16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_f16mf8(<vscale x 8 x half> %acc, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i64 noundef %fpmr) #0 {
# | entry:
# |   %acc.addr = alloca <vscale x 8 x half>, align 16
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %acc, ptr %acc.addr, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %acc.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %3 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmmla.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmmla.nxv8f16(<vscale x 8 x half>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f8f16mm,+sve,+sve2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000562457682eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056245767fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056245768362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa3ada49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa3adaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa3ada49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa3ada31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562457618bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562457618a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005624575fd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005624572ace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005624572acb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa3ada32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa3ada330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa3ada330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005624572aca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c (442 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16m1x2(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16m2x2(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16m4x2(ptr noundef %base, <vscale x 16 x i32> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f32m1x2(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f32m2x2(ptr noundef %base, <vscale x 4 x i32
# | ...
# `---data was truncated (10240/123655) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563256312eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056325630fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056325631362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f94f3905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f94f395c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f94f3905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f94f38ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005632562a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005632562a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056325628d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563255f3ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563255f3cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f94f38eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f94f38ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f94f38ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563255f3ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c (443 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +sme -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +sme -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svreadz_hor_za8_s8_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.readz.horiz.x2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.readz.horiz.x2.nxv16i8(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svreadz_hor_za8_u8_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.readz.horiz.x2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svreadz_hor_za8_mf8_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.readz.horiz.x2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svreadz_hor_za16_s16_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.readz.horiz.x2.nxv8i16(i32 0, i32 %0)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.readz.horiz.x2.nxv8i16(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svreadz_hor_za16_u16_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.readz.horiz.x2.nxv8i16(i32 1, i32 %0)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svreadz_hor_za16_f16_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.readz.horiz.x2.nxv8f16(i32 0, i32 %0)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.readz.horiz.x2.nxv8f16(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svreadz_hor_za16_bf16_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.readz.horiz.x2.nxv8bf16(i32 1, i32 %0)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.readz.horiz.x2.nxv8bf16(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svreadz_hor_za32_s32_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.readz.horiz.x2.nxv4i32(i32 0, i32 %0)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.readz.horiz.x2.nxv4i32(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svreadz_hor_za32_u32_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.readz.horiz.x2.nxv4i32(i32 2, i32 %0)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svreadz_hor_za32_f32_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.readz.horiz.x2.nxv4f32(i32 3, i32 %0)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.readz.horiz.x2.nxv4f32(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svreadz_hor_za64_s64_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sme.readz.horiz.x2.nxv2i64(i32 0, i32 %0)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sme.readz.horiz.x2.nxv2i64(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svreadz_hor_za64_u64_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sme.readz.horiz.x2.nxv2i64(i32 4, i32 %0)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double> } @test_svreadz_hor_za64_f64_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sme.readz.horiz.x2.nxv2f64(i32 7, i32 %0)
# |   ret { <vscale x 2 x double>, <vscale x 2 x double> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sme.readz.horiz.x2.nxv2f64(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svreadz_ver_za8_s8_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.readz.vert.x2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.readz.vert.x2.nxv16i8(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svreadz_ver_za8_u8_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.readz.vert.x2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svreadz_ver_za8_mf8_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.readz.vert.x2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svreadz_ver_za16_s16_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.readz.vert.x2.nxv8i16(i32 0, i32 %0)
# |   ret { <vscale x 8 x i16>, <vscale x
# | ...
# `---data was truncated (10240/66009) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055a21b3f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a21b3eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a21b3f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f06af049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f06af0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f06af049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f06af031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a21b387bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a21b387a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a21b36c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a21b01be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a21b01bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f06af032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f06af0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f06af0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a21b01ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c (444 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsub_vv_i8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsub_vx_i8mf8(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsub_vv_i8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsub_vx_i8mf4(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsub_vv_i8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsub_vx_i8mf2(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsub_vv_i8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsub_vx_i8m1(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnmsub_vv_i8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x
# | ...
# `---data was truncated (10240/208199) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564256937eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564256934e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056425693862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc4ff133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc4ff18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc4ff133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc4ff11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005642568cdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005642568cda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005642568b28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564256561e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564256561b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc4ff11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc4ff11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc4ff11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564256561a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c (445 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmplt_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpgt.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %2, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpgt.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmplt_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpgt.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %2, <vscale x 8 x i16> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpgt.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmplt_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpgt.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %2, <vscale x 4 x i32> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpgt.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmplt_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpgt.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %2, <vscale x 2 x i64> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpgt.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmplt_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmphi.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %2, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmphi.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmplt_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmphi.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %2, <vscale x 8 x i16> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmphi.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmplt_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmphi.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %2, <vscale x 4 x i32> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmphi.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmplt_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr,
# | ...
# `---data was truncated (10240/41923) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ade2e74eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ade2e71e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ade2e7562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3bf7533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3bf758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3bf7533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3bf751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ade2e0abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ade2e0aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ade2def8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ade2a9ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ade2a9eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3bf751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3bf751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3bf751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ade2a9ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c (446 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svbfmlalt_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalt(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlalt(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlalt_lane_0_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalt.lane.v2(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 0)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlalt.lane.v2(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlalt_lane_7_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalt.lane.v2(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 7)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlalt_n_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, bfloat noundef %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca bfloat, align 2
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store bfloat %z, ptr %z.addr, align 2
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load bfloat, ptr %z.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalt(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005619b57ddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005619b57dae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005619b57de62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa162333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa16238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa162333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa16231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005619b5773bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005619b5773a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005619b57588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005619b5407e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005619b5407b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa16231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa16231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa16231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005619b5407a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c (447 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtmad_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.ftmad.x.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 0)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ftmad.x.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtmad_f16_1(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.ftmad.x.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 7)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtmad_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.ftmad.x.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 0)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ftmad.x.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtmad_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.ftmad.x.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i32 0)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ftmad.x.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056403c8a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056403c8a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056403c8a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8116533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f811658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8116533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f811651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056403c83dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056403c83da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056403c8228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056403c4d1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056403c4d1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f811651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f811651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f811651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056403c4d1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c (448 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f16m1x2(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f16m2x2(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f32m1x2(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f32m2x2(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f32m4x2(ptr noundef %base, <vscale x 8 x i64
# | ...
# `---data was truncated (10240/110129) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cd61adceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cd61ad9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cd61add62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f04b6a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f04b6aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f04b6a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f04b6a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cd61a72bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cd61a72a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cd61a578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cd61706e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cd61706b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f04b6a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f04b6a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f04b6a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cd61706a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c (449 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla2_f16(i32 noundef %slice_base, <vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1, <vscale x 8 x half> %zm.coerce0, <vscale x 8 x half> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zm.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %5, 1
# |   %8 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %8, 1
# |   call void @llvm.aarch64.sme.fmlal.vg2x2.nxv8f16(i32 %4, <vscale x 8 x half> %6, <vscale x 8 x half> %7, <vscale x 8 x half> %9, <vscale x 8 x half> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmlal.vg2x2.nxv8f16(i32, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla2_bf16(i32 noundef %slice_base, <vscale x 8 x bfloat> %zn.coerce0, <vscale x 8 x bfloat> %zn.coerce1, <vscale x 8 x bfloat> %zm.coerce0, <vscale x 8 x bfloat> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zm.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %5, 1
# |   %8 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %8, 1
# |   call void @llvm.aarch64.sme.fmlal.vg2x2.nxv8bf16(i32 %4, <vscale x 8 x bfloat> %6, <vscale x 8 x bfloat> %7, <vscale x 8 x bfloat> %9, <vscale x 8 x bfloat> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmlal.vg2x2.nxv8bf16(i32, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla2_u16(i32 noundef %slice_base, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zm.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 1
# |   %8 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 1
# |   call void @llvm.aarch64.sme.umlal.vg2x2.nxv8i16(i32 %4, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %9, <vscale x 8 x i16> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umlal.vg2x2.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla2_s16(i32 noundef %slice_base, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zm.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 1
# |   %8 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 1
# |   call void @llvm.aarch64.sme.smlal.vg2x2.nxv8i16(i32 %4, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %9, <vscale x 8 x i16> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smlal.vg2x2.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla4
# | ...
# `---data was truncated (10240/73614) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055e20be57eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e20be54e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e20be5862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f54a2d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54a2d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f54a2d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f54a2d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e20bdedbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e20bdeda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e20bdd28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e20ba81e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e20ba81b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f54a2d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54a2d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54a2d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e20ba81a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c (450 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmin_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmin_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmin_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmin_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmin_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmin_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmin_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmin_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmin_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/222475) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005572fa014eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005572fa011e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005572fa01562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f458c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f458c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f458c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f458c51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005572f9faabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005572f9faaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005572f9f8f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005572f9c3ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005572f9c3eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f458c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f458c51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f458c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005572f9c3ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c (451 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsrl_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsrl_vx_u8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsrl_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsrl_vx_u8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsrl_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsrl_vx_u8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsrl_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsrl_vx_u8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsrl_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsrl_vx_u8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsrl_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>
# | ...
# `---data was truncated (10240/98343) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005591cd7beeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005591cd7bbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005591cd7bf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8bac649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8bac6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8bac649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8bac631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005591cd754bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005591cd754a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005591cd7398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005591cd3e8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005591cd3e8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8bac632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8bac6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8bac6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005591cd3e8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c (452 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlastp_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call i64 @llvm.aarch64.sve.lastp.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.lastp.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlastp_b16(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.lastp.nxv8i1(<vscale x 8 x i1> %2, <vscale x 8 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.lastp.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlastp_b32(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.lastp.nxv4i1(<vscale x 4 x i1> %2, <vscale x 4 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.lastp.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlastp_b64(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.lastp.nxv2i1(<vscale x 2 x i1> %2, <vscale x 2 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.lastp.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2p2" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e221f3eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e221f3be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e221f3f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa47f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa47f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa47f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa47f631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e221ed4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e221ed4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e221eb98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e221b68e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e221b68b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa47f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa47f6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa47f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e221b68a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c (453 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b29b1f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b29b1eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b29b1f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f048a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f048a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f048a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f048a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b29b187bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b29b187a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b29b16c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b29ae1be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b29ae1bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f048a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f048a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f048a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b29ae1ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c (454 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcompact_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.compact.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.compact.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcompact_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.compact.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.compact.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcompact_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.compact.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcompact_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.compact.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcompact_mf8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.compact.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcompact_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.compact.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.compact.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcompact_bf16(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.compact.nxv8bf16(<vscale x 8 x i1> %2, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.compact.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2p2" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000558b0c3f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558b0c3f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558b0c3f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7b51649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7b516a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7b51649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7b51631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558b0c38ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558b0c38ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558b0c3738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558b0c022e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558b0c022b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7b51632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7b516330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7b516330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558b0c022a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c (455 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f16m1x5(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f32m1x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f64m1x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558c0f509eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558c0f506e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558c0f50a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0b67a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0b67aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0b67a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0b67a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c0f49fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558c0f49fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558c0f4848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558c0f133e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558c0f133b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0b67a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0b67a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0b67a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c0f133a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/bf16-dotprod-intrinsics.c (456 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/bf16-dotprod-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +bf16  -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +bf16 -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vbfdot_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x bfloat>, align 8
# |   %__p2.addr.i = alloca <4 x bfloat>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   %b.addr = alloca <4 x bfloat>, align 8
# |   store <2 x float> %r, ptr %r.addr, align 8
# |   store <4 x bfloat> %a, ptr %a.addr, align 8
# |   store <4 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %r.addr, align 8
# |   %1 = load <4 x bfloat>, ptr %a.addr, align 8
# |   %2 = load <4 x bfloat>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__p1.addr.i, align 8
# |   store <4 x bfloat> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vbfdot.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vbfdot1.i = bitcast <8 x i8> %4 to <4 x bfloat>
# |   %vbfdot2.i = bitcast <8 x i8> %5 to <4 x bfloat>
# |   %vbfdot3.i = call <2 x float> @llvm.aarch64.neon.bfdot.v2f32.v4bf16(<2 x float> %vbfdot.i, <4 x bfloat> %vbfdot1.i, <4 x bfloat> %vbfdot2.i)
# |   store <2 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vbfdotq_f32(<4 x float> noundef %r, <8 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <8 x bfloat>, align 16
# |   %__p2.addr.i = alloca <8 x bfloat>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %r.addr = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x bfloat>, align 16
# |   %b.addr = alloca <8 x bfloat>, align 16
# |   store <4 x float> %r, ptr %r.addr, align 16
# |   store <8 x bfloat> %a, ptr %a.addr, align 16
# |   store <8 x bfloat> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %r.addr, align 16
# |   %1 = load <8 x bfloat>, ptr %a.addr, align 16
# |   %2 = load <8 x bfloat>, ptr %b.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__p1.addr.i, align 16
# |   store <8 x bfloat> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vbfdot.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vbfdot1.i = bitcast <16 x i8> %4 to <8 x bfloat>
# |   %vbfdot2.i = bitcast <16 x i8> %5 to <8 x bfloat>
# |   %vbfdot3.i = call <4 x float> @llvm.aarch64.neon.bfdot.v4f32.v8bf16(<4 x float> %vbfdot.i, <8 x bfloat> %vbfdot1.i, <8 x bfloat> %vbfdot2.i)
# |   store <4 x float> %vbfdot3.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vbfdot_lane_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x bfloat>, align 8
# |   %__p2.addr.i = alloca <4 x bfloat>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   %b.addr = alloca <4 x bfloat>, align 8
# |   %__ret_810 = alloca <2 x float>, align 8
# |   %__s0_810 = alloca <2 x float>, align 8
# |   %__s1_810 = alloca <4 x bfloat>, align 8
# |   %__s2_810 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca <2 x float>, align 8
# |   %__ret = alloca <2 x float>, align 8
# |   %__s0 = alloca <2 x float>, align 8
# |   %ref.tmp1 = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x float>, align 8
# |   %tmp2 = alloca <2 x float>, align 8
# |   store <2 x float> %r, ptr %r.addr, align 8
# |   store <4 x bfloat> %a, ptr %a.addr, align 8
# |   store <4 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %r.addr, align 8
# |   store <2 x float> %0, ptr %__s0_810, align 8
# |   %1 = load <4 x bfloat>, ptr %a.addr, align 8
# |   store <4 x bfloat> %1, ptr %__s1_810, align 8
# |   %2 = load <4 x bfloat>, ptr %b.addr, align 8
# |   store <4 x bfloat> %2, ptr %__s2_810, align 8
# |   %3 = load <2 x float>, ptr %__s0_810, align 8
# |   %4 = load <4 x bfloat>, ptr %__s1_810, align 8
# |   %5 = load <2 x float>, ptr %__s2_810, align 8
# |   store <2 x float> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x float>
# |   %lane = shufflevector <2 x float> %7, <2 x float> %7, <2 x i32> zeroinitializer
# |   store <2 x float> %lane, ptr %ref.tmp1, align 8
# |   %8 = load <2 x float>, ptr %ref.tmp1, align 8
# |   store <2 x float> %8, ptr %__ret, align 8
# |   %9 = load <2 x float>, ptr %__ret, align 8
# |   store <2 x float> %9, ptr %tmp, align 8
# |   %10 = load <2 x float>, ptr %tmp, align 8
# |   store <2 x float> %10, ptr %ref.tmp, align 8
# |   %11 = load <4 x bfloat>, ptr %ref.tmp, align 8
# |   store <2 x float> %3, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %4, ptr %__p1.addr.i, align 8
# |   store <4 x bfloat> %11, ptr %__p2.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %14 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vbfdot.i = bitcast <8 x i8> %12 to <2 x float>
# |   %vbfdot1.i = bitcast <8 x i8> %13 to <4 x bfloat>
# |   %vbfdot2.i = bitcast <8 x i8> %14 to <4 x bfloat>
# |   %vbfdot3.i = call <2 x float> @llvm.aarch64.neon.bfdot.v2f32.v4bf16(<2 x float> %vbfdot.i, <4 x bfloat> %vbfdot1.i, <4 x bfloat> %vbfdot2.i)
# |   store <2 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8
# |   %15 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %15, ptr %__ret.i, align 8
# |   %16 = load <2 x float>, ptr %__ret.i, align 8
# |   store <2 x float> %16, ptr %__ret_810, align 8
# |   %17 = load <2 x float>, ptr %__ret_810, align 8
# |   store <2 x float> %17, ptr %tmp2, align 8
# |   %18 = load <2 x float>, ptr %tmp2, align 8
# |   ret <2 x float> %18
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vbfdotq_laneq_f32(<4 x float> noundef %r, <8 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <8 x bfloat>, align 16
# |   %__p2.addr.i = alloca <8 x bfloat>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %r.addr = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x bfloat>, align 16
# |   %b.addr = alloca <8 x bfloat>, align 16
# |   %__ret_812 = alloca <4 x float>, align 16
# |   %__s0_812 = alloca <4 x float>, align 16
# |   %__s1_812 = alloca <8 x bfloat>, align 16
# |   %__s2_812 = alloca <8 x bfloat>, align 16
# |   %ref.tmp = alloca <4 x float>, align 16
# |   %__ret = alloca <4 x float>, align 16
# |   %__s0 = alloca <4 x float>, align 16
# |   %ref.tmp1 = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x float>, align 16
# |   %tmp2 = alloca <4 x float>, align 16
# |   store <4 x float> %r, ptr %r.addr, align 16
# |   store <8 x bfloat> %a, ptr %a.addr, align 16
# |   store <8 x bfloat> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %r.addr, align 16
# |   store <4 x float> %0, ptr %__s0_812, align 16
# |   %1 = load <8 x bfloat>, ptr %a.addr, align 16
# |   store <8 x bfloat> %1, ptr %__s1_812, align 16
# |   %2 = load <8 x bfloat>, ptr %b.addr, align 16
# |   store <8 x bfloat> %2, ptr %__s2_812, align 16
# |   %3 = load <4 x float>, ptr %__s0_812, align 16
# |   %4 = load <8 x bfloat>, ptr %__s1_812, align 16
# |   %5 = load <4 x float>, ptr %__s2_812, align 16
# |   store <4 x float> %5, ptr %__s0, align 16
# |   %6 = load <16 x i8>, ptr %__s0, align 16
# |   %7 = bitcast <16 x i8> %6 to <4 x float>
# |   %lane = shufflevector <4 x float> %7, <4 x float> %7, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
# |   store <4 x float> %lane, ptr %ref.tmp1, align 16
# |   %8 = load <4 x float>, ptr %ref.tmp1, align 16
# |   store <4 x float> %8, ptr %__ret, align 16
# |   %9 = load <4 x float>, ptr %__ret, align 16
# |   store <4 x float> %9, ptr %tmp, align 16
# |   %10 = load <4 x float>, ptr %tmp, align 16
# |   store <4 x float> %10, ptr %ref.tmp, align 16
# |   %11 = load <8 x bfloat>, ptr %ref.tmp, align 16
# |   store <4 x float> %3, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %4, ptr %__p1.addr.i, align 16
# |   store <8 x bfloat> %11, ptr %__p2.addr.i, align 16
# |   %12 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %13 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %14 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vbfdot.i = bitcast <16 x i8> %12 to <4 x float>
# |   %vbfdot1.i = bitcast <16 x i8> %13 to <8 x bfloat>
# |   %vbfdot2.i = bitcast <16 x i8> %14 to <8 x bfloat>
# |   %vbfdot3.i = call <4 x float> @llvm.aarch64.neon.bfdot.v4f32.v8bf16(<4 x float> %vbfdot.i, <8 x bfloat> %vbfdot1.i, <8 x bfloat> %vbfdot2.i)
# |   store <4 x float> %vbfdot3.i, ptr %ref.tmp.i, align 16
# |   %15 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %15, ptr %__ret.i, align 16
# |   %16 = load <4 x float>, ptr %__ret.i, align 16
# |   store <4 x float> %16, ptr %__ret_812, align 16
# |   %17 = load <4 x float>, ptr %__ret_812, align 16
# |   store <4 x float> %17, ptr %tmp2, align 16
# |   %18 = load <4 x float>, ptr %tmp2, align 16
# |   ret <4 x float> %18
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vbfdot_laneq_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x bfloat>, align 8
# |   %__p2.addr.i = alloca <4 x bfloat>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x float>,
# | ...
# `---data was truncated (10240/54685) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005636fad45eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005636fad42e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005636fad4662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd498f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd498f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd498f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd498f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005636facdbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005636facdba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005636facc08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005636fa96fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005636fa96fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd498f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd498f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd498f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005636fa96fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c (457 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrinta_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frinta.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frinta.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrinta_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frinta.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frinta.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrinta_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frinta.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frinta.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrinta_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.frinta.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrinta_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frinta.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrinta_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frinta.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrinta_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frinta.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrinta_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frinta.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrinta_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frinta.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000559768116eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559768113e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055976811762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc36c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc36c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc36c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc36c231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005597680acbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005597680aca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005597680918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559767d40e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559767d40b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc36c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc36c2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc36c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559767d40a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c (458 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 31)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.cntb(i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_1() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_2() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_3() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_4() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 4)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_5() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 5)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_6() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 6)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_7() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_8() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 8)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_9() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 9)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_10() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 10)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_11() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 11)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_12() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 12)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_13() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 13)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_14() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 29)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_15() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 30)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_16() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 31)
# |   ret i64 %0
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x00005642f1445eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005642f1442e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005642f144662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f89f2d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f89f2d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f89f2d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f89f2d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005642f13dbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005642f13dba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005642f13c08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005642f106fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005642f106fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f89f2d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f89f2d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f89f2d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005642f106fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c (459 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1>, ptr, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_1(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_2(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_3(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_4(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_5(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_6(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 8)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_7(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 9)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 10)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_9(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 11)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_10(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 12)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_11(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 13)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_vnum(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i32>, ptr %1, i64 %2
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %3, ptr %4, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_gather_u32base(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prfw.gather.scalar.offset.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1, i64 0, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.aarch64.sve.prfw.gather.scalar.offset.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64, i32 immarg) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_gather_u64base(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store 
# | ...
# `---data was truncated (10240/17826) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560002f2aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560002f27e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560002f2b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f24c3133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f24c318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f24c3133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f24c311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560002ec0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560002ec0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560002ea58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560002b54e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560002b54b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f24c311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f24c311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f24c311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560002b54a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c (460 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpnext_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.pnext.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.pnext.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpnext_b16(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.pnext.nxv8i1(<vscale x 8 x i1> %2, <vscale x 8 x i1> %3)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.pnext.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpnext_b32(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.pnext.nxv4i1(<vscale x 4 x i1> %2, <vscale x 4 x i1> %3)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.pnext.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpnext_b64(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.pnext.nxv2i1(<vscale x 2 x i1> %2, <vscale x 2 x i1> %3)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.pnext.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000564d3b852eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564d3b84fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564d3b85362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f73ad849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f73ad8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f73ad849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f73ad831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d3b7e8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564d3b7e8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564d3b7cd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564d3b47ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564d3b47cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f73ad832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73ad8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73ad8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d3b47ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c (461 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svmul_single_f16_x2(<vscale x 8 x half> %zdn.coerce0, <vscale x 8 x half> %zdn.coerce1, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zdn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 1
# |   %5 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmul.single.x2.nxv8f16(<vscale x 8 x half> %3, <vscale x 8 x half> %4, <vscale x 8 x half> %5)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmul.single.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svmul_single_f16_x4(<vscale x 8 x half> %zdn.coerce0, <vscale x 8 x half> %zdn.coerce1, <vscale x 8 x half> %zdn.coerce2, <vscale x 8 x half> %zdn.coerce3, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %1, <vscale x 8 x half> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zdn.coerce3, 3
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, 1
# |   %7 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, 2
# |   %8 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, 3
# |   %9 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %10 = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmul.single.x4.nxv8f16(<vscale x 8 x half> %5, <vscale x 8 x half> %6, <vscale x 8 x half> %7, <vscale x 8 x half> %8, <vscale x 8 x half> %9)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmul.single.x4.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svmul_f16_x2(<vscale x 8 x half> %zdn.coerce0, <vscale x 8 x half> %zdn.coerce1, <vscale x 8 x half> %zm.coerce0, <vscale x 8 x half> %zm.coerce1) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zdn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn, align 16
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zm.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zdn1, ptr %zdn.addr, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %4, 1
# |   %7 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %7, 0
# |   %9 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %7, 1
# |   %10 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmul.x2.nxv8f16(<vscale x 8 x half> %5, <vscale x 8 x half> %6, <vscale x 8 x half> %8, <vscale x 8 x half> %9)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmul.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svmul_f16_x4(<vscale x 8 x half> %zdn.coerce0, <vscale x 8 x half> %zdn.coerce1, <vscale x 8 x half> %zdn.coerce2, <vscale x 8 x half> %zdn.coerce3, <vscale x 8 x half> %zm.coerce0, <vscale x 8 x half> %zm.coerce1, <vscale x 8 x half> %zm.coerce2, <vscale x 8 x half> %zm.coerce3) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %1, <vscale x 8 x half> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zdn.coerce3, 3
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn, align 16
# |   %4 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zm.coerce0, 0
# |   %5 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, <vscale x 8 x half> %zm.coerce1, 1
# |   %6 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %5, <vscale x 8 x half> %zm.coerce2, 2
# |   %7 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %6, <vscale x 8 x half> %zm.coerce3, 3
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %7, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %zdn1, ptr %zdn.addr, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x
# | ...
# `---data was truncated (10240/37760) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055591a6a9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055591a6a6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055591a6aa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc88641bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc8864725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc88641ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc886403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055591a63fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055591a63fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055591a6248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055591a2d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055591a2d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc886404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc8864050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc8864050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055591a2d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c (462 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhsu_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhsu_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmulhsu_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 
# | ...
# `---data was truncated (10240/98445) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d088745eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d088742e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d08874662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1a9d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1a9d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1a9d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1a9d031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0886dbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d0886dba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d0886c08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d08836fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d08836fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1a9d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1a9d0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1a9d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d08836fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c (463 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmacc_vv_i8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmacc_vx_i8mf8(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmacc_vv_i8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmacc_vx_i8mf4(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmacc_vv_i8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmacc_vx_i8mf2(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmacc_vv_i8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmacc_vx_i8m1(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmacc_vv_i8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |  
# | ...
# `---data was truncated (10240/207749) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005614f7da9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005614f7da6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005614f7daa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c84e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c84ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c84e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c84e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005614f7d3fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005614f7d3fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005614f7d248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005614f79d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005614f79d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1c84e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c84e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c84e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005614f79d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/builtins-arm-exclusive.c (464 of 27911)
******************** TEST 'Clang :: CodeGen/builtins-arm-exclusive.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Werror -triple thumbv8-linux-gnueabi -fno-signed-char -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Werror -triple thumbv8-linux-gnueabi -fno-signed-char -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8-unknown-linux-gnueabi"
# | 
# | %struct.Simple = type { i8, i8 }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ldrex(ptr noundef %addr, ptr noundef %addr64, ptr noundef %addrfloat) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   %addr64.addr = alloca ptr, align 4
# |   %addrfloat.addr = alloca ptr, align 4
# |   %sum = alloca i32, align 4
# |   store ptr %addr, ptr %addr.addr, align 4
# |   store ptr %addr64, ptr %addr64.addr, align 4
# |   store ptr %addrfloat, ptr %addrfloat.addr, align 4
# |   store i32 0, ptr %sum, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %ldrex = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i8) %0)
# |   %1 = trunc i32 %ldrex to i8
# |   %conv = zext i8 %1 to i32
# |   %2 = load i32, ptr %sum, align 4
# |   %add = add nsw i32 %2, %conv
# |   store i32 %add, ptr %sum, align 4
# |   %3 = load ptr, ptr %addr.addr, align 4
# |   %ldrex1 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i16) %3)
# |   %4 = trunc i32 %ldrex1 to i16
# |   %conv2 = sext i16 %4 to i32
# |   %5 = load i32, ptr %sum, align 4
# |   %add3 = add nsw i32 %5, %conv2
# |   store i32 %add3, ptr %sum, align 4
# |   %6 = load ptr, ptr %addr.addr, align 4
# |   %ldrex4 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %6)
# |   %7 = load i32, ptr %sum, align 4
# |   %add5 = add nsw i32 %7, %ldrex4
# |   store i32 %add5, ptr %sum, align 4
# |   %8 = load ptr, ptr %addr.addr, align 4
# |   %ldrexd = call { i32, i32 } @llvm.arm.ldrexd(ptr %8)
# |   %9 = extractvalue { i32, i32 } %ldrexd, 1
# |   %10 = extractvalue { i32, i32 } %ldrexd, 0
# |   %11 = zext i32 %9 to i64
# |   %12 = zext i32 %10 to i64
# |   %shl = shl nuw i64 %11, 32
# |   %13 = or i64 %shl, %12
# |   %14 = load i32, ptr %sum, align 4
# |   %conv6 = sext i32 %14 to i64
# |   %add7 = add nsw i64 %conv6, %13
# |   %conv8 = trunc i64 %add7 to i32
# |   store i32 %conv8, ptr %sum, align 4
# |   %15 = load ptr, ptr %addr64.addr, align 4
# |   %ldrexd9 = call { i32, i32 } @llvm.arm.ldrexd(ptr %15)
# |   %16 = extractvalue { i32, i32 } %ldrexd9, 1
# |   %17 = extractvalue { i32, i32 } %ldrexd9, 0
# |   %18 = zext i32 %16 to i64
# |   %19 = zext i32 %17 to i64
# |   %shl10 = shl nuw i64 %18, 32
# |   %20 = or i64 %shl10, %19
# |   %21 = load i32, ptr %sum, align 4
# |   %conv11 = sext i32 %21 to i64
# |   %add12 = add nsw i64 %conv11, %20
# |   %conv13 = trunc i64 %add12 to i32
# |   store i32 %conv13, ptr %sum, align 4
# |   %22 = load ptr, ptr %addrfloat.addr, align 4
# |   %ldrex14 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %22)
# |   %23 = bitcast i32 %ldrex14 to float
# |   %24 = load i32, ptr %sum, align 4
# |   %conv15 = sitofp i32 %24 to float
# |   %add16 = fadd float %conv15, %23
# |   %conv17 = fptosi float %add16 to i32
# |   store i32 %conv17, ptr %sum, align 4
# |   %25 = load ptr, ptr %addr.addr, align 4
# |   %ldrexd18 = call { i32, i32 } @llvm.arm.ldrexd(ptr %25)
# |   %26 = extractvalue { i32, i32 } %ldrexd18, 1
# |   %27 = extractvalue { i32, i32 } %ldrexd18, 0
# |   %28 = zext i32 %26 to i64
# |   %29 = zext i32 %27 to i64
# |   %shl19 = shl nuw i64 %28, 32
# |   %30 = or i64 %shl19, %29
# |   %31 = bitcast i64 %30 to double
# |   %32 = load i32, ptr %sum, align 4
# |   %conv20 = sitofp i32 %32 to double
# |   %add21 = fadd double %conv20, %31
# |   %conv22 = fptosi double %add21 to i32
# |   store i32 %conv22, ptr %sum, align 4
# |   %33 = load ptr, ptr %addr.addr, align 4
# |   %ldrex23 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %33)
# |   %34 = inttoptr i32 %ldrex23 to ptr
# |   %35 = load i32, ptr %34, align 4
# |   %36 = load i32, ptr %sum, align 4
# |   %add24 = add nsw i32 %36, %35
# |   store i32 %add24, ptr %sum, align 4
# |   %37 = load ptr, ptr %addr.addr, align 4
# |   %ldrex25 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %37)
# |   %38 = inttoptr i32 %ldrex25 to ptr
# |   %a = getelementptr inbounds nuw %struct.Simple, ptr %38, i32 0, i32 0
# |   %39 = load i8, ptr %a, align 1
# |   %conv26 = zext i8 %39 to i32
# |   %40 = load i32, ptr %sum, align 4
# |   %add27 = add nsw i32 %40, %conv26
# |   store i32 %add27, ptr %sum, align 4
# |   %41 = load i32, ptr %sum, align 4
# |   ret i32 %41
# | }
# | 
# | ; Function Attrs: nounwind
# | declare i32 @llvm.arm.ldrex.p0(ptr) #1
# | 
# | ; Function Attrs: nounwind
# | declare { i32, i32 } @llvm.arm.ldrexd(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ldaex(ptr noundef %addr, ptr noundef %addr64, ptr noundef %addrfloat) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   %addr64.addr = alloca ptr, align 4
# |   %addrfloat.addr = alloca ptr, align 4
# |   %sum = alloca i32, align 4
# |   store ptr %addr, ptr %addr.addr, align 4
# |   store ptr %addr64, ptr %addr64.addr, align 4
# |   store ptr %addrfloat, ptr %addrfloat.addr, align 4
# |   store i32 0, ptr %sum, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %ldrex = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i8) %0)
# |   %1 = trunc i32 %ldrex to i8
# |   %conv = zext i8 %1 to i32
# |   %2 = load i32, ptr %sum, align 4
# |   %add = add nsw i32 %2, %conv
# |   store i32 %add, ptr %sum, align 4
# |   %3 = load ptr, ptr %addr.addr, align 4
# |   %ldrex1 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i16) %3)
# |   %4 = trunc i32 %ldrex1 to i16
# |   %conv2 = sext i16 %4 to i32
# |   %5 = load i32, ptr %sum, align 4
# |   %add3 = add nsw i32 %5, %conv2
# |   store i32 %add3, ptr %sum, align 4
# |   %6 = load ptr, ptr %addr.addr, align 4
# |   %ldrex4 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %6)
# |   %7 = load i32, ptr %sum, align 4
# |   %add5 = add nsw i32 %7, %ldrex4
# |   store i32 %add5, ptr %sum, align 4
# |   %8 = load ptr, ptr %addr.addr, align 4
# |   %ldrexd = call { i32, i32 } @llvm.arm.ldaexd(ptr %8)
# |   %9 = extractvalue { i32, i32 } %ldrexd, 1
# |   %10 = extractvalue { i32, i32 } %ldrexd, 0
# |   %11 = zext i32 %9 to i64
# |   %12 = zext i32 %10 to i64
# |   %shl = shl nuw i64 %11, 32
# |   %13 = or i64 %shl, %12
# |   %14 = load i32, ptr %sum, align 4
# |   %conv6 = sext i32 %14 to i64
# |   %add7 = add nsw i64 %conv6, %13
# |   %conv8 = trunc i64 %add7 to i32
# |   store i32 %conv8, ptr %sum, align 4
# |   %15 = load ptr, ptr %addr64.addr, align 4
# |   %ldrexd9 = call { i32, i32 } @llvm.arm.ldaexd(ptr %15)
# |   %16 = extractvalue { i32, i32 } %ldrexd9, 1
# |   %17 = extractvalue { i32, i32 } %ldrexd9, 0
# |   %18 = zext i32 %16 to i64
# |   %19 = zext i32 %17 to i64
# |   %shl10 = shl nuw i64 %18, 32
# |   %20 = or i64 %shl10, %19
# |   %21 = load i32, ptr %sum, align 4
# |   %conv11 = sext i32 %21 to i64
# |   %add12 = add nsw i64 %conv11, %20
# |   %conv13 = trunc i64 %add12 to i32
# |   store i32 %conv13, ptr %sum, align 4
# |   %22 = load ptr, ptr %addrfloat.addr, align 4
# |   %ldrex14 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %22)
# |   %23 = bitcast i32 %ldrex14 to float
# |   %24 = load i32, ptr %sum, align 4
# |   %conv15 = sitofp i32 %24 to float
# |   %add16 = fadd float %conv15, %23
# |   %conv17 = fptosi float %add16 to i32
# |   store i32 %conv17, ptr %sum, align 4
# |   %25 = load ptr, ptr %addr.addr, align 4
# |   %ldrexd18 = call { i32, i32 } @llvm.arm.ldaexd(ptr %25)
# |   %26 = extractvalue { i32, i32 } %ldrexd18, 1
# |   %27 = extractvalue { i32, i32 } %ldrexd18, 0
# |   %28 = zext i32 %26 to i64
# |   %29 = zext i32 %27 to i64
# |   %shl19 = shl nuw i64 %28, 32
# |   %30 = or i64 %shl19, %29
# |   %31 = bitcast i64 %30 to double
# |   %32 = load i32, ptr %sum, align 4
# |   %conv20 = sitofp i32 %32 to double
# |   %add21 = fadd double %conv20, %31
# |   %conv22 = fptosi double %add21 to i32
# |   store i32 %conv22, ptr %sum, align 4
# |   %33 = load ptr, ptr %addr.addr, align 4
# |   %ldrex23 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %33)
# |   %34 = inttoptr i32 %ldrex23 to ptr
# |   %35 = load i32, ptr %34, align 4
# |   %36 = load i32, ptr %sum, align 4
# |   %add24 = add nsw i32 %36, %35
# |   store i32 %add24, ptr %sum, align 4
# |   %37 = load ptr, ptr %addr.addr, align 4
# |   %ldrex25 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %37)
# |   %38 = inttoptr i32 %ldrex25 to ptr
# |   %a = getelementptr inbounds nuw %struct.Simple, ptr %38, i32 0, i32 0
# |   %39 = load i8, ptr %a, align 1
# |   %conv26 = zext i8 %39 to i32
# |   %40 = load i32, ptr %sum, align 4
# |   %add27 = add nsw i32 %40, %conv26
# |   store i32 %add27, ptr %sum, align 4
# |   %41 = load i32, ptr %sum, align 4
# |   ret i32 %41
# | }
# | 
# | ; Function Attrs: nounwind
# | declare i32 @llvm.arm.ldaex.p0(ptr) #1
# | 
# | ; Function Attrs: nounwind
# | declare { i32, i32 } @llvm.arm.ldaexd(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_strex(ptr noundef %addr) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   %res = alloca i32, align 4
# |   %var = alloca %struct.Simple, align 1
# |   %tmp = alloca i64, align 8
# |   %tmp8 = alloca double, align 8
# |   store ptr %addr, ptr %addr.addr, align 4
# |   store i32 0, ptr %res, align 4
# |   call void @llvm.memset.p0.i32(ptr align 1 %var, i8 0, i32 2, i1 false)
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %strex = call i32 @llvm.arm.strex.p0(i32 4, ptr elementtype(i8) %0)
# |   %1 = load i32, ptr %res, align 4
# |   %or = or i32 %1, %strex
# |   store i32 %or, ptr %res, align 4
# |   %2 = load ptr, ptr %addr.addr, align 4
# |   %strex1 = call i32 @llvm.arm.strex.p0(i32 42, ptr elementtype(i16) %2)
# |   %3 = load i32, ptr %res, align 4
# |   %or2 = or i32 %3, %strex1
# |   store i32 %or2, ptr %res, align 4
# |   %4 = load ptr, ptr %addr.addr, align 4
# |   %strex3 = call i32 @llvm.arm.strex.p0(i32 42, ptr elementtype(i32) %4)
# |   %5 = load i32, ptr %res, align 4
# |   %or4 = or i32 %5, %strex3
# |   store i32 %or4, ptr %res, align 4
# |   store i64 42, ptr %tmp, align 8
# |   %6 = load { i32, i32 }, ptr %tmp, align 8
# |   %7 = extractvalue { i32, i32 } %6, 0
# |   %8 = extractvalue { i32, i32 } %6, 1
# |   %9 = load ptr, ptr %addr.addr, align 4
# |   %strexd = call i32 @llvm.arm.strexd(i32 %7, i32 %8, ptr %9)
# |   %10 = load i32, ptr %res, align 4
# |   %or5 = or i32 %10, %strexd
# |   store i32 %or5, ptr %res, align 4
# |   %11 = load ptr, ptr %addr.addr, align 4
# |   %strex6 = call i32 @llvm.arm.strex.p0(i32 1076754509, ptr elementtype(i32) %11)
# |   %12 = load i32, ptr %res, align 4
# |   %or7 = or i32 %12, %strex6
# |   store i32 %or7, ptr %res, align 4
# |   store double 3.141590e+00, ptr %tmp8, align 8
# |   %13 = load { i32, i32 }, ptr %tmp8, align 8
# |   %14 = extractvalue { i32, i32 } %13, 0
# |   %15 = extractvalue { i32, i32 } %13, 1
# |   %16 = load ptr, ptr %addr.addr, align 4
# |   %strexd9 = call i32 @llvm.arm.strexd(i32 %14, i32 %15, ptr %16)
# |   %17 = load i32, ptr %res, align 4
# |   %or10 = or i32 %17, %strexd9
# |   store i32 %or10, ptr %res, align 4
# |   %18 = load ptr, ptr %addr.addr, ali
# | ...
# `---data was truncated (10240/16971) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fecd4d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fecd4d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fecd4d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff673733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff67378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff673733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff67371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fecd46ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fecd46ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fecd4538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fecd102e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fecd102b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff67371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff67371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff67371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fecd102a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/recpe.c (465 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/recpe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrecpe_f16(<vscale x 8 x half> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x half> @llvm.aarch64.sve.frecpe.x.nxv8f16(<vscale x 8 x half> %0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frecpe.x.nxv8f16(<vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrecpe_f32(<vscale x 4 x float> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x float> @llvm.aarch64.sve.frecpe.x.nxv4f32(<vscale x 4 x float> %0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frecpe.x.nxv4f32(<vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrecpe_f64(<vscale x 2 x double> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x double> @llvm.aarch64.sve.frecpe.x.nxv2f64(<vscale x 2 x double> %0)
# |   ret <vscale x 2 x double> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frecpe.x.nxv2f64(<vscale x 2 x double>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x0000558f367c7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558f367c4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558f367c862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4251133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f425118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4251133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f425111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f3675dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558f3675da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558f367428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558f363f1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558f363f1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f425111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f425111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f425111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f363f1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c (466 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_s8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   call void @llvm.aarch64.sve.stnt1.nxv16i8.p0(<vscale x 16 x i8> %2, <vscale x 16 x i1> %0, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.stnt1.nxv16i8.p0(<vscale x 16 x i8>, <vscale x 16 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_s16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.stnt1.nxv8i16.p0(<vscale x 8 x i16> %2, <vscale x 8 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.stnt1.nxv8i16.p0(<vscale x 8 x i16>, <vscale x 8 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_s32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.stnt1.nxv4i32.p0(<vscale x 4 x i32> %2, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.stnt1.nxv4i32.p0(<vscale x 4 x i32>, <vscale x 4 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.stnt1.nxv2i64.p0(<vscale x 2 x i64> %2, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.stnt1.nxv2i64.p0(<vscale x 2 x i64>, <vscale x 2 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_u8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   call void @llvm.aarch64.sve.stnt1.nxv16i8.p0(<vscale x 16 x i8> %2, <vscale x 16 x i1> %0, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_u16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.stnt1.nxv8i16.p0(<vscale x 8 x i16> %2, <vscale x 8 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_u32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.stnt1.nxv4i32.p0(<vscale x 4 x i32> %2, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.stnt1.nxv2i64.p0(<vscale x 2 x i64> %2, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_f16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x half> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x half> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x half>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.stnt1.nxv8f16.p0(<vscale x 8 x half> %2, <vscale x 8 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.stnt1.nxv8f16.p0(<vscale x 8 x half>, <vscale x 8 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_f32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x float> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x float> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.stnt1.nxv4f32.p0(<vscale x 4 x float> %2, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.stnt1.nxv4f32.p0(<vscale x 4 x float>, <vscale x 4 x i1>, ptr
# | ...
# `---data was truncated (10240/26796) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005583cde17eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005583cde14e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005583cde1862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff54e81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff54e8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff54e81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff54e803507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005583cddadbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005583cddada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005583cdd928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005583cda41e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005583cda41b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff54e804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff54e8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff54e8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005583cda41a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c (467 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_lane_bf16_idx1(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i32 1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.lane.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_lane_bf16_idx3(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i32 3)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_lane_bf16_idx7(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i32 7)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16b16,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055baa051beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055baa0518e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055baa051c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f22a6333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f22a638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f22a6333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f22a631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055baa04b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055baa04b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055baa04968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055baa0145e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055baa0145b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f22a631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f22a631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f22a631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055baa0145a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c (468 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_v
# | ...
# `---data was truncated (10240/228865) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ae6f5adeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ae6f5aae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ae6f5ae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe986849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe9868a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe986849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe986831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ae6f543bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ae6f543a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ae6f5288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ae6f1d7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ae6f1d7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe986832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe9868330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe9868330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ae6f1d7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c (469 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_gather_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_gather_u64base_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_gather_s64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = sext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1>, ptr, <vscale x 2 x i64>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_gather_s64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = sext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_gather_u64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = sext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_gather_u64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = sext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_gather_u64base_offset_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/18766) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x00005622d387beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005622d3878e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005622d387c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe9e2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe9e2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe9e2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe9e2f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005622d3811bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005622d3811a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005622d37f68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005622d34a5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005622d34a5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe9e2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe9e2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe9e2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005622d34a5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c (470 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svbrkb_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.brkb.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.brkb.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svbrkb_b_m(<vscale x 16 x i1> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i1>, align 2
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %inactive, ptr %inactive.addr, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %inactive.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.brkb.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.brkb.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000557acc8ebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557acc8e8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557acc8ec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f93a6e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f93a6ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f93a6e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f93a6e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557acc881bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557acc881a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557acc8668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557acc515e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557acc515b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f93a6e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f93a6e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f93a6e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557acc515a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c (471 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b8_s32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.whilele.nxv16i1.i32(i32 %0, i32 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.whilele.nxv16i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b16_s32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.whilele.nxv8i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.whilele.nxv8i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b32_s32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.whilele.nxv4i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.whilele.nxv4i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b64_s32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.whilele.nxv2i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.whilele.nxv2i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b8_u32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.whilels.nxv16i1.i32(i32 %0, i32 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.whilels.nxv16i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b16_u32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.whilels.nxv8i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.whilels.nxv8i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b32_u32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.whilels.nxv4i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.whilels.nxv4i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b64_u32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.whilels.nxv2i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.whilels.nxv2i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b8_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.whilele.nxv16i1.i64(i64 %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.whilele.nxv16i1.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b16_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.whilele.nxv8i1.i64(i64 %0, i64 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.whilele.nxv8i1.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b32_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.whilele.nxv4i1.i64(i64 %0, i64 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.whilele.nxv4i1.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b64_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.whilele.nxv2i1.i64(i64 %0, i64 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.whilele.nxv2i1.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b8_u64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/13340) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e9c4a61eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e9c4a5ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e9c4a6262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1dd1049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1dd10a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1dd1049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1dd1031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e9c49f7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e9c49f7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e9c49dc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e9c468be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e9c468bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1dd1032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1dd10330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1dd10330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e9c468ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c (472 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svminnm_single_bf16_x2(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 1
# |   %5 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fminnm.single.x2.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %5)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fminnm.single.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svminnm_single_f16_x2(<vscale x 8 x half> %zdn.coerce0, <vscale x 8 x half> %zdn.coerce1, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zdn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 1
# |   %5 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fminnm.single.x2.nxv8f16(<vscale x 8 x half> %3, <vscale x 8 x half> %4, <vscale x 8 x half> %5)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fminnm.single.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svminnm_single_f32_x2(<vscale x 4 x float> %zdn.coerce0, <vscale x 4 x float> %zdn.coerce1, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zdn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zdn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zdn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fminnm.single.x2.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4, <vscale x 4 x float> %5)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fminnm.single.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double> } @test_svminnm_single_f64_x2(<vscale x 2 x double> %zdn.coerce0, <vscale x 2 x double> %zdn.coerce1, <vscale x 2 x double> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %zdn.addr = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %zm.addr = alloca <vscale x 2 x double>, align 16
# |   %0 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } poison, <vscale x 2 x double> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } %0, <vscale x 2 x double> %zdn.coerce1, 1
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %zdn, align 16
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 2 x double> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %2, 0
# |   %4 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %2, 1
# |   %5 = load <vscale x 2 x double>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.fminnm.single.x2.nxv2f64(<vscale x 2 x double> %3, <vscale x 2 x double> %4, <vscale x 2 x double> %5)
# |   ret { <vscale x 2 x double>, <vscale x 2 x double> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.fminnm.single.x2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svminnm_single_bf16_x4(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zdn.coerce2, <vscale x 8 x bfloat> %zdn.coerce3, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, <vscale x 8 x bfloat> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zdn.coerce3, 3
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 1
# |   %7 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 2
# |   %8 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 3
# |   %9 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %10 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fminnm.single.x4.nxv8bf16(<vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %6, <vscale x 8 x bfloat> %7, <vscale x 8 x bfloat> %8, <vscale x 8 x bfloat> %9)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %10
# | }
# | 
# | ; Funct
# | ...
# `---data was truncated (10240/50311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055995ecc0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055995ecbde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055995ecc162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2672c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2672ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2672c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2672c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055995ec56bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055995ec56a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055995ec3b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055995e8eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055995e8eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2672c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2672c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2672c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055995e8eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c (473 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzp2_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp2q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uzp2q.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzp2_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp2q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uzp2q.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzp2_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp2q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uzp2q.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzp2_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzp2q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uzp2q.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzp2_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp2q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzp2_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp2q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzp2_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp2q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzp2_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzp2q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svuzp2_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.uzp2q.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.uzp2q.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svuzp2_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.uzp2q.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.uzp2q.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svuzp2_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.uzp2q.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.uzp2q.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svuzp2_bf16(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.uzp2q.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.uzp2q.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d270ee9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d270ee6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d270eea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe916d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe916d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe916d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe916d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d270e7fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d270e7fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d270e648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d270b13e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d270b13b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe916d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe916d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe916d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d270b13a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c (474 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_i8mf8(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_i8mf4(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_i8mf2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_i8m1(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_i8m2(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_i8m4(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_u8mf8(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_u8mf4(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_u8mf2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_u8m1(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_xu_f_w_u8m2(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_xu_f_w_u8m4(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.
# | ...
# `---data was truncated (10240/164791) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ece8327eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ece8324e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ece832862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f842fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f842faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f842fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f842fa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ece82bdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ece82bda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ece82a28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ece7f51e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ece7f51b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f842fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f842fa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f842fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ece7f51a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/fp8-cast.c (475 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-cast.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +neon -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_f8_f8(<8 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <8 x i8>, ptr %x.addr, align 8
# |   ret <8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @testq_f8_f8(<16 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   %0 = load <16 x i8>, ptr %x.addr, align 16
# |   ret <16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_f8_s8(<8 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <8 x i8>, ptr %x.addr, align 8
# |   ret <8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_s8_f8(<8 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <8 x i8>, ptr %x.addr, align 8
# |   ret <8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @testq_f8_s8(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   %0 = load <16 x i8>, ptr %x.addr, align 16
# |   ret <16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @testq_s8_f8(<16 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   %0 = load <16 x i8>, ptr %x.addr, align 16
# |   ret <16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_f8_f32(<2 x float> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <2 x float>, align 8
# |   store <2 x float> %x, ptr %x.addr, align 8
# |   %0 = load <2 x float>, ptr %x.addr, align 8
# |   %1 = bitcast <2 x float> %0 to <8 x i8>
# |   ret <8 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_f32_f8(<8 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <8 x i8>, ptr %x.addr, align 8
# |   %1 = bitcast <8 x i8> %0 to <2 x float>
# |   ret <2 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @testq_f8_f32(<4 x float> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <4 x float>, align 16
# |   store <4 x float> %x, ptr %x.addr, align 16
# |   %0 = load <4 x float>, ptr %x.addr, align 16
# |   %1 = bitcast <4 x float> %0 to <16 x i8>
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @testq_f32_f8(<16 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   %0 = load <16 x i8>, ptr %x.addr, align 16
# |   %1 = bitcast <16 x i8> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @testq_f8_p128(i128 noundef %x) #0 {
# | entry:
# |   %x.addr = alloca i128, align 16
# |   store i128 %x, ptr %x.addr, align 16
# |   %0 = load i128, ptr %x.addr, align 16
# |   %1 = bitcast i128 %0 to <16 x i8>
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @testq_p128_f8(<16 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   %0 = load <16 x i8>, ptr %x.addr, align 16
# |   %1 = bitcast <16 x i8> %0 to i128
# |   ret i128 %1
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg
# |  #0 0x00005609a1e16eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005609a1e13e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005609a1e1762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5278d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5278d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5278d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5278d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005609a1dacbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005609a1daca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005609a1d918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005609a1a40e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005609a1a40b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5278d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5278d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5278d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005609a1a40a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c (476 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_i8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_i8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_i8mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8_v_i8m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8_v_i8m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_u8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_u8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_u8mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv
# | ...
# `---data was truncated (10240/53726) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560093ec0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560093ebde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560093ec162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa647f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa647f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa647f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa647eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560093e56bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560093e56a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560093e3b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560093aeae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560093aeab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa647eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa647eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa647eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560093aeaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c (477 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_s32_x2(<vscale x 4 x i32> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.x2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sdot.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_u32_x2(<vscale x 4 x i32> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.udot.x2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.udot.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdot_f32_x2(<vscale x 4 x float> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fdot.x2.nxv4f32(<vscale x 4 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fdot.x2.nxv4f32(<vscale x 4 x float>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_n_s32_x2(<vscale x 4 x i32> %op1, <vscale x 8 x i16> %op2, i16 noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca i16, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store i16 %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load i16, ptr %op3.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.x2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_n_u32_x2(<vscale x 4 x i32> %op1, <vscale x 8 x i16> %op2, i16 noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca i16, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store i16 %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load i16, ptr %op3.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.udot.x2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdot_n_f32_x2(<vscale x 4 x float> %op1, <vscale x 8 x half> %op2, half noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca half, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store half %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = load half, ptr %op3.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x half> poison, half %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x half> %.splatinsert, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fdot.x2.nxv4f32(<vscale x 4 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %.splat)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_lane_s32_x2(<vscale x 4 x i32> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.lane.x2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i32 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sdot.lane.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_lane_u32_x2(<vscale x 4 x i32> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.udot.lane.x2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i32 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.udot.lane.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdot_lane_f32_x2(<vscale x 4 x float> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fdot.lane.x2.nxv4f32(<vscale x 4 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i32 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fdot.lane.x2.nxv4f32(<vscale x 4 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i32 immarg) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync no
# | ...
# `---data was truncated (10240/10512) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000559cc918eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559cc918be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559cc918f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5c2d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5c2d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5c2d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5c2d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559cc9124bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559cc9124a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559cc91098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559cc8db8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559cc8db8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5c2d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5c2d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5c2d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559cc8db8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c (478 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svbrka_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.brka.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.brka.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svbrka_b_m(<vscale x 16 x i1> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i1>, align 2
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %inactive, ptr %inactive.addr, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %inactive.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.brka.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.brka.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056542b02feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056542b02ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056542b03062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe698333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe69838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe698333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe69831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056542afc5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056542afc5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056542afaa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056542ac59e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056542ac59b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe69831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe69831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe69831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056542ac59a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c (479 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacle_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.facge.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %2, <vscale x 8 x half> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.facge.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacle_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.facge.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %2, <vscale x 4 x float> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.facge.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacle_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.facge.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %2, <vscale x 2 x double> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.facge.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacle_n_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, float noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca float, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store float %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 4 x float> poison, float %2, i64 0
# |   %.splat = shufflevector <vscale x 4 x float> %.splatinsert, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.facge.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %.splat, <vscale x 4 x float> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacle_n_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, double noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca double, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store double %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load double, ptr %op2.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 2 x double> poison, double %2, i64 0
# |   %.splat = shufflevector <vscale x 2 x double> %.splatinsert, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.facge.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %.splat, <vscale x 2 x double> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000557f3d84eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557f3d84be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557f3d84f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5455249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54552a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5455249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5455231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f3d7e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557f3d7e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557f3d7c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557f3d478e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557f3d478b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5455232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54552330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54552330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f3d478a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c (480 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_lane_za32_f8_vg1x2(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load i32, ptr %slice.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %7 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   call void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x2(i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x2(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_lane_za32_f8_vg1x4(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %4 = load i32, ptr %slice.addr, align 4
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 2
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 3
# |   %10 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %11 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %11)
# |   call void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x4(i32 %4, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x4(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_lane_za16_f8_vg1x2(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load i32, ptr %slice.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %7 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   call void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x2(i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x2(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_lane_za16_f8_vg1x4(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %4 = load i32, ptr %slice.addr, align 4
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 2
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 3
# |   %10 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %11 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %11)
# |   call void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x4(i32 %4, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x4(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_ra
# | ...
# `---data was truncated (10240/35066) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim
# |  #0 0x000055ac501c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ac501c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ac501c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff20d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff20d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff20d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff20d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac5015ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ac5015ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ac501438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ac4fdf2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ac4fdf2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff20d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff20d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff20d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac4fdf2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c (481 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1uw_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1uw_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1uw_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1uw_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e4b336ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e4b3369e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e4b336d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7822533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f782258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7822533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f782251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e4b3302bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e4b3302a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e4b32e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e4b2f96e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e4b2f96b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f782251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f782251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f782251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e4b2f96a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c (482 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef2_s8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svundef2_s16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svundef2_s32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svundef2_s64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef2_u8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svundef2_u16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svundef2_u32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svundef2_u64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svundef2_f16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svundef2_f32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double> } @test_svundef2_f64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x double>, <vscale x 2 x double> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef2_mf8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svundef2_bf16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } undef
# | }
# | 
# | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | !llvm.errno.tbaa = !{!4}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# | !4 = !{!5, !6, i64 0}
# | !5 = !{!"__libc_errno", !6, i64 0}
# | !6 = !{!"int", !7, i64 0}
# | !7 = !{!"omnipotent char", !8, i64 0}
# | !8 = !{!"Simple C/C++ TBAA"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005568e1a84eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005568e1a81e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005568e1a8562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdb0801bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdb080725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdb0801ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdb08003507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005568e1a1abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005568e1a1aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005568e19ff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005568e16aee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005568e16aeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdb08004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdb080050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdb080050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005568e16aea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c (483 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +xandesvbfhcvt -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4_rm_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2_rm_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1_rm_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2_rm_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4_rm_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync
# | ...
# `---data was truncated (10240/10618) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561df3583eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561df3580e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561df358462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f497b21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f497b2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f497b21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f497b203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561df3519bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561df3519a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561df34fe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561df31ade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561df31adb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f497b204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f497b2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f497b2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561df31ada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c (484 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16ff_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16ff_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %6
# | }
# | 
# | ; Fun
# | ...
# `---data was truncated (10240/34633) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cff8927eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cff8924e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cff892862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f76dbc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f76dbc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f76dbc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f76dbc03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cff88bdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cff88bda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cff88a28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cff8551e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cff8551b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f76dbc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f76dbc050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f76dbc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cff8551a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c (485 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svzip_s8_x4(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 3
# |   %9 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x4.nxv16i8(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svzip_u8_x4(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 3
# |   %9 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x4.nxv16i8(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svzip_mf8_x4(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 3
# |   %9 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x4.nxv16i8(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svzip_s16_x4(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zn.coerce2, <vscale x 8 x i16> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zn.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 1
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 2
# |   %8 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 3
# |   %9 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.zip.x4.nxv8i16(<vscale x 8 x i16> %5, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %8)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.zip.x4.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | ...
# `---data was truncated (10240/67329) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055fd3addeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fd3addbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fd3addf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6a48933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6a4898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6a48933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6a4891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd3ad74bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fd3ad74a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fd3ad598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fd3aa08e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fd3aa08b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6a4891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6a4891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6a4891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd3aa08a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/arm64-lanes.c (486 of 27911)
******************** TEST 'Clang :: CodeGen/arm64-lanes.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c"
# | target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-apple-ios7"
# | 
# | ; Function Attrs: noinline nounwind
# | define i8 @test_vdupb_lane_s8(<8 x i8> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store <8 x i8> %src, ptr %src.addr, align 8
# |   %0 = load <8 x i8>, ptr %src.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vget_lane = extractelement <8 x i8> %1, i32 2
# |   store i8 %vget_lane, ptr %ref.tmp, align 1
# |   %2 = load i8, ptr %ref.tmp, align 1
# |   store i8 %2, ptr %__ret, align 1
# |   %3 = load i8, ptr %__ret, align 1
# |   store i8 %3, ptr %tmp, align 1
# |   %4 = load i8, ptr %tmp, align 1
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define i8 @test_vdupb_lane_u8(<8 x i8> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store <8 x i8> %src, ptr %src.addr, align 8
# |   %0 = load <8 x i8>, ptr %src.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vget_lane = extractelement <8 x i8> %1, i32 2
# |   store i8 %vget_lane, ptr %ref.tmp, align 1
# |   %2 = load i8, ptr %ref.tmp, align 1
# |   store i8 %2, ptr %__ret, align 1
# |   %3 = load i8, ptr %__ret, align 1
# |   store i8 %3, ptr %tmp, align 1
# |   %4 = load i8, ptr %tmp, align 1
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define i16 @test_vduph_lane_s16(<4 x i16> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <4 x i16>, align 8
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store <4 x i16> %src, ptr %src.addr, align 8
# |   %0 = load <4 x i16>, ptr %src.addr, align 8
# |   store <4 x i16> %0, ptr %__s0, align 8
# |   %1 = load <4 x i16>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i16> %1, i32 2
# |   store i16 %vget_lane, ptr %ref.tmp, align 2
# |   %2 = load i16, ptr %ref.tmp, align 2
# |   store i16 %2, ptr %__ret, align 2
# |   %3 = load i16, ptr %__ret, align 2
# |   store i16 %3, ptr %tmp, align 2
# |   %4 = load i16, ptr %tmp, align 2
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define i16 @test_vduph_lane_u16(<4 x i16> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <4 x i16>, align 8
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store <4 x i16> %src, ptr %src.addr, align 8
# |   %0 = load <4 x i16>, ptr %src.addr, align 8
# |   store <4 x i16> %0, ptr %__s0, align 8
# |   %1 = load <4 x i16>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i16> %1, i32 2
# |   store i16 %vget_lane, ptr %ref.tmp, align 2
# |   %2 = load i16, ptr %ref.tmp, align 2
# |   store i16 %2, ptr %__ret, align 2
# |   %3 = load i16, ptr %__ret, align 2
# |   store i16 %3, ptr %tmp, align 2
# |   %4 = load i16, ptr %tmp, align 2
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define i32 @test_vdups_lane_s32(<2 x i32> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <2 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <2 x i32> %src, ptr %src.addr, align 8
# |   %0 = load <2 x i32>, ptr %src.addr, align 8
# |   store <2 x i32> %0, ptr %__s0, align 8
# |   %1 = load <2 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x i32> %1, i32 0
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define i32 @test_vdups_lane_u32(<2 x i32> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <2 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <2 x i32> %src, ptr %src.addr, align 8
# |   %0 = load <2 x i32>, ptr %src.addr, align 8
# |   store <2 x i32> %0, ptr %__s0, align 8
# |   %1 = load <2 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x i32> %1, i32 0
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define float @test_vdups_lane_f32(<2 x float> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <2 x float>, align 8
# |   %__ret = alloca float, align 4
# |   %__s0 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca float, align 4
# |   %tmp = alloca float, align 4
# |   store <2 x float> %src, ptr %src.addr, align 8
# |   %0 = load <2 x float>, ptr %src.addr, align 8
# |   store <2 x float> %0, ptr %__s0, align 8
# |   %1 = load <2 x float>, ptr %__s0, align 8
# |   %vdups_lane = extractelement <2 x float> %1, i32 0
# |   store float %vdups_lane, ptr %ref.tmp, align 4
# |   %2 = load float, ptr %ref.tmp, align 4
# |   store float %2, ptr %__ret, align 4
# |   %3 = load float, ptr %__ret, align 4
# |   store float %3, ptr %tmp, align 4
# |   %4 = load float, ptr %tmp, align 4
# |   ret float %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define i64 @test_vdupd_lane_s64(<1 x i64> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <1 x i64>, align 8
# |   %__ret = alloca i64, align 8
# |   %__s0 = alloca <1 x i64>, align 8
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   store <1 x i64> %src, ptr %src.addr, align 8
# |   %0 = load <1 x i64>, ptr %src.addr, align 8
# |   store <1 x i64> %0, ptr %__s0, align 8
# |   %1 = load <1 x i64>, ptr %__s0, align 8
# |   %vget_lane = extractelement <1 x i64> %1, i32 0
# |   store i64 %vget_lane, ptr %ref.tmp, align 8
# |   %2 = load i64, ptr %ref.tmp, align 8
# |   store i64 %2, ptr %__ret, align 8
# |   %3 = load i64, ptr %__ret, align 8
# |   store i64 %3, ptr %tmp, align 8
# |   %4 = load i64, ptr %tmp, align 8
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define i64 @test_vdupd_lane_u64(<1 x i64> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <1 x i64>, align 8
# |   %__ret = alloca i64, align 8
# |   %__s0 = alloca <1 x i64>, align 8
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   store <1 x i64> %src, ptr %src.addr, align 8
# |   %0 = load <1 x i64>, ptr %src.addr, align 8
# |   store <1 x i64> %0, ptr %__s0, align 8
# |   %1 = load <1 x i64>, ptr %__s0, align 8
# |   %vget_lane = extractelement <1 x i64> %1, i32 0
# |   store i64 %vget_lane, ptr %ref.tmp, align 8
# |   %2 = load i64, ptr %ref.tmp, align 8
# |   store i64 %2, ptr %__ret, align 8
# |   %3 = load i64, ptr %__ret, align 8
# |   store i64 %3, ptr %tmp, align 8
# |   %4 = load i64, ptr %tmp, align 8
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define double @test_vdupd_lane_f64(<1 x double> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <1 x double>, align 8
# |   %__ret = alloca double, align 8
# |   %__s0 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca double, align 8
# |   %tmp = alloca double, align 8
# |   store <1 x double> %src, ptr %src.addr, align 8
# |   %0 = load <1 x double>, ptr %src.addr, align 8
# |   store <1 x double> %0, ptr %__s0, align 8
# |   %1 = load <1 x double>, ptr %__s0, align 8
# |   %vdupd_lane = extractelement <1 x double> %1, i32 0
# |   store double %vdupd_lane, ptr %ref.tmp, align 8
# |   %2 = load double, ptr %ref.tmp, align 8
# |   store double %2, ptr %__ret, align 8
# |   %3 = load double, ptr %__ret, align 8
# |   store double %3, ptr %tmp, align 8
# |   %4 = load double, ptr %tmp, align 8
# |   ret double %4
# | }
# | 
# | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005642a8f55eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005642a8f52e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005642a8f5662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2ec8a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2ec8aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2ec8a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2ec8a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005642a8eebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005642a8eeba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005642a8ed08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005642a8b7fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005642a8b7fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2ec8a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2ec8a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2ec8a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005642a8b7fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c (487 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f16m1x3(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_f16m2x3(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f32m1x3(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_f32m2x3(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f64m1x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captu
# | ...
# `---data was truncated (10240/87308) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f9faa64eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f9faa61e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f9faa6562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f03d3a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03d3aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f03d3a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f03d3a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f9fa9fabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f9fa9faa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f9fa9df8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f9fa68ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f9fa68eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f03d3a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03d3a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03d3a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f9fa68ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c (488 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpgt_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpgt.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpgt.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpgt_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpgt.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpgt.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpgt_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpgt.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpgt.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpgt_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpgt.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpgt.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpgt_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmphi.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmphi.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpgt_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmphi.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmphi.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpgt_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmphi.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmphi.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpgt_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr,
# | ...
# `---data was truncated (10240/41923) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000562807532eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056280752fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056280753362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2dd4649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2dd46a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2dd4649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2dd4631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005628074c8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005628074c8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005628074ad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056280715ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056280715cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2dd4632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2dd46330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2dd46330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056280715ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c (489 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wf_bf16_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wf_bf16_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x floa
# | ...
# `---data was truncated (10240/199588) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de258a8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055de258a5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055de258a962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe368449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe3684a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe368449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe368431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de2583ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055de2583ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055de258238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055de254d2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055de254d2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe368432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe3684330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe3684330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de254d2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c (490 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_vv_i16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_vx_i16mf4(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_wv_i16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_wx_i16mf4(<vscale x 1 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_vv_i16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_vx_i16mf2(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_wv_i16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_wx_i16mf2(<vscale x 2 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsub_vv_i16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsub_vx_i16m1(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsub_wv_i16m
# | ...
# `---data was truncated (10240/134565) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563d3c142eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563d3c13fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563d3c14362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff181f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff181f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff181f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff181f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d3c0d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563d3c0d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563d3c0bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563d3bd6ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563d3bd6cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff181f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff181f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff181f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d3bd6ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c (491 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgt_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgt_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgt_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgt_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgt_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgt_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgt_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i
# | ...
# `---data was truncated (10240/63579) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558e1cdb0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558e1cdade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558e1cdb162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f190e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f190e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f190e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f190e31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558e1cd46bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558e1cd46a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558e1cd2b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558e1c9dae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558e1c9dab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f190e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f190e31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f190e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558e1c9daa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c (492 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmul_vv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmul_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmul_vv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmul_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmul_vv_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmul_vx_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmul_vv_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmul_vx_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmul_vv_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.add
# | ...
# `---data was truncated (10240/153913) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c97874beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c978748e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c97874c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3337a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3337aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3337a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3337a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9786e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c9786e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c9786c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c978375e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c978375b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3337a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3337a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3337a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c978375a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/nor.c (493 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/nor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svnor_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.nor.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.nor.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x00005616a5e7eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005616a5e7be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005616a5e7f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd9f9d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd9f9d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd9f9d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd9f9d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005616a5e14bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005616a5e14a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005616a5df98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005616a5aa8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005616a5aa8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd9f9d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd9f9d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd9f9d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005616a5aa8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c (494 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_f32mf2(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_f32m1(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_f32m2(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_f32m4(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16.nx
# | ...
# `---data was truncated (10240/90875) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d48cb38eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d48cb35e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d48cb3962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc297649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc2976a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc297649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc297631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d48cacebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d48cacea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d48cab38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d48c762e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d48c762b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc297632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc2976330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc2976330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d48c762a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c (495 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f16mf4(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f16mf2(ptr noundef %base, <vscale x 2 x i64> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f16m1(ptr noundef %base, <vscale x 4 x i64> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f16m2(ptr noundef %base, <vscale x 8 x i64> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f32mf2(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f32m1(ptr noundef %base, <vscale x 2 x i64> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f32m2(ptr noundef %base, <vscale x 4 x i64> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f32m4(ptr noundef %base, <vscale x 8 x i64> %bindex, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f64m1(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; F
# | ...
# `---data was truncated (10240/102296) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005555d4219eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005555d4216e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005555d421a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5fc4e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5fc4e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5fc4e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5fc4e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005555d41afbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005555d41afa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005555d41948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005555d3e43e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005555d3e43b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5fc4e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5fc4e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5fc4e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005555d3e43a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c (496 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_cvt_f16_x2(<vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 1
# |   %5 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %5)
# |   %6 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x2.nxv8f16(<vscale x 8 x half> %3, <vscale x 8 x half> %4)
# |   ret <vscale x 16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_cvt_f32_x4(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zn.coerce2, <vscale x 4 x float> %zn.coerce3, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, <vscale x 4 x float> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zn.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %4 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 1
# |   %7 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 2
# |   %8 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 3
# |   %9 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %9)
# |   %10 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x4(<vscale x 4 x float> %5, <vscale x 4 x float> %6, <vscale x 4 x float> %7, <vscale x 4 x float> %8)
# |   ret <vscale x 16 x i8> %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x4(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_cvtn_f32_x4(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zn.coerce2, <vscale x 4 x float> %zn.coerce3, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, <vscale x 4 x float> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zn.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %4 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 1
# |   %7 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 2
# |   %8 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 3
# |   %9 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %9)
# |   %10 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtn.x4(<vscale x 4 x float> %5, <vscale x 4 x float> %6, <vscale x 4 x float> %7, <vscale x 4 x float> %8)
# |   ret <vscale x 16 x i8> %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtn.x4(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_cvt_bf16_x2(<vscale x 8 x bfloat> %zn.coerce0, <vscale x 8 x bfloat> %zn.coerce1, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zn1, ptr %zn.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 1
# |   %5 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %5)
# |   %6 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x2.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %4)
# |   ret <vscale x 16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_cvt1_f16_x2(<vscale x 16 x i8> %zn, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fp8.cvt1.x2.nxv8f16(<vscale x 16 x i8> %0)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fp8.cvt1.x2.nxv8f16(<vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_cvt2_f16_x2(<vscale x 16 x i8> %zn, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr
# | ...
# `---data was truncated (10240/17058) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000056216c4fbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056216c4f8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056216c4fc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8672c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8672ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8672c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8672c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056216c491bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056216c491a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056216c4768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056216c125e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056216c125b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8672c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8672c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8672c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056216c125a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c (497 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevw_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevw_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevw_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevw_u64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevw_s64_x(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevw_u64_x(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055bb59794eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bb59791e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bb5979562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f980df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f980df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f980df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f980df1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bb5972abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bb5972aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bb5970f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bb593bee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bb593beb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f980df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f980df1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f980df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bb593bea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c (498 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_gather_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_gather_u64base_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_gather_s64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = zext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1>, ptr, <vscale x 2 x i64>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_gather_s64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = zext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_gather_u64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = zext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_gather_u64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = zext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff
# | ...
# `---data was truncated (10240/18920) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d0cb9c7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d0cb9c4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d0cb9c862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f116781bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f11678725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f116781ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1167803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0cb95dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d0cb95da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d0cb9428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d0cb5f1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d0cb5f1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1167804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f11678050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f11678050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d0cb5f1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon/load.c (499 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/load.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | %struct.float16x8x2_t = type { [2 x <8 x half>] }
# | %struct.float32x4x2_t = type { [2 x <4 x float>] }
# | %struct.float64x2x2_t = type { [2 x <2 x double>] }
# | %struct.mfloat8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.poly16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.poly64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.poly8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.int16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.int32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.int64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.int8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.uint16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.uint32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.uint64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.uint8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.float16x4x2_t = type { [2 x <4 x half>] }
# | %struct.float32x2x2_t = type { [2 x <2 x float>] }
# | %struct.float64x1x2_t = type { [2 x <1 x double>] }
# | %struct.mfloat8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.poly16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.poly64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.poly8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.int16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.int32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.int64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.int8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.uint16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.uint32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.uint64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.uint8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.float16x8x3_t = type { [3 x <8 x half>] }
# | %struct.float32x4x3_t = type { [3 x <4 x float>] }
# | %struct.float64x2x3_t = type { [3 x <2 x double>] }
# | %struct.mfloat8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.poly16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.poly64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.poly8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.int16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.int32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.int64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.int8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.uint16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.uint32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.uint64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.uint8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.float16x4x3_t = type { [3 x <4 x half>] }
# | %struct.float32x2x3_t = type { [3 x <2 x float>] }
# | %struct.float64x1x3_t = type { [3 x <1 x double>] }
# | %struct.mfloat8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.poly16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.poly64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.poly8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.int16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.int32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.int64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.int8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.uint16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.uint32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.uint64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.uint8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.float16x8x4_t = type { [4 x <8 x half>] }
# | %struct.float32x4x4_t = type { [4 x <4 x float>] }
# | %struct.float64x2x4_t = type { [4 x <2 x double>] }
# | %struct.mfloat8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.poly16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.poly64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.poly8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.int16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.int32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.int64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.int8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.uint16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.uint32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.uint64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.uint8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.float16x4x4_t = type { [4 x <4 x half>] }
# | %struct.float32x2x4_t = type { [4 x <2 x float>] }
# | %struct.float64x1x4_t = type { [4 x <1 x double>] }
# | %struct.mfloat8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.poly16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.poly64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.poly8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.int16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.int32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.int64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.int8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.uint16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.uint32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.uint64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.uint8x8x4_t = type { [4 x <8 x i8>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vld1q_f16(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca <8 x half>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %0, align 2
# |   store <8 x half> %1, ptr %ref.tmp, align 16
# |   %2 = load <8 x half>, ptr %ref.tmp, align 16
# |   store <8 x half> %2, ptr %__ret, align 16
# |   %3 = load <8 x half>, ptr %__ret, align 16
# |   store <8 x half> %3, ptr %tmp, align 16
# |   %4 = load <8 x half>, ptr %tmp, align 16
# |   ret <8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vld1q_f32(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca <4 x float>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x float>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %0, align 4
# |   store <4 x float> %1, ptr %ref.tmp, align 16
# |   %2 = load <4 x float>, ptr %ref.tmp, align 16
# |   store <4 x float> %2, ptr %__ret, align 16
# |   %3 = load <4 x float>, ptr %__ret, align 16
# |   store <4 x float> %3, ptr %tmp, align 16
# |   %4 = load <4 x float>, ptr %tmp, align 16
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vld1q_f64(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca <2 x double>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x double>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load <2 x double>, ptr %0, align 8
# |   store <2 x double> %1, ptr %ref.tmp, align 16
# |   %2 = load <2 x double>, ptr %ref.tmp, align 16
# |   store <2 x double> %2, ptr %__ret, align 16
# |   %3 = load <2 x double>, ptr %__ret, align 16
# |   store <2 x double> %3, ptr %tmp, align 16
# |   %4 = load <2 x double>, ptr %tmp, align 16
# |   ret <2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vld1q_mf8(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca <16 x i8>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <16 x i8>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %0, align 1
# |   store <16 x i8> %1, ptr %ref.tmp, align 16
# |   %2 = load <16 x i8>, ptr %ref.tmp, align 16
# |   store <16 x i8> %2, ptr %__ret, align 16
# |   %3 = load <16 x i8>, ptr %__ret, align 16
# |   store <16 x i8> %3, ptr %tmp, align 16
# |   %4 = load <16 x i8>, ptr %tmp, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vld1q_p16(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x i16>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %0, align 2
# |   store <8 x i16> %1, ptr %ref.tmp, align 16
# |   %2 = load <8 x i16>, ptr %ref.tmp, align 16
# |   store <8 x i16> %2, ptr %__ret, align 16
# |   %3 = load <8 x i16>, ptr %__ret, align 16
# |   store <8 x i16> %3, ptr %tmp, align 16
# |   %4 = load <8 x i16>, ptr %tmp, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vld1q_p64(ptr noundef %ptr) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %__ret = alloca <2 x i64>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x i64>, align 16
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load <2 x i64>, ptr %0, align 8
# |   store <2 x i64> %1, ptr %ref.tmp, align 16
# |   %2 = load <2 x i64>, ptr %ref.tmp, align 16
# |   store <2 x i64> %2, ptr %__ret, align 16
# |   %3 = load <2 x i64>, ptr %__ret, align 16
# |   store <2 x i64> %3, ptr %tmp, align 16
# |   %4 = load <2 x i64>, ptr %tmp, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vld1q_p8(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca <16 x i8>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <16 x i8>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %0, align 1
# |   store <16 x i8> %1, ptr %ref.tmp, align 16
# |   %2 = load <16 x i8>, ptr %ref.tmp, align 16
# |   store <16 x i8> %2, ptr %__ret, align 16
# |   %3 = load <16 x i8>, ptr %__ret, align 16
# |   store <16 x i8> %3, ptr %tmp, align 16
# |   %4 = load <16 x i8>, ptr %tmp, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vld1q_s16(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x i16>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %0, align 2
# |   store <8 x i16> %1, ptr %ref.tmp, align 16
# |   %2 = load <8 x i16>, ptr %ref.tmp, align 16
# |   store <8 x i16> %2, ptr %__ret, align 16
# |   %3 = load <8 x i16>, ptr %__ret, align 16
# |   store <8 x i16> %3, ptr %tmp, align 16
# |   %4 = load <8 x i16>, ptr %tmp, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vld1q_s32(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca <4 x i32>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x i32>, align 16
# |   store ptr %a
# | ...
# `---data was truncated (10240/415795) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine
# |  #0 0x000055b6efa1ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b6efa19e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b6efa1d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f500d505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f500d55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f500d505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f500d4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b6ef9b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b6ef9b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b6ef9978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b6ef646e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b6ef646b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f500d4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f500d4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f500d4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b6ef646a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c (500 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf8_i64m2(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf8_i64m4(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf8_i64m8(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf8_i64m2_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf8_i64m4_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf8_i64m8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d5d454feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d5d454ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d5d455062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2bf0049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2bf00a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2bf0049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2bf0031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d5d44e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d5d44e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d5d44ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d5d4179e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d5d4179b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2bf0032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2bf00330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2bf00330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d5d4179a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c (501 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmacc_vv_i16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmacc_vx_i16mf4_tu(<vscale x 1 x i16> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmacc_vv_i16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmacc_vx_i16mf2_tu(<vscale x 2 x i16> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmacc_vv_i16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmacc_vx_i16m1_tu(<vscale x 4 x i16> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmacc_vv_i16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmacc_vx_i16m2_tu(<vscale x 8 x i16> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmacc_vv_i16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.ad
# | ...
# `---data was truncated (10240/150649) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559e3dda0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559e3dd9de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559e3dda162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f735861bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f73586725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f735861ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7358603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e3dd36bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559e3dd36a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559e3dd1b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559e3d9cae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559e3d9cab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7358604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73586050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73586050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e3d9caa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c (502 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccu_vv_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccu_vx_u16mf4(<vscale x 1 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccu_vv_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccu_vx_u16mf2(<vscale x 2 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccu_vv_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccu_vx_u16m1(<vscale x 4 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccu_vv_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccu_vx_u16m2(<vscale x 8 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccu_vv_u16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, pt
# | ...
# `---data was truncated (10240/79679) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c59b6aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563c59b67e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563c59b6b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f49cf733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f49cf78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f49cf733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f49cf71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c59b00bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563c59b00a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563c59ae58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563c59794e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563c59794b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f49cf71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f49cf71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f49cf71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c59794a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c (503 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsrl_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsrl_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsrl_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsrl_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsrl_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsrl_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsrl_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsrl_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsrl_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %o
# | ...
# `---data was truncated (10240/223855) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ef852ceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ef852cbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ef852cf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff07733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff0778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff07733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff0771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ef85264bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ef85264a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ef852498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ef84ef8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ef84ef8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007eff0771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff0771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff0771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ef84ef8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c (504 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svinsr_n_s8(<vscale x 16 x i8> %op1, i8 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca i8, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store i8 %op2, ptr %op2.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.insr.nxv16i8(<vscale x 16 x i8> %0, i8 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.insr.nxv16i8(<vscale x 16 x i8>, i8) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svinsr_n_s16(<vscale x 8 x i16> %op1, i16 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca i16, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store i16 %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.insr.nxv8i16(<vscale x 8 x i16> %0, i16 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.insr.nxv8i16(<vscale x 8 x i16>, i16) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svinsr_n_s32(<vscale x 4 x i32> %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca i32, align 4
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.insr.nxv4i32(<vscale x 4 x i32> %0, i32 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.insr.nxv4i32(<vscale x 4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svinsr_n_s64(<vscale x 2 x i64> %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.insr.nxv2i64(<vscale x 2 x i64> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.insr.nxv2i64(<vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svinsr_n_u8(<vscale x 16 x i8> %op1, i8 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca i8, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store i8 %op2, ptr %op2.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.insr.nxv16i8(<vscale x 16 x i8> %0, i8 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svinsr_n_u16(<vscale x 8 x i16> %op1, i16 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca i16, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store i16 %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.insr.nxv8i16(<vscale x 8 x i16> %0, i16 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svinsr_n_u32(<vscale x 4 x i32> %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca i32, align 4
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.insr.nxv4i32(<vscale x 4 x i32> %0, i32 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svinsr_n_u64(<vscale x 2 x i64> %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.insr.nxv2i64(<vscale x 2 x i64> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svinsr_n_f16(<vscale x 8 x half> %op1, half noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca half, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store half %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.insr.nxv8f16(<vscale x 8 x half> %0, half %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.insr.nxv8f16(<vscale x 8 x half>, half) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svinsr_n_f32(<vscale x 4 x float> %op1, float noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca float, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store float %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.insr.nxv4f32(<vscale x 4 x float> %0, float %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.insr.nxv4f32(<vscale x 4 x float>, float) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svinsr_n_f64(<vscale x 2 x double> %op1, double noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca double, align 8
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store double %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load double, ptr %op2.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.insr.nxv2f64(<vscale x 2 x double> %0, double %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.insr.nxv2f64(<vscale x 2 x double>, double) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svinsr_n_bf16(<vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.insr.nxv8bf16(<vscale x 8 x bfloat> %0, bfloat %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.insr.nxv8bf16(<vscale x 8 x bfloat>, bfloat) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560da10b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560da10b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560da10b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d63933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d6398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d63933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d6391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560da104bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560da104ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560da10308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560da0cdfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560da0cdfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8d6391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d6391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d6391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560da0cdfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c (505 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2_s8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data.coerce0, <vscale x 16 x i8> %data.coerce1) #0 {
# | entry:
# |   %data = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %data.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %data, align 16
# |   %data1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %data1, ptr %data.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %data.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   call void @llvm.aarch64.sve.st2.nxv16i8.p0(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i1> %2, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st2.nxv16i8.p0(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2_s16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data.coerce0, <vscale x 8 x i16> %data.coerce1) #0 {
# | entry:
# |   %data = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %data.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %data, align 16
# |   %data1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %data1, ptr %data.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %data.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 1
# |   %7 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %2)
# |   call void @llvm.aarch64.sve.st2.nxv8i16.p0(<vscale x 8 x i16> %5, <vscale x 8 x i16> %6, <vscale x 8 x i1> %7, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st2.nxv8i16.p0(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2_s32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data.coerce0, <vscale x 4 x i32> %data.coerce1) #0 {
# | entry:
# |   %data = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %data.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %data, align 16
# |   %data1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %data1, ptr %data.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %data.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 1
# |   %7 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %2)
# |   call void @llvm.aarch64.sve.st2.nxv4i32.p0(<vscale x 4 x i32> %5, <vscale x 4 x i32> %6, <vscale x 4 x i1> %7, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st2.nxv4i32.p0(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data.coerce0, <vscale x 2 x i64> %data.coerce1) #0 {
# | entry:
# |   %data = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %data.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %data, align 16
# |   %data1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %data1, ptr %data.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %data.addr, align 16
# |   %5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 1
# |   %7 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %2)
# |   call void @llvm.aarch64.sve.st2.nxv2i64.p0(<vscale x 2 x i64> %5, <vscale x 2 x i64> %6, <vscale x 2 x i1> %7, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st2.nxv2i64.p0(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2_u8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data.coerce0, <vscale x 16 x i8> %data.coerce1) #0 {
# | entry:
# |   %data = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %data.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %data, align 16
# |   %data1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %data1, ptr %data.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %data.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   call void @llvm.aarch64.sve.st2.nxv16i8.p0(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i1> %2, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2_u16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data.coerce0, <vscale x 8 x i16> %data.coerce1) #0 {
# | entry:
# |   %data = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %data.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %data, align 16
# |   %data1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> }
# | ...
# `---data was truncated (10240/45653) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d9742c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d9742c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d9742c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe4bcb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe4bcb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe4bcb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe4bcb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d97425ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d97425ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d9742438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d973ef2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d973ef2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe4bcb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe4bcb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe4bcb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d973ef2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c (506 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsmul_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsmul_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsmul_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsmul_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsmul_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsmul_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsmul_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsmul_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsmul_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsmul_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsm
# | ...
# `---data was truncated (10240/99585) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555802022eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055580201fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055580202362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5c4fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5c4faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5c4fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5c4fa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555801fb8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555801fb8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555801f9d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555801c4ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555801c4cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5c4fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5c4fa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5c4fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555801c4ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu (507 of 27911)
******************** TEST 'Clang :: CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -o -
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu
# RUN: at line 6
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple spirv64-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK-SPIRV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple spirv64-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -o -
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK-SPIRV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu
# RUN: at line 7
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -disable-O0-optnone -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2 | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu --check-prefixes=OPT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -disable-O0-optnone -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu"
# | target datalayout = "e-m:e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-p10:32:32-p11:32:32-p12:32:32-p13:32:32-p14:32:32-p15:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
# | target triple = "amdgpu-amd-amdhsa"
# | 
# | %struct.S = type { ptr, ptr }
# | %struct.T = type { [2 x ptr] }
# | %struct.SS = type { ptr }
# | 
# | @__hip_cuid_ = addrspace(1) global i8 0
# | @llvm.compiler.used = appending addrspace(1) global [1 x ptr] [ptr addrspacecast (ptr addrspace(1) @__hip_cuid_ to ptr)], section "llvm.metadata"
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind
# | define dso_local amdgpu_kernel void @_Z7kernel1Pi(ptr addrspace(1) noundef %x.coerce) #0 {
# | entry:
# |   %x = alloca ptr, align 8, addrspace(5)
# |   %x.addr = alloca ptr, align 8, addrspace(5)
# |   %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr
# |   store ptr addrspace(1) %x.coerce, ptr addrspace(5) %x, align 8
# |   %x1 = load ptr, ptr addrspace(5) %x, align 8
# |   store ptr %x1, ptr %x.addr.ascast, align 8
# |   %0 = load ptr, ptr %x.addr.ascast, align 8
# |   %arrayidx = getelementptr inbounds i32, ptr %0, i64 0
# |   %1 = load i32, ptr %arrayidx, align 4
# |   %inc = add nsw i32 %1, 1
# |   store i32 %inc, ptr %arrayidx, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind
# | define dso_local amdgpu_kernel void @_Z7kernel2Ri(ptr addrspace(1) noundef nonnull align 4 dereferenceable(4) %x.coerce) #0 {
# | entry:
# |   %x = alloca ptr, align 8, addrspace(5)
# |   %x.addr = alloca ptr, align 8, addrspace(5)
# |   %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr
# |   store ptr addrspace(1) %x.coerce, ptr addrspace(5) %x, align 8
# |   %x1 = load ptr, ptr addrspace(5) %x, align 8
# |   store ptr %x1, ptr %x.addr.ascast, align 8
# |   %0 = load ptr, ptr %x.addr.ascast, align 8, !nonnull !3, !align !4
# |   %1 = load i32, ptr %0, align 4
# |   %inc = add nsw i32 %1, 1
# |   store i32 %inc, ptr %0, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind
# | define dso_local amdgpu_kernel void @_Z7kernel3PU3AS2iPU3AS1i(ptr addrspace(2) noundef %x, ptr addrspace(1) noundef %y) #0 {
# | entry:
# |   %x.addr = alloca ptr addrspace(2), align 8, addrspace(5)
# |   %y.addr = alloca ptr addrspace(1), align 8, addrspace(5)
# |   %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr
# |   %y.addr.ascast = addrspacecast ptr addrspace(5) %y.addr to ptr
# |   store ptr addrspace(2) %x, ptr %x.addr.ascast, align 8
# |   store ptr addrspace(1) %y, ptr %y.addr.ascast, align 8
# |   %0 = load ptr addrspace(2), ptr %x.addr.ascast, align 8
# |   %arrayidx = getelementptr inbounds i32, ptr addrspace(2) %0, i64 0
# |   %1 = load i32, ptr addrspace(2) %arrayidx, align 4
# |   %2 = load ptr addrspace(1), ptr %y.addr.ascast, align 8
# |   %arrayidx1 = getelementptr inbounds i32, ptr addrspace(1) %2, i64 0
# |   store i32 %1, ptr addrspace(1) %arrayidx1, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: convergent mustprogress noinline nounwind
# | define dso_local void @_Z4funcPi(ptr noundef %x) #1 {
# | entry:
# |   %x.addr = alloca ptr, align 8, addrspace(5)
# |   %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr
# |   store ptr %x, ptr %x.addr.ascast, align 8
# |   %0 = load ptr, ptr %x.addr.ascast, align 8
# |   %arrayidx = getelementptr inbounds i32, ptr %0, i64 0
# |   %1 = load i32, ptr %arrayidx, align 4
# |   %inc = add nsw i32 %1, 1
# |   store i32 %inc, ptr %arrayidx, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind
# | define dso_local amdgpu_kernel void @_Z7kernel41S(ptr addrspace(4) noundef byref(%struct.S) align 8 %0) #0 {
# | entry:
# |   %s = alloca %struct.S, align 8, addrspace(5)
# |   call void @llvm.memcpy.p5.p4.i64(ptr addrspace(5) align 8 %s, ptr addrspace(4) align 8 %0, i64 16, i1 false)
# |   %s.ascast = addrspacecast ptr addrspace(5) %s to ptr
# |   %x = getelementptr inbounds nuw %struct.S, ptr %s.ascast, i32 0, i32 0
# |   %1 = load ptr, ptr %x, align 8
# |   %arrayidx = getelementptr inbounds i32, ptr %1, i64 0
# |   %2 = load i32, ptr %arrayidx, align 4
# |   %inc = add nsw i32 %2, 1
# |   store i32 %inc, ptr %arrayidx, align 4
# |   %y = getelementptr inbounds nuw %struct.S, ptr %s.ascast, i32 0, i32 1
# |   %3 = load ptr, ptr %y, align 8
# |   %arrayidx1 = getelementptr inbounds float, ptr %3, i64 0
# |   %4 = load float, ptr %arrayidx1, align 4
# |   %add = fadd contract float %4, 1.000000e+00
# |   store float %add, ptr %arrayidx1, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.memcpy.p5.p4.i64(ptr addrspace(5) noalias writeonly captures(none), ptr addrspace(4) noalias readonly captures(none), i64, i1 immarg) #2
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind
# | define dso_local amdgpu_kernel void @_Z7kernel5P1S(ptr addrspace(1) noundef %s.coerce) #0 {
# | entry:
# |   %s = alloca ptr, align 8, addrspace(5)
# |   %s.addr = alloca ptr, align 8, addrspace(5)
# |   %s.addr.ascast = addrspacecast ptr addrspace(5) %s.addr to ptr
# |   store ptr addrspace(1) %s.coerce, ptr addrspace(5) %s, align 8
# |   %s1 = load ptr, ptr addrspace(5) %s, align 8
# |   store ptr %s1, ptr %s.addr.ascast, align 8
# |   %0 = load ptr, ptr %s.addr.ascast, align 8
# |   %x = getelementptr inbounds nuw %struct.S, ptr %0, i32 0, i32 0
# |   %1 = load ptr, ptr %x, align 8
# |   %arrayidx = getelementptr inbounds i32, ptr %1, i64 0
# |   %2 = load i32, ptr %arrayidx, align 4
# |   %inc = add nsw i32 %2, 1
# |   store i32 %inc, ptr %arrayidx, align 4
# |   %3 = load ptr, ptr %s.addr.ascast, align 8
# |   %y = getelementptr inbounds nuw %struct.S, ptr %3, i32 0, i32 1
# |   %4 = load ptr, ptr %y, align 8
# |   %arrayidx2 = getelementptr inbounds float, ptr %4, i64 0
# |   %5 = load float, ptr %arrayidx2, align 4
# |   %add = fadd contract float %5, 1.000000e+00
# |   store float %add, ptr %arrayidx2, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind
# | define dso_local amdgpu_kernel void @_Z7kernel61T(ptr addrspace(4) noundef byref(%struct.T) align 8 %0) #0 {
# | entry:
# |   %t = alloca %struct.T, align 8, addrspace(5)
# |   call void @llvm.memcpy.p5.p4.i64(ptr addrspace(5) align 8 %t, ptr addrspace(4) align 8 %0, i64 16, i1 false)
# |   %t.ascast = addrspacecast ptr addrspace(5) %t to ptr
# |   %x = getelementptr inbounds nuw %struct.T, ptr %t.ascast, i32 0, i32 0
# |   %arrayidx = getelementptr inbounds [2 x ptr], ptr %x, i64 0, i64 0
# |   %1 = load ptr, ptr %arrayidx, align 8
# |   %arrayidx1 = getelementptr inbounds float, ptr %1, i64 0
# |   %2 = load float, ptr %arrayidx1, align 4
# |   %add = fadd contract float %2, 1.000000e+00
# |   store float %add, ptr %arrayidx1, align 4
# |   %x2 = getelementptr inbounds nuw %struct.T, ptr %t.ascast, i32 0, i32 0
# |   %arrayidx3 = getelementptr inbounds [2 x ptr], ptr %x2, i64 0, i64 1
# |   %3 = load ptr, ptr %arrayidx3, align 8
# |   %arrayidx4 = getelementptr inbounds float, ptr %3, i64 0
# |   %4 = load float, ptr %arrayidx4, align 4
# |   %add5 = fadd contract float %4, 2.000000e+00
# |   store float %add5, ptr %arrayidx4, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind
# | define dso_local amdgpu_kernel void @_Z7kernel7Pi(ptr addrspace(1) noalias noundef %x.coerce) #0 {
# | entry:
# |   %x = alloca ptr, align 8, addrspace(5)
# |   %x.addr = alloca ptr, align 8, addrspace(5)
# |   %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr
# |   store ptr addrspace(1) %x.coerce, ptr addrspace(5) %x, align 8
# |   %x1 = load ptr, ptr addrspace(5) %x, align 8
# |   store ptr %x1, ptr %x.addr.ascast, align 8
# |   %0 = load ptr, ptr %x.addr.ascast, align 8
# |   %arrayidx = getelementptr inbounds i32, ptr %0, i64 0
# |   %1 = load i32, ptr %arrayidx, align 4
# |   %inc = add nsw i32 %1, 1
# |   store i32 %inc, ptr %arrayidx, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind
# | define dso_local amdgpu_kernel void @_Z7kernel82SS(ptr addrspace(1) %a.coerce) #0 {
# | entry:
# |   %a = alloca %struct.SS, align 8, addrspace(5)
# |   %coerce.dive = getelementptr inbounds nuw %struct.SS, ptr addrspace(5) %a, i32 0, i32 0
# |   store ptr addrspace(1) %a.coerce, ptr addrspace(5) %coerce.dive, align 8
# |   %a.ascast = addrspacecast ptr addrspace(5) %a to ptr
# |   %x = getelementptr inbounds nuw %struct.SS, ptr %a.ascast, i32 0, i32 0
# |   %0 = load ptr, ptr %x, align 8
# |   %1 = load float, ptr %0, align 4
# |   %add = fadd contract float %1, 3.000000e+00
# |   store float %add, ptr %0, align 4
# |   ret void
# | }
# | 
# | attributes #0 = { convergent mustprogress noinline norecurse nounwind "amdgpu-flat-work-group-size"="1,1024" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size" }
# | attributes #1 = { convergent mustprogress noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size" }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1}
# | !llvm.ident = !{!2}
# | 
# | !0 = !{i32 1, !"amdhsa_code_object_version", i32 600}
# | !1 = !{i32 1, !"amdgpu_printf_kind", !"hostcall"}
# | !2 = !{!"clang version 24.0.0"}
# | !3 = !{}
# | !4 = !{i64 4}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2
# |  #0 0x0000555ecdec2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555ecdebfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555ecdec362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9a9b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9a9b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9a9b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9a9b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555ecde58bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555ecde58a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555ecde3d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555ecdaece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555ecdaecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9a9b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9a9b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9a9b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555ecdaeca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu --check-prefixes=OPT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu --check-prefixes=OPT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c (508 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsge_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsge_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsge_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsge_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsge_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsge_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsge_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsge_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsge_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsge_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsge_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsge.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> %0, 
# | ...
# `---data was truncated (10240/95081) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d354347eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d354344e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d35434862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0bc8449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0bc84a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0bc8449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0bc8431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d3542ddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d3542dda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d3542c28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d353f71e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d353f71b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0bc8432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0bc84330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0bc84330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d353f71a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c (509 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 31)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.cnth(i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_1() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_2() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_3() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_4() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 4)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_5() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 5)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_6() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 6)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_7() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_8() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 8)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_9() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 9)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_10() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 10)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_11() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 11)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_12() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 12)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_13() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 13)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_14() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 29)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_15() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 30)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_16() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 31)
# |   ret i64 %0
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055b6bd583eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b6bd580e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b6bd58462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4deef05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4deef5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4deef05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4deeeed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b6bd519bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b6bd519a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b6bd4fe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b6bd1ade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b6bd1adb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4deeeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4deeeef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4deeeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b6bd1ada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c (510 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8mf8x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8mf4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_u8mf8x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_u8mf4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_u8mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_u8m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple,
# | ...
# `---data was truncated (10240/27986) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cb052b2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cb052afe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cb052b362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f75e6533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f75e658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f75e6533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f75e651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb05248bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cb05248a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cb0522d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cb04edce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cb04edcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f75e651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f75e651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f75e651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb04edca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c (511 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsmul_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsmul_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsmul_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsmul_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsmul_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsmul_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsmul_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsmul_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsmul_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/225205) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562424582eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056242457fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056242458362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f22c3249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f22c32a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f22c3249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f22c3231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562424518bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562424518a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005624244fd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005624241ace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005624241acb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f22c3232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f22c32330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f22c32330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005624241aca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c (512 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svneg_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.neg.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.neg.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svneg_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.neg.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.neg.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svneg_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.neg.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.neg.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svneg_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.neg.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.neg.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svneg_s8_m(<vscale x 16 x i8> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i8>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.neg.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svneg_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.neg.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svneg_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.neg.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svneg_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.neg.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svneg_s8_x(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.neg.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svneg_s16_x(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.neg.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svneg_s32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1
# | ...
# `---data was truncated (10240/20016) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055cd016e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cd016e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cd016e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9954d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9954d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9954d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9954d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cd0167bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cd0167ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cd016608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cd0130fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cd0130fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9954d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9954d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9954d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cd0130fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c (513 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b8_s32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.whilelt.nxv16i1.i32(i32 %0, i32 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.whilelt.nxv16i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b16_s32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.whilelt.nxv8i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.whilelt.nxv8i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b32_s32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.whilelt.nxv4i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.whilelt.nxv4i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b64_s32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.whilelt.nxv2i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.whilelt.nxv2i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b8_u32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.whilelo.nxv16i1.i32(i32 %0, i32 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.whilelo.nxv16i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b16_u32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.whilelo.nxv8i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.whilelo.nxv8i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b32_u32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.whilelo.nxv4i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.whilelo.nxv4i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b64_u32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.whilelo.nxv2i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.whilelo.nxv2i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b8_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.whilelt.nxv16i1.i64(i64 %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.whilelt.nxv16i1.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b16_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.whilelt.nxv8i1.i64(i64 %0, i64 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.whilelt.nxv8i1.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b32_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.whilelt.nxv4i1.i64(i64 %0, i64 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.whilelt.nxv4i1.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b64_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.whilelt.nxv2i1.i64(i64 %0, i64 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.whilelt.nxv2i1.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b8_u64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/13340) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ac446fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ac446f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ac446fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2dfce1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2dfce725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2dfce1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2dfce03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac44692bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ac44692a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ac446778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ac44326e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ac44326b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2dfce04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2dfce050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2dfce050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac44326a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c (514 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vzext_vf2_u16mf4(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vzext_vf2_u16mf2(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vzext_vf2_u16m1(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vzext_vf2_u16m2(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vzext_vf2_u16m4(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vzext_vf2_u16m8(<vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf2_u32mf2(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf2_u32m1(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf2_u32m2(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vzext_vf2_u32m4(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vzext_vf2_u32m8(<vscale x 16 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf2_u64m1(<vscale x 1 x i32> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf2_u64m2(<vscale x 2 x i32> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>,
# | ...
# `---data was truncated (10240/28571) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005565856caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005565856c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005565856cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1ecf849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1ecf8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1ecf849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1ecf831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556585660bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556585660a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005565856458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005565852f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005565852f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1ecf832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1ecf8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1ecf8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005565852f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c (515 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzip2_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zip2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.zip2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzip2_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zip2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.zip2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzip2_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zip2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.zip2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzip2_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zip2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.zip2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzip2_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zip2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzip2_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zip2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzip2_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zip2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzip2_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zip2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svzip2_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.zip2.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.zip2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svzip2_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.zip2.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.zip2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svzip2_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.zip2.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.zip2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svzip2_b8(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.zip2.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.zip2.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svzip2_b16(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.zip2.b16(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | ...
# `---data was truncated (10240/13404) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e470e57eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e470e54e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e470e5862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f75ac305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f75ac35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f75ac305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f75ac2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e470dedbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e470deda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e470dd28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e470a81e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e470a81b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f75ac2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f75ac2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f75ac2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e470a81a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c (516 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svsetffr() #0 {
# | entry:
# |   call void @llvm.aarch64.sve.setffr()
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.sve.setffr() #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000561a3bbe6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561a3bbe3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561a3bbe762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b6a049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b6a0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b6a049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b6a031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a3bb7cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561a3bb7ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561a3bb618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561a3b810e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561a3b810b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5b6a032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b6a0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b6a0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a3b810a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c (517 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vslidedown_vx_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vslidedown_vx_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vslidedown_vx_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vslidedown_vx_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vslidedown_vx_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vslidedown_vx_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vslidedown_vx_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vslidedown_vx_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vslidedown_vx_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %src, i64 noundef %offset, i64 no
# | ...
# `---data was truncated (10240/287205) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555e2976beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555e29768e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555e2976c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe6db133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe6db18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe6db133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe6db11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555e29701bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555e29701a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555e296e68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555e29395e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555e29395b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe6db11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe6db11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe6db11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555e29395a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c (518 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f16m1x3(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f16m2x3(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f32m1x3(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f32m2x3(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f64m1x3(ptr noundef %base, <vscale x 1 x i32
# | ...
# `---data was truncated (10240/99762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005613a58eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005613a58ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005613a58ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd78561bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd7856725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd78561ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd785603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005613a5884bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005613a5884a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005613a58698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005613a5518e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005613a5518b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd785604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd7856050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd7856050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005613a5518a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon/store.c (519 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/store.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | %struct.float64x1x2_t = type { [2 x <1 x double>] }
# | %struct.float64x1x3_t = type { [3 x <1 x double>] }
# | %struct.float64x1x4_t = type { [4 x <1 x double>] }
# | %struct.mfloat8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.mfloat8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.mfloat8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.poly64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.poly64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.poly64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.float64x2x2_t = type { [2 x <2 x double>] }
# | %struct.float64x2x3_t = type { [3 x <2 x double>] }
# | %struct.float64x2x4_t = type { [4 x <2 x double>] }
# | %struct.mfloat8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.mfloat8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.mfloat8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.poly64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.poly64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.poly64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.float16x4x2_t = type { [2 x <4 x half>] }
# | %struct.float32x2x2_t = type { [2 x <2 x float>] }
# | %struct.poly16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.poly8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.int16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.int32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.int64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.int8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.uint16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.uint32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.uint64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.uint8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.float16x4x3_t = type { [3 x <4 x half>] }
# | %struct.float32x2x3_t = type { [3 x <2 x float>] }
# | %struct.poly16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.poly8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.int16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.int32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.int64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.int8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.uint16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.uint32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.uint64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.uint8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.float16x4x4_t = type { [4 x <4 x half>] }
# | %struct.float32x2x4_t = type { [4 x <2 x float>] }
# | %struct.poly16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.poly8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.int16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.int32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.int64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.int8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.uint16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.uint32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.uint64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.uint8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.float16x8x2_t = type { [2 x <8 x half>] }
# | %struct.float32x4x2_t = type { [2 x <4 x float>] }
# | %struct.poly16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.poly8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.int16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.int32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.int64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.int8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.uint16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.uint32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.uint64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.uint8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.float16x8x3_t = type { [3 x <8 x half>] }
# | %struct.float32x4x3_t = type { [3 x <4 x float>] }
# | %struct.poly16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.poly8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.int16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.int32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.int64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.int8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.uint16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.uint32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.uint64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.uint8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.float16x8x4_t = type { [4 x <8 x half>] }
# | %struct.float32x4x4_t = type { [4 x <4 x float>] }
# | %struct.poly16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.poly8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.int16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.int32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.int64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.int8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.uint16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.uint32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.uint64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.uint8x16x4_t = type { [4 x <16 x i8>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_f16(ptr noundef %a, <4 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %__s1 = alloca <4 x half>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   %0 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <4 x half>
# |   store <4 x half> %3, ptr %1, align 2
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_f32(ptr noundef %a, <2 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %__s1 = alloca <2 x float>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <2 x float>
# |   store <2 x float> %3, ptr %1, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_f64(ptr noundef %a, <1 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %__s1 = alloca <1 x double>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   %0 = load <1 x double>, ptr %b.addr, align 8
# |   store <1 x double> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <1 x double>
# |   store <1 x double> %3, ptr %1, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_mf8(ptr noundef %a, <8 x i8> %val) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %val.addr = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <8 x i8> %val, ptr %val.addr, align 8
# |   %0 = load <8 x i8>, ptr %val.addr, align 8
# |   store <8 x i8> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   store <8 x i8> %2, ptr %1, align 1
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_p16(ptr noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   %__s1 = alloca <4 x i16>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <4 x i16>
# |   store <4 x i16> %3, ptr %1, align 2
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_p64(ptr noundef %ptr, <1 x i64> noundef %val) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %val.addr = alloca <1 x i64>, align 8
# |   %__s1 = alloca <1 x i64>, align 8
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store <1 x i64> %val, ptr %val.addr, align 8
# |   %0 = load <1 x i64>, ptr %val.addr, align 8
# |   store <1 x i64> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %ptr.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <1 x i64>
# |   store <1 x i64> %3, ptr %1, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_p8(ptr noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   store <8 x i8> %2, ptr %1, align 1
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1q_f16(ptr noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <8 x half>, align 16
# |   %__s1 = alloca <8 x half>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %__s1, align 16
# |   %3 = bitcast <16 x i8> %2 to <8 x half>
# |   store <8 x half> %3, ptr %1, align 2
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1q_f32(ptr noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <4 x float>, align 16
# |   %__s1 = alloca <4 x float>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x float> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %__s1, align 16
# |   %3 = bitcast <16 x i8> %2 to <4 x float>
# |   store <4 x float> %3, ptr %1, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1q_f64(ptr noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <2 x double>, align 16
# |   %__s1 = alloca <2 x double>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <2 x double>, ptr %b.addr, align 16
# |   store <2 x double> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr
# | ...
# `---data was truncated (10240/446007) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# |  #0 0x0000562122e68eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562122e65e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562122e6962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f63b1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f63b1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f63b1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f63b1b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562122dfebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562122dfea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562122de38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562122a92e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562122a92b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f63b1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f63b1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f63b1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562122a92a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c (520 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfwmacc_4x4x4_f32mf2(<vscale x 1 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 4 x bfloat>, <vscale x 1 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfwmacc_4x4x4_f32m1(<vscale x 2 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 4 x bfloat>, <vscale x 2 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfwmacc_4x4x4_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfwmacc_4x4x4_f32m4(<vscale x 8 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfwmacc_4x4x4_f32m8(<vscale x 16 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(<vscale x 16 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 4 x bfloat>, <vscale x 16 x bfloat>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvfwmaccqqq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvfwmaccqqq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559302bffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559302bfce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559302c0062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc1eeb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc1eeb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc1eeb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc1eeaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559302b95bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559302b95a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559302b7a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559302829e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559302829b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc1eeaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc1eeaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc1eeaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559302829a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c (521 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei16_v_i8mf8x6
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e7eb331eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e7eb32ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e7eb33262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f18edd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f18edd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f18edd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f18edd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e7eb2c7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e7eb2c7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e7eb2ac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e7eaf5be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e7eaf5bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f18edd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f18edd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f18edd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e7eaf5ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c (522 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_f16mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_f16mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_f16m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_i16mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_i16mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_i16m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_u16mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_u16mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_u16m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_f16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsse
# | ...
# `---data was truncated (10240/20441) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ea81ba6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ea81ba3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ea81ba762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f05e8b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f05e8b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f05e8b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f05e8b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ea81b3cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ea81b3ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ea81b218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ea817d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ea817d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f05e8b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f05e8b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f05e8b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ea817d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c (523 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svreinterpret_svbool_svcnt(target("aarch64.svcount") %cnt) #0 {
# | entry:
# |   %cnt.addr = alloca target("aarch64.svcount"), align 2
# |   store target("aarch64.svcount") %cnt, ptr %cnt.addr, align 2
# |   %0 = load target("aarch64.svcount"), ptr %cnt.addr, align 2
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.from.svcount(target("aarch64.svcount") %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.from.svcount(target("aarch64.svcount")) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local target("aarch64.svcount") @test_svreinterpret_svcnt_svbool(<vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = call target("aarch64.svcount") @llvm.aarch64.sve.convert.to.svcount(<vscale x 16 x i1> %0)
# |   ret target("aarch64.svcount") %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare target("aarch64.svcount") @llvm.aarch64.sve.convert.to.svcount(<vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000559bcdbeaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559bcdbe7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559bcdbeb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007effca849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007effca8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007effca849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007effca831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559bcdb80bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559bcdb80a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559bcdb658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559bcd814e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559bcd814b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007effca832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007effca8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007effca8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559bcd814a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c (524 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vslide1down_vx_i8mf8(<vscale x 1 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vslide1down_vx_i8mf4(<vscale x 2 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vslide1down_vx_i8mf2(<vscale x 4 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vslide1down_vx_i8m1(<vscale x 8 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vslide1down_vx_i8m2(<vscale x 16 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vslide1down_vx_i8m4(<vscale x 32 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vslide1down_vx_i8m8(<vscale x 64 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vslide1down_vx_i16mf4(<vscale x 1 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vslide1down_vx_i16mf2(<vscale x 2 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vslide1down.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vslide1down.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vslide1down_vx_i16m1(<vscale x 4 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vslide1down.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vslide1down.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vslide1down_vx_i16m2(<vscale x 8 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale 
# | ...
# `---data was truncated (10240/87191) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559e06468eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559e06465e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559e0646962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f178e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f178e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f178e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f178e51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e063febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559e063fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559e063e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559e06092e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559e06092b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f178e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f178e51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f178e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e06092a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c (525 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005607187d9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005607187d6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005607187da62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f542a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f542a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f542a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f542a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056071876fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056071876fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005607187548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560718403e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560718403b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f542a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f542a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f542a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560718403a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c (526 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclamp_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.uclamp.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uclamp.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclamp_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.uclamp.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uclamp.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclamp_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.uclamp.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uclamp.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svclamp_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   %op3.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x i64> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.uclamp.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uclamp.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055df6b229eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055df6b226e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055df6b22a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f93a0133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f93a018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f93a0133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f93a011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055df6b1bfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055df6b1bfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055df6b1a48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055df6ae53e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055df6ae53b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f93a011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f93a011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f93a011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055df6ae53a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c (527 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsra_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsra_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsra_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsra_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsra_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsra_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsra_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsra_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsra_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %o
# | ...
# `---data was truncated (10240/223855) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005558ef595eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005558ef592e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005558ef59662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faecc849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faecc8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faecc849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faecc831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005558ef52bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005558ef52ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005558ef5108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005558ef1bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005558ef1bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faecc832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faecc8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faecc8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005558ef1bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c (528 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_tu(<vscale x 1
# | ...
# `---data was truncated (10240/295853) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb6ae2beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fb6ae28e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fb6ae2c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2238533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f223858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2238533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f223851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb6adc1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fb6adc1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fb6ada68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fb6aa55e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fb6aa55b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f223851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f223851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f223851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb6aa55a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c (529 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsubr_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.subr.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.subr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsubr_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.subr.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.subr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsubr_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svsubr_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.subr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.subr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsubr_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.subr.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsubr_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.subr.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsubr_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svsubr_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.subr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsubr_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vsc
# | ...
# `---data was truncated (10240/72568) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e3894e6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e3894e3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e3894e762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fda59933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fda5998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fda59933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fda5991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e38947cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e38947ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e3894618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e389110e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e389110b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fda5991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fda5991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fda5991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e389110a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c (530 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsrl_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsrl_vx_u8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsrl_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsrl_vx_u8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsrl_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsrl_vx_u8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsrl_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsrl_vx_u8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsrl_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsrl_vx_u8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsrl_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/98351) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055db92891eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055db9288ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055db9289262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f914b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f914b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f914b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f914b31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055db92827bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055db92827a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055db9280c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055db924bbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055db924bbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f914b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f914b31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f914b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055db924bba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c (531 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vle16ff_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(<vscale x 1 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(<vscale x 1 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vle16ff_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(<vscale x 2 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 2 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(<vscale x 2 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vle16ff_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(<vscale x 4 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 4 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(<vscale x 4 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vle16ff_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(<vscale x 8 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(<vscale x 8 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vle16ff_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(<vscale x 16 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 16 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 16 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(<vscale x 16 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vle16ff_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(<vscale x 32 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 32 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 32 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(<vscale x 32 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16ff_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(<vscale x 1 x i16> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i16>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i16>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 1 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(<vscale x 1 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16ff_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(<vscale x 2 x i16> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x i16>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i16>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 2 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(<vscale x
# | ...
# `---data was truncated (10240/93466) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558daea5aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558daea57e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558daea5b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f44d1333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f44d138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f44d1333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f44d131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558dae9f0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558dae9f0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558dae9d58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558dae684e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558dae684b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f44d131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44d131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44d131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558dae684a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c (532 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpne_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpne_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpne_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpne_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpne_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpne_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpne_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpne_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_r
# | ...
# `---data was truncated (10240/34127) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000563d2c9f6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563d2c9f3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563d2c9f762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f26bb449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f26bb4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f26bb449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f26bb431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d2c98cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563d2c98ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563d2c9718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563d2c620e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563d2c620b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f26bb432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f26bb4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f26bb4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d2c620a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c (533 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulh_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulh_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulh_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulh_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulh_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulh_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulh_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulh_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulh_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x
# | ...
# `---data was truncated (10240/222925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561713dbdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561713dbae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561713dbe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007effcec1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007effcec725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007effcec1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007effcec03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561713d53bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561713d53a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561713d388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005617139e7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005617139e7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007effcec04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007effcec050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007effcec050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005617139e7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c (534 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_u64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_u64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tu
# | ...
# `---data was truncated (10240/16560) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b2defe9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b2defe6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b2defea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa98af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa98af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa98af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa98af1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b2def7fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b2def7fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b2def648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b2dec13e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b2dec13b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa98af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa98af1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa98af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b2dec13a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c (535 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1>, ptr, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_1(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_2(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_3(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_4(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_5(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_6(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 8)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_7(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 9)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 10)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_9(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 11)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_10(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 12)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_11(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 13)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_vnum(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i16>, ptr %1, i64 %2
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %3, ptr %4, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_gather_u32base(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prfh.gather.scalar.offset.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1, i64 0, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.aarch64.sve.prfh.gather.scalar.offset.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64, i32 immarg) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_gather_u64base(<vscale x 16 x i1> %pg, <vscale x 2 x i64
# | ...
# `---data was truncated (10240/18010) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055fd043efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fd043ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fd043f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f61fad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f61fad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f61fad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f61fad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd04385bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fd04385a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fd0436a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fd04019e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fd04019b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f61fad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61fad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61fad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd04019a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c (536 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1uh_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1uh_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1uh_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1uh_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1uh_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1uh_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1uh_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1uh_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560740bbbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560740bb8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560740bbc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa269c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa269ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa269c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa269c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560740b51bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560740b51a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560740b368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005607407e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005607407e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa269c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa269c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa269c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607407e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c (537 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvtnt_bf16_f32_x(<vscale x 8 x bfloat> %even, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %even.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 8 x bfloat> %even, ptr %even.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %even.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fcvtnt.bf16f32.v2(<vscale x 8 x bfloat> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fcvtnt.bf16f32.v2(<vscale x 8 x bfloat>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvtnt_bf16_f32_m(<vscale x 8 x bfloat> %even, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %even.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 8 x bfloat> %even, ptr %even.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %even.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fcvtnt.bf16f32.v2(<vscale x 8 x bfloat> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005651c7107eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005651c7104e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005651c710862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f703dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f703dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f703dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f703dd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005651c709dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005651c709da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005651c70828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005651c6d31e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005651c6d31b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f703dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f703dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f703dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005651c6d31a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c (538 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmla_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %6 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmla.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fnmla.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svnmla_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %6 = call <vscale x 4 x float> @llvm.aarch64.sve.fnmla.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %5, <vscale x 4 x float> %2, <vscale x 4 x float> %3)
# |   ret <vscale x 4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fnmla.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svnmla_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %6 = call <vscale x 2 x double> @llvm.aarch64.sve.fnmla.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %5, <vscale x 2 x double> %2, <vscale x 2 x double> %3)
# |   ret <vscale x 2 x double> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fnmla.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmla_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmla.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svnmla_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fnmla.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svnmla_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fnmla.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmla_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmla.u.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind w
# | ...
# `---data was truncated (10240/26173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560c61e3deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560c61e3ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560c61e3e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd1f2733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd1f278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd1f2733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd1f271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c61dd3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560c61dd3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560c61db88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560c61a67e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560c61a67b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd1f271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd1f271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd1f271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c61a67a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c (539 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f16m1x8(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f32m1x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f64m1x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef
# | ...
# `---data was truncated (10240/69988) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556fae87deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556fae87ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556fae87e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec90c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec90ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec90c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec90c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556fae813bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556fae813a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556fae7f88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556fae4a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556fae4a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fec90c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec90c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec90c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556fae4a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c (540 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccsu_vv_i16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccsu_vx_i16mf4(<vscale x 1 x i16> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccsu_vv_i16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccsu_vx_i16mf2(<vscale x 2 x i16> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccsu_vv_i16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccsu_vx_i16m1(<vscale x 4 x i16> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccsu_vv_i16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccsu_vx_i16m2(<vscale x 8 x i16> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccsu_vv_i16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store 
# | ...
# `---data was truncated (10240/79861) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bcd75e0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bcd75dde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bcd75e162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f01c6e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f01c6ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f01c6e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f01c6e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bcd7576bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bcd7576a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bcd755b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bcd720ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bcd720ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f01c6e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f01c6e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f01c6e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bcd720aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c (541 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_bf16m4x2_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005621039d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005621039d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005621039d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa18d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa18d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa18d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa18d631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056210396bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056210396ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005621039508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005621035ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005621035ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa18d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa18d6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa18d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005621035ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c (542 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintm_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintm.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frintm.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintm_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintm.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frintm.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintm_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintm.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frintm.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintm_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.frintm.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintm_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frintm.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintm_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frintm.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintm_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintm.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintm_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintm.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintm_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintm.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055f5d1381eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f5d137ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f5d138262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe3d1d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe3d1d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe3d1d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe3d1ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f5d1317bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f5d1317a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f5d12fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f5d0fabe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f5d0fabb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe3d1ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe3d1cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe3d1cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f5d0faba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c (543 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willret
# | ...
# `---data was truncated (10240/365423) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564bf496eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564bf496be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564bf496f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3e09249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3e092a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3e09249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3e09231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564bf4904bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564bf4904a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564bf48e98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564bf4598e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564bf4598b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3e09232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3e092330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3e092330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564bf4598a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c (544 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_f32mf2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_f32m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_f32m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_i32mf2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_i32m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_i32m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_u32mf2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_u32m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_u32m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_f32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_f32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_f32m2x3_m(<vscale x 4 x i1> %mask, ptr noun
# | ...
# `---data was truncated (10240/17567) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563308d42eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563308d3fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563308d4362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b16533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b1658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b16533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b1651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563308cd8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563308cd8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563308cbd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056330896ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056330896cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5b1651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b1651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b1651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056330896ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll (545 of 27911)
******************** TEST 'Clang :: CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-diagnostic-handler-remarks-with-hotness.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-diagnostic-handler-remarks-with-hotness.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-diagnostic-handler-remarks-with-hotness.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll
# |  #0 0x000055d60817aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d608177e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d60817b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3c6a41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3c6a4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3c6a41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3c6a403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d608110bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d608110a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d6080f58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d607da4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d607da4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3c6a404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3c6a4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3c6a4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d607da4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c (546 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svset2_s8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %x.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 16 x i8> %x, ptr %x.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %x.addr, align 16
# |   %4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %3, 1
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svset2_s16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %x.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 8 x i16> %x, ptr %x.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %x.addr, align 16
# |   %4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %3, 0
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svset2_s32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1, <vscale x 4 x i32> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %4 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %3, 1
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svset2_s64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1, <vscale x 2 x i64> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %x.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 2 x i64> %x, ptr %x.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %x.addr, align 16
# |   %4 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %3, 0
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svset2_u8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %x.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 16 x i8> %x, ptr %x.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %x.addr, align 16
# |   %4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %3, 1
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svset2_u16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %x.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 8 x i16> %x, ptr %x.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %x.addr, align 16
# |   %4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %3, 0
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svset2_u32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1, <vscale x 4 x i32> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %4 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %3, 1
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svset2_u64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1, <vscale x 2 x i64> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %x.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 2 x i64> %x, ptr %x.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %x.addr, align 16
# |   %4 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %3, 0
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x ha
# | ...
# `---data was truncated (10240/18235) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ba8ca28eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ba8ca25e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ba8ca2962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe022933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe02298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe022933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe02291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba8c9bebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ba8c9bea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ba8c9a38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ba8c652e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ba8c652b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe02291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe02291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe02291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba8c652a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-vector-bitwise-ops.c (547 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-bitwise-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @and_bool(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i1>, align 2
# |   %b.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %a, ptr %a.addr, align 2
# |   store <vscale x 16 x i1> %b, ptr %b.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %a.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %b.addr, align 2
# |   %and = and <vscale x 16 x i1> %0, %1
# |   ret <vscale x 16 x i1> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @and_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %and = and <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @and_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %and = and <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @and_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %and = and <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @and_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %and = and <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @and_u8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %and = and <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @and_u16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %and = and <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @and_u32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %and = and <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @and_u64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %and = and <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @or_bool(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i1>, align 2
# |   %b.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %a, ptr %a.addr, align 2
# |   store <vscale x 16 x i1> %b, ptr %b.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %a.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %b.addr, align 2
# |   %or = or <vscale x 16 x i1> %0, %1
# |   ret <vscale x 16 x i1> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @or_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %or = or <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @or_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %or = or <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @or_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %or = or <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @or_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %or = or <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @or_u8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %or = or <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @or_u16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %or = or <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @or_u32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %or = or <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @or_u64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %or = or <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @xor_bool(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) #0 {
# | entry:
# |   %a.addr = alloca <vsca
# | ...
# `---data was truncated (10240/18831) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055c8feafdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c8feafae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c8feafe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff9ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff9ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff9ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff9ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c8fea93bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c8fea93a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c8fea788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c8fe727e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c8fe727b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007eff9ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff9ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff9ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c8fe727a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c (548 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e5fb58ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e5fb589e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e5fb58d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff48d81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff48d8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff48d81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff48d803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e5fb522bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e5fb522a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e5fb5078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e5fb1b6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e5fb1b6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff48d804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff48d8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff48d8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e5fb1b6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c (549 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_f64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_f64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_f64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_i64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_i64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_i64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_u64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale 
# | ...
# `---data was truncated (10240/60817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fc8633beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fc86338e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fc8633c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff5de133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff5de18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff5de133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff5de11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fc862d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fc862d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fc862b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fc85f65e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fc85f65b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff5de11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff5de11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff5de11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fc85f65a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c (550 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svabd_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.sabd.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.sabd.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svabd_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.sabd.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sabd.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svabd_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.sabd.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sabd.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svabd_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.sabd.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sabd.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svabd_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.uabd.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uabd.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svabd_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.uabd.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uabd.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svabd_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.uabd.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uabd.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svabd_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale
# | ...
# `---data was truncated (10240/74195) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000561391d5beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561391d58e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561391d5c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7af5733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7af578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7af5733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7af571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561391cf1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561391cf1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561391cd68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561391985e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561391985b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7af571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7af571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7af571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561391985a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c (551 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_cvtn_f16_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fcvtn.x2.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fcvtn.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_cvtn_bf16_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.bfcvtn.x2(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.bfcvtn.x2(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_qcvtn_u8_u32_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %zn.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 1
# |   %7 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 2
# |   %8 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 3
# |   %9 = call <vscale x 16 x i8> @llvm.aarch64.sve.uqcvtn.x4.nxv4i32(<vscale x 4 x i32> %5, <vscale x 4 x i32> %6, <vscale x 4 x i32> %7, <vscale x 4 x i32> %8)
# |   ret <vscale x 16 x i8> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uqcvtn.x4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_qcvtn_u16_u64_x4(<vscale x 2 x i64> %zn.coerce0, <vscale x 2 x i64> %zn.coerce1, <vscale x 2 x i64> %zn.coerce2, <vscale x 2 x i64> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, <vscale x 2 x i64> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %zn.coerce3, 3
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 1
# |   %7 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 2
# |   %8 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 3
# |   %9 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqcvtn.x4.nxv2i64(<vscale x 2 x i64> %5, <vscale x 2 x i64> %6, <vscale x 2 x i64> %7, <vscale x 2 x i64> %8)
# |   ret <vscale x 8 x i16> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqcvtn.x4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_qcvtn_s8_s32_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %zn.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 1
# |   %7 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 2
# |   %8 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 3
# |   %9 = call <vscale x 16 x i8> @llvm.aarch64.sve.sqcvtn.x4.nxv4i32(<vscale x 4 x i32> %5, <vscale x 4 x i32> %6, <vscale x 4 x i32> %7, <vscale x 4 x i32> %8)
# |   ret <vscale x 16 x i8> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.sqcvtn.x4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_loc
# | ...
# `---data was truncated (10240/17734) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000558733c77eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558733c74e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558733c7862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8a90a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8a90a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8a90a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8a90a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558733c0dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558733c0da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558733bf28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005587338a1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005587338a1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8a90a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8a90a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8a90a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005587338a1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c (552 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmaxnm_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fmaxnm.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %4, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fmaxnm.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmaxnm_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %4, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svmaxnm_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fmaxnm.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %4, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fmaxnm.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmaxnm_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fmaxnm.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmaxnm_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svmaxnm_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.fmaxnm.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmaxnm_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fmaxnm.u.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fmaxnm.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmaxnm_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.u.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.u.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svmaxnm_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.ad
# | ...
# `---data was truncated (10240/22107) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000564807eb4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564807eb1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564807eb562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7a09b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7a09b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7a09b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7a09b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564807e4abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564807e4aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564807e2f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564807adee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564807adeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7a09b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7a09b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7a09b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564807adea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c (553 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfslide1down_vf_f16mf4(<vscale x 1 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfslide1down_vf_f16mf2(<vscale x 2 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfslide1down_vf_f16m1(<vscale x 4 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfslide1down_vf_f16m2(<vscale x 8 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfslide1down_vf_f16m4(<vscale x 16 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfslide1down_vf_f16m8(<vscale x 32 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfslide1down_vf_f32mf2(<vscale x 1 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfslide1down_vf_f32m1(<vscale x 2 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfslide1down_vf_f32m2(<vscale x 4 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfslide1down.nxv4f32.f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, float %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfslide1down.nxv4f32.f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfslide1down_vf_f32m4(<vscale x 8 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfslide1down.nxv8f32.f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, float %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfslide1down.nxv8f32.f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, float, i64)
# | ...
# `---data was truncated (10240/34765) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005640685cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005640685c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005640685cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6a16449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6a164a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6a16449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6a16431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564068561bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564068561a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005640685468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005640681f5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005640681f5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6a16432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6a164330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6a164330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005640681f5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c (554 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrsub_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrsub_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrsub_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrsub_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrsub_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrsub_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrsub_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrsub_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrsub_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vsc
# | ...
# `---data was truncated (10240/147382) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a2fdec6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a2fdec3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a2fdec762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9ab5b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9ab5b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9ab5b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9ab5b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a2fde5cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a2fde5ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a2fde418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a2fdaf0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a2fdaf0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9ab5b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9ab5b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9ab5b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a2fdaf0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c (555 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmadc_vvm_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmadc_vxm_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmadc_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmadc_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmadc_vvm_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmadc_vxm_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmadc_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmadc_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmadc_vvm_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmadc_vxm_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   
# | ...
# `---data was truncated (10240/169917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ef74923eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ef74920e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ef7492462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcdf4249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcdf42a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcdf4249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcdf4231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ef748b9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ef748b9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ef7489e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ef7454de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ef7454db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcdf4232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcdf42330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcdf42330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ef7454da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c (556 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-f8f32 -target-feature +sme-f8f16 -target-feature +sme-mop4 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-f8f32 -target-feature +sme-f8f16 -target-feature +sme-mop4 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za16_mf8_mf8_fpm(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %2)
# |   call void @llvm.aarch64.sme.fp8.fmop4a.za16.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmop4a.za16.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x2_za16_mf8_mf8_fpm(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1, i64 noundef %fpmr) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm1, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %6)
# |   call void @llvm.aarch64.sme.fp8.fmop4a.za16.1x2.nxv16i8(i32 1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmop4a.za16.1x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x1_za16_mf8_mf8_fpm(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %6)
# |   call void @llvm.aarch64.sme.fp8.fmop4a.za16.2x1.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmop4a.za16.2x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x2_za16_mf8_mf8_fpm(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 0
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 1
# |   %10 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %10)
# |   call void @llvm.aarch64.sme.fp8.fmop4a.za16.2x2.nxv16i8(i32 1, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmop4a.za16.2x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za32_mf8_mf8_fpm(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %2)
# |   call void @llvm.aarch64.sme.fp8.fmop4a.za32.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmop4a.za32.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x2_za32_mf8_mf8_fpm(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1, i64 noundef %fpmr) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm1, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %6)
# |   call void @llvm.aarch64.sme.fp8.fmop4a.za32.1x2.nxv16i8(i32 1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmop4a.za32.1x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vsc
# | ...
# `---data was truncated (10240/15164) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000560a5a82deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560a5a82ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560a5a82e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f05c6849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f05c68a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f05c6849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f05c6831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a5a7c3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560a5a7c3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560a5a7a88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560a5a457e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560a5a457b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f05c6832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f05c68330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f05c68330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a5a457a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-vls-arith-ops.c (557 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-arith-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone -mvscale-min=4 -mvscale-max=4   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @add_i8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %add = add <64 x i8> %0, %1
# |   store <64 x i8> %add, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8>, <64 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @add_i16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %add = add <32 x i16> %0, %1
# |   store <32 x i16> %add, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16>, <32 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i32> @add_i32(<vscale x 4 x i32> noundef %a.coerce, <vscale x 4 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i32>, align 16
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca <16 x i32>, align 16
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %b.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i32>, ptr %b.addr, align 16
# |   %add = add <16 x i32> %0, %1
# |   store <16 x i32> %add, ptr %retval, align 16
# |   %2 = load <16 x i32>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> poison, <16 x i32> %2, i64 0)
# |   ret <vscale x 4 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32>, <16 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i64> @add_i64(<vscale x 2 x i64> noundef %a.coerce, <vscale x 2 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i64>, align 16
# |   %a.addr = alloca <8 x i64>, align 16
# |   %b.addr = alloca <8 x i64>, align 16
# |   %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %a.coerce, i64 0)
# |   %b = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %b.coerce, i64 0)
# |   store <8 x i64> %a, ptr %a.addr, align 16
# |   store <8 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i64>, ptr %a.addr, align 16
# |   %1 = load <8 x i64>, ptr %b.addr, align 16
# |   %add = add <8 x i64> %0, %1
# |   store <8 x i64> %add, ptr %retval, align 16
# |   %2 = load <8 x i64>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> poison, <8 x i64> %2, i64 0)
# |   ret <vscale x 2 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64>, <8 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @add_u8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %add = add <64 x i8> %0, %1
# |   store <64 x i8> %add, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @add_u16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %add = add <32 x i16> %0, %1
# |   store <32 x i16> %add, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i32> @add_u32(<vscale x 4 x i32> noundef %a.coerce, <vscale x 4 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i32>, align 16
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca <16 x i32>, align 16
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %b.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i32>, ptr %b.addr, align 16
# |   %add = add <16 x i32> %0, %1
# |   store <16 x i32> %add, ptr %retval, align 16
# |   %2 = load <16 x i32>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> poison, <16 x i32> %2, i64 0)
# |   ret <vscale x 4 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i64> @add_u64(<vscale x 2 x i64> noundef %a.coerce, <vscale x 2 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i64>, align 16
# |   %a.addr = alloca <8 x i64>, align 16
# |   %b.addr = alloca <8 x i64>, align 16
# |   %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %a.coerce, i64 0)
# |   %b = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %b.coerce, i64 0)
# |   store <8 x i64> %a, ptr %a.addr, align 16
# |   store <8 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i64>, ptr %a.addr, align 16
# |   %1 = load <8 x i64>, ptr %b.addr, align 16
# |   %add = add <8 x i64> %0, %1
# |   store <8 x i64> %add, ptr %retval, align 16
# |   %2 = load <8 x i64>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> poison, <8 x i64> %2, i64 0)
# |   ret <vscale x 2 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x half> @add_f16(<vscale x 8 x half> noundef %a.coerce, <vscale x 8 x half> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x half>, align 16
# |   %a.addr = alloca <32 x half>, align 16
# |   %b.addr = alloca <32 x half>, align 16
# |   %a = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> %a.coerce, i64 0)
# |   %b = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> %b.coerce, i64 0)
# |   store <32 x half> %a, ptr %a.addr, align 16
# |   store <32 x half> %b, ptr %b.addr, align 16
# |   %0 = load <32 x ha
# | ...
# `---data was truncated (10240/161192) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x0000563c002c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563c002bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563c002c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9546649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f95466a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9546649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9546631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c00257bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563c00257a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563c0023c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563bffeebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563bffeebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9546632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f95466330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f95466330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563bffeeba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_add.c (558 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_add.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svadd_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.add.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.add.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svadd_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.add.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.add.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadd_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadd_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.add.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.add.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svadd_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.add.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svadd_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.add.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadd_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadd_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.add.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svadd_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, pt
# | ...
# `---data was truncated (10240/72449) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055b98ada2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b98ad9fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b98ada362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4dc2533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4dc258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4dc2533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4dc251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b98ad38bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b98ad38a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b98ad1d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b98a9cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b98a9ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4dc251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4dc251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4dc251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b98a9cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c (559 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsub_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsub_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsub_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsub_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsub_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsub_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsub_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsub_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | ...
# `---data was truncated (10240/34356) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557d9265deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557d9265ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557d9265e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6111105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f611115c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6111105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f61110ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557d925f3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557d925f3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557d925d88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557d92287e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557d92287b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f61110eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61110ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61110ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557d92287a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c (560 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svbmopa_u32(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   call void @llvm.aarch64.sme.bmopa.za32.nxv4i32(i32 3, <vscale x 4 x i1> %4, <vscale x 4 x i1> %5, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.bmopa.za32.nxv4i32(i32 immarg, <vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svbmopa_s32(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   call void @llvm.aarch64.sme.bmopa.za32.nxv4i32(i32 3, <vscale x 4 x i1> %4, <vscale x 4 x i1> %5, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svbmops_u32(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   call void @llvm.aarch64.sme.bmops.za32.nxv4i32(i32 3, <vscale x 4 x i1> %4, <vscale x 4 x i1> %5, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.bmops.za32.nxv4i32(i32 immarg, <vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svbmops_s32(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   call void @llvm.aarch64.sme.bmops.za32.nxv4i32(i32 3, <vscale x 4 x i1> %4, <vscale x 4 x i1> %5, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005622683ebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005622683e8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005622683ec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f26be733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f26be78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f26be733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f26be71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562268381bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562268381a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005622683668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562268015e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562268015b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f26be71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f26be71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f26be71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562268015a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c (561 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_f32mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_f32m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_i32mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_i32m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_u32mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_u32m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs:
# | ...
# `---data was truncated (10240/16382) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c7836dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c7836dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c7836e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f450cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f450cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f450cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f450cf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c783675bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c783675a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c78365a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c783309e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c783309b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f450cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f450cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f450cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c783309a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c (562 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsra_wv_i8mf8(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsra_wx_i8mf8(<vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsra_wv_i8mf4(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsra_wx_i8mf4(<vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsra_wv_i8mf2(<vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsra_wx_i8mf2(<vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsra_wv_i8m1(<vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsra_wx_i8m1(<vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsra_wv_i8m2(<vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsra_wx_i8m2(<vscale x 16 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8>, <vscale x 1
# | ...
# `---data was truncated (10240/68509) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563f5450eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563f5450be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563f5450f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6cc2533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6cc258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6cc2533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6cc251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563f544a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563f544a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563f544898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563f54138e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563f54138b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6cc251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6cc251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6cc251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563f54138a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vabavq.c (563 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vabavq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vabav.v16i8(i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vabav.v16i8(i32, i32, <16 x i8>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vabav.v8i16(i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vabav.v8i16(i32, i32, <8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load <4 x i32>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vabav.v4i32(i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vabav.v4i32(i32, i32, <4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_u8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vabav.v16i8(i32 1, i32 %0, <16 x i8> %1, <16 x i8> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_u16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vabav.v8i16(i32 1, i32 %0, <8 x i16> %1, <8 x i16> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_u32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load <4 x i32>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vabav.v4i32(i32 1, i32 %0, <4 x i32> %1, <4 x i32> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4)
# |   %6 = call i32 @llvm.arm.mve.vabav.predicated.v16i8.v16i1(i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2, <16 x i1> %5)
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vabav.predicated.v16i8.v16i1(i32, i32, <16 x i8>, <16 x i8>, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
# |   %6 = call i32 @llvm.arm.mve.vabav.predicated.v8i16.v8i1(i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2, <8 x i1> %5)
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vabav.predicated.v8i16.v8i1(i32, i32, <8 x i16>, <8 x i16>, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load <4 x i32>, ptr %c.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call i32 @llvm.arm.mve.vabav.predicated.v4i32.v4i1(i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2, <4 x i1> %5)
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vabav.predicated.v4i32.v4i1(i32, i32, <4 x i32>, <4 x i32>, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_u8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4)
# |   %6 = call i32 @llvm.arm.mve.vabav.predicated.v16i8.v16i1(i32 1, i32 %0, <16 x i8> %1, <16 x i8> %2, <16 x i1> %5)
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_u16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
# |   %6 = call i32 @llvm.arm.mve.vabav.predicated.v8i16.v8i1(i32 1, i32 %0, <8 x i16> %1, <8 x i16> %2, <8 x i1> %5)
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_u32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %
# | ...
# `---data was truncated (10240/11173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000561da33cceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561da33c9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561da33cd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9983d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9983d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9983d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9983ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561da3362bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561da3362a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561da33478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561da2ff6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561da2ff6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9983ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9983cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9983cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561da2ff6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c (564 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f16m1x4(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_f16m2x4(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f32m1x4(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_f32m2x4(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f64m1x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/82983) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558beb0eaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558beb0e7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558beb0eb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b5ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b5caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b5ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b5ca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558beb080bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558beb080a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558beb0658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558bead14e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558bead14b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3b5ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b5ca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b5ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558bead14a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c (565 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vpairo_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vpairo.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vpairo.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vpairo_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vpairo.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vpairo.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vpairo_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vpairo.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vpairo.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vpairo_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vpairo.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vpairo.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vpairo_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vpairo.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vpairo.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vpairo_vv_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vpairo.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vpairo.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vpairo_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vpairo.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vpairo.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vpairo_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vpairo.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vpairo.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vpairo_vv_f32m2_tu(<vscale
# | ...
# `---data was truncated (10240/288267) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556792686eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556792683e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055679268762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f74a5505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f74a555c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f74a5505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f74a54ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055679261cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055679261ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005567926018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005567922b0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005567922b0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f74a54eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f74a54ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f74a54ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005567922b0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp (566 of 27911)
******************** TEST 'Clang :: CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O1 -disable-llvm-passes -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp -o - -triple=x86_64-linux-gnu | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=lower-expect -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O1 -disable-llvm-passes -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp -o - -triple=x86_64-linux-gnu
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | ; Function Attrs: mustprogress nounwind
# | define dso_local void @_Z3ab1Ri(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 8
# |   store ptr %i, ptr %i.addr, align 8, !tbaa !6
# |   %call = call noundef zeroext i1 @_Z1av()
# |   br i1 %call, label %land.lhs.true, label %land.end
# | 
# | land.lhs.true:                                    ; preds = %entry
# |   %call1 = call noundef zeroext i1 @_Z1bv()
# |   br i1 %call1, label %land.rhs, label %land.end
# | 
# | land.rhs:                                         ; preds = %land.lhs.true
# |   %call2 = call noundef zeroext i1 @_Z1av()
# |   br label %land.end
# | 
# | land.end:                                         ; preds = %land.rhs, %land.lhs.true, %entry
# |   %0 = phi i1 [ false, %land.lhs.true ], [ false, %entry ], [ %call2, %land.rhs ]
# |   %conv = zext i1 %0 to i64
# |   %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1)
# |   %tobool = icmp ne i64 %expval, 0
# |   br i1 %tobool, label %if.then, label %if.else
# | 
# | if.then:                                          ; preds = %land.end
# |   %1 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %2 = load i32, ptr %1, align 4, !tbaa !11
# |   %inc = add nsw i32 %2, 1
# |   store i32 %inc, ptr %1, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.else:                                          ; preds = %land.end
# |   %3 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %4 = load i32, ptr %3, align 4, !tbaa !11
# |   %dec = add nsw i32 %4, -1
# |   store i32 %dec, ptr %3, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.end:                                           ; preds = %if.else, %if.then
# |   ret void
# | }
# | 
# | declare noundef zeroext i1 @_Z1av() #1
# | 
# | declare noundef zeroext i1 @_Z1bv() #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.expect.i64(i64, i64) #2
# | 
# | ; Function Attrs: mustprogress nounwind
# | define dso_local void @_Z2alRi(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 8
# |   store ptr %i, ptr %i.addr, align 8, !tbaa !6
# |   %call = call noundef zeroext i1 @_Z1av()
# |   %call.expval = call i1 @llvm.expect.i1(i1 %call, i1 true)
# |   br i1 %call.expval, label %land.lhs.true, label %if.else
# | 
# | land.lhs.true:                                    ; preds = %entry
# |   %call1 = call noundef zeroext i1 @_Z1bv()
# |   %call1.expval = call i1 @llvm.expect.i1(i1 %call1, i1 true)
# |   br i1 %call1.expval, label %land.lhs.true2, label %if.else
# | 
# | land.lhs.true2:                                   ; preds = %land.lhs.true
# |   %call3 = call noundef zeroext i1 @_Z1cv()
# |   %call3.expval = call i1 @llvm.expect.i1(i1 %call3, i1 true)
# |   br i1 %call3.expval, label %if.then, label %if.else
# | 
# | if.then:                                          ; preds = %land.lhs.true2
# |   %0 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %1 = load i32, ptr %0, align 4, !tbaa !11
# |   %inc = add nsw i32 %1, 1
# |   store i32 %inc, ptr %0, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.else:                                          ; preds = %land.lhs.true2, %land.lhs.true, %entry
# |   %2 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %3 = load i32, ptr %2, align 4, !tbaa !11
# |   %dec = add nsw i32 %3, -1
# |   store i32 %dec, ptr %2, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.end:                                           ; preds = %if.else, %if.then
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i1 @llvm.expect.i1(i1, i1) #2
# | 
# | declare noundef zeroext i1 @_Z1cv() #1
# | 
# | ; Function Attrs: mustprogress nounwind
# | define dso_local void @_Z3ab0Ri(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 8
# |   store ptr %i, ptr %i.addr, align 8, !tbaa !6
# |   %call = call noundef zeroext i1 @_Z1av()
# |   br i1 %call, label %land.lhs.true, label %land.end
# | 
# | land.lhs.true:                                    ; preds = %entry
# |   %call1 = call noundef zeroext i1 @_Z1bv()
# |   br i1 %call1, label %land.rhs, label %land.end
# | 
# | land.rhs:                                         ; preds = %land.lhs.true
# |   %call2 = call noundef zeroext i1 @_Z1cv()
# |   br label %land.end
# | 
# | land.end:                                         ; preds = %land.rhs, %land.lhs.true, %entry
# |   %0 = phi i1 [ false, %land.lhs.true ], [ false, %entry ], [ %call2, %land.rhs ]
# |   %conv = zext i1 %0 to i64
# |   %expval = call i64 @llvm.expect.i64(i64 %conv, i64 0)
# |   %tobool = icmp ne i64 %expval, 0
# |   br i1 %tobool, label %if.then, label %if.else
# | 
# | if.then:                                          ; preds = %land.end
# |   %1 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %2 = load i32, ptr %1, align 4, !tbaa !11
# |   %inc = add nsw i32 %2, 1
# |   store i32 %inc, ptr %1, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.else:                                          ; preds = %land.end
# |   %3 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %4 = load i32, ptr %3, align 4, !tbaa !11
# |   %dec = add nsw i32 %4, -1
# |   store i32 %dec, ptr %3, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.end:                                           ; preds = %if.else, %if.then
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress nounwind
# | define dso_local void @_Z2auRi(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 8
# |   store ptr %i, ptr %i.addr, align 8, !tbaa !6
# |   %call = call noundef zeroext i1 @_Z1av()
# |   br i1 %call, label %land.lhs.true, label %if.else
# | 
# | land.lhs.true:                                    ; preds = %entry
# |   %call1 = call noundef zeroext i1 @_Z1bv()
# |   br i1 %call1, label %land.lhs.true2, label %if.else
# | 
# | land.lhs.true2:                                   ; preds = %land.lhs.true
# |   %call3 = call noundef zeroext i1 @_Z1cv()
# |   %call3.expval = call i1 @llvm.expect.i1(i1 %call3, i1 false)
# |   br i1 %call3.expval, label %if.then, label %if.else
# | 
# | if.then:                                          ; preds = %land.lhs.true2
# |   %0 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %1 = load i32, ptr %0, align 4, !tbaa !11
# |   %inc = add nsw i32 %1, 1
# |   store i32 %inc, ptr %0, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.else:                                          ; preds = %land.lhs.true2, %land.lhs.true, %entry
# |   %2 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %3 = load i32, ptr %2, align 4, !tbaa !11
# |   %dec = add nsw i32 %3, -1
# |   store i32 %dec, ptr %2, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.end:                                           ; preds = %if.else, %if.then
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress nounwind
# | define dso_local void @_Z3ob1Ri(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 8
# |   store ptr %i, ptr %i.addr, align 8, !tbaa !6
# |   %call = call noundef zeroext i1 @_Z1av()
# |   br i1 %call, label %lor.end, label %lor.lhs.false
# | 
# | lor.lhs.false:                                    ; preds = %entry
# |   %call1 = call noundef zeroext i1 @_Z1bv()
# |   br i1 %call1, label %lor.end, label %lor.rhs
# | 
# | lor.rhs:                                          ; preds = %lor.lhs.false
# |   %call2 = call noundef zeroext i1 @_Z1av()
# |   br label %lor.end
# | 
# | lor.end:                                          ; preds = %lor.rhs, %lor.lhs.false, %entry
# |   %0 = phi i1 [ true, %lor.lhs.false ], [ true, %entry ], [ %call2, %lor.rhs ]
# |   %conv = zext i1 %0 to i64
# |   %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1)
# |   %tobool = icmp ne i64 %expval, 0
# |   br i1 %tobool, label %if.then, label %if.else
# | 
# | if.then:                                          ; preds = %lor.end
# |   %1 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   store i32 0, ptr %1, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.else:                                          ; preds = %lor.end
# |   %2 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %3 = load i32, ptr %2, align 4, !tbaa !11
# |   %dec = add nsw i32 %3, -1
# |   store i32 %dec, ptr %2, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.end:                                           ; preds = %if.else, %if.then
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress nounwind
# | define dso_local void @_Z2olRi(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 8
# |   store ptr %i, ptr %i.addr, align 8, !tbaa !6
# |   %call = call noundef zeroext i1 @_Z1av()
# |   br i1 %call, label %if.then, label %lor.lhs.false
# | 
# | lor.lhs.false:                                    ; preds = %entry
# |   %call1 = call noundef zeroext i1 @_Z1bv()
# |   br i1 %call1, label %if.then, label %lor.lhs.false2
# | 
# | lor.lhs.false2:                                   ; preds = %lor.lhs.false
# |   %call3 = call noundef zeroext i1 @_Z1cv()
# |   %call3.expval = call i1 @llvm.expect.i1(i1 %call3, i1 true)
# |   br i1 %call3.expval, label %if.then, label %if.else
# | 
# | if.then:                                          ; preds = %lor.lhs.false2, %lor.lhs.false, %entry
# |   %0 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   store i32 0, ptr %0, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.else:                                          ; preds = %lor.lhs.false2
# |   %1 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %2 = load i32, ptr %1, align 4, !tbaa !11
# |   %dec = add nsw i32 %2, -1
# |   store i32 %dec, ptr %1, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.end:                                           ; preds = %if.else, %if.then
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress nounwind
# | define dso_local void @_Z3ob0Ri(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 8
# |   store ptr %i, ptr %i.addr, align 8, !tbaa !6
# |   %call = call noundef zeroext i1 @_Z1av()
# |   br i1 %call, label %lor.end, label %lor.lhs.false
# | 
# | lor.lhs.false:                                    ; preds = %entry
# |   %call1 = call noundef zeroext i1 @_Z1bv()
# |   br i1 %call1, label %lor.end, label %lor.rhs
# | 
# | lor.rhs:     
# | ...
# `---data was truncated (10240/28468) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=lower-expect -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=lower-expect -S
# |  #0 0x00005607c6388eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005607c6385e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005607c638962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ac7249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ac72a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ac7249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ac7231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607c631ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005607c631ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005607c63038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005607c5fb2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005607c5fb2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8ac7232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ac72330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ac72330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607c5fb2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c (567 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf8x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_u8mf8x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_u8mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_u8mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_u8m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, pt
# | ...
# `---data was truncated (10240/18980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005642e03e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005642e03e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005642e03e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d6d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d6d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d6d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d6d431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005642e0379bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005642e0379a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005642e035e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005642e000de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005642e000db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8d6d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d6d4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d6d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005642e000da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp (568 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d    -target-feature +v -target-feature +zfh -target-feature +zvfh    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @_Z21test_vget_v_i8m2_i8m1u14__rvv_int8m2_t(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> %0, i64 8)
# |   ret <vscale x 8 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @_Z21test_vset_v_i8m1_i8m2u14__rvv_int8m2_tu14__rvv_int8m1_t(<vscale x 16 x i8> %dest, <vscale x 8 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x i8>, align 1
# |   %val.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 16 x i8> %dest, ptr %dest.addr, align 1
# |   store <vscale x 8 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 8)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8>, <vscale x 8 x i8>, i64 immarg) #1
# | 
# | attributes #0 = { mustprogress noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005634f272beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005634f2728e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005634f272c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f589a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f589a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f589a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f589a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005634f26c1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005634f26c1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005634f26a68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005634f2355e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005634f2355b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f589a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f589a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f589a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005634f2355a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c (569 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svfrinta_f32_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frinta.x2.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frinta.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svfrinta_f32_x4(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zn.coerce2, <vscale x 4 x float> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, <vscale x 4 x float> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zn.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 1
# |   %7 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 2
# |   %8 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 3
# |   %9 = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frinta.x4.nxv4f32(<vscale x 4 x float> %5, <vscale x 4 x float> %6, <vscale x 4 x float> %7, <vscale x 4 x float> %8)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frinta.x4.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svfrintam_f32_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frintm.x2.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frintm.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svfrintm_f32_x4(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zn.coerce2, <vscale x 4 x float> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, <vscale x 4 x float> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zn.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 1
# |   %7 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 2
# |   %8 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 3
# |   %9 = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frintm.x4.nxv4f32(<vscale x 4 x float> %5, <vscale x 4 x float> %6, <vscale x 4 x float> %7, <vscale x 4 x float> %8)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frintm.x4.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svfrintn_f32_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frintn.x2.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn me
# | ...
# `---data was truncated (10240/17932) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055b9d57a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b9d57a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b9d57a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa71a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa71a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa71a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa71a231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b9d573cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b9d573ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b9d57218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b9d53d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b9d53d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa71a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa71a2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa71a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b9d53d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c (570 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs1, <vsc
# | ...
# `---data was truncated (10240/148835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559653114eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559653111e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055965311562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb0b7905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb0b795c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb0b7905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb0b78ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005596530aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005596530aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055965308f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559652d3ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559652d3eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb0b78eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb0b78ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb0b78ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559652d3ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c (571 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svexpand_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.expand.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.expand.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svexpand_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.expand.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.expand.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svexpand_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.expand.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svexpand_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.expand.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svexpand_mf8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.expand.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svexpand_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.expand.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.expand.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svexpand_bf16(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.expand.nxv8bf16(<vscale x 8 x i1> %2, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.expand.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svexpand_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.expand.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.expand.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svexpand_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.expand.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.expand.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svexpand_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.expand.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svexpand_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.expand.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svexpand_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, al
# | ...
# `---data was truncated (10240/12168) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055bd9b84eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bd9b84be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bd9b84f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb577733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb57778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb577733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb57771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bd9b7e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bd9b7e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bd9b7c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bd9b478e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bd9b478b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb57771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb57771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb57771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bd9b478a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c (572 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svunpk_s16_x2(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sunpk.x2.nxv8i16(<vscale x 16 x i8> %0)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sunpk.x2.nxv8i16(<vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svunpk_u16_x2(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uunpk.x2.nxv8i16(<vscale x 16 x i8> %0)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uunpk.x2.nxv8i16(<vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svunpk_s32_x2(<vscale x 8 x i16> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sunpk.x2.nxv4i32(<vscale x 8 x i16> %0)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sunpk.x2.nxv4i32(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svunpk_u32_x2(<vscale x 8 x i16> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.uunpk.x2.nxv4i32(<vscale x 8 x i16> %0)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.uunpk.x2.nxv4i32(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svunpk_s64_x2(<vscale x 4 x i32> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sunpk.x2.nxv2i64(<vscale x 4 x i32> %0)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sunpk.x2.nxv2i64(<vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svunpk_u64_x2(<vscale x 4 x i32> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.uunpk.x2.nxv2i64(<vscale x 4 x i32> %0)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.uunpk.x2.nxv2i64(<vscale x 4 x i32>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000555ae59e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555ae59e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555ae59e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fad32f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fad32f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fad32f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fad32f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555ae597bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555ae597ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555ae59608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555ae560fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555ae560fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fad32f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fad32f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fad32f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555ae560fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c (573 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfslide1down_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfslide1down_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfslide1down_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfslide1down_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfslide1down_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfslide1down_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfslide1down_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load float, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfslide1down_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load float, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfslide1down_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %src, float noundef %value, i64 noundef
# | ...
# `---data was truncated (10240/78336) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560c47be2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560c47bdfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560c47be362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd2e0d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd2e0d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd2e0d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd2e0d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c47b78bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560c47b78a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560c47b5d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560c4780ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560c4780cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd2e0d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd2e0d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd2e0d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c4780ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c (574 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzipq2_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zipq2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.zipq2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzipq2_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zipq2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.zipq2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzipq2_u32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zipq2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.zipq2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzipq2_u64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zipq2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.zipq2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzipq2_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zipq2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzipq2_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zipq2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzipq2_s32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zipq2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzipq2_s64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zipq2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svzipq2_f16(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.zipq2.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.zipq2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svzipq2_f32(<vscale x 4 x float> %zn, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x float>, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.zipq2.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.zipq2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svzipq2_f64(<vscale x 2 x double> %zn, <vscale x 2 x double> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x double>, align 16
# |   %zm.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x double> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.zipq2.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.zipq2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svzipq2_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.zipq2.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.zipq2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzipq2_mf8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zipq2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %
# | ...
# `---data was truncated (10240/10910) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055d63cb65eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d63cb62e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d63cb6662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b8bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b8bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b8bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b8bd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d63cafbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d63cafba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d63cae08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d63c78fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d63c78fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4b8bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b8bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b8bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d63c78fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c (575 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmls_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %6 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmls.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fnmls.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svnmls_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %6 = call <vscale x 4 x float> @llvm.aarch64.sve.fnmls.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %5, <vscale x 4 x float> %2, <vscale x 4 x float> %3)
# |   ret <vscale x 4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fnmls.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svnmls_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %6 = call <vscale x 2 x double> @llvm.aarch64.sve.fnmls.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %5, <vscale x 2 x double> %2, <vscale x 2 x double> %3)
# |   ret <vscale x 2 x double> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fnmls.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmls_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmls.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svnmls_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fnmls.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svnmls_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fnmls.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmls_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmls.u.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind w
# | ...
# `---data was truncated (10240/26173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055862f35beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055862f358e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055862f35c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3929a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3929a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3929a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3929a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055862f2f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055862f2f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055862f2d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055862ef85e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055862ef85b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3929a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3929a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3929a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055862ef85a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/len.c (576 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/len.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c         | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_u8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 16
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.vscale.i64() #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_s8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 16
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 8
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 8
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_f16(<vscale x 8 x half> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 8
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_bf16(<vscale x 8 x bfloat> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 8
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 4
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 4
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_f32(<vscale x 4 x float> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 4
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 2
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 2
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_f64(<vscale x 2 x double> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 2
# |   ret i64 %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x00005584eef4deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005584eef4ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005584eef4e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6214249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f62142a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6214249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6214231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005584eeee3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005584eeee3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005584eeec88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005584eeb77e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005584eeb77b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6214232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f62142330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f62142330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005584eeb77a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/orv.c (577 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/orv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svorv_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.orv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.orv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svorv_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.orv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.orv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svorv_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.orv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.orv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svorv_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.orv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.orv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svorv_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.orv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svorv_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.orv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svorv_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.orv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svorv_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.orv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x0000563b6fb73eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563b6fb70e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563b6fb7462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1229733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f122978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1229733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f122971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b6fb09bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563b6fb09a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563b6faee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563b6f79de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563b6f79db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f122971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f122971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f122971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b6f79da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c (578 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnj_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnj_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnj_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnj_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnj_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnj_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnj_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnj_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnj_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, <v
# | ...
# `---data was truncated (10240/157467) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055966745beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559667458e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055966745c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd57b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd57b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd57b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd57b431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005596673f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005596673f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005596673d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559667085e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559667085b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd57b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd57b4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd57b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559667085a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c (579 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme2  -target-feature +sme  -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme2 -target-feature +sme -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_u8_1(<vscale x 16 x i8> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.write.lane.zt.nxv16i8(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_s8_2(<vscale x 16 x i8> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_u16_3(<vscale x 8 x i16> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv8i16(i32 0, <vscale x 8 x i16> %0, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.write.lane.zt.nxv8i16(i32 immarg, <vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_s16_1(<vscale x 8 x i16> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv8i16(i32 0, <vscale x 8 x i16> %0, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_u32_2(<vscale x 4 x i32> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv4i32(i32 0, <vscale x 4 x i32> %0, i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.write.lane.zt.nxv4i32(i32 immarg, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_s32_3(<vscale x 4 x i32> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv4i32(i32 0, <vscale x 4 x i32> %0, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_u64_0(<vscale x 2 x i64> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv2i64(i32 0, <vscale x 2 x i64> %0, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.write.lane.zt.nxv2i64(i32 immarg, <vscale x 2 x i64>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_s64_1(<vscale x 2 x i64> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv2i64(i32 0, <vscale x 2 x i64> %0, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_f16_2(<vscale x 8 x half> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv8f16(i32 0, <vscale x 8 x half> %0, i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.write.lane.zt.nxv8f16(i32 immarg, <vscale x 8 x half>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_bf16_3(<vscale x 8 x bfloat> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv8bf16(i32 0, <vscale x 8 x bfloat> %0, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.write.lane.zt.nxv8bf16(i32 immarg, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_f32_0(<vscale x 4 x float> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv4f32(i32 0, <vscale x 4 x float> %0, i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.write.lane.zt.nxv4f32(i32 immarg, <vscale x 4 x float>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_f64_1(<vscale x 2 x double> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv2f64(i32 0, <vscale x 2 x double> %0, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.write.lane.zt.nxv2f64(i32 immarg, <vscale x 2 x double>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_zt_u8(<vscale x 16 x i8> %v) #2 {
# | entry:
# |   %v.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write)
# | declare void @llvm.aarch64.sme.write.zt.nxv16i8(i32 immarg, <vscale x 16 x i8>) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_zt_s8(<vscale x 16 x i8> %v) #2 {
# | entry:
# |   %v.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_zt_u16(<vscale x 8 x i16> %v) #2 {
# | entry:
# |   %v.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.zt.nxv8i16(i32 0, <vscale x 8 x i16> %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write)
# | declare void @llvm.aarch64.sme.write.zt.nxv8i16(i32 immarg, <vscale x 8 x i16>) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_zt_s16(<vscale x 8 x i16> %v) #2 {
# | entry:
# |   %v.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.zt.nxv8i16(i32 0, <vscale x 8 x i16> %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_zt_u32(<vscale x 4 x i32> %v) #2 {
# | entry:
# |   %v.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.zt.nxv4i32(i32 0, <vscale x 4 x i32> %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write)
# | declare void @llvm.aarch64.sme.write.zt.nxv4i32(i32 immarg, <vscale x 4 x i32>) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_zt_s32(<vscale x 4 x i32> %v) #2 {
# | entry:
# |   %v.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.zt.nxv4i32(i32 0, <vscale x 4 x i32> %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_zt_u64(<vscale x 2 x i64> %v) #2 {
# | entry:
# |   %v.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.zt.nxv2i64(i32 0, <vscale x 2 x i64> %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write)
# | declare void @llvm.aarch64.sme.write.zt.nxv2i64(i32 immarg, <vscale x 2 x i64>) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_zt_s64(<vscale x 2 x i64> %v) #2 {
# | entry:
# |   %
# | ...
# `---data was truncated (10240/13584) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055dcae1daeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dcae1d7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dcae1db62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2eae133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2eae18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2eae133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2eae11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dcae170bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dcae170a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dcae1558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dcade04e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dcade04b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2eae11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2eae11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2eae11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dcade04a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c (580 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsub_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsub_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsub_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsub_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsub_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsub_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsub_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsub_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsub_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsub_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsub_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/175155) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565240a8eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565240a8be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000565240a8f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9722f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9722f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9722f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9722f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565240a24bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565240a24a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000565240a098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005652406b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005652406b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9722f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9722f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9722f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005652406b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c (581 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1sh_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sh_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1sh_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sh_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1sh_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sh_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1sh_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sh_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056335a992eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056335a98fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056335a99362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3f0ee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3f0eea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3f0ee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3f0ee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056335a928bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056335a928a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056335a90d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056335a5bce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056335a5bcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3f0ee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3f0ee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3f0ee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056335a5bca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c (582 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_s8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x i32> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x i64> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_u8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x i32> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x i64> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_f16(<vscale x 8 x half> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x half> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_f32(<vscale x 4 x float> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x float> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_f64(<vscale x 2 x double> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x double> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_s8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   ret <vscale x 8 x i16> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x i32> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x i64> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_u8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   ret <vscale x 8 x i16> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x i32> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x i64> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_f16(<vscale x 8 x half> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x half> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_f32(<vscale x 4 x float> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x float> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_f64(<vscale x 2 x double> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x double> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svreinterpret_s32_s8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svreinterpret_s32_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svreinterpret_s32_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   ret <vscale x 4 x i32>
# | ...
# `---data was truncated (10240/58597) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e6515c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e6515c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e6515c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fea88449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fea884a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fea88449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fea88431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e65155abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e65155aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e65153f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e6511eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e6511eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fea88432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fea884330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fea884330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e6511eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon/perm.c (583 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/perm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -disable-O0-optnone -flax-vector-conversions=none           -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c --check-prefixes=LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -disable-O0-optnone -flax-vector-conversions=none -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | %struct.int8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.int16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.uint8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.uint16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.poly8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.poly16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.mfloat8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.int32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.float32x2x2_t = type { [2 x <2 x float>] }
# | %struct.uint32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.int8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.int16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.int32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.float32x4x2_t = type { [2 x <4 x float>] }
# | %struct.uint8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.uint16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.uint32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.poly8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.poly16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.mfloat8x16x2_t = type { [2 x <16 x i8>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vzip1_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <8 x i8> %2, <8 x i8> %3, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vzip1q_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %2, <16 x i8> %3, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
# |   store <16 x i8> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vzip1_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <4 x i16> %2, <4 x i16> %3, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vzip1q_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   %1 = load <8 x i16>, ptr %b.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %3 = load <8 x i16>, ptr %__p1.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %2, <8 x i16> %3, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
# |   store <8 x i16> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vzip1_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <2 x i32> %2, <2 x i32> %3, <2 x i32> <i32 0, i32 2>
# |   store <2 x i32> %shuffle.i, ptr %__ret.i, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vzip1q_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   %1 = load <4 x i32>, ptr %b.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <4 x i32> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %3 = load <4 x i32>, ptr %__p1.addr.i, align 16
# |   %shuffle.i = shufflevector <4 x i32> %2, <4 x i32> %3, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
# |   store <4 x i32> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vzip1q_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__p1.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %a.addr = alloca <2 x i64>, align 16
# |   %b.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %3 = load <2 x i64>, ptr %__p1.addr.i, align 16
# |   %shuffle.i = shufflevector <2 x i64> %2, <2 x i64> %3, <2 x i32> <i32 0, i32 2>
# |   store <2 x i64> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vzip1_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <8 x i8> %2, <8 x i8> %3, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vzip1q_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %2, <16 x i8> %3, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
# |   store <16 x i8> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vzip1_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, 
# | ...
# `---data was truncated (10240/231562) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# |  #0 0x000055fbbdf72eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fbbdf6fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fbbdf7362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5d34933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5d3498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5d34933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5d3491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fbbdf08bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fbbdf08a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fbbdeed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fbbdb9ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fbbdb9cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5d3491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5d3491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5d3491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fbbdb9ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c --check-prefixes=LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c --check-prefixes=LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c (584 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vslideup_vx_f16mf4_tu(<vscale x 1 x half> %dest, <vscale x 1 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vslideup_vx_f16mf2_tu(<vscale x 2 x half> %dest, <vscale x 2 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vslideup_vx_f16m1_tu(<vscale x 4 x half> %dest, <vscale x 4 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vslideup_vx_f16m2_tu(<vscale x 8 x half> %dest, <vscale x 8 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vslideup_vx_f16m4_tu(<vscale x 16 x half> %dest, <vscale x 16 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vslideup_vx_f16m8_tu(<vscale x 32 x half> %dest, <vscale x 32 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vslideup_vx_f32mf2_tu(<vscale x 1 x float> %dest, <vscale x 1 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vslideup_vx_f32m1_tu(<vscale x 2 x float> %dest, <vscale x 2 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vslideup_vx_f32m2_tu(<vscale x 4 x float> %dest, <vscale x 4 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %dest, ptr %dest.addr, align 4
# |   s
# | ...
# `---data was truncated (10240/280209) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bfe4af0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bfe4aede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bfe4af162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f93c8849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f93c88a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f93c8849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f93c8831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bfe4a86bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bfe4a86a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bfe4a6b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bfe471ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bfe471ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f93c8832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f93c88330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f93c88330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bfe471aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c (585 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsll_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsll_vx_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsll_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsll_vx_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsll_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsll_vx_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsll_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsll_vx_i8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsll_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsll_vx_i8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsll_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>
# | ...
# `---data was truncated (10240/176535) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555fecb1deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555fecb1ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555fecb1e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc6ad61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc6ad6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc6ad61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc6ad603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555fecab3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555fecab3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555feca988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555fec747e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555fec747b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc6ad604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc6ad6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc6ad6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555fec747a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c (586 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e32_v_f32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e32_v_f32m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_i32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_i32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e32_v_i32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | de
# | ...
# `---data was truncated (10240/70971) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055825afbbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055825afb8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055825afbc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd32f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd32f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd32f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd32f031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055825af51bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055825af51a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055825af368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055825abe5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055825abe5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd32f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd32f0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd32f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055825abe5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c (587 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svld3_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld3.sret.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld3.sret.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svld3_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld3.sret.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld3.sret.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svld3_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld3.sret.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld3.sret.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svld3_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld3.sret.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld3.sret.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svld3_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld3.sret.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svld3_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld3.sret.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svld3_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld3.sret.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svld3_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld3.sret.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svld3_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld3.sret.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld3.sret.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svld3_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld3.sret.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld3.sret.nxv4f32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @test_svld3_f64(<vscale x
# | ...
# `---data was truncated (10240/26187) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ef473ceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ef473cbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ef473cf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff3d6a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff3d6a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff3d6a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff3d6a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ef47364bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ef47364a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ef473498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ef46ff8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ef46ff8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff3d6a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff3d6a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff3d6a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ef46ff8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c (588 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1(<vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vx_u64m1(<vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmulh_vv_u64m2(<vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmulh_vx_u64m2(<vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmulh_vv_u64m4(<vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmulh_vx_u64m4(<vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmulh_vv_u64m8(<vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmulh_vx_u64m8(<vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vx_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = loa
# | ...
# `---data was truncated (10240/18917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055692fea0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055692fe9de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055692fea162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7d1db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7d1db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7d1db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7d1db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055692fe36bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055692fe36a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055692fe1b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055692facae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055692facab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7d1db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7d1db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7d1db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055692facaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c (589 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldnt1_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnt1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.ldnt1.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnt1_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ldnt1.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.ldnt1.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnt1_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ldnt1.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ldnt1.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnt1_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ldnt1.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ldnt1.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldnt1_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnt1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnt1_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ldnt1.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnt1_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ldnt1.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnt1_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ldnt1.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svldnt1_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.ldnt1.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ldnt1.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svldnt1_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.ldnt1.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ldnt1.nxv4f32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svldnt1_f64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.ldnt1.nxv2f64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ldnt1.nxv2f64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldnt1_mf8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnt1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldnt1_vnum_s8(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %b
# | ...
# `---data was truncated (10240/22231) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e8b577eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e8b577be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e8b577f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f28fae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f28faea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f28fae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f28fae31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e8b5714bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e8b5714a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e8b56f98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e8b53a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e8b53a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f28fae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f28fae330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f28fae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e8b53a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c (590 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_u_s_w4_u8m8_i8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.u.s.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.u.s.i64.nxv64i8.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056056f008eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056056f005e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056056f00962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f59adf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f59adf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f59adf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f59adf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056056ef9ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056056ef9ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056056ef838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056056ec32e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056056ec32b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f59adf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f59adf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f59adf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056056ec32a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c (591 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.6a -target-feature +f8f16mm -target-feature +fp8  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.6a -target-feature +f8f16mm -target-feature +fp8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <8 x half> @test_vmmlaq_f16_mf8(<8 x half> noundef %p0, <16 x i8> %p1, <16 x i8> %p2, i64 noundef %p3) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <8 x half>, align 16
# |   %p0.addr = alloca <8 x half>, align 16
# |   %p1.addr = alloca <16 x i8>, align 16
# |   %p2.addr = alloca <16 x i8>, align 16
# |   %p3.addr = alloca i64, align 8
# |   store <8 x half> %p0, ptr %p0.addr, align 16
# |   store <16 x i8> %p1, ptr %p1.addr, align 16
# |   store <16 x i8> %p2, ptr %p2.addr, align 16
# |   store i64 %p3, ptr %p3.addr, align 8
# |   %0 = load <8 x half>, ptr %p0.addr, align 16
# |   %1 = load <16 x i8>, ptr %p1.addr, align 16
# |   %2 = load <16 x i8>, ptr %p2.addr, align 16
# |   %3 = load i64, ptr %p3.addr, align 8
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %fmmla.i = bitcast <16 x i8> %4 to <8 x half>
# |   %fmmla1.i = call <8 x half> @llvm.aarch64.neon.fmmla.v8f16.v16i8(<8 x half> %fmmla.i, <16 x i8> %5, <16 x i8> %6)
# |   store <8 x half> %fmmla1.i, ptr %ref.tmp.i, align 16
# |   %8 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %8, ptr %__ret.i, align 16
# |   %9 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.aarch64.neon.fmmla.v8f16.v16i8(<8 x half>, <16 x i8>, <16 x i8>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+cmpbr,+complxnum,+cpa,+crc,+cssc,+dit,+dotprod,+f8f16mm,+faminmax,+flagm,+fp-armv8,+fp8,+fullfp16,+hbc,+hinte,+i8mm,+jsconv,+lse,+lsui,+lut,+mec,+mops,+neon,+occmo,+pauth,+predres,+ras,+rasv2,+rcpc,+rdm,+rme,+sb,+spe-eef,+specres2,+ssbs,+sve,+sve2,+sve2p1,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v8.9a,+v8a,+v9.1a,+v9.2a,+v9.3a,+v9.4a,+v9.5a,+v9.6a,+v9a,+wfxt" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055faa22dbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055faa22d8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055faa22dc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f08aa933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f08aa98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f08aa933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f08aa91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055faa2271bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055faa2271a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055faa22568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055faa1f05e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055faa1f05b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f08aa91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f08aa91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f08aa91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055faa1f05a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c (592 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcvtn_f8_bf16(<vscale x 8 x bfloat> %zn_zm.coerce0, <vscale x 8 x bfloat> %zn_zm.coerce1, i64 noundef %fpm) #0 {
# | entry:
# |   %zn_zm = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zn_zm.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %fpm.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zn_zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zn_zm.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zn_zm, align 16
# |   %zn_zm1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn_zm, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zn_zm1, ptr %zn_zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn_zm.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 1
# |   %5 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %5)
# |   %6 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtn.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %4)
# |   ret <vscale x 16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtn.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcvtn_f8_f16(<vscale x 8 x half> %zn_zm.coerce0, <vscale x 8 x half> %zn_zm.coerce1, i64 noundef %fpm) #0 {
# | entry:
# |   %zn_zm = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zn_zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %fpm.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn_zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn_zm.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn_zm, align 16
# |   %zn_zm1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn_zm, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn_zm1, ptr %zn_zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn_zm.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 1
# |   %5 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %5)
# |   %6 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtn.nxv8f16(<vscale x 8 x half> %3, <vscale x 8 x half> %4)
# |   ret <vscale x 16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtn.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcvtnb_f8_f32(<vscale x 4 x float> %zn_zm.coerce0, <vscale x 4 x float> %zn_zm.coerce1, i64 noundef %fpm) #0 {
# | entry:
# |   %zn_zm = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn_zm.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %fpm.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn_zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn_zm.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn_zm, align 16
# |   %zn_zm1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn_zm, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn_zm1, ptr %zn_zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn_zm.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %5)
# |   %6 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtnb.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret <vscale x 16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtnb.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcvtnt_f8_f32(<vscale x 16 x i8> %zd, <vscale x 4 x float> %zn_zm.coerce0, <vscale x 4 x float> %zn_zm.coerce1, i64 noundef %fpm) #0 {
# | entry:
# |   %zn_zm = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zd.addr = alloca <vscale x 16 x i8>, align 16
# |   %zn_zm.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %fpm.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn_zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn_zm.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn_zm, align 16
# |   %zn_zm1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn_zm, align 16
# |   store <vscale x 16 x i8> %zd, ptr %zd.addr, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn_zm1, ptr %zn_zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %zd.addr, align 16
# |   %3 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn_zm.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %3, 0
# |   %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %3, 1
# |   %6 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %6)
# |   %7 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtnt.nxv4f32(<vscale x 16 x i8> %2, <vscale x 4 x float> %4, <vscale x 4 x float> %5)
# |   ret <vscale x 16 x i8> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtnt.nxv4f32(<vscale x 16 x i8>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp8,+sve,+sve2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005580cc8aeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005580cc8abe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005580cc8af62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab7df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab7df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab7df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab7df1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005580cc844bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005580cc844a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005580cc8298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005580cc4d8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005580cc4d8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fab7df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab7df1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab7df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005580cc4d8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve/maxnmv.c (593 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/maxnmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @test_svmaxnmv_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call half @llvm.aarch64.sve.fmaxnmv.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret half %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.sve.fmaxnmv.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @test_svmaxnmv_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call float @llvm.aarch64.sve.fmaxnmv.nxv4f32(<vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret float %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.sve.fmaxnmv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @test_svmaxnmv_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call double @llvm.aarch64.sve.fmaxnmv.nxv2f64(<vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret double %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.sve.fmaxnmv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x000055e5e71ddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e5e71dae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e5e71de62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3efd933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3efd98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3efd933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3efd91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e5e7173bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e5e7173a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e5e71588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e5e6e07e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e5e6e07b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3efd91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3efd91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3efd91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e5e6e07a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c (594 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fe33fadeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fe33faae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fe33fae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f05c1333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f05c138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f05c1333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f05c131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fe33f43bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fe33f43a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fe33f288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fe33bd7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fe33bd7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f05c131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f05c131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f05c131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fe33bd7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c (595 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.6a -target-feature +f8f32mm -target-feature +fp8  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.6a -target-feature +f8f32mm -target-feature +fp8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <4 x float> @test_vmmlaq_f32_mf8(<4 x float> noundef %p0, <16 x i8> %p1, <16 x i8> %p2, i64 noundef %p3) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <4 x float>, align 16
# |   %p0.addr = alloca <4 x float>, align 16
# |   %p1.addr = alloca <16 x i8>, align 16
# |   %p2.addr = alloca <16 x i8>, align 16
# |   %p3.addr = alloca i64, align 8
# |   store <4 x float> %p0, ptr %p0.addr, align 16
# |   store <16 x i8> %p1, ptr %p1.addr, align 16
# |   store <16 x i8> %p2, ptr %p2.addr, align 16
# |   store i64 %p3, ptr %p3.addr, align 8
# |   %0 = load <4 x float>, ptr %p0.addr, align 16
# |   %1 = load <16 x i8>, ptr %p1.addr, align 16
# |   %2 = load <16 x i8>, ptr %p2.addr, align 16
# |   %3 = load i64, ptr %p3.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %fmmla.i = call <4 x float> @llvm.aarch64.neon.fmmla.v4f32.v16i8(<4 x float> %4, <16 x i8> %5, <16 x i8> %6)
# |   store <4 x float> %fmmla.i, ptr %ref.tmp.i, align 16
# |   %8 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %8, ptr %__ret.i, align 16
# |   %9 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.aarch64.neon.fmmla.v4f32.v16i8(<4 x float>, <16 x i8>, <16 x i8>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+cmpbr,+complxnum,+cpa,+crc,+cssc,+dit,+dotprod,+f8f32mm,+faminmax,+flagm,+fp-armv8,+fp8,+fullfp16,+hbc,+hinte,+i8mm,+jsconv,+lse,+lsui,+lut,+mec,+mops,+neon,+occmo,+pauth,+predres,+ras,+rasv2,+rcpc,+rdm,+rme,+sb,+spe-eef,+specres2,+ssbs,+sve,+sve2,+sve2p1,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v8.9a,+v8a,+v9.1a,+v9.2a,+v9.3a,+v9.4a,+v9.5a,+v9.6a,+v9a,+wfxt" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000563276abdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563276abae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563276abe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8838049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f88380a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8838049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8838031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563276a53bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563276a53a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563276a388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005632766e7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005632766e7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8838032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f88380330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f88380330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005632766e7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c (596 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svextq_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.extq.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 0)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.extq.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svextq_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.extq.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 4)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svextq_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.extq.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.extq.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svextq_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.extq.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 5)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svextq_u32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.extq.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 2)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.extq.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svextq_s32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.extq.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 3)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextq_u64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.extq.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.extq.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextq_s64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.extq.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 0)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svextq_f16(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.extq.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 7)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.extq.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svextq_f32(<vscale x 4 x float> %zn, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x float>, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.extq.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 2)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.extq.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svextq_f64(<vscale x 2 x double> %zn, <vscale x 2 x double> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x double>, align 16
# |   %zm.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x double> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.extq.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i32 0)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.extq.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svextq_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.extq.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i32 6)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.extq.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svextq_mf8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr,
# | ...
# `---data was truncated (10240/11061) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000560600a57eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560600a54e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560600a5862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f094e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f094e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f094e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f094e431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005606009edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005606009eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005606009d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560600681e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560600681b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f094e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f094e4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f094e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560600681a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c (597 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f16m1x6(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f32m1x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f64m1x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei64_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de3a45aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055de3a457e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055de3a45b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f598661bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f59866725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f598661ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5986603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de3a3f0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055de3a3f0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055de3a3d58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055de3a084e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055de3a084b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5986604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f59866050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f59866050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de3a084a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c (598 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmerge_vvm_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmerge_vxm_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmerge_vvm_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmerge_vxm_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmerge_vvm_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmerge_vxm_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmerge_vvm_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmerge_vxm_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmerge_vvm_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr =
# | ...
# `---data was truncated (10240/124514) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ebe0cc7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ebe0cc4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ebe0cc862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f64e2733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f64e278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f64e2733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f64e271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ebe0c5dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ebe0c5da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ebe0c428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ebe08f1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ebe08f1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f64e271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f64e271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f64e271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ebe08f1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c (599 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4(<vscale x 16 x half> %vd, <vscale x 16 x half> %v
# | ...
# `---data was truncated (10240/148843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556bade61eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556bade5ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556bade6262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f015e81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f015e8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f015e81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f015e803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556baddf7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556baddf7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556badddc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556bada8be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556bada8bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f015e804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f015e8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f015e8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556bada8ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c (600 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zknh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c  -check-prefix=RV32ZKNH
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zknh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha256sig0(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sha256sig0(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha256sig1(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sha256sig1(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha256sum0(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sha256sum0(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha256sum1(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sha256sum1(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha512sig0h(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.sha512sig0h(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha512sig0l(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.sha512sig0l(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha512sig1h(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.sha512sig1h(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha512sig1l(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.sha512sig1l(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha512sum0r(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.sha512sum0r(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha512sum1r(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.sha512sum1r(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha256sig0(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha256sig1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha256sum0(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha256sum1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha512sig0h(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha512sig0l(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha512sig1h(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha512sig1l(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha512sum0r(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha512sum1r(i32, i32) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zknh" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zknh1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b148509eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b148506e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b14850a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0590b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0590b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0590b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0590b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b14849fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b14849fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b1484848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b148133e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b148133b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0590b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0590b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0590b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b148133a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c -check-prefix=RV32ZKNH
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c -check-prefix=RV32ZKNH
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve/rsqrts.c (601 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/rsqrts.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrsqrts_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.frsqrts.x.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frsqrts.x.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrsqrts_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.frsqrts.x.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frsqrts.x.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrsqrts_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.frsqrts.x.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frsqrts.x.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x000055f42e194eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f42e191e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f42e19562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fafb2c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fafb2ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fafb2c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fafb2c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f42e12abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f42e12aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f42e10f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f42ddbee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f42ddbeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fafb2c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fafb2c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fafb2c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f42ddbea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c (602 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> %0, <vscale x 32 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load
# | ...
# `---data was truncated (10240/410391) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c4f107eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c4f107be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c4f107f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe8a3c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe8a3ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe8a3c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe8a3c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c4f1014bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c4f1014a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c4f0ff98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c4f0ca8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c4f0ca8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe8a3c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe8a3c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe8a3c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c4f0ca8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c (603 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f16m1x6(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f32m1x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f64m1x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei32_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d00049eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558d00046e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558d0004a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7f02449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7f024a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7f02449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7f02431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558cfffdfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558cfffdfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558cfffc48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558cffc73e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558cffc73b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7f02432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7f024330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7f024330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558cffc73a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c (604 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f16m1x5(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f32m1x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f64m1x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005556268deeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005556268dbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005556268df62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcf88849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcf888a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcf88849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcf88831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555626874bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555626874a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005556268598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555626508e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555626508b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcf88832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcf888330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcf888330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555626508a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c (605 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_i8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e8_v_i8mf2x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e8_v_i8m1x7_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_u8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_u8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e8_v_u8mf2x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e8_v_u8m1x7_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv8i1(target("riscv.vector.tup
# | ...
# `---data was truncated (10240/11031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d33f85eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558d33f82e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558d33f8662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2937f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2937f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2937f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2937f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d33f1bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558d33f1ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558d33f008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558d33bafe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558d33bafb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2937f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2937f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2937f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d33bafa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c (606 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vle32ff_v_f32mf2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.mask.nxv1f32.i64.p0(<vscale x 1 x float> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.mask.nxv1f32.i64.p0(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vle32ff_v_f32m1_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.mask.nxv2f32.i64.p0(<vscale x 2 x float> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 2 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.mask.nxv2f32.i64.p0(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vle32ff_v_f32m2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.mask.nxv4f32.i64.p0(<vscale x 4 x float> poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 4 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.mask.nxv4f32.i64.p0(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vle32ff_v_f32m4_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.mask.nxv8f32.i64.p0(<vscale x 8 x float> poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 8 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.mask.nxv8f32.i64.p0(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vle32ff_v_f32m8_m(<vscale x 16 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.mask.nxv16f32.i64.p0(<vscale x 16 x float> poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 16 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 16 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.mask.nxv16f32.i64.p0(<vscale x 16 x float>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32ff_v_i32mf2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.mask.nxv1i32.i64.p0(<vscale x 1 x i32> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x i32>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i32>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.mask.nxv1i32.i64.p0(<vscale x 1 x i32>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32ff_v_i32m1_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.mask.nxv2i32.i64.p0(<vscale x 2 x i32> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 2 x i32>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i32>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.mask.nxv2i32.i64.p0(<vscale x 2 x i32>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32ff_v_i32m2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.mask.nxv4i32.i64.p0(<vscale x 4 x i32> poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   
# | ...
# `---data was truncated (10240/19123) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f188edbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f188ed8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f188edc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7928905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f792895c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7928905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f79288ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f188e71bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f188e71a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f188e568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f188b05e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f188b05b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f79288eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f79288ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f79288ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f188b05a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c (607 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf4_f16m1(<vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf2_f16m1(<vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m1_f16m1(<vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m2_f16m1(<vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m4_f16m1(<vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m8_f16m1(<vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32mf2_f32m1(<vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m1_f32m1(<vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m2_f32m1(<vscale x 4 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x
# | ...
# `---data was truncated (10240/68062) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555f39b97eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555f39b94e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555f39b9862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f24f8333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f24f838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f24f8333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f24f831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f39b2dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555f39b2da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555f39b128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555f397c1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555f397c1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f24f831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f24f831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f24f831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f397c1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c (608 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzpq1_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzpq1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uzpq1.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzpq1_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzpq1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uzpq1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzpq1_u32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzpq1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uzpq1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzpq1_u64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzpq1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uzpq1.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzpq1_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzpq1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzpq1_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzpq1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzpq1_s32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzpq1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzpq1_s64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzpq1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svuzpq1_f16(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.uzpq1.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.uzpq1.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svuzpq1_f32(<vscale x 4 x float> %zn, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x float>, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.uzpq1.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.uzpq1.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svuzpq1_f64(<vscale x 2 x double> %zn, <vscale x 2 x double> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x double>, align 16
# |   %zm.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x double> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.uzpq1.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.uzpq1.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svuzpq1_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.uzpq1.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.uzpq1.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzpq1_mf8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzpq1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %
# | ...
# `---data was truncated (10240/10910) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000559690bdeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559690bdbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559690bdf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faee8333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faee838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faee8333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faee831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559690b74bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559690b74a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559690b598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559690808e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559690808b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faee831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faee831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faee831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559690808a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c (609 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrinti_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frinti.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frinti.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrinti_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frinti.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frinti.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrinti_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frinti.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frinti.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrinti_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.frinti.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrinti_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frinti.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrinti_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frinti.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrinti_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frinti.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrinti_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frinti.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrinti_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frinti.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005598fb8ddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005598fb8dae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005598fb8de62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ed7249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ed72a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ed7249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ed7231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005598fb873bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005598fb873a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005598fb8588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005598fb507e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005598fb507b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4ed7232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ed72330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ed72330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005598fb507a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c (610 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdiv_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdiv_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdiv_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdiv_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdiv_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdiv_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdiv_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdiv_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdiv_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/222475) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563abc73deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563abc73ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563abc73e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa01ba1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa01ba725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa01ba1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa01ba03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563abc6d3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563abc6d3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563abc6b88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563abc367e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563abc367b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa01ba04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa01ba050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa01ba050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563abc367a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c (611 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhsu_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhsu_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1,
# | ...
# `---data was truncated (10240/223801) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005586546a0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055865469de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005586546a162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8908d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8908d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8908d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8908d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558654636bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558654636a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055865461b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005586542cae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005586542cab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8908d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8908d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8908d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005586542caa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c (612 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_bf16mf4x3(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_bf16mf2x3(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_bf16m1x3(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_bf16m2x3(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i
# | ...
# `---data was truncated (10240/12756) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056032e4e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056032e4e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056032e4e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f75e8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f75e818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f75e8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f75e811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056032e47bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056032e47ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056032e4608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056032e10fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056032e10fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f75e811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f75e811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f75e811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056032e10fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c (613 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vv_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vf_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wv_bf16mf4_f32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wf_bf16_f32mf2(<vscale x 1 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vv_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vf_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wv_bf16mf2_f32m1(<vscale x 2 x float> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wf_bf16_f32m1(<vscale x 2 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwadd_vv_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwadd_vf_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.a
# | ...
# `---data was truncated (10240/86092) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de2d432eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055de2d42fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055de2d43362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd4f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd4f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd4f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd4f831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de2d3c8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055de2d3c8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055de2d3ad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055de2d05ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055de2d05cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbd4f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd4f8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd4f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de2d05ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c (614 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsaddu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsaddu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsaddu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsaddu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsaddu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsaddu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsaddu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsaddu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsaddu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, ali
# | ...
# `---data was truncated (10240/223367) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005654e2cdfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005654e2cdce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005654e2ce062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4fc4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4fc438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4fc4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4fc431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005654e2c75bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005654e2c75a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005654e2c5a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005654e2909e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005654e2909b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4fc431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4fc431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4fc431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005654e2909a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c (615 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vncvt_x_x_w_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8>, <vscale x 32 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr
# | ...
# `---data was truncated (10240/126428) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558fd16d1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558fd16cee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558fd16d262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab14c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab14ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab14c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab14c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558fd1667bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558fd1667a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558fd164c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558fd12fbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558fd12fbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fab14c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab14c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab14c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558fd12fba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c (616 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrem_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrem_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrem_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrem_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrem_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrem_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrem_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrem_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrem_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrem.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrem.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrem_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrem.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrem.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vrem_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/97639) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a656a74eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a656a71e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a656a7562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb0441bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb044725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb0441ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb04403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a656a0abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a656a0aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a6569ef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a65669ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a65669eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feb04404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb044050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb044050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a65669ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c (617 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svabs_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.abs.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.abs.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svabs_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.abs.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.abs.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svabs_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.abs.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.abs.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svabs_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.abs.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.abs.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svabs_s8_m(<vscale x 16 x i8> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i8>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.abs.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svabs_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.abs.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svabs_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.abs.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svabs_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.abs.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svabs_s8_x(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.abs.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svabs_s16_x(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.abs.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svabs_s32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1
# | ...
# `---data was truncated (10240/20016) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000557316c53eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557316c50e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557316c5462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9c8ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9c8ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9c8ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9c8ad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557316be9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557316be9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557316bce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055731687de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055731687db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9c8ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9c8ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9c8ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055731687da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c (618 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdf_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdf.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdf.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdf_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdf_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdf_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesdf_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdf_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdf_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretur
# | ...
# `---data was truncated (10240/20190) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005591546a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005591546a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005591546a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d0d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d0d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d0d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d0d11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055915463bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055915463ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005591546208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005591542cfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005591542cfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8d0d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d0d11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d0d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005591542cfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c (619 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f16m1x4(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f16m2x4(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f32m1x4(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f32m2x4(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f64m1x4(ptr noundef %base, <vscale x 1 x i32
# | ...
# `---data was truncated (10240/99762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559530a32eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559530a2fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559530a3362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe25dd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe25dd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe25dd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe25dced507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005595309c8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005595309c8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005595309ad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055953065ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055953065cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe25dceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe25dcef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe25dcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055953065ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminnmaq.c (620 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminnmaq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %0)
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %2)
# |   %4 = call <8 x half> @llvm.minnum.v8f16(<8 x half> %1, <8 x half> %3)
# |   ret <8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.fabs.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.minnum.v8f16(<8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmaq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %0)
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %2)
# |   %4 = call <4 x float> @llvm.minnum.v4f32(<4 x float> %1, <4 x float> %3)
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.fabs.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmaq_m_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x half> @llvm.arm.mve.vminnma.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vminnma.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmaq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x float> @llvm.arm.mve.vminnma.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4)
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vminnma.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>) #2
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558089fc7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558089fc4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558089fc862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6ad4849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6ad48a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6ad4849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6ad4831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558089f5dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558089f5da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558089f428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558089bf1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558089bf1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6ad4832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6ad48330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6ad48330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558089bf1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c (621 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei64_v_f16mf4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei64_v_f16mf2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei64_v_f16m1(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei64_v_f16m2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei64_v_f32mf2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei64_v_f32m1(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei64_v_f32m2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei64_v_f32m4(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vloxei64_v_f64m1(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vloxei64_v_f64m2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.p0.nxv2i64.i64(<vscale x 2 x double> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.p0.nxv2i64.i64(<vscale x 2 x double>, ptr 
# | ...
# `---data was truncated (10240/91267) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562cffa15eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562cffa12e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562cffa1662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b26133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b2618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b26133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b2611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562cff9abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562cff9aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562cff9908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562cff63fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562cff63fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3b2611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b2611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b2611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562cff63fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c (622 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16mf4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16mf2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m1_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m8_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, a
# | ...
# `---data was truncated (10240/44177) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eab2f3eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eab2f3be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eab2f3f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9d72f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9d72f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9d72f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9d72f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eab2ed4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eab2ed4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eab2eb98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eab2b68e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eab2b68b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9d72f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9d72f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9d72f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eab2b68a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c (623 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562a13860eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562a1385de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562a1386162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc15f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc15f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc15f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc15f831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562a137f6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562a137f6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562a137db8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562a1348ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562a1348ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc15f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc15f8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc15f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562a1348aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c (624 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f16m1x4(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f16m2x4(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f32m1x4(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f32m2x4(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f64m1x4(ptr noundef %base, <vscale x 1 x i16
# | ...
# `---data was truncated (10240/99762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a8383abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a8383a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a8383ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0c9fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0c9faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0c9fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0c9fa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a838341bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a838341a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a8383268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a837fd5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a837fd5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0c9fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0c9fa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0c9fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a837fd5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c (625 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmaxu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmaxu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmaxu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmaxu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmaxu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmaxu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmaxu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmaxu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmaxu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op
# | ...
# `---data was truncated (10240/222917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d619acdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d619acae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d619ace62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe6c3133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe6c318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe6c3133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe6c311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d619a63bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d619a63a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d619a488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d6196f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d6196f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe6c311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe6c311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe6c311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d6196f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c (626 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svlastb_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.lastb.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.lastb.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svlastb_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.lastb.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.lastb.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svlastb_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.lastb.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.lastb.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlastb_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.lastb.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.lastb.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svlastb_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.lastb.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svlastb_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.lastb.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svlastb_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.lastb.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlastb_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.lastb.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @test_svlastb_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call half @llvm.aarch64.sve.lastb.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret half %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare half @llvm.aarch64.sve.lastb.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @test_svlastb_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call float @llvm.aarch64.sve.lastb.nxv4f32(<vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret float %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare float @llvm.aarch64.sve.lastb.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @test_svlastb_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call double @llvm.aarch64.sve.lastb.nxv2f64(<vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret double %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare double @llvm.aarch64.sve.lastb.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local bfloat @test_svlastb_bf16(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call bfloat @llvm.aarch64.sve.lastb.nxv8bf16(<vscale x 8 x i1> %2, <vscale x 8 x bfloat> %1)
# |   ret bfloat %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willretur
# | ...
# `---data was truncated (10240/10821) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e2967e2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e2967dfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e2967e362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa44a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa44a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa44a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa44a11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e296778bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e296778a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e29675d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e29640ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e29640cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa44a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa44a11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa44a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e29640ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c (627 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svrev_s8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.vector.reverse.nxv16i8(<vscale x 16 x i8> %0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.reverse.nxv16i8(<vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrev_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.vector.reverse.nxv8i16(<vscale x 8 x i16> %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.vector.reverse.nxv8i16(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrev_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.vector.reverse.nxv4i32(<vscale x 4 x i32> %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.vector.reverse.nxv4i32(<vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrev_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.vector.reverse.nxv2i64(<vscale x 2 x i64> %0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.vector.reverse.nxv2i64(<vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svrev_u8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.vector.reverse.nxv16i8(<vscale x 16 x i8> %0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrev_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.vector.reverse.nxv8i16(<vscale x 8 x i16> %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrev_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.vector.reverse.nxv4i32(<vscale x 4 x i32> %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrev_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.vector.reverse.nxv2i64(<vscale x 2 x i64> %0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrev_f16(<vscale x 8 x half> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x half> @llvm.vector.reverse.nxv8f16(<vscale x 8 x half> %0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.reverse.nxv8f16(<vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrev_f32(<vscale x 4 x float> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x float> @llvm.vector.reverse.nxv4f32(<vscale x 4 x float> %0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.vector.reverse.nxv4f32(<vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrev_f64(<vscale x 2 x double> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x double> @llvm.vector.reverse.nxv2f64(<vscale x 2 x double> %0)
# |   ret <vscale x 2 x double> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.vector.reverse.nxv2f64(<vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svrev_b8(<vscale x 16 x i1> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %1 = call <vscale x 16 x i1> @llvm.vector.reverse.nxv16i1(<vscale x 16 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.vector.reverse.nxv16i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svrev_b16(<vscale x 16 x i1> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.rev.b16(<vscale x 16 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.rev.b16(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svrev_b32(<vscale x 16 x i1> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.rev.b32(<vscale x 16 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.rev.b32(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svrev_b64(<vscale x 16 x i1> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.rev.b64(<vscale x 16 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.rev.b64(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svrev_bf16(<vscale x 8 x bfloat> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.reverse.nxv8bf16(<vscale x 8 x bfloat> %0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.reverse.nxv8bf16(<vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000564995eaeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564995eabe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564995eaf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5533733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f553378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5533733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f553371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564995e44bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564995e44a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564995e298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564995ad8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564995ad8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f553371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f553371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f553371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564995ad8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c (628 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei8_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8
# | ...
# `---data was truncated (10240/160141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563111c60eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563111c5de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563111c6162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd242e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd242ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd242e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd242e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563111bf6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563111bf6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563111bdb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056311188ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056311188ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd242e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd242e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd242e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056311188aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c (629 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasub_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasub_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasub_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasub_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasub_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasub_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasub_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasub_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasub_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/225205) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556ca9293eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556ca9290e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556ca929462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3deb649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3deb6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3deb649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3deb631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ca9229bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556ca9229a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556ca920e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556ca8ebde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556ca8ebdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3deb632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3deb6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3deb6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556ca8ebda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c (630 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzip2_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zip2q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.zip2q.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzip2_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zip2q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.zip2q.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzip2_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zip2q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.zip2q.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzip2_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zip2q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.zip2q.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzip2_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zip2q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzip2_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zip2q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzip2_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zip2q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzip2_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zip2q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svzip2_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.zip2q.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.zip2q.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svzip2_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.zip2q.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.zip2q.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svzip2_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.zip2q.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.zip2q.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svzip2_bf16(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.zip2q.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.zip2q.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005574d5f5feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005574d5f5ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005574d5f6062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f91af449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f91af4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f91af449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f91af431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005574d5ef5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005574d5ef5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005574d5eda8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005574d5b89e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005574d5b89b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f91af432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f91af4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f91af4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005574d5b89a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-vls-bitwise-ops.c (631 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-bitwise-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone -mvscale-min=4 -mvscale-max=4   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i1> @and_bool(<vscale x 16 x i1> noundef %0, <vscale x 16 x i1> noundef %1) #0 {
# | entry:
# |   %retval = alloca <8 x i8>, align 2
# |   %a.addr = alloca <8 x i8>, align 2
# |   %b.addr = alloca <8 x i8>, align 2
# |   %a.coerce = bitcast <vscale x 16 x i1> %0 to <vscale x 2 x i8>
# |   %a = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> %a.coerce, i64 0)
# |   %b.coerce = bitcast <vscale x 16 x i1> %1 to <vscale x 2 x i8>
# |   %b = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> %b.coerce, i64 0)
# |   store <8 x i8> %a, ptr %a.addr, align 2
# |   store <8 x i8> %b, ptr %b.addr, align 2
# |   %2 = load <8 x i8>, ptr %a.addr, align 2
# |   %3 = load <8 x i8>, ptr %b.addr, align 2
# |   %and = and <8 x i8> %2, %3
# |   store <8 x i8> %and, ptr %retval, align 2
# |   %4 = load <8 x i8>, ptr %retval, align 2
# |   %cast.scalable = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> poison, <8 x i8> %4, i64 0)
# |   %5 = bitcast <vscale x 2 x i8> %cast.scalable to <vscale x 16 x i1>
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8>, <8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @and_i8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %and = and <64 x i8> %0, %1
# |   store <64 x i8> %and, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8>, <64 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @and_i16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %and = and <32 x i16> %0, %1
# |   store <32 x i16> %and, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16>, <32 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i32> @and_i32(<vscale x 4 x i32> noundef %a.coerce, <vscale x 4 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i32>, align 16
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca <16 x i32>, align 16
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %b.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i32>, ptr %b.addr, align 16
# |   %and = and <16 x i32> %0, %1
# |   store <16 x i32> %and, ptr %retval, align 16
# |   %2 = load <16 x i32>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> poison, <16 x i32> %2, i64 0)
# |   ret <vscale x 4 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32>, <16 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i64> @and_i64(<vscale x 2 x i64> noundef %a.coerce, <vscale x 2 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i64>, align 16
# |   %a.addr = alloca <8 x i64>, align 16
# |   %b.addr = alloca <8 x i64>, align 16
# |   %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %a.coerce, i64 0)
# |   %b = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %b.coerce, i64 0)
# |   store <8 x i64> %a, ptr %a.addr, align 16
# |   store <8 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i64>, ptr %a.addr, align 16
# |   %1 = load <8 x i64>, ptr %b.addr, align 16
# |   %and = and <8 x i64> %0, %1
# |   store <8 x i64> %and, ptr %retval, align 16
# |   %2 = load <8 x i64>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> poison, <8 x i64> %2, i64 0)
# |   ret <vscale x 2 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64>, <8 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @and_u8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %and = and <64 x i8> %0, %1
# |   store <64 x i8> %and, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @and_u16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %and = and <32 x i16> %0, %1
# |   store <32 x i16> %and, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i32> @and_u32(<vscale x 4 x i32> noundef %a.coerce, <vscale x 4 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i32>, align 16
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca <16 x i32>, align 16
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %b.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i32>, ptr %b.addr, align 16
# |   %and = and <16 x i32> %0, %1
# |   store <16 x i32> %and, ptr %retval, align 16
# |   %2 = load <16 x i32>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> poison, <16 x i32> %2, i64 0)
# |   ret <vscale x 4 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i64> @and_u64(<vscale x
# | ...
# `---data was truncated (10240/35910) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x0000558a11fd3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558a11fd0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558a11fd462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3becc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3becca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3becc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3becc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a11f69bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558a11f69a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558a11f4e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558a11bfde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558a11bfdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3becc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3becc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3becc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a11bfda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c (632 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uwq_u32(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1uwq.nxv4i32.p0(<vscale x 1 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1uwq.nxv4i32.p0(<vscale x 1 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uwq_vnum_u32(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = getelementptr <vscale x 1 x i32>, ptr %1, i64 -8
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1uwq.nxv4i32.p0(<vscale x 1 x i1> %2, ptr %3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uwq_s32(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1uwq.nxv4i32.p0(<vscale x 1 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uwq_vnum_s32(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = getelementptr <vscale x 1 x i32>, ptr %1, i64 7
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1uwq.nxv4i32.p0(<vscale x 1 x i1> %2, ptr %3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svld1uwq_f32(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.ld1uwq.nxv4f32.p0(<vscale x 1 x i1> %2, ptr %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ld1uwq.nxv4f32.p0(<vscale x 1 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svld1uwq_vnum_f32(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = getelementptr <vscale x 1 x float>, ptr %1, i64 -8
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.ld1uwq.nxv4f32.p0(<vscale x 1 x i1> %2, ptr %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1udq_u64(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1udq.nxv2i64.p0(<vscale x 1 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1udq.nxv2i64.p0(<vscale x 1 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1udq_vnum_u64(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = getelementptr <vscale x 1 x i64>, ptr %1, i64 7
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1udq.nxv2i64.p0(<vscale x 1 x i1> %2, ptr %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1udq_s64(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1udq.nxv2i64.p0(<vscale x 1 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1udq_vnum_s64(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = getelementptr <vscale x 1 x i64>, ptr %1, i64 -8
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1udq.nxv2i64.p0(<vscale x 1 x i1> %2, ptr %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svld1udq_f64(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.ld1udq.nxv2f64.p0(<vscale x 1 x i1> %2, ptr %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ld1udq.nxv2f64.p0(<vscale x 1 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svld1udq_vnum_f64(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = getelementptr <vscale x 1 x double>, ptr %1, i64 7
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.ld1udq.nxv2f64.p0(<vscale x 1 x i1> %2, ptr %3)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"
# | ...
# `---data was truncated (10240/10573) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055f600c6ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f600c69e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f600c6d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3368b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3368b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3368b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3368b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f600c02bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f600c02a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f600be78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f600896e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f600896b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3368b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3368b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3368b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f600896a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c (633 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaadd_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaadd_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaadd_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaadd_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaadd_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaadd_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaadd_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaadd_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaadd_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, al
# | ...
# `---data was truncated (10240/225213) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b108d1ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b108d19e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b108d1d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7d7181bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7d718725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7d7181ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7d71803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b108cb2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b108cb2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b108c978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b108946e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b108946b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7d71804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7d718050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7d718050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b108946a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c (634 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vfms_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <4 x half>, align 8
# |   %__p1.addr.i2 = alloca <4 x half>, align 8
# |   %__p2.addr.i3 = alloca <4 x half>, align 8
# |   %__ret.i4 = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <4 x half>, ptr %__p0.addr.i, align 8
# |   %4 = load <4 x half>, ptr %__p1.addr.i, align 8
# |   %fneg.i = fneg <4 x half> %4
# |   %5 = load <4 x half>, ptr %__p2.addr.i, align 8
# |   store <4 x half> %3, ptr %__p0.addr.i1, align 8
# |   store <4 x half> %fneg.i, ptr %__p1.addr.i2, align 8
# |   store <4 x half> %5, ptr %__p2.addr.i3, align 8
# |   %6 = load <8 x i8>, ptr %__p0.addr.i1, align 8
# |   %7 = load <8 x i8>, ptr %__p1.addr.i2, align 8
# |   %8 = load <8 x i8>, ptr %__p2.addr.i3, align 8
# |   %9 = bitcast <8 x i8> %6 to <4 x half>
# |   %10 = bitcast <8 x i8> %7 to <4 x half>
# |   %11 = bitcast <8 x i8> %8 to <4 x half>
# |   %12 = call <4 x half> @llvm.fma.v4f16(<4 x half> %10, <4 x half> %11, <4 x half> %9)
# |   store <4 x half> %12, ptr %ref.tmp.i, align 8
# |   %13 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %13, ptr %__ret.i4, align 8
# |   %14 = load <4 x half>, ptr %__ret.i4, align 8
# |   store <4 x half> %14, ptr %__ret.i, align 8
# |   %15 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %15
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vfmsq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <8 x half>, align 16
# |   %__p1.addr.i2 = alloca <8 x half>, align 16
# |   %__p2.addr.i3 = alloca <8 x half>, align 16
# |   %__ret.i4 = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <8 x half>, ptr %__p0.addr.i, align 16
# |   %4 = load <8 x half>, ptr %__p1.addr.i, align 16
# |   %fneg.i = fneg <8 x half> %4
# |   %5 = load <8 x half>, ptr %__p2.addr.i, align 16
# |   store <8 x half> %3, ptr %__p0.addr.i1, align 16
# |   store <8 x half> %fneg.i, ptr %__p1.addr.i2, align 16
# |   store <8 x half> %5, ptr %__p2.addr.i3, align 16
# |   %6 = load <16 x i8>, ptr %__p0.addr.i1, align 16
# |   %7 = load <16 x i8>, ptr %__p1.addr.i2, align 16
# |   %8 = load <16 x i8>, ptr %__p2.addr.i3, align 16
# |   %9 = bitcast <16 x i8> %6 to <8 x half>
# |   %10 = bitcast <16 x i8> %7 to <8 x half>
# |   %11 = bitcast <16 x i8> %8 to <8 x half>
# |   %12 = call <8 x half> @llvm.fma.v8f16(<8 x half> %10, <8 x half> %11, <8 x half> %9)
# |   store <8 x half> %12, ptr %ref.tmp.i, align 16
# |   %13 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %13, ptr %__ret.i4, align 16
# |   %14 = load <8 x half>, ptr %__ret.i4, align 16
# |   store <8 x half> %14, ptr %__ret.i, align 16
# |   %15 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %15
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vfma_n_f16(<4 x half> noundef %a, <4 x half> noundef %b, half noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca half, align 2
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca <4 x half>, align 8
# |   %__s1 = alloca <4 x half>, align 8
# |   %__s2 = alloca half, align 2
# |   %.compoundliteral = alloca <4 x half>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store half %c, ptr %c.addr, align 2
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__s0, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %1, ptr %__s1, align 8
# |   %2 = load half, ptr %c.addr, align 2
# |   store half %2, ptr %__s2, align 2
# |   %3 = load <4 x half>, ptr %__s0, align 8
# |   %4 = load <4 x half>, ptr %__s1, align 8
# |   %5 = load half, ptr %__s2, align 2
# |   %vecinit = insertelement <4 x half> poison, half %5, i32 0
# |   %6 = load half, ptr %__s2, align 2
# |   %vecinit1 = insertelement <4 x half> %vecinit, half %6, i32 1
# |   %7 = load half, ptr %__s2, align 2
# |   %vecinit2 = insertelement <4 x half> %vecinit1, half %7, i32 2
# |   %8 = load half, ptr %__s2, align 2
# |   %vecinit3 = insertelement <4 x half> %vecinit2, half %8, i32 3
# |   store <4 x half> %vecinit3, ptr %.compoundliteral, align 8
# |   %9 = load <4 x half>, ptr %.compoundliteral, align 8
# |   store <4 x half> %3, ptr %__p0.addr.i, align 8
# |   store <4 x half> %4, ptr %__p1.addr.i, align 8
# |   store <4 x half> %9, ptr %__p2.addr.i, align 8
# |   %10 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %11 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %13 = bitcast <8 x i8> %10 to <4 x half>
# |   %14 = bitcast <8 x i8> %11 to <4 x half>
# |   %15 = bitcast <8 x i8> %12 to <4 x half>
# |   %16 = call <4 x half> @llvm.fma.v4f16(<4 x half> %14, <4 x half> %15, <4 x half> %13)
# |   store <4 x half> %16, ptr %ref.tmp.i, align 8
# |   %17 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %17, ptr %__ret.i, align 8
# |   %18 = load <4 x half>, ptr %__ret.i, align 8
# |   store <4 x half> %18, ptr %__ret, align 8
# |   %19 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %19, ptr %tmp, align 8
# |   %20 = load <4 x half>, ptr %tmp, align 8
# |   ret <4 x half> %20
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vfmaq_n_f16(<8 x half> noundef %a, <8 x half> noundef %b, half noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca half, align 2
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca <8 x half>, align 16
# |   %__s1 = alloca <8 x half>, align 16
# |   %__s2 = alloca half, align 2
# |   %.compoundliteral = alloca <8 x half>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store half %c, ptr %c.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__s0, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %1, ptr %__s1, align 16
# |   %2 = load half, ptr %c.addr, align 2
# |   store half %2, ptr %__s2, align 2
# |   %3 = load <8 x half>, ptr %__s0, align 16
# |   %4 = load <8 x half>, ptr %__s1, align 16
# |   %5 = load half, ptr %__s2, align 2
# |   %vecinit = insertelement <8 x half> poison, half %5, i32 0
# |   %6 = load half, ptr %__s2, align 2
# |   %vecinit1 = insertelement <8 x half> %vecinit, half %6, i32 1
# |   %7 = load half, ptr %__s2, align 2
# |   %vecinit2 = insertelement <8 x half> %vecinit1, half %7, i32 2
# |   %8 = load half, ptr %__s2, align 2
# |   %vecinit3 = insertelement <8 x half> %vecinit2, half %8, i32 3
# |   %9 = load half, ptr %__s2, align 2
# |   %vecinit4 = insertelement <8 x half> %vecinit3, half %9, i32 4
# |   %10 = load half, ptr %__s2, align 2
# |   %vecinit5 = insertelement <8 x half> %vecinit4, half %10, i32 5
# |   %11 = load half, ptr %__s2, align 2
# |   %vecinit6 = insertelement <8 x half> %vecinit5, half %11, i32 6
# |   %12 = load half, ptr %__s2, align 2
# |   %vecinit7 = insertelement <8 x half> %vecinit6, half %12, i32 7
# |   store <8 x half> %vecinit7, ptr %.compoundliteral, align 16
# |   %13 = load <8 x half>, ptr %.compoundliteral, align 16
# |   store <8 x half> %3, ptr %__p0.addr.i, align 16
# |   store <8 x half> %4, ptr %__p1.addr.i, align 16
# |   store <8 x half> %13, ptr %__p2.addr.i, align 16
# |   %14 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %15 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %16 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %17 = bitcast <16 x i8> %14 to <8 x half>
# |   %18 = bitcast <16 x i8> %15 to <8 x half>
# |   %19 = bitcast <16 x i8> %16 to <8 x half>
# |   %20 = call <8 x half> @llvm.fma.v8f16(<8 x half> %18, <8 x half> %19, <8 x half> %17)
# |   store <8 x half> %20, ptr %ref.tmp.i, align 16
# |   %21 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %21, ptr %__ret.i, align 16
# |   %22 = load <8 x half>, ptr %__ret.i, align 16
# |   store <8 x half> %22, ptr %__ret, align 16
# |   %23 = load <8 x half>, ptr %__ret, align 16
# |   store <8 x half> %23, ptr %tmp, align 16
# |   %24 = load <8 x half>, ptr %tmp, align 16
# |   ret <8 x half
# | ...
# `---data was truncated (10240/31903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055f8bace9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f8bace6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f8bacea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbe7fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbe7faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbe7fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbe7fa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f8bac7fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f8bac7fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f8bac648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f8ba913e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f8ba913b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbe7fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbe7fa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbe7fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f8ba913a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c (635 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vbrev8_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vbrev8_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vbrev8_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vbrev8_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vbrev8_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vbrev8_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vbrev8_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vbrev8_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vbrev8_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vbrev8_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vbrev8_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vbrev8.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vbrev8.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vbrev8_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vbrev8.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vbrev8.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vbrev8_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vbrev8.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale 
# | ...
# `---data was truncated (10240/40937) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055978e00deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055978e00ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055978e00e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd4f2c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd4f2ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd4f2c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd4f2c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055978dfa3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055978dfa3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055978df888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055978dc37e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055978dc37b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd4f2c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd4f2c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd4f2c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055978dc37a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c (636 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4(<vscale x 16 x half> %vd, <vsc
# | ...
# `---data was truncated (10240/149137) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b39093eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563b39090e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563b3909462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4da2c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4da2ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4da2c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4da2c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b39029bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563b39029a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563b3900e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563b38cbde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563b38cbdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4da2c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4da2c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4da2c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b38cbda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c (637 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef3_s8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svundef3_s16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svundef3_s32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svundef3_s64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef3_u8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svundef3_u16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svundef3_u32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svundef3_u64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svundef3_f16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svundef3_f32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @test_svundef3_f64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef3_mf8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svundef3_bf16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } undef
# | }
# | 
# | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | !llvm.errno.tbaa = !{!4}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# | !4 = !{!5, !6, i64 0}
# | !5 = !{!"__libc_errno", !6, i64 0}
# | !6 = !{!"int", !7, i64 0}
# | !7 = !{!"omnipotent char", !8, i64 0}
# | !8 = !{!"Simple C/C++ TBAA"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005601026d1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005601026cee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005601026d262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f93f2d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f93f2d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f93f2d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f93f2d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560102667bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560102667a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056010264c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005601022fbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005601022fbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f93f2d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f93f2d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f93f2d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005601022fba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c (638 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8dot2 -target-feature +fp8dot4 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8dot2 -target-feature +fp8dot4 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdot_f32_mf8(<vscale x 4 x float> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fdot.nxv4f32(<vscale x 4 x float> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fp8.fdot.nxv4f32(<vscale x 4 x float>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdot_n_f32_mf8(<vscale x 4 x float> %zda, <vscale x 16 x i8> %zn, <1 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <1 x i8>, align 1
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <1 x i8> %zm, ptr %zm.addr, align 1
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <1 x i8>, ptr %zm.addr, align 1
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = extractelement <1 x i8> %2, i64 0
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %4, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fdot.nxv4f32(<vscale x 4 x float> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svdot_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fdot.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.fdot.nxv8f16(<vscale x 8 x half>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svdot_n_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <1 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <1 x i8>, align 1
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <1 x i8> %zm, ptr %zm.addr, align 1
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <1 x i8>, ptr %zm.addr, align 1
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = extractelement <1 x i8> %2, i64 0
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %4, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fdot.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdot_lane_f32_mf8(<vscale x 4 x float> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fdot.lane.nxv4f32(<vscale x 4 x float> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fp8.fdot.lane.nxv4f32(<vscale x 4 x float>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svdot_lane_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fdot.lane.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 7)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.fdot.lane.nxv8f16(<vscale x 8 x half>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp8dot2,+fp8dot4,+sve,+sve2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055cdabdf4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cdabdf1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cdabdf562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5454a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5454a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5454a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5454a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cdabd8abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cdabd8aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cdabd6f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cdaba1ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cdaba1eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5454a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5454a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5454a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cdaba1ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c (639 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_f16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_f16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_f16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_i16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_i16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_i16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_u16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_u16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_u16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", 
# | ...
# `---data was truncated (10240/23365) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f3379ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564f33799e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564f3379d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4dc6049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4dc60a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4dc6049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4dc6031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f33732bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564f33732a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564f337178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564f333c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564f333c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4dc6032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4dc60330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4dc60330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f333c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c (640 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsqrshr_u16_u32_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqrshr.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, i32 16)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqrshr.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsqrshr_s16_s32_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshr.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, i32 16)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqrshr.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsqrshr_u8_u32_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %zn.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 1
# |   %7 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 2
# |   %8 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 3
# |   %9 = call <vscale x 16 x i8> @llvm.aarch64.sve.uqrshr.x4.nxv4i32(<vscale x 4 x i32> %5, <vscale x 4 x i32> %6, <vscale x 4 x i32> %7, <vscale x 4 x i32> %8, i32 8)
# |   ret <vscale x 16 x i8> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uqrshr.x4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsqrshr_s8_s32_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %zn.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 1
# |   %7 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 2
# |   %8 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 3
# |   %9 = call <vscale x 16 x i8> @llvm.aarch64.sve.sqrshr.x4.nxv4i32(<vscale x 4 x i32> %5, <vscale x 4 x i32> %6, <vscale x 4 x i32> %7, <vscale x 4 x i32> %8, i32 8)
# |   ret <vscale x 16 x i8> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.sqrshr.x4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsqrshr_u16_u64_x4(<vscale x 2 x i64> %zn.coerce0, <vscale x 2 x i64> %zn.coerce1, <vscale x 2 x i64> %zn.coerce2, <vscale x 2 x i64> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, <vscale x 2 x i64> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %zn.coerce3, 3
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 1
# |   %7 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 2
# |   %8 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 3
# |   %9 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqrshr.x4.nxv2i64(<vscale x 2 x i64> %5, <vscale x 2 x i64> %6, <vscale x 2 x i64> %7, <vscale x 2 x i64> %8, i32 16)
# |   ret <vscale x 8 x i16> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqrshr.x4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscal
# | ...
# `---data was truncated (10240/33461) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055f58f521eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f58f51ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f58f52262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb4f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb4f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb4f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb4f31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f58f4b7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f58f4b7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f58f49c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f58f14be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f58f14bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffb4f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb4f31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb4f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f58f14ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c (641 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1q_scatter_u64base_offset_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv2i64.nxv2i64(<vscale x 2 x i64> %3, <vscale x 1 x i1> %4, <vscale x 2 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv2i64.nxv2i64(<vscale x 2 x i64>, <vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1q_scatter_u64base_offset_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv2i64.nxv2i64(<vscale x 2 x i64> %3, <vscale x 1 x i1> %4, <vscale x 2 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1q_scatter_u64base_offset_u32(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %4 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv4i32.nxv2i64(<vscale x 4 x i32> %3, <vscale x 1 x i1> %4, <vscale x 2 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv4i32.nxv2i64(<vscale x 4 x i32>, <vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1q_scatter_u64base_offset_s32(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %4 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv4i32.nxv2i64(<vscale x 4 x i32> %3, <vscale x 1 x i1> %4, <vscale x 2 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1q_scatter_u64base_offset_u16(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %4 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv8i16.nxv2i64(<vscale x 8 x i16> %3, <vscale x 1 x i1> %4, <vscale x 2 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv8i16.nxv2i64(<vscale x 8 x i16>, <vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1q_scatter_u64base_offset_s16(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %4 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv8i16.nxv2i64(<vscale x 8 x i16> %3, <vscale x 1 x i1> %4, <vscale x 2 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1q_scatter_u64base_offset_u8(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %4 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv16i8.nxv2i64(<vscale x 16 x i8> %3, <vscale x 1 x i1> %4, <vscale x 2 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv16i8.nxv2i64(<vscale x 16 x i8>, <vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1q_scatter_u64base_offset_s8(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %4 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv16i8.nxv2i64(<vscale x 16 x i8> %3, <vscale x 1 x i1> %
# | ...
# `---data was truncated (10240/93831) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055eae897eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eae897be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eae897f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efccdd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efccdd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efccdd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efccdd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eae8914bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eae8914a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eae88f98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eae85a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eae85a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efccdd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efccdd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efccdd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eae85a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c (642 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vslidedown_vx_f16mf4(<vscale x 1 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vslidedown_vx_f16mf2(<vscale x 2 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vslidedown_vx_f16m1(<vscale x 4 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vslidedown_vx_f16m2(<vscale x 8 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vslidedown_vx_f16m4(<vscale x 16 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vslidedown_vx_f16m8(<vscale x 32 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vslidedown_vx_f32mf2(<vscale x 1 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vslidedown_vx_f32m1(<vscale x 2 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vslidedown_vx_f32m2(<vscale x 4 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vslidedown_vx_f32m4(<vscale x 8 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64, i64,
# | ...
# `---data was truncated (10240/120460) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005572b2e36eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005572b2e33e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005572b2e3762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb0da41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb0da4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb0da41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb0da403507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005572b2dccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005572b2dcca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005572b2db18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005572b2a60e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005572b2a60b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb0da404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb0da4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb0da4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005572b2a60a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c (643 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f16m1x5(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f32m1x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f64m1x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a825107eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a825104e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a82510862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa252d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa252d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa252d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa252d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a82509dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a82509da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a8250828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a824d31e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a824d31b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa252d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa252d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa252d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a824d31a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c (644 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557002b2eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557002b2be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557002b2f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9fc0733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9fc078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9fc0733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9fc071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557002ac4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557002ac4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557002aa98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557002758e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557002758b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9fc071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9fc071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9fc071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557002758a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c (645 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f16m1x4(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_f16m2x4(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f32m1x4(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_f32m2x4(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f64m1x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captu
# | ...
# `---data was truncated (10240/87308) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562f9c2caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562f9c2c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562f9c2cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2915849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f29158a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2915849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2915831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562f9c260bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562f9c260a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562f9c2458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562f9bef4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562f9bef4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2915832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f29158330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f29158330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562f9bef4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c (646 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgather_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %index.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %index.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgather_vx_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %index.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgather_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %index.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %index.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgather_vx_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %index.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgather_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %index.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %index.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgather_vx_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %index.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgather_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %index.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgather_vx_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %index.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgather_vv_f16m4_tu(<vscale x 16 x half> %ma
# | ...
# `---data was truncated (10240/619127) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005571e73ceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005571e73cbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005571e73cf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb90f21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb90f2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb90f21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb90f203507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005571e7364bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005571e7364a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005571e73498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005571e6ff8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005571e6ff8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb90f204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb90f2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb90f2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005571e6ff8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c (647 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f16m1x5(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f32m1x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f64m1x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei8_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none
# | ...
# `---data was truncated (10240/61673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559694942eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055969493fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055969494362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7cc9649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7cc96a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7cc9649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7cc9631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005596948d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005596948d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005596948bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055969456ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055969456cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7cc9632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7cc96330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7cc96330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055969456ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c (648 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_w_bf16mf4_f8e4m3mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_w_bf16mf4_f8e4m3mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_w_bf16mf2_f8e4m3mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_w_bf16mf2_f8e4m3mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_w_bf16m1_f8e4m3mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_sat_f_f_w_bf16m1_f8e4m3mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_f_f_w_bf16m2_f8e4m3m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_sat_f_f_w_bf16m2_f8e4m3m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_f_f_w_bf16m4_f8e4m3m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_sat_f_f_w_bf16m4_f8e4m3m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_f_f_w_bf16m8_f8e4m3m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.f.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> poison, <vscale x 32 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.f.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_sat_f_f_w_bf16m8_f8e4m3m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x
# | ...
# `---data was truncated (10240/84802) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b8f6d00eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b8f6cfde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b8f6d0162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0de2733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0de278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0de2733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0de271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b8f6c96bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b8f6c96a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b8f6c7b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b8f692ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b8f692ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0de271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0de271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0de271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b8f692aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c (649 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmulhu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = allo
# | ...
# `---data was truncated (10240/98179) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559775116eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559775113e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055977511762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f13bcd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13bcd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f13bcd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f13bcd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005597750acbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005597750aca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005597750918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559774d40e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559774d40b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f13bcd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13bcd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13bcd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559774d40a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c (650 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vctz_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vctz_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vctz.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vctz.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vctz_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vctz.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vctz.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vctz_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vctz.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vctz.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vctz_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vctz.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vctz.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vctz_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vctz.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vctz.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vctz_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vctz.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vctz.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vctz_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vctz.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vctz.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vctz_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vctz.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vctz.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vctz_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vctz.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vctz.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test
# | ...
# `---data was truncated (10240/94993) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557a0c4bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557a0c4b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557a0c4bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f29ec449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f29ec4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f29ec449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f29ec431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557a0c452bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557a0c452a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557a0c4378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557a0c0e6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557a0c0e6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f29ec432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f29ec4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f29ec4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557a0c0e6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c (651 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_w_bf16mf4_f8e4m3mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_w_bf16mf4_f8e4m3mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_w_bf16mf2_f8e4m3mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_w_bf16mf2_f8e4m3mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_w_bf16m1_f8e4m3mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_sat_f_f_w_bf16m1_f8e4m3mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_f_f_w_bf16m2_f8e4m3m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_sat_f_f_w_bf16m2_f8e4m3m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_f_f_w_bf16m4_f8e4m3m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_sat_f_f_w_bf16m4_f8e4m3m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %
# | ...
# `---data was truncated (10240/201226) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560e3bb39eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560e3bb36e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560e3bb3a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffaa8533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffaa858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffaa8533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffaa851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e3bacfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560e3bacfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560e3bab48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560e3b763e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560e3b763b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffaa851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffaa851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffaa851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e3b763a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c (652 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_i16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_i16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_i16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_u16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_u16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8),
# | ...
# `---data was truncated (10240/53330) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f46c944eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f46c941e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f46c94562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f219af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f219af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f219af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f219af1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f46c8dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f46c8daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f46c8bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f46c56ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f46c56eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f219af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f219af1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f219af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f46c56ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c (653 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vgmul_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vgmul_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vgmul_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vgmul_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vgmul_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d3ea37eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558d3ea34e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558d3ea3862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2174933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f217498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2174933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f217491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d3e9cdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558d3e9cda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558d3e9b28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558d3e661e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558d3e661b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f217491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f217491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f217491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d3e661a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c (654 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vor_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vor_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vor_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vor_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vor_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vor_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vor_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vor_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vor_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.add
# | ...
# `---data was truncated (10240/424041) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d6f2fe3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d6f2fe0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d6f2fe462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f52fb849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f52fb8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f52fb849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f52fb831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d6f2f79bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d6f2f79a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d6f2f5e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d6f2c0de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d6f2c0db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f52fb832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f52fb8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f52fb8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d6f2c0da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c (655 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei32_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i
# | ...
# `---data was truncated (10240/32100) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b51be88eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b51be85e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b51be8962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f758dc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f758dc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f758dc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f758dc03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b51be1ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b51be1ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b51be038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b51bab2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b51bab2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f758dc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f758dc050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f758dc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b51bab2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c (656 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16mf4(ptr noundef %base, <vscale x 1 x i16> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16mf2(ptr noundef %base, <vscale x 2 x i16> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16m1(ptr noundef %base, <vscale x 4 x i16> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16m2(ptr noundef %base, <vscale x 8 x i16> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16m4(ptr noundef %base, <vscale x 16 x i16> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16m8(ptr noundef %base, <vscale x 32 x i16> %bindex, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> %2, ptr %0, <vscale x 32 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f32mf2(ptr noundef %base, <vscale x 1 x i16> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f32m1(ptr noundef %base, <vscale x 2 x i16> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f32m2(ptr noundef %base, <vscale x 4 x i16> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i16> %1, i6
# | ...
# `---data was truncated (10240/132470) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056210ceb7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056210ceb4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056210ceb862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f169b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f169b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f169b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f169b31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056210ce4dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056210ce4da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056210ce328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056210cae1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056210cae1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f169b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f169b31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f169b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056210cae1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c (657 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhu_vv_u64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhu_vx_u64m1(<vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulhu_vv_u64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulhu_vx_u64m2(<vscale x 2 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulhu_vv_u64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 4 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulhu_vx_u64m4(<vscale x 4 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulhu_vv_u64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 8 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulhu_vx_u64m8(<vscale x 8 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhu_vv_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhu_vx_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load i64, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulhu.mask.nxv1i64.i6
# | ...
# `---data was truncated (10240/18619) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e60b6e7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e60b6e4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e60b6e862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faf3cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faf3cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faf3cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faf3cc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e60b67dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e60b67da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e60b6628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e60b311e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e60b311b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faf3cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faf3cc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faf3cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e60b311a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmlldav.c (658 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmlldav.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaq_s16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <8 x i16>, ptr %b.addr, align 8
# |   %5 = load <8 x i16>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 0, i32 0, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32, i32, i32, i32, i32, <8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <4 x i32>, ptr %b.addr, align 8
# |   %5 = load <4 x i32>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 0, i32 0, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32, i32, i32, i32, i32, <4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaq_u16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <8 x i16>, ptr %b.addr, align 8
# |   %5 = load <8 x i16>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 1, i32 0, i32 0, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaq_u32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <4 x i32>, ptr %b.addr, align 8
# |   %5 = load <4 x i32>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 1, i32 0, i32 0, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaxq_s16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <8 x i16>, ptr %b.addr, align 8
# |   %5 = load <8 x i16>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 0, i32 1, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaxq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <4 x i32>, ptr %b.addr, align 8
# |   %5 = load <4 x i32>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 0, i32 1, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlsldavaq_s16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <8 x i16>, ptr %b.addr, align 8
# |   %5 = load <8 x i16>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 1, i32 0, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlsldavaq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <4 x i32>, ptr %b.addr, align 8
# |   %5 = load <4 x i32>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 1, i32 0, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlsldaxvaq_s16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <8 x i16>, ptr %b.addr, align 8
# |   %5 = load <8 x i16>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 1, i32 1, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlsldavaxq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <4 x i32>, ptr %b.addr, align 8
# |   %5 = load <4 x i32>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 1, i32 1, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vrmlaldavhaq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, al
# | ...
# `---data was truncated (10240/58468) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000563e04d22eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563e04d1fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563e04d2362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc03c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc03c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc03c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc03c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e04cb8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563e04cb8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563e04c9d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563e0494ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563e0494cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc03c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc03c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc03c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e0494ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c (659 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlse16_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16.p0.i64(<vscale x 1 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlse16_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16.p0.i64(<vscale x 2 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlse16_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16.p0.i64(<vscale x 4 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlse16_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16.p0.i64(<vscale x 8 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlse16_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16.p0.i64(<vscale x 16 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlse16_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16.p0.i64(<vscale x 32 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vlse16_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16.p0.i64(<vscale x 1 x i16> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vlse16_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16.p0.i64(<vscale x 2 x i16> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vlse16_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vlse.nxv4i16.p0.i64(<vscale x 4 x i16> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i16> @llvm.riscv
# | ...
# `---data was truncated (10240/83637) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556c01e7ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556c01e79e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556c01e7d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3591849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f35918a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3591849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3591831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556c01e12bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556c01e12a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556c01df78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556c01aa6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556c01aa6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3591832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f35918330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f35918330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556c01aa6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c (660 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_f16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_f16mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_f16m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_f16m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_i16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_i16mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_i16m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_i16m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_u16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store tar
# | ...
# `---data was truncated (10240/30818) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005609e5595eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005609e5592e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005609e559662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7000b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7000b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7000b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7000b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005609e552bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005609e552ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005609e55108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005609e51bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005609e51bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7000b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7000b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7000b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005609e51bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c (661 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +f64mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +f64mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1ro_mf8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1ro_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1ro_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1ro.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.ld1ro.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1ro_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1ro.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1ro.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1ro_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1ro.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1ro.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1ro_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1ro_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1ro.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1ro_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1ro.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1ro_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1ro.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svld1ro_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.ld1ro.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ld1ro.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svld1ro_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.ld1ro.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ld1ro.nxv4f32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svld1ro_f64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.ld1ro.nxv2f64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ld1ro.nxv2f64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svld1ro_bf16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr 
# | ...
# `---data was truncated (10240/11274) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055803efb6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055803efb3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055803efb762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2c07705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2c0775c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2c07705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2c076ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055803ef4cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055803ef4ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055803ef318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055803ebe0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055803ebe0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2c076eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2c076ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2c076ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055803ebe0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c (662 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f16m1x3(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_f16m2x3(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f32m1x3(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_f32m2x3(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f64m1x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/87892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dca61d1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dca61cee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dca61d262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feff9305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feff935c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feff9305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feff92ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dca6167bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dca6167a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dca614c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dca5dfbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dca5dfbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feff92eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feff92ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feff92ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dca5dfba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c (663 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_tu(<vscale x 1
# | ...
# `---data was truncated (10240/295853) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056220e22eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056220e22be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056220e22f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7fde333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7fde38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7fde333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7fde31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056220e1c4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056220e1c4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056220e1a98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056220de58e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056220de58b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7fde31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7fde31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7fde31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056220de58a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c (664 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svld2q_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld2q.sret.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld2q.sret.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svld2q_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld2q.sret.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svld2q_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld2q.sret.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld2q.sret.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svld2q_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld2q.sret.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svld2q_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld2q.sret.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld2q.sret.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svld2q_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld2q.sret.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svld2q_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld2q.sret.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld2q.sret.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svld2q_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld2q.sret.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svld2q_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld2q.sret.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld2q.sret.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svld2q_bf16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.ld2q.sret.nxv8bf16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.ld2q.sret.nxv8bf16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svld2q_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld2q.sret.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | d
# | ...
# `---data was truncated (10240/75038) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055ff0c888eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ff0c885e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ff0c88962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f61e7649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f61e76a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f61e7649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f61e7631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ff0c81ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ff0c81ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ff0c8038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ff0c4b2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ff0c4b2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f61e7632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61e76330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61e76330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ff0c4b2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c (665 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei32_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei32_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i
# | ...
# `---data was truncated (10240/25624) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563bdb279eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563bdb276e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563bdb27a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4463f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4463f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4463f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4463f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563bdb20fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563bdb20fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563bdb1f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563bdaea3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563bdaea3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4463f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4463f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4463f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563bdaea3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c (666 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vunzipo_v_f16mf4(<vscale x 2 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(<vscale x 1 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(<vscale x 1 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vunzipo_v_f16mf2(<vscale x 4 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(<vscale x 2 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(<vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vunzipo_v_f16m1(<vscale x 8 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vunzipo_v_f16m2(<vscale x 16 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(<vscale x 8 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(<vscale x 8 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vunzipo_v_f16m4(<vscale x 32 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(<vscale x 16 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(<vscale x 16 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vunzipo_v_f32mf2(<vscale x 2 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(<vscale x 1 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(<vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vunzipo_v_f32m1(<vscale x 4 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vunzipo_v_f32m2(<vscale x 8 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(<vscale x 4 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(<vscale x 4 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vunzipo_v_f32m4(<vscale x 16 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(<vscale x 8 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(<vscale x 8 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vunzipo_v_f64m1(<vscale x 2 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64(<vscale x 1 x double>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vunzipo_v_f64m2(<vscale x 4 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.vunzipo.nxv2f64.nxv4f64.i64(<vscale x 2 x double> poison, <vscale x 4 x double> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vunzipo.nxv2f64.nxv4f64.i64(<vscale x 2 x double>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vunzipo_v_f64m4(<vscale x 8 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.vunzipo.nxv4f64.nxv8f64.i64(<vscale x 4 x double> poison, <vscale x 8 x double> %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.vunzipo.nxv4f64.nxv8f64.i64(<vscale x 4 x double>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @
# | ...
# `---data was truncated (10240/35774) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005647a5d46eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005647a5d43e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005647a5d4762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f03f0e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03f0ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f03f0e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f03f0e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005647a5cdcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005647a5cdca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005647a5cc18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005647a5970e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005647a5970b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f03f0e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03f0e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03f0e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005647a5970a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c (667 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005600aee50eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005600aee4de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005600aee5162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc42c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc42c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc42c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc42c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005600aede6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005600aede6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005600aedcb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005600aea7ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005600aea7ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc42c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc42c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc42c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005600aea7aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c (668 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f16m1x4(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f16m2x4(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f32m1x4(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f32m2x4(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f64m1x4(ptr noundef %base, <vscale x 1 x i16
# | ...
# `---data was truncated (10240/99762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005582e4948eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005582e4945e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005582e494962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa77081bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa7708725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa77081ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa770803507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005582e48debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005582e48dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005582e48c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005582e4572e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005582e4572b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa770804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa7708050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa7708050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005582e4572a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c (669 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadd_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadd_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadd_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadd_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadd_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadd_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadd_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadd_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vadd_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vadd_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vadd_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/175163) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c19c3beeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c19c3bbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c19c3bf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6293c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6293c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6293c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6293c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c19c354bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c19c354a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c19c3398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c19bfe8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c19bfe8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6293c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6293c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6293c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c19bfe8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c (670 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmseq_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmseq_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmseq_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmseq_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmseq_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmseq_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmseq_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmseq_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmseq_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmseq_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmseq_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> %0, 
# | ...
# `---data was truncated (10240/171381) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a44020deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a44020ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a44020e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f25f5049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f25f50a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f25f5049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f25f5031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a4401a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a4401a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a4401888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a43fe37e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a43fe37b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f25f5032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f25f50330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f25f50330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a43fe37a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c (671 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmmla_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fmmla.nxv4f32.nxv8bf16(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fmmla.nxv4f32.nxv8bf16(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000556e8bb7eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556e8bb7be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556e8bb7f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc1aca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc1acaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc1aca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc1aca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e8bb14bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556e8bb14a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556e8baf98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556e8b7a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556e8b7a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc1aca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc1aca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc1aca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e8b7a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c (672 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f16m1x4(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_f16m2x4(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f32m1x4(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_f32m2x4(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f64m1x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/87892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561697ef3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561697ef0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561697ef462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbfb421bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbfb42725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbfb421ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbfb4203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561697e89bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561697e89a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561697e6e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561697b1de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561697b1db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbfb4204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbfb42050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbfb42050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561697b1da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-vector-compare-ops.c (673 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-compare-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @eq_bool(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i1>, align 2
# |   %b.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %a, ptr %a.addr, align 2
# |   store <vscale x 16 x i1> %b, ptr %b.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %a.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %b.addr, align 2
# |   %cmp = icmp eq <vscale x 16 x i1> %0, %1
# |   ret <vscale x 16 x i1> %cmp
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @eq_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %cmp = icmp eq <vscale x 16 x i8> %0, %1
# |   %sext = sext <vscale x 16 x i1> %cmp to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @eq_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %cmp = icmp eq <vscale x 8 x i16> %0, %1
# |   %sext = sext <vscale x 8 x i1> %cmp to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @eq_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %cmp = icmp eq <vscale x 4 x i32> %0, %1
# |   %sext = sext <vscale x 4 x i1> %cmp to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @eq_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %cmp = icmp eq <vscale x 2 x i64> %0, %1
# |   %sext = sext <vscale x 2 x i1> %cmp to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @eq_u8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %cmp = icmp eq <vscale x 16 x i8> %0, %1
# |   %sext = sext <vscale x 16 x i1> %cmp to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @eq_u16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %cmp = icmp eq <vscale x 8 x i16> %0, %1
# |   %sext = sext <vscale x 8 x i1> %cmp to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @eq_u32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %cmp = icmp eq <vscale x 4 x i32> %0, %1
# |   %sext = sext <vscale x 4 x i1> %cmp to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @eq_u64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %cmp = icmp eq <vscale x 2 x i64> %0, %1
# |   %sext = sext <vscale x 2 x i1> %cmp to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @eq_f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x half>, align 16
# |   %b.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %b.addr, align 16
# |   %cmp = fcmp oeq <vscale x 8 x half> %0, %1
# |   %sext = sext <vscale x 8 x i1> %cmp to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @eq_f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x float>, align 16
# |   %b.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %b.addr, align 16
# |   %cmp = fcmp oeq <vscale x 4 x float> %0, %1
# |   %sext = sext <vscale x 4 x i1> %cmp to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @eq_f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x double>, align 16
# |   %b.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %b.addr, align 16
# |   %cmp = fcmp oeq <vscale x 2 x double> %0, %1
# |   %sext = sext <vscale x 2 x i1> %cmp to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @neq_bool(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i1>, align 2
# |   %b.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %a, ptr %a.addr, align 2
# |   store <vscale x 16 x i1> %b, ptr %b.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %a.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %b.addr, align 2
# |   %cmp = icmp ne <vscale x 16 x i1> %0, %1
# |   ret <vscale x 16 x i1> %cmp
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @neq_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %cmp = icmp ne <vscale x 16 x i8> %0, %1
# |   %sext = sext <vscale x 16 x i1> %cmp to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @neq_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %cmp = icmp ne <vscale x 8 x i16> %0, %1
# |   %sext = sext <vscale x 8 x i1> %cmp to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @neq_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %cmp = icmp ne <vscale x 4 x i32> %0, %1
# |   %sext = sext <vscale x 4 x i1> %cmp to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @neq_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   stor
# | ...
# `---data was truncated (10240/44453) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x0000560ef0ff5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560ef0ff2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560ef0ff662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f61ae649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f61ae6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f61ae649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f61ae631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ef0f8bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560ef0f8ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560ef0f708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560ef0c1fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560ef0c1fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f61ae632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61ae6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61ae6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ef0c1fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c (674 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsltu_vv_u8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsltu_vx_u8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsltu_vv_u8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsltu_vx_u8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsltu_vv_u8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsltu_vx_u8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsltu_vv_u8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsltu_vx_u8m1_b8(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsltu_vv_u8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsltu_vx_u8m2_b4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsltu_vv_u8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsltu.nxv32i8.n
# | ...
# `---data was truncated (10240/95347) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561016097eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561016094e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056101609862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f305f81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f305f8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f305f81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f305f803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056101602dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056101602da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005610160128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561015cc1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561015cc1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f305f804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f305f8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f305f8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561015cc1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c (675 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svrdffr() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr()
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.rdffr() #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svrdffr_z(<vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr.z(<vscale x 16 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.rdffr.z(<vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x0000559526294eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559526291e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055952629562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f03a1449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03a14a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f03a1449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f03a1431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055952622abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055952622aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055952620f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559525ebee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559525ebeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f03a1432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03a14330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03a14330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559525ebea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c (676 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslideup_vx_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vslideup.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslideup.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslideup_vx_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vslideup.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslideup.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslideup_vx_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vslideup.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslideup.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslideup_vx_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vslideup.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vslideup.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vslideup_vx_bf16m4(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vslideup.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vslideup.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vslideup_vx_bf16m8(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vslideup.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vslideup.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslideup_vx_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vslideup.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslideup.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslideup_vx_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vslideup.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslideup.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>,
# | ...
# `---data was truncated (10240/16521) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559c4652ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559c46529e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559c4652d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa6b1249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa6b12a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa6b1249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa6b1231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c464c2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559c464c2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559c464a78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559c46156e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559c46156b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa6b1232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa6b12330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa6b12330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c46156a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c (677 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b0645b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b0645b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b0645b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3683b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3683b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3683b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3683aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b06454dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b06454da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b0645328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b0641e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b0641e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3683aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3683aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3683aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b0641e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c (678 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssub_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssub_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssub_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssub_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssub_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssub_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssub_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssub_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssub_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x
# | ...
# `---data was truncated (10240/222925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dc6f04beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dc6f048e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dc6f04c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8a00249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8a002a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8a00249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8a00231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc6efe1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dc6efe1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dc6efc68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dc6ec75e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dc6ec75b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8a00232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8a002330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8a002330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc6ec75a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c (679 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vcompress_vm_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vcompress_vm_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vcompress_vm_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vcompress_vm_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vcompress_vm_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x i1> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vcompress_vm_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, <vscale x 32 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x i1> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563af8647eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563af8644e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563af864862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6653b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6653b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6653b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6653b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563af85ddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563af85dda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563af85c28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563af8271e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563af8271b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6653b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6653b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6653b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563af8271a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm.c (680 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_n_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shl <16 x i8> %0, splat (i8 5)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_n_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shl <8 x i16> %0, splat (i16 5)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_n_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = shl <4 x i32> %0, splat (i32 18)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_n_s8_trivial(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shl <16 x i8> %0, zeroinitializer
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_n_s16_trivial(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shl <8 x i16> %0, zeroinitializer
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_n_s32_trivial(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = shl <4 x i32> %0, zeroinitializer
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_n_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shl <16 x i8> %0, splat (i8 3)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_n_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shl <8 x i16> %0, splat (i16 11)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_n_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = shl <4 x i32> %0, splat (i32 7)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_n_u8_trivial(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shl <16 x i8> %0, zeroinitializer
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_n_u16_trivial(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shl <8 x i16> %0, zeroinitializer
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_n_u32_trivial(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = shl <4 x i32> %0, zeroinitializer
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrq_n_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = ashr <16 x i8> %0, splat (i8 4)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrq_n_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = ashr <8 x i16> %0, splat (i16 10)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshrq_n_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = ashr <4 x i32> %0, splat (i32 19)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrq_n_s8_trivial(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = ashr <16 x i8> %0, splat (i8 7)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrq_n_s16_trivial(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = ashr <8 x i16> %0, splat (i16 15)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshrq_n_s32_trivial(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = ashr <4 x i32> %0, splat (i32 31)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrq_n_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = lshr <16 x i8> %0, splat (i8 1)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrq_n_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = lshr <8 x i16> %0, splat (i16 10)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshrq_n_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = lshr <4 x i32> %0, splat (i32 10)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrq_n_u8_trivial(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   ret <16 x i8> zeroinitializer
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrq_n_u16_trivial(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   ret <8 x i16> zeroinitializer
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshrq_n_u32_trivial(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   ret <4 x i32> zeroinitializer
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = call <16 x i8> @llvm.arm.mve.shl.imm.predicated.v16i8.v16i1(<16 x i8> %0, i32 6, <16 x i1> %3, <16 x i8> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.shl.imm.predicated.v16i8.v16i1(<16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_m_n_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.shl.imm.predicated.v8i16.v8i1(<8 x i16> %0, i32 13, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.shl.imm.predicated.v8i16.v8i1(<8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinlin
# | ...
# `---data was truncated (10240/66359) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aea6c3beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aea6c38e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aea6c3c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb76e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb76ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb76e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb76e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aea6bd1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aea6bd1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aea6bb68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aea6865e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aea6865b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffb76e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb76e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb76e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aea6865a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c (681 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_tu(<vs
# | ...
# `---data was truncated (10240/295861) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d5f4b30eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d5f4b2de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d5f4b3162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0fccc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0fccca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0fccc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0fccc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d5f4ac6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d5f4ac6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d5f4aab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d5f475ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d5f475ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0fccc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0fccc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0fccc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d5f475aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c (682 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadd_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadd_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadd_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadd_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadd_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadd_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadd_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadd_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vadd_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/424843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d721042eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d72103fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d72104362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1de6249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1de62a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1de6249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1de6231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d720fd8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d720fd8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d720fbd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d720c6ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d720c6cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1de6232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1de62330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1de62330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d720c6ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c (683 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesem_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesem.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesem.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesem_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesem_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesem_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesem_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesem_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesem_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare
# | ...
# `---data was truncated (10240/20141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005622531a9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005622531a6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005622531aa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1de8049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1de80a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1de8049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1de8031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056225313fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056225313fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005622531248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562252dd3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562252dd3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1de8032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1de80330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1de80330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562252dd3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c (684 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei16_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558112630eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055811262de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055811263162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7bf4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7bf438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7bf4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7bf431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005581125c6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005581125c6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005581125ab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055811225ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055811225ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7bf431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7bf431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7bf431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055811225aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c (685 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.
# | ...
# `---data was truncated (10240/101394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c91c91beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c91c918e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c91c91c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0448849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f04488a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0448849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0448831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c91c8b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c91c8b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c91c8968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c91c545e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c91c545b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0448832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f04488330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f04488330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c91c545a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c (686 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm3me_vv_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm3me_vv_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm3me_vv_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm3me_vv_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm3me_vv_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005587496e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005587496e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005587496ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b22a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b22aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b22a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b22a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055874967fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055874967fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005587496648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558749313e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558749313b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3b22a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b22a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b22a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558749313a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c (687 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsub_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsub_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsub_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsub_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsub_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsub_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsub_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsub_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsub_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsub_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsub_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/175163) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005602ed0fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005602ed0f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005602ed0fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f30f9a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f30f9aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f30f9a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f30f9a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005602ed092bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005602ed092a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005602ed0778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005602ecd26e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005602ecd26b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f30f9a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f30f9a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f30f9a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005602ecd26a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c (688 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei8_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_f32m1x2_tu(target("riscv.vector.
# | ...
# `---data was truncated (10240/295525) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556fde14eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556fde14be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556fde14f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f19a841bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f19a84725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f19a841ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f19a8403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556fde0e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556fde0e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556fde0c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556fddd78e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556fddd78b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f19a8404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f19a84050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f19a84050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556fddd78a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c (689 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f16m1x3(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_f16m2x3(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f32m1x3(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_f32m2x3(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f64m1x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/87892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b57598deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b57598ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b57598e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f774e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f774e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f774e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f774e11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b575923bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b575923a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b5759088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b5755b7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b5755b7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f774e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f774e11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f774e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b5755b7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c (690 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmax_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretu
# | ...
# `---data was truncated (10240/61937) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f77db7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559f77db4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559f77db862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f12d5533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f12d558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f12d5533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f12d551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f77d4dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559f77d4da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559f77d328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559f779e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559f779e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f12d551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f12d551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f12d551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f779e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c (691 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16mf4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16mf4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, p
# | ...
# `---data was truncated (10240/33435) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a5386eceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a5386e9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a5386ed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f99f6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f99f6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f99f6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f99f6b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a538682bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a538682a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a5386678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a538316e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a538316b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f99f6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f99f6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f99f6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a538316a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c (692 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve-f16f32mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve-f16f32mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_f32f16(<vscale x 4 x float> %acc, <vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
# | entry:
# |   %acc.addr = alloca <vscale x 4 x float>, align 16
# |   %a.addr = alloca <vscale x 8 x half>, align 16
# |   %b.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 4 x float> %acc, ptr %acc.addr, align 16
# |   store <vscale x 8 x half> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %acc.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %a.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %b.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fmmla.nxv4f32.nxv8f16(<vscale x 4 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fmmla.nxv4f32.nxv8f16(<vscale x 4 x float>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-f16f32mm" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055641d6bfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055641d6bce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055641d6c062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe659449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe6594a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe659449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe659431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055641d655bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055641d655a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055641d63a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055641d2e9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055641d2e9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe659432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe6594330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe6594330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055641d2e9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c (693 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3e
# | ...
# `---data was truncated (10240/228857) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055646a66beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055646a668e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055646a66c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa264d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa264d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa264d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa264d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055646a601bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055646a601a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055646a5e68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055646a295e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055646a295b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa264d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa264d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa264d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055646a295a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c (694 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaaddu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaaddu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaaddu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaaddu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaaddu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaaddu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaaddu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaaddu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaaddu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# | 
# | ...
# `---data was truncated (10240/225655) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005644d397ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005644d3979e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005644d397d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f432e41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f432e4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f432e41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f432e403507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005644d3912bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005644d3912a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005644d38f78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005644d35a6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005644d35a6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f432e404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f432e4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f432e4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005644d35a6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c (695 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_f64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_f64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_i64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_i64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_u64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_u64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_f64m1x4_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("r
# | ...
# `---data was truncated (10240/36023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563ce548beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563ce5488e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563ce548c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c69249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c692a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c69249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c69231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ce5421bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563ce5421a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563ce54068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563ce50b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563ce50b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7c69232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c692330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c692330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ce50b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve/dup.c (696 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/dup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o -        /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdup_n_s8(i8 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i8, align 1
# |   store i8 %op, ptr %op.addr, align 1
# |   %0 = load i8, ptr %op.addr, align 1
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdup_n_s16(i16 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i16, align 2
# |   store i16 %op, ptr %op.addr, align 2
# |   %0 = load i16, ptr %op.addr, align 2
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdup_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdup_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdup_n_u8(i8 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i8, align 1
# |   store i8 %op, ptr %op.addr, align 1
# |   %0 = load i8, ptr %op.addr, align 1
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdup_n_u16(i16 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i16, align 2
# |   store i16 %op, ptr %op.addr, align 2
# |   %0 = load i16, ptr %op.addr, align 2
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdup_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdup_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svdup_n_f16(half noundef %op) #0 {
# | entry:
# |   %op.addr = alloca half, align 2
# |   store half %op, ptr %op.addr, align 2
# |   %0 = load half, ptr %op.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.aarch64.sve.dup.x.nxv8f16(half %0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.dup.x.nxv8f16(half) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdup_n_f32(float noundef %op) #0 {
# | entry:
# |   %op.addr = alloca float, align 4
# |   store float %op, ptr %op.addr, align 4
# |   %0 = load float, ptr %op.addr, align 4
# |   %1 = call <vscale x 4 x float> @llvm.aarch64.sve.dup.x.nxv4f32(float %0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.dup.x.nxv4f32(float) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svdup_n_f64(double noundef %op) #0 {
# | entry:
# |   %op.addr = alloca double, align 8
# |   store double %op, ptr %op.addr, align 8
# |   %0 = load double, ptr %op.addr, align 8
# |   %1 = call <vscale x 2 x double> @llvm.aarch64.sve.dup.x.nxv2f64(double %0)
# |   ret <vscale x 2 x double> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.dup.x.nxv2f64(double) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svdup_n_b8(i1 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i8, align 1
# |   %storedv = zext i1 %op to i8
# |   store i8 %storedv, ptr %op.addr, align 1
# |   %0 = load i8, ptr %op.addr, align 1
# |   %loadedv = icmp ne i8 %0, 0
# |   %.splatinsert = insertelement <vscale x 16 x i1> poison, i1 %loadedv, i64 0
# |   %.splat = shufflevector <vscale x 16 x i1> %.splatinsert, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
# |   ret <vscale x 16 x i1> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svdup_n_b16(i1 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i8, align 1
# |   %storedv = zext i1 %op to i8
# |   store i8 %storedv, ptr %op.addr, align 1
# |   %0 = load i8, ptr %op.addr, align 1
# |   %loadedv = icmp ne i8 %0, 0
# |   %.splatinsert = insertelement <vscale x 8 x i1> poison, i1 %loadedv, i64 0
# |   %.splat = shufflevector <vscale x 8 x i1> %.splatinsert, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %.splat)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svdup_n_b32(i1 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i8, align 1
# |   %storedv = zext i1 %op to i8
# |   store i8 %storedv, ptr %op.addr, align 1
# |   %0 = load i8, ptr %op.addr, align 1
# |   %loadedv = icmp ne i8 %0, 0
# |   %.splatinsert = insertelement <vscale x 4 x i1> poison, i1 %loadedv, i64 0
# |   %.splat = shufflevector <vscale x 4 x i1> %.splatinsert, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %.splat)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svdup_n_b64(i1 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i8, align 1
# |   %storedv = zext i1 %op to i8
# |   store i8 %storedv, ptr %op.addr, align 1
# |   %0 = load i8, ptr %op.addr, align 1
# |   %loadedv = icmp ne i8 %0, 0
# |   %.splatinsert = insertelement <vscale x 2 x i1> poison, i1 %loadedv, i64 0
# |   %.splat = shufflevector <vscale x 2 x i1> %.splatinsert, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %.splat)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svdup_n_bf16(bfloat noundef %op) #0 {
# | entry:
# |   %op.addr = alloca bfloat, align 2
# |   store bfloat %op, ptr %op.addr, align 2
# |   %0 = load bfloat, ptr %op.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.dup.x.nxv8bf16(bfloat %0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.dup.x.nxv8bf16(bfloat) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdup_n_s8_z(<vscale x 16 x i1> %pg, i8 noundef %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca i8, align 1
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store i8 %op, ptr %op.addr, align 1
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load i8, ptr %op.addr, align 1
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, i8 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.dup.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, i8) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdup_n_s16_z(<vscale x 16 x i1> %pg, i16 noundef %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca i16, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store i16 %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load i16, ptr %op.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vsca
# | ...
# `---data was truncated (10240/49557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S
# |  #0 0x00005592e3013eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005592e3010e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005592e301462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9b6dd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9b6dd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9b6dd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9b6dced507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005592e2fa9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005592e2fa9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005592e2f8e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005592e2c3de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005592e2c3db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9b6dceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9b6dcef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9b6dcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005592e2c3da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/arm64_vdupq_n_f64.c (697 of 27911)
******************** TEST 'Clang :: CodeGen/arm64_vdupq_n_f64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c"
# | target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-apple-ios7"
# | 
# | ; Function Attrs: noinline nounwind
# | define <2 x double> @test_vdupq_n_f64(double noundef %w) #0 {
# | entry:
# |   %__p0.addr.i = alloca double, align 8
# |   %__ret.i = alloca <2 x double>, align 16
# |   %.compoundliteral.i = alloca <2 x double>, align 16
# |   %w.addr = alloca double, align 8
# |   store double %w, ptr %w.addr, align 8
# |   %0 = load double, ptr %w.addr, align 8
# |   store double %0, ptr %__p0.addr.i, align 8
# |   %1 = load double, ptr %__p0.addr.i, align 8
# |   %vecinit.i = insertelement <2 x double> poison, double %1, i32 0
# |   %2 = load double, ptr %__p0.addr.i, align 8
# |   %vecinit1.i = insertelement <2 x double> %vecinit.i, double %2, i32 1
# |   store <2 x double> %vecinit1.i, ptr %.compoundliteral.i, align 16
# |   %3 = load <2 x double>, ptr %.compoundliteral.i, align 16
# |   store <2 x double> %3, ptr %__ret.i, align 16
# |   %4 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x float> @test_vdupq_n_f32(float noundef %w) #0 {
# | entry:
# |   %__p0.addr.i = alloca float, align 4
# |   %__ret.i = alloca <4 x float>, align 16
# |   %.compoundliteral.i = alloca <4 x float>, align 16
# |   %w.addr = alloca float, align 4
# |   store float %w, ptr %w.addr, align 4
# |   %0 = load float, ptr %w.addr, align 4
# |   store float %0, ptr %__p0.addr.i, align 4
# |   %1 = load float, ptr %__p0.addr.i, align 4
# |   %vecinit.i = insertelement <4 x float> poison, float %1, i32 0
# |   %2 = load float, ptr %__p0.addr.i, align 4
# |   %vecinit1.i = insertelement <4 x float> %vecinit.i, float %2, i32 1
# |   %3 = load float, ptr %__p0.addr.i, align 4
# |   %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %3, i32 2
# |   %4 = load float, ptr %__p0.addr.i, align 4
# |   %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %4, i32 3
# |   store <4 x float> %vecinit3.i, ptr %.compoundliteral.i, align 16
# |   %5 = load <4 x float>, ptr %.compoundliteral.i, align 16
# |   store <4 x float> %5, ptr %__ret.i, align 16
# |   %6 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <2 x double> @test_vdupq_lane_f64(<1 x double> noundef %V) #0 {
# | entry:
# |   %V.addr = alloca <1 x double>, align 8
# |   %__ret_379 = alloca <2 x double>, align 16
# |   %__s0_379 = alloca <1 x double>, align 8
# |   %__ret = alloca <2 x double>, align 16
# |   %__s0 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x double>, align 16
# |   %tmp1 = alloca <2 x double>, align 16
# |   store <1 x double> %V, ptr %V.addr, align 8
# |   %0 = load <1 x double>, ptr %V.addr, align 8
# |   store <1 x double> %0, ptr %__s0_379, align 8
# |   %1 = load <1 x double>, ptr %__s0_379, align 8
# |   store <1 x double> %1, ptr %__s0, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = bitcast <8 x i8> %2 to <1 x double>
# |   %lane = shufflevector <1 x double> %3, <1 x double> %3, <2 x i32> zeroinitializer
# |   store <2 x double> %lane, ptr %ref.tmp, align 16
# |   %4 = load <2 x double>, ptr %ref.tmp, align 16
# |   store <2 x double> %4, ptr %__ret, align 16
# |   %5 = load <2 x double>, ptr %__ret, align 16
# |   store <2 x double> %5, ptr %tmp, align 16
# |   %6 = load <2 x double>, ptr %tmp, align 16
# |   store <2 x double> %6, ptr %__ret_379, align 16
# |   %7 = load <2 x double>, ptr %__ret_379, align 16
# |   store <2 x double> %7, ptr %tmp1, align 16
# |   %8 = load <2 x double>, ptr %tmp1, align 16
# |   ret <2 x double> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <2 x double> @test_vmovq_n_f64(double noundef %w) #0 {
# | entry:
# |   %__p0.addr.i = alloca double, align 8
# |   %__ret.i = alloca <2 x double>, align 16
# |   %.compoundliteral.i = alloca <2 x double>, align 16
# |   %w.addr = alloca double, align 8
# |   store double %w, ptr %w.addr, align 8
# |   %0 = load double, ptr %w.addr, align 8
# |   store double %0, ptr %__p0.addr.i, align 8
# |   %1 = load double, ptr %__p0.addr.i, align 8
# |   %vecinit.i = insertelement <2 x double> poison, double %1, i32 0
# |   %2 = load double, ptr %__p0.addr.i, align 8
# |   %vecinit1.i = insertelement <2 x double> %vecinit.i, double %2, i32 1
# |   store <2 x double> %vecinit1.i, ptr %.compoundliteral.i, align 16
# |   %3 = load <2 x double>, ptr %.compoundliteral.i, align 16
# |   store <2 x double> %3, ptr %__ret.i, align 16
# |   %4 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x half> @test_vmov_n_f16(ptr noundef %a1) #0 {
# | entry:
# |   %a1.addr = alloca ptr, align 8
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca half, align 2
# |   %.compoundliteral = alloca <4 x half>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   store ptr %a1, ptr %a1.addr, align 8
# |   %0 = load ptr, ptr %a1.addr, align 8
# |   %1 = load half, ptr %0, align 2
# |   store half %1, ptr %__s0, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %vecinit = insertelement <4 x half> poison, half %2, i32 0
# |   %3 = load half, ptr %__s0, align 2
# |   %vecinit1 = insertelement <4 x half> %vecinit, half %3, i32 1
# |   %4 = load half, ptr %__s0, align 2
# |   %vecinit2 = insertelement <4 x half> %vecinit1, half %4, i32 2
# |   %5 = load half, ptr %__s0, align 2
# |   %vecinit3 = insertelement <4 x half> %vecinit2, half %5, i32 3
# |   store <4 x half> %vecinit3, ptr %.compoundliteral, align 8
# |   %6 = load <4 x half>, ptr %.compoundliteral, align 8
# |   store <4 x half> %6, ptr %__ret, align 8
# |   %7 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %7, ptr %tmp, align 8
# |   %8 = load <4 x half>, ptr %tmp, align 8
# |   ret <4 x half> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x half> @test_vmovq_n_f16(ptr noundef %a1) #0 {
# | entry:
# |   %a1.addr = alloca ptr, align 8
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca half, align 2
# |   %.compoundliteral = alloca <8 x half>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   store ptr %a1, ptr %a1.addr, align 8
# |   %0 = load ptr, ptr %a1.addr, align 8
# |   %1 = load half, ptr %0, align 2
# |   store half %1, ptr %__s0, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %vecinit = insertelement <8 x half> poison, half %2, i32 0
# |   %3 = load half, ptr %__s0, align 2
# |   %vecinit1 = insertelement <8 x half> %vecinit, half %3, i32 1
# |   %4 = load half, ptr %__s0, align 2
# |   %vecinit2 = insertelement <8 x half> %vecinit1, half %4, i32 2
# |   %5 = load half, ptr %__s0, align 2
# |   %vecinit3 = insertelement <8 x half> %vecinit2, half %5, i32 3
# |   %6 = load half, ptr %__s0, align 2
# |   %vecinit4 = insertelement <8 x half> %vecinit3, half %6, i32 4
# |   %7 = load half, ptr %__s0, align 2
# |   %vecinit5 = insertelement <8 x half> %vecinit4, half %7, i32 5
# |   %8 = load half, ptr %__s0, align 2
# |   %vecinit6 = insertelement <8 x half> %vecinit5, half %8, i32 6
# |   %9 = load half, ptr %__s0, align 2
# |   %vecinit7 = insertelement <8 x half> %vecinit6, half %9, i32 7
# |   store <8 x half> %vecinit7, ptr %.compoundliteral, align 16
# |   %10 = load <8 x half>, ptr %.compoundliteral, align 16
# |   store <8 x half> %10, ptr %__ret, align 16
# |   %11 = load <8 x half>, ptr %__ret, align 16
# |   store <8 x half> %11, ptr %tmp, align 16
# |   %12 = load <8 x half>, ptr %tmp, align 16
# |   ret <8 x half> %12
# | }
# | 
# | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005614d4b5ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005614d4b59e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005614d4b5d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f502a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f502a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f502a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f502a31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005614d4af2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005614d4af2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005614d4ad78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005614d4786e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005614d4786b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f502a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f502a31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f502a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005614d4786a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c (698 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmulx_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fmulx.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %4, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fmulx.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmulx_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fmulx.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %4, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fmulx.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svmulx_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fmulx.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %4, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fmulx.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmulx_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fmulx.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmulx_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fmulx.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svmulx_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.fmulx.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmulx_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fmulx.u.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fmulx.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmulx_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fmulx.u.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fmulx.u.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svmulx_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 
# | ...
# `---data was truncated (10240/22063) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c635fadeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c635faae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c635fae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa597333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa59738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa597333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa59731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c635f43bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c635f43a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c635f288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c635bd7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c635bd7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa59731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa59731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa59731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c635bd7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c (699 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhsu_vv_i64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhsu_vx_i64m1(<vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulhsu_vv_i64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulhsu_vx_i64m2(<vscale x 2 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulhsu_vv_i64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 4 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulhsu_vx_i64m4(<vscale x 4 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulhsu_vv_i64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 8 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulhsu_vx_i64m8(<vscale x 8 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhsu_vv_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhsu_vx_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load i64, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llv
# | ...
# `---data was truncated (10240/18669) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005589a32eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005589a32ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005589a32ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f824db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f824db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f824db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f824db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589a3284bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005589a3284a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005589a32698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005589a2f18e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005589a2f18b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f824db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f824db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f824db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005589a2f18a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c (700 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcls_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.cls.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.cls.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcls_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.cls.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.cls.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcls_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.cls.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.cls.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcls_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.cls.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.cls.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcls_s8_m(<vscale x 16 x i8> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i8>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.cls.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcls_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.cls.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcls_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.cls.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcls_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.cls.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcls_s8_x(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.cls.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcls_s16_x(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.cls.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcls_s32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1
# | ...
# `---data was truncated (10240/11769) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005615cb842eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005615cb83fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005615cb84362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff6fb049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff6fb0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff6fb049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff6fb031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005615cb7d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005615cb7d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005615cb7bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005615cb46ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005615cb46cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff6fb032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff6fb0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff6fb0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615cb46ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c (701 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtrn1_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.trn1q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.trn1q.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtrn1_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.trn1q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.trn1q.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtrn1_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.trn1q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.trn1q.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtrn1_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.trn1q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.trn1q.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtrn1_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.trn1q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtrn1_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.trn1q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtrn1_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.trn1q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtrn1_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.trn1q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtrn1_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.trn1q.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.trn1q.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtrn1_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.trn1q.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.trn1q.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtrn1_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.trn1q.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.trn1q.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svtrn1_bf16(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.trn1q.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.trn1q.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055889af15eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055889af12e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055889af1662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd549333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd54938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd549333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd54931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055889aeabbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055889aeaba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055889ae908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055889ab3fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055889ab3fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd54931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd54931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd54931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055889ab3fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c (702 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsleu_vv_u8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsleu_vx_u8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsleu_vv_u8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsleu_vx_u8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsleu_vv_u8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsleu_vx_u8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsleu_vv_u8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsleu_vx_u8m1_b8(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsleu_vv_u8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsleu_vx_u8m2_b4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsleu_vv_u8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsleu.n
# | ...
# `---data was truncated (10240/95355) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005619c1172eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005619c116fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005619c117362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6d34905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6d3495c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6d34905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6d348ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005619c1108bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005619c1108a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005619c10ed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005619c0d9ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005619c0d9cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6d348eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6d348ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6d348ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005619c0d9ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve/eorv.c (703 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/eorv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_sveorv_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.eorv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.eorv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_sveorv_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.eorv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.eorv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_sveorv_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.eorv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.eorv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_sveorv_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.eorv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.eorv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_sveorv_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.eorv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_sveorv_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.eorv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_sveorv_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.eorv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_sveorv_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.eorv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x0000560689f9aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560689f97e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560689f9b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8220533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f822058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8220533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f822051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560689f30bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560689f30a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560689f158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560689bc4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560689bc4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f822051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f822051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f822051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560689bc4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c (704 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei64_v_f16mf4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei64_v_f16mf2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei64_v_f16m1(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei64_v_f16m2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei64_v_f32mf2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei64_v_f32m1(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei64_v_f32m2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei64_v_f32m4(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vloxei64_v_f64m1(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vloxei64_v_f64m2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.p0.nxv2i64.i64(<vscale x 2 x double> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.p0.nxv2i64.i64(<vscale x 2 x doubl
# | ...
# `---data was truncated (10240/91275) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b6779d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b6779d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b6779d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e84f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e84f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e84f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e84f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b67796ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b67796ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b6779538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b677602e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b677602b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8e84f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e84f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e84f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b677602a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c (705 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrnbq_n_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 3, i32 0, i32 0, i32 0, i32 0, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8>, <8 x i16>, i32, i32, i32, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrnbq_n_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 9, i32 0, i32 0, i32 0, i32 0, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16>, <4 x i32>, i32, i32, i32, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrnbq_n_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 0, i32 0, i32 1, i32 1, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrnbq_n_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 3, i32 0, i32 0, i32 1, i32 1, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrntq_n_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrntq_n_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 10, i32 0, i32 0, i32 0, i32 0, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrntq_n_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 6, i32 0, i32 0, i32 1, i32 1, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrntq_n_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 10, i32 0, i32 0, i32 1, i32 1, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrnbq_m_n_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 4, i32 0, i32 0, i32 0, i32 0, i32 0, <8 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8>, <8 x i16>, i32, i32, i32, i32, i32, i32, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrnbq_m_n_s32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 13, i32 0, i32 0, i32 0, i32 0, i32 0, <4 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16>, <4 x i32>, i32, i32, i32, i32, i32, i32, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrnbq_m_n_u16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 7, i32 0, i32 0, i32 1, i32 1, i32 0, <8 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrnbq_m_n_u32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 15, i32 0, i32 0, i32 1, i32 1, i32 0, <4 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrntq_m_n_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 6, i32 0, i32 0, i32 0, i32 0, i32 1, <8 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrntq_m_n_s32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 
# | ...
# `---data was truncated (10240/73182) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005615c3e95eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005615c3e92e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005615c3e9662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3bbf133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3bbf18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3bbf133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3bbf11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005615c3e2bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005615c3e2ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005615c3e108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005615c3abfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005615c3abfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3bbf11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3bbf11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3bbf11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615c3abfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c (706 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f755cc9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f755cc6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f755cca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7da3b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7da3b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7da3b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7da3b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f755c5fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f755c5fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f755c448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f7558f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f7558f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7da3b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7da3b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7da3b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f7558f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c (707 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcnt_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.cnt.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.cnt.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcnt_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcnt_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcnt_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.cnt.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.cnt.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcnt_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.cnt.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcnt_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcnt_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcnt_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.cnt.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcnt_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8f16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8f16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcnt_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4f32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4f32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcnt_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.cnt.nxv2f64(<vscale x 2 x i64> zeroi
# | ...
# `---data was truncated (10240/32102) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000556b26e3aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556b26e37e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556b26e3b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f928c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f928c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f928c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f928c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b26dd0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556b26dd0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556b26db58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556b26a64e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556b26a64b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f928c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f928c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f928c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b26a64a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c (708 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svadd_vector_single2_s8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.add.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.add.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svadd_vector_single2_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.add.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svadd_vector_single2_s16(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.add.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.add.single.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svadd_vector_single2_u16(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.add.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svadd_vector_single2_s32(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.add.single.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.add.single.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svadd_vector_single2_u32(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.add.single.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svadd_vector_single2_s64(<vscale x 2 x i64> %zn.coerce0, <vscale x 2 x i64> %zn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zn.coerce1, 1
# |   store { <vscale x
# | ...
# `---data was truncated (10240/34761) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005596d4367eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005596d4364e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005596d436862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f183c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f183c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f183c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f183c831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005596d42fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005596d42fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005596d42e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005596d3f91e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005596d3f91b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f183c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f183c8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f183c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005596d3f91a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c (709 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cc486ceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cc486cbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cc486cf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ec4c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ec4ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ec4c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ec4c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc48664bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cc48664a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cc486498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cc482f8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cc482f8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5ec4c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ec4c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ec4c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc482f8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c (710 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_i16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_i16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_i16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local targ
# | ...
# `---data was truncated (10240/70855) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055802b62eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055802b62be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055802b62f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f56be249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56be2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f56be249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f56be231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055802b5c4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055802b5c4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055802b5a98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055802b258e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055802b258b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f56be232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56be2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56be2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055802b258a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c (711 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfle_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfle_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfle_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64
# | ...
# `---data was truncated (10240/66565) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b6447eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b6447ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b6447ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb3a6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb3a618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb3a6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb3a611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b644784bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b644784a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b6447698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b644418e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b644418b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb3a611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb3a611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb3a611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b644418a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c (712 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfwma -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vf_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vf_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vf_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vf_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <
# | ...
# `---data was truncated (10240/101483) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558f52bfdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558f52bfae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558f52bfe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2dd3a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2dd3aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2dd3a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2dd3a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f52b93bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558f52b93a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558f52b788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558f52827e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558f52827b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2dd3a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2dd3a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2dd3a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f52827a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c (713 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei16_v_f16mf4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei16_v_f16mf2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei16_v_f16m1(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei16_v_f16m2(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei16_v_f16m4(ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vloxei16_v_f16m8(ptr noundef %base, <vscale x 32 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> poison, ptr %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei16_v_f32mf2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei16_v_f32m1(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei16_v_f32m2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei16_v_f32m4(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i16.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i16.i64(<vscale x 8 x floa
# | ...
# `---data was truncated (10240/118156) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056373f6a4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056373f6a1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056373f6a562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b85649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b856a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b85649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b85631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056373f63abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056373f63aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056373f61f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056373f2cee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056373f2ceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8b85632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b856330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b856330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056373f2cea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c (714 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vunzipo_v_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 2 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(<vscale x 1 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(<vscale x 1 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vunzipo_v_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 4 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(<vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(<vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vunzipo_v_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 8 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vunzipo_v_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 16 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(<vscale x 8 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(<vscale x 8 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vunzipo_v_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 32 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(<vscale x 16 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(<vscale x 16 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vunzipo_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 2 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(<vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(<vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vunzipo_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 4 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(<vscale x 2 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vunzipo_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 8 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(<vscale x 4 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(<vscale x 4 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vunzipo_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 16 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(<vscale x 8 x float> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(<vscale x 8 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vunzipo_v_f64m1_tu(<vscale x 1 x double> %vd, <vscale x 2 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x double>, ptr %vs.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declar
# | ...
# `---data was truncated (10240/44434) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bb87a9ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bb87a99e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bb87a9d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd706333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd70638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd706333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd70631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bb87a32bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bb87a32a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bb87a178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bb876c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bb876c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd70631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd70631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd70631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bb876c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c (715 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4au_vx_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4au_vx_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_
# | ...
# `---data was truncated (10240/13617) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b7572d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b7572d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b7572d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3d93505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3d9355c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3d93505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3d934ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b75726ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b75726ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b7572538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b756f02e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b756f02b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3d934eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3d934ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3d934ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b756f02a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c (716 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vle32ff_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(<vscale x 1 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 1 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(<vscale x 1 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vle32ff_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(<vscale x 2 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 2 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(<vscale x 2 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vle32ff_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(<vscale x 4 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(<vscale x 4 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vle32ff_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(<vscale x 8 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 8 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(<vscale x 8 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vle32ff_v_f32m8_tu(<vscale x 16 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(<vscale x 16 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 16 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 16 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(<vscale x 16 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32ff_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(<vscale x 1 x i32> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i32>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i32>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(<vscale x 1 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32ff_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(<vscale x 2 x i32> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x i32>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i32>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(<vscale x 2 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32ff_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.nxv4i32.i64.p0(<vscale x 4 x i32> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x i32>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.
# | ...
# `---data was truncated (10240/78156) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dabe932eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dabe92fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dabe93362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f290d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f290d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f290d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f290d031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dabe8c8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dabe8c8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dabe8ad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dabe55ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dabe55cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f290d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f290d0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f290d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dabe55ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c (717 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmul_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmul_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmul_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmul_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmul_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmul_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmul_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmul_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | ...
# `---data was truncated (10240/302389) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557540d6eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557540d6be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557540d6f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe012705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe01275c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe012705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe0126ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557540d04bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557540d04a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557540ce98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557540998e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557540998b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe0126eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe0126ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe0126ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557540998a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c (718 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f16m1x4(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f16m2x4(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f32m1x4(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f32m2x4(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f64m1x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64
# | ...
# `---data was truncated (10240/99178) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cf4ffa7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cf4ffa4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cf4ffa862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4aef449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4aef4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4aef449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4aef431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf4ff3dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cf4ff3da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cf4ff228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cf4fbd1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cf4fbd1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4aef432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4aef4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4aef4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf4fbd1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/v8.6a-neon-intrinsics.c (719 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/v8.6a-neon-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.6a -target-feature +i8mm  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.6a -target-feature +i8mm -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmmlaq_s32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %r.addr = alloca <4 x i32>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   store <4 x i32> %r, ptr %r.addr, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <4 x i32>, ptr %r.addr, align 16
# |   %1 = load <16 x i8>, ptr %a.addr, align 16
# |   %2 = load <16 x i8>, ptr %b.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vmmla.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vmmla1.i = call <4 x i32> @llvm.aarch64.neon.smmla.v4i32.v16i8(<4 x i32> %vmmla.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vmmla1.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmmlaq_u32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %r.addr = alloca <4 x i32>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   store <4 x i32> %r, ptr %r.addr, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <4 x i32>, ptr %r.addr, align 16
# |   %1 = load <16 x i8>, ptr %a.addr, align 16
# |   %2 = load <16 x i8>, ptr %b.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vmmla.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vmmla1.i = call <4 x i32> @llvm.aarch64.neon.ummla.v4i32.v16i8(<4 x i32> %vmmla.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vmmla1.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vusmmlaq_s32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %r.addr = alloca <4 x i32>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   store <4 x i32> %r, ptr %r.addr, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <4 x i32>, ptr %r.addr, align 16
# |   %1 = load <16 x i8>, ptr %a.addr, align 16
# |   %2 = load <16 x i8>, ptr %b.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vusmmla.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vusmmla1.i = call <4 x i32> @llvm.aarch64.neon.usmmla.v4i32.v16i8(<4 x i32> %vusmmla.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vusmmla1.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vusdot_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x i32>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <2 x i32> %r, ptr %r.addr, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %r.addr, align 8
# |   %1 = load <8 x i8>, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %b.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vusdot.i = bitcast <8 x i8> %3 to <2 x i32>
# |   %vusdot1.i = call <2 x i32> @llvm.aarch64.neon.usdot.v2i32.v8i8(<2 x i32> %vusdot.i, <8 x i8> %4, <8 x i8> %5)
# |   store <2 x i32> %vusdot1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vusdot_lane_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x i32>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret_845 = alloca <2 x i32>, align 8
# |   %__s0_845 = alloca <2 x i32>, align 8
# |   %__s1_845 = alloca <8 x i8>, align 8
# |   %__s2_845 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <2 x i32>, align 8
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp1 = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   %tmp2 = alloca <2 x i32>, align 8
# |   store <2 x i32> %r, ptr %r.addr, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %r.addr, align 8
# |   store <2 x i32> %0, ptr %__s0_845, align 8
# |   %1 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %1, ptr %__s1_845, align 8
# |   %2 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %2, ptr %__s2_845, align 8
# |   %3 = load <2 x i32>, ptr %__s0_845, align 8
# |   %4 = load <8 x i8>, ptr %__s1_845, align 8
# |   %5 = load <2 x i32>, ptr %__s2_845, align 8
# |   store <2 x i32> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x i32>
# |   %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> zeroinitializer
# |   store <2 x i32> %lane, ptr %ref.tmp1, align 8
# |   %8 = load <2 x i32>, ptr %ref.tmp1, align 8
# |   store <2 x i32> %8, ptr %__ret, align 8
# |   %9 = load <2 x i32>, ptr %__ret, align 8
# |   store <2 x i32> %9, ptr %tmp, align 8
# |   %10 = load <2 x i32>, ptr %tmp, align 8
# |   store <2 x i32> %10, ptr %ref.tmp, align 8
# |   %11 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <2 x i32> %3, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %4, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %11, ptr %__p2.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %14 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vusdot.i = bitcast <8 x i8> %12 to <2 x i32>
# |   %vusdot1.i = call <2 x i32> @llvm.aarch64.neon.usdot.v2i32.v8i8(<2 x i32> %vusdot.i, <8 x i8> %13, <8 x i8> %14)
# |   store <2 x i32> %vusdot1.i, ptr %ref.tmp.i, align 8
# |   %15 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %15, ptr %__ret.i, align 8
# |   %16 = load <2 x i32>, ptr %__ret.i, align 8
# |   store <2 x i32> %16, ptr %__ret_845, align 8
# |   %17 = load <2 x i32>, ptr %__ret_845, align 8
# |   store <2 x i32> %17, ptr %tmp2, align 8
# |   %18 = load <2 x i32>, ptr %tmp2, align 8
# |   ret <2 x i32> %18
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vsudot_lane_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x i32>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret_841 = alloca <2 x i32>, align 8
# |   %__s0_841 = alloca <2 x i32>, align 8
# |   %__s1_841 = alloca <8 x i8>, align 8
# |   %__s2_841 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <2 x i32>, align 8
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp1 = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   %tmp2 = alloca <2 x i32>, align 8
# |   store <2 x i32> %r, ptr %r.addr, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %r.addr, align 8
# |   store <2 x i32> %0, ptr %__s0_841, align 8
# |   %1 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %1, ptr %__s1_841, align 8
# |   %2 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %2, ptr %__s2_841, align 8
# |   %3 = load <2 x i32>, ptr %__s0_841, align 8
# |   %4 = load <2 x i32>, ptr %__s2_841, align 8
# |   store <2 x i32> %4, ptr %__s0, align 8
# | 
# | ...
# `---data was truncated (10240/31781) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000056178fee8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056178fee5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056178fee962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f823d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f823d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f823d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f823d231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056178fe7ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056178fe7ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056178fe638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056178fb12e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056178fb12b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f823d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f823d2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f823d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056178fb12a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c (720 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.ld1.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svld1_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.ld1.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ld1.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svld1_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.ld1.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ld1.nxv4f32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svld1_f64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.ld1.nxv2f64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ld1.nxv2f64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1_mf8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1_vnum_s8(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = 
# | ...
# `---data was truncated (10240/63749) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x00005582caa4beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005582caa48e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005582caa4c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efe1cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efe1cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efe1cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efe1cb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005582ca9e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005582ca9e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005582ca9c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005582ca675e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005582ca675b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efe1cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efe1cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efe1cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005582ca675a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c (721 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_x_v_bf16mf4(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_x_v_bf16mf2(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_x_v_bf16m1(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_x_v_bf16m2(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_x_v_bf16m4(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_x_v_bf16m8(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_xu_v_bf16mf4(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_xu_v_bf16mf2(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_xu_v_bf16m1(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_xu_v_bf16m2(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_xu_v_bf16m4(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_xu_v_bf16m8(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv32bf16
# | ...
# `---data was truncated (10240/33616) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055864bcc5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055864bcc2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055864bcc662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa053b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa053b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa053b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa053aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055864bc5bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055864bc5ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055864bc408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055864b8efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055864b8efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa053aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa053aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa053aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055864b8efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c (722 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf8_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf4_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf2_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m1_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m2_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m4_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m8_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmaxu_vs_u16mf4_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556dd1978eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556dd1975e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556dd197962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7abc733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7abc78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7abc733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7abc71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556dd190ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556dd190ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556dd18f38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556dd15a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556dd15a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7abc71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7abc71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7abc71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556dd15a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c (723 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei8_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %m
# | ...
# `---data was truncated (10240/160133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563baadc5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563baadc2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563baadc662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0034f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0034f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0034f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0034f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563baad5bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563baad5ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563baad408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563baa9efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563baa9efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0034f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0034f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0034f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563baa9efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c (724 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svset3_s8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %tuple.coerce2, <vscale x 16 x i8> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %x.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %tuple.coerce2, 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 16 x i8> %x, ptr %x.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %4 = load <vscale x 16 x i8>, ptr %x.addr, align 16
# |   %5 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, <vscale x 16 x i8> %4, 1
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svset3_s16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %tuple.coerce2, <vscale x 8 x i16> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %x.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %tuple.coerce2, 2
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 8 x i16> %x, ptr %x.addr, align 16
# |   %3 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %4 = load <vscale x 8 x i16>, ptr %x.addr, align 16
# |   %5 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, <vscale x 8 x i16> %4, 2
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svset3_s32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1, <vscale x 4 x i32> %tuple.coerce2, <vscale x 4 x i32> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %tuple.coerce2, 2
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   %3 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %4 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %5 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, <vscale x 4 x i32> %4, 0
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svset3_s64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1, <vscale x 2 x i64> %tuple.coerce2, <vscale x 2 x i64> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %x.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, <vscale x 2 x i64> %tuple.coerce2, 2
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 2 x i64> %x, ptr %x.addr, align 16
# |   %3 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple.addr, align 16
# |   %4 = load <vscale x 2 x i64>, ptr %x.addr, align 16
# |   %5 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3, <vscale x 2 x i64> %4, 1
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svset3_u8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %tuple.coerce2, <vscale x 16 x i8> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %x.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %tuple.coerce2, 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 16 x i8> %x, ptr %x.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %4 = load <vscale x 16 x i8>, ptr %x.addr, align 16
# |   %5 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, <vscale x 16 x i8> %4, 2
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svset3_u16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %tuple.coerce2, <vscale x 8 x i16> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %x.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %tuple.coerce2, 2
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 8 x i16> %x, ptr %x.addr, align 16
# |   %3 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %4 = load <vscale x 8 x i16>, ptr %x.addr, align 16
# |   %5 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, <vscale x 8 x i16> %4, 0
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svset3_u32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1, <vscale x 4 x i32> %tuple.coerce2, <vscale
# | ...
# `---data was truncated (10240/25462) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055b7572a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b7572a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b7572a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e39d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e39d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e39d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e39d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b75723bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b75723ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b7572208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b756ecfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b756ecfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0e39d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e39d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e39d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b756ecfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c (725 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +faminmax -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +faminmax -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svamax_f16_x2(<vscale x 8 x half> %zdn.coerce0, <vscale x 8 x half> %zdn.coerce1, <vscale x 8 x half> %zm.coerce0, <vscale x 8 x half> %zm.coerce1) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zdn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn, align 16
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zm.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zdn1, ptr %zdn.addr, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %4, 1
# |   %7 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %7, 0
# |   %9 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %7, 1
# |   %10 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.famax.x2.nxv8f16(<vscale x 8 x half> %5, <vscale x 8 x half> %6, <vscale x 8 x half> %8, <vscale x 8 x half> %9)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.famax.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svamax_f32_x2(<vscale x 4 x float> %zdn.coerce0, <vscale x 4 x float> %zdn.coerce1, <vscale x 4 x float> %zm.coerce0, <vscale x 4 x float> %zm.coerce1) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zdn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zdn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zdn, align 16
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zm.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zdn1, ptr %zdn.addr, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %4, 1
# |   %7 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %7, 0
# |   %9 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %7, 1
# |   %10 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.famax.x2.nxv4f32(<vscale x 4 x float> %5, <vscale x 4 x float> %6, <vscale x 4 x float> %8, <vscale x 4 x float> %9)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.famax.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double> } @test_svamax_f64_x2(<vscale x 2 x double> %zdn.coerce0, <vscale x 2 x double> %zdn.coerce1, <vscale x 2 x double> %zm.coerce0, <vscale x 2 x double> %zm.coerce1) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %zm = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %zdn.addr = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %zm.addr = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %0 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } poison, <vscale x 2 x double> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } %0, <vscale x 2 x double> %zdn.coerce1, 1
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %zdn, align 16
# |   %2 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } poison, <vscale x 2 x double> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } %2, <vscale x 2 x double> %zm.coerce1, 1
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %zm, align 16
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %zdn1, ptr %zdn.addr, align 16
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %4, 0
# |   %6 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %4, 1
# |   %7 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %7, 0
# |   %9 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %7, 1
# |   %10 = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sme.famax.x2.nxv2f64(<vscale x 2 x double> %5, <vscale x 2 x double> %6, <vscale x 2 x double> %8, <vscale x 2 x double> %9)
# |   ret { <vscale x 2 x double>, <vscale x 2 x double> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sme.famax.x2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svamin_f16_x2(<vscale x 8 x half> %zdn.coerce0, <vscale x 8 x half> %zdn.coerce1, <vscale x 8 x half> %zm.coerce0, <vscale x 8 x half> %zm.coerce1) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zdn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn, align 16
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zm.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zdn1, ptr %zdn.addr, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %4, 1
# |   %7 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %7, 0
# |   %9 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %7, 1
# |   %10 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.famin.x2.nxv8f16(<vscale x 8 x half> %5, <vscale x 8 x half> %6, <vscale x 8 x half> %8, <vscale x 8 x half> %9)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.famin.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8
# | ...
# `---data was truncated (10240/45703) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055eaddcaceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eaddca9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eaddcad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb6d1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb6d178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb6d1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb6d171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eaddc42bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eaddc42a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eaddc278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eadd8d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eadd8d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb6d171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb6d171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb6d171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eadd8d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c (726 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_i64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_u64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_i64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_u64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("
# | ...
# `---data was truncated (10240/18506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c7c5733eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c7c5730e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c7c573462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f02c9d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f02c9d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f02c9d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f02c9d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c7c56c9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c7c56c9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c7c56ae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c7c535de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c7c535db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f02c9d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f02c9d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f02c9d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c7c535da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c (727 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadrh_u32base_s32index(<vscale x 4 x i32> %bases, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.adrh.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.adrh.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadrh_u64base_s64index(<vscale x 2 x i64> %bases, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.adrh.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.adrh.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadrh_u32base_u32index(<vscale x 4 x i32> %bases, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.adrh.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadrh_u64base_u64index(<vscale x 2 x i64> %bases, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.adrh.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000559101d55eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559101d52e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559101d5662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5361649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f53616a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5361649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5361631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559101cebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559101ceba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559101cd08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055910197fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055910197fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5361632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f53616330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f53616330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055910197fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c (728 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_gather_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_gather_u64base_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_gather_s64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = zext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1>, ptr, <vscale x 2 x i64>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_gather_s64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = zext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_gather_u64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = zext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_gather_u64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = zext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_gather_u64base_offset_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/18766) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x0000556608dcaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556608dc7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556608dcb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2bcc133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2bcc18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2bcc133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2bcc11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556608d60bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556608d60a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556608d458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005566089f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005566089f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2bcc11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2bcc11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2bcc11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005566089f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c (729 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei8_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei8_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei8_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei8_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei8_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i8> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vluxei8_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, <vscale x 32 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i8> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei8_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei8_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei8_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.
# | ...
# `---data was truncated (10240/288058) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed51414eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ed51411e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ed5141562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3e26249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3e262a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3e26249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3e26231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed513aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ed513aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ed5138f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ed5103ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ed5103eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3e26232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3e262330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3e262330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed5103ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c (730 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f16m1x3(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f16m2x3(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f32m1x3(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f32m2x3(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f64m1x3(ptr noundef %base, <vscale x 1 x i16
# | ...
# `---data was truncated (10240/99762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c388e32eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c388e2fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c388e3362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f49ec105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f49ec15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f49ec105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f49ec0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c388dc8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c388dc8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c388dad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c388a5ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c388a5cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f49ec0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f49ec0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f49ec0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c388a5ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c (731 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacge_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.facge.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.facge.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacge_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.facge.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.facge.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacge_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.facge.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.facge.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacge_n_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, float noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca float, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store float %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 4 x float> poison, float %2, i64 0
# |   %.splat = shufflevector <vscale x 4 x float> %.splatinsert, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.facge.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %.splat)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacge_n_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, double noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca double, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store double %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load double, ptr %op2.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 2 x double> poison, double %2, i64 0
# |   %.splat = shufflevector <vscale x 2 x double> %.splatinsert, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.facge.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %.splat)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000556dd4ae6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556dd4ae3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556dd4ae762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb098849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb0988a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb098849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb098831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556dd4a7cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556dd4a7ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556dd4a618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556dd4710e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556dd4710b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb098832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb0988330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb0988330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556dd4710a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c (732 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulh_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulh_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulh_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulh_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulh_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulh_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulh_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulh_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulh_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulh_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmulh_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr
# | ...
# `---data was truncated (10240/97905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558174737eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558174734e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055817473862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa166f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa166f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa166f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa166f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005581746cdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005581746cda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005581746b28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558174361e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558174361b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa166f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa166f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa166f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558174361a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c (733 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vle16_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vle.nxv1f16.p0.i64(<vscale x 1 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x half> @llvm.riscv.vle.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vle16_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vle.nxv2f16.p0.i64(<vscale x 2 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x half> @llvm.riscv.vle.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vle16_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vle.nxv4f16.p0.i64(<vscale x 4 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x half> @llvm.riscv.vle.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vle16_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vle.nxv8f16.p0.i64(<vscale x 8 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x half> @llvm.riscv.vle.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vle16_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vle.nxv16f16.p0.i64(<vscale x 16 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x half> @llvm.riscv.vle.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vle16_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vle.nxv32f16.p0.i64(<vscale x 32 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x half> @llvm.riscv.vle.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16.p0.i64(<vscale x 1 x i16> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16.p0.i64(<vscale x 2 x i16> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vle16_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16.p0.i64(<vscale x 4 x i16> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vle16_v_i16m2_tu(<vscale x 8 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.p0.i64(<vscale x 8 x i16> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.p0.i64(<vscale x 8 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vle16_v_i16m4_tu(<vscale x 16 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64
# | ...
# `---data was truncated (10240/71955) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e310c06eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e310c03e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e310c0762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fccc7f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fccc7f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fccc7f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fccc7f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e310b9cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e310b9ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e310b818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e310830e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e310830b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fccc7f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fccc7f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fccc7f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e310830a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/neon/add.c (734 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/add.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c --check-prefix=LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vadd_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %add.i = add <8 x i8> %2, %3
# |   store <8 x i8> %add.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vadd_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %add.i = add <4 x i16> %2, %3
# |   store <4 x i16> %add.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vadd_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %add.i = add <2 x i32> %2, %3
# |   store <2 x i32> %add.i, ptr %__ret.i, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vadd_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   %3 = load <1 x i64>, ptr %__p1.addr.i, align 8
# |   %add.i = add <1 x i64> %2, %3
# |   store <1 x i64> %add.i, ptr %__ret.i, align 8
# |   %4 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vadd_f32(<2 x float> noundef %a, <2 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %add.i = fadd <2 x float> %2, %3
# |   store <2 x float> %add.i, ptr %__ret.i, align 8
# |   %4 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vadd_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %add.i = add <8 x i8> %2, %3
# |   store <8 x i8> %add.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vadd_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %add.i = add <4 x i16> %2, %3
# |   store <4 x i16> %add.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vadd_u32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %add.i = add <2 x i32> %2, %3
# |   store <2 x i32> %add.i, ptr %__ret.i, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vadd_u64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   %3 = load <1 x i64>, ptr %__p1.addr.i, align 8
# |   %add.i = add <1 x i64> %2, %3
# |   store <1 x i64> %add.i, ptr %__ret.i, align 8
# |   %4 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vaddq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %add.i = add <16 x i8> %2, %3
# |   store <16 x i8> %add.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vaddq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   %1 = load <8 x i16>, ptr %b.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %3 = load <8 x i16>, ptr %__p1.addr.i, align 16
# |   %add.i = add <8 x i16> %2, %3
# |   store <8 x i16> %add.i, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vaddq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   %1 = load <4 x i32>, ptr %b
# | ...
# `---data was truncated (10240/221881) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# |  #0 0x000055dd2c5f6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dd2c5f3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dd2c5f762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3dfb133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3dfb18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3dfb133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3dfb11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd2c58cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dd2c58ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dd2c5718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dd2c220e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dd2c220b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3dfb11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3dfb11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3dfb11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd2c220a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c --check-prefix=LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c --check-prefix=LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/arm64_vcopy.c (735 of 27911)
******************** TEST 'Clang :: CodeGen/arm64_vcopy.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c"
# | target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-apple-ios7"
# | 
# | ; Function Attrs: noinline nounwind
# | define <16 x i8> @test_vcopyq_laneq_s8(<16 x i8> noundef %a1, <16 x i8> noundef %a2) #0 {
# | entry:
# |   %a1.addr = alloca <16 x i8>, align 16
# |   %a2.addr = alloca <16 x i8>, align 16
# |   %__ret_336 = alloca <16 x i8>, align 16
# |   %__s0_336 = alloca <16 x i8>, align 16
# |   %__s2_336 = alloca <16 x i8>, align 16
# |   %__ret = alloca <16 x i8>, align 16
# |   %__s0 = alloca i8, align 1
# |   %__ret1 = alloca i8, align 1
# |   %__s02 = alloca <16 x i8>, align 16
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   %__s1 = alloca <16 x i8>, align 16
# |   %ref.tmp3 = alloca <16 x i8>, align 16
# |   %tmp4 = alloca <16 x i8>, align 16
# |   %tmp5 = alloca <16 x i8>, align 16
# |   store <16 x i8> %a1, ptr %a1.addr, align 16
# |   store <16 x i8> %a2, ptr %a2.addr, align 16
# |   %0 = load <16 x i8>, ptr %a1.addr, align 16
# |   store <16 x i8> %0, ptr %__s0_336, align 16
# |   %1 = load <16 x i8>, ptr %a2.addr, align 16
# |   store <16 x i8> %1, ptr %__s2_336, align 16
# |   %2 = load <16 x i8>, ptr %__s2_336, align 16
# |   store <16 x i8> %2, ptr %__s02, align 16
# |   %3 = load <16 x i8>, ptr %__s02, align 16
# |   %vgetq_lane = extractelement <16 x i8> %3, i32 13
# |   store i8 %vgetq_lane, ptr %ref.tmp, align 1
# |   %4 = load i8, ptr %ref.tmp, align 1
# |   store i8 %4, ptr %__ret1, align 1
# |   %5 = load i8, ptr %__ret1, align 1
# |   store i8 %5, ptr %tmp, align 1
# |   %6 = load i8, ptr %tmp, align 1
# |   store i8 %6, ptr %__s0, align 1
# |   %7 = load <16 x i8>, ptr %__s0_336, align 16
# |   store <16 x i8> %7, ptr %__s1, align 16
# |   %8 = load i8, ptr %__s0, align 1
# |   %9 = load <16 x i8>, ptr %__s1, align 16
# |   %vset_lane = insertelement <16 x i8> %9, i8 %8, i32 3
# |   store <16 x i8> %vset_lane, ptr %ref.tmp3, align 16
# |   %10 = load <16 x i8>, ptr %ref.tmp3, align 16
# |   store <16 x i8> %10, ptr %__ret, align 16
# |   %11 = load <16 x i8>, ptr %__ret, align 16
# |   store <16 x i8> %11, ptr %tmp4, align 16
# |   %12 = load <16 x i8>, ptr %tmp4, align 16
# |   store <16 x i8> %12, ptr %__ret_336, align 16
# |   %13 = load <16 x i8>, ptr %__ret_336, align 16
# |   store <16 x i8> %13, ptr %tmp5, align 16
# |   %14 = load <16 x i8>, ptr %tmp5, align 16
# |   ret <16 x i8> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <16 x i8> @test_vcopyq_laneq_u8(<16 x i8> noundef %a1, <16 x i8> noundef %a2) #0 {
# | entry:
# |   %a1.addr = alloca <16 x i8>, align 16
# |   %a2.addr = alloca <16 x i8>, align 16
# |   %__ret_328 = alloca <16 x i8>, align 16
# |   %__s0_328 = alloca <16 x i8>, align 16
# |   %__s2_328 = alloca <16 x i8>, align 16
# |   %__ret = alloca <16 x i8>, align 16
# |   %__s0 = alloca i8, align 1
# |   %__ret1 = alloca i8, align 1
# |   %__s02 = alloca <16 x i8>, align 16
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   %__s1 = alloca <16 x i8>, align 16
# |   %ref.tmp3 = alloca <16 x i8>, align 16
# |   %tmp4 = alloca <16 x i8>, align 16
# |   %tmp5 = alloca <16 x i8>, align 16
# |   store <16 x i8> %a1, ptr %a1.addr, align 16
# |   store <16 x i8> %a2, ptr %a2.addr, align 16
# |   %0 = load <16 x i8>, ptr %a1.addr, align 16
# |   store <16 x i8> %0, ptr %__s0_328, align 16
# |   %1 = load <16 x i8>, ptr %a2.addr, align 16
# |   store <16 x i8> %1, ptr %__s2_328, align 16
# |   %2 = load <16 x i8>, ptr %__s2_328, align 16
# |   store <16 x i8> %2, ptr %__s02, align 16
# |   %3 = load <16 x i8>, ptr %__s02, align 16
# |   %vgetq_lane = extractelement <16 x i8> %3, i32 13
# |   store i8 %vgetq_lane, ptr %ref.tmp, align 1
# |   %4 = load i8, ptr %ref.tmp, align 1
# |   store i8 %4, ptr %__ret1, align 1
# |   %5 = load i8, ptr %__ret1, align 1
# |   store i8 %5, ptr %tmp, align 1
# |   %6 = load i8, ptr %tmp, align 1
# |   store i8 %6, ptr %__s0, align 1
# |   %7 = load <16 x i8>, ptr %__s0_328, align 16
# |   store <16 x i8> %7, ptr %__s1, align 16
# |   %8 = load i8, ptr %__s0, align 1
# |   %9 = load <16 x i8>, ptr %__s1, align 16
# |   %vset_lane = insertelement <16 x i8> %9, i8 %8, i32 3
# |   store <16 x i8> %vset_lane, ptr %ref.tmp3, align 16
# |   %10 = load <16 x i8>, ptr %ref.tmp3, align 16
# |   store <16 x i8> %10, ptr %__ret, align 16
# |   %11 = load <16 x i8>, ptr %__ret, align 16
# |   store <16 x i8> %11, ptr %tmp4, align 16
# |   %12 = load <16 x i8>, ptr %tmp4, align 16
# |   store <16 x i8> %12, ptr %__ret_328, align 16
# |   %13 = load <16 x i8>, ptr %__ret_328, align 16
# |   store <16 x i8> %13, ptr %tmp5, align 16
# |   %14 = load <16 x i8>, ptr %tmp5, align 16
# |   ret <16 x i8> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i16> @test_vcopyq_laneq_s16(<8 x i16> noundef %a1, <8 x i16> noundef %a2) #0 {
# | entry:
# |   %a1.addr = alloca <8 x i16>, align 16
# |   %a2.addr = alloca <8 x i16>, align 16
# |   %__ret_346 = alloca <8 x i16>, align 16
# |   %__s0_346 = alloca <8 x i16>, align 16
# |   %__s2_346 = alloca <8 x i16>, align 16
# |   %__ret = alloca <8 x i16>, align 16
# |   %__s0 = alloca i16, align 2
# |   %__ret1 = alloca i16, align 2
# |   %__s02 = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   %__s1 = alloca <8 x i16>, align 16
# |   %ref.tmp3 = alloca <8 x i16>, align 16
# |   %tmp4 = alloca <8 x i16>, align 16
# |   %tmp5 = alloca <8 x i16>, align 16
# |   store <8 x i16> %a1, ptr %a1.addr, align 16
# |   store <8 x i16> %a2, ptr %a2.addr, align 16
# |   %0 = load <8 x i16>, ptr %a1.addr, align 16
# |   store <8 x i16> %0, ptr %__s0_346, align 16
# |   %1 = load <8 x i16>, ptr %a2.addr, align 16
# |   store <8 x i16> %1, ptr %__s2_346, align 16
# |   %2 = load <8 x i16>, ptr %__s2_346, align 16
# |   store <8 x i16> %2, ptr %__s02, align 16
# |   %3 = load <8 x i16>, ptr %__s02, align 16
# |   %vgetq_lane = extractelement <8 x i16> %3, i32 7
# |   store i16 %vgetq_lane, ptr %ref.tmp, align 2
# |   %4 = load i16, ptr %ref.tmp, align 2
# |   store i16 %4, ptr %__ret1, align 2
# |   %5 = load i16, ptr %__ret1, align 2
# |   store i16 %5, ptr %tmp, align 2
# |   %6 = load i16, ptr %tmp, align 2
# |   store i16 %6, ptr %__s0, align 2
# |   %7 = load <8 x i16>, ptr %__s0_346, align 16
# |   store <8 x i16> %7, ptr %__s1, align 16
# |   %8 = load i16, ptr %__s0, align 2
# |   %9 = load <8 x i16>, ptr %__s1, align 16
# |   %vset_lane = insertelement <8 x i16> %9, i16 %8, i32 3
# |   store <8 x i16> %vset_lane, ptr %ref.tmp3, align 16
# |   %10 = load <8 x i16>, ptr %ref.tmp3, align 16
# |   store <8 x i16> %10, ptr %__ret, align 16
# |   %11 = load <8 x i16>, ptr %__ret, align 16
# |   store <8 x i16> %11, ptr %tmp4, align 16
# |   %12 = load <8 x i16>, ptr %tmp4, align 16
# |   store <8 x i16> %12, ptr %__ret_346, align 16
# |   %13 = load <8 x i16>, ptr %__ret_346, align 16
# |   store <8 x i16> %13, ptr %tmp5, align 16
# |   %14 = load <8 x i16>, ptr %tmp5, align 16
# |   ret <8 x i16> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i16> @test_vcopyq_laneq_u16(<8 x i16> noundef %a1, <8 x i16> noundef %a2) #0 {
# | entry:
# |   %a1.addr = alloca <8 x i16>, align 16
# |   %a2.addr = alloca <8 x i16>, align 16
# |   %__ret_334 = alloca <8 x i16>, align 16
# |   %__s0_334 = alloca <8 x i16>, align 16
# |   %__s2_334 = alloca <8 x i16>, align 16
# |   %__ret = alloca <8 x i16>, align 16
# |   %__s0 = alloca i16, align 2
# |   %__ret1 = alloca i16, align 2
# |   %__s02 = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   %__s1 = alloca <8 x i16>, align 16
# |   %ref.tmp3 = alloca <8 x i16>, align 16
# |   %tmp4 = alloca <8 x i16>, align 16
# |   %tmp5 = alloca <8 x i16>, align 16
# |   store <8 x i16> %a1, ptr %a1.addr, align 16
# |   store <8 x i16> %a2, ptr %a2.addr, align 16
# |   %0 = load <8 x i16>, ptr %a1.addr, align 16
# |   store <8 x i16> %0, ptr %__s0_334, align 16
# |   %1 = load <8 x i16>, ptr %a2.addr, align 16
# |   store <8 x i16> %1, ptr %__s2_334, align 16
# |   %2 = load <8 x i16>, ptr %__s2_334, align 16
# |   store <8 x i16> %2, ptr %__s02, align 16
# |   %3 = load <8 x i16>, ptr %__s02, align 16
# |   %vgetq_lane = extractelement <8 x i16> %3, i32 7
# |   store i16 %vgetq_lane, ptr %ref.tmp, align 2
# |   %4 = load i16, ptr %ref.tmp, align 2
# |   store i16 %4, ptr %__ret1, align 2
# |   %5 = load i16, ptr %__ret1, align 2
# |   store i16 %5, ptr %tmp, align 2
# |   %6 = load i16, ptr %tmp, align 2
# |   store i16 %6, ptr %__s0, align 2
# |   %7 = load <8 x i16>, ptr %__s0_334, align 16
# |   store <8 x i16> %7, ptr %__s1, align 16
# |   %8 = load i16, ptr %__s0, align 2
# |   %9 = load <8 x i16>, ptr %__s1, align 16
# |   %vset_lane = insertelement <8 x i16> %9, i16 %8, i32 3
# |   store <8 x i16> %vset_lane, ptr %ref.tmp3, align 16
# |   %10 = load <8 x i16>, ptr %ref.tmp3, align 16
# |   store <8 x i16> %10, ptr %__ret, align 16
# |   %11 = load <8 x i16>, ptr %__ret, align 16
# |   store <8 x i16> %11, ptr %tmp4, align 16
# |   %12 = load <8 x i16>, ptr %tmp4, align 16
# |   store <8 x i16> %12, ptr %__ret_334, align 16
# |   %13 = load <8 x i16>, ptr %__ret_334, align 16
# |   store <8 x i16> %13, ptr %tmp5, align 16
# |   %14 = load <8 x i16>, ptr %tmp5, align 16
# |   ret <8 x i16> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x i32> @test_vcopyq_laneq_s32(<4 x i32> noundef %a1, <4 x i32> noundef %a2) #0 {
# | entry:
# |   %a1.addr = alloca <4 x i32>, align 16
# |   %a2.addr = alloca <4 x i32>, align 16
# |   %__ret_340 = alloca <4 x i32>, align 16
# |   %__s0_340 = alloca <4 x i32>, align 16
# |   %__s2_340 = alloca <4 x i32>, align 16
# |   %__ret = alloca <4 x i32>, align 16
# |   %__s0 = alloca i32, align 4
# |   %__ret1 = alloca i32, align 4
# |   %__s02 = alloca <4 x i32>, align 16
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   %__s1 = alloca <4 x i32>, align 16
# |   %ref.tmp3 = alloca <4 x i32>, align 16
# |   %tmp4 = alloca <4 x i32>, align 16
# |   %tmp5 = alloca <4 x i32>, align 16
# |   store <4 x i32> %a1, ptr %a1.addr, align 16
# |   store <4 x i32> %a2, ptr %a2.addr, align 16
# |   %0 = load <4 x i32>, ptr %a1.addr, align 16
# |   store <4 x i32> %0, ptr %__s0_340, align 16
# |   %1 = load <4 x i32>, ptr %a2.addr, align 16
# |   store <4 x i32> %1, ptr %__s2_340, align 16
# |   %2 = load <4 x i32>, ptr %__s2_340, align 16
# |   store <4 x i32> %2, ptr %__s02, align 16
# |   %3 = load <4 x i32>, ptr %__s02, align 16
# |   %vgetq_lane = extractelement <4 x i32> %3, i32 3
# |   store i32 %vgetq_lane, ptr %ref.tmp, align 4
# |   %4 = load i32, ptr %ref.tmp, align 4
# |   store i32 %4, ptr %__ret1, align 4
# |   %5 = load i32, ptr %__ret1, align 4
# |   store i32 %5, ptr %tmp, align 4
# |   %6 = load i32, ptr %tmp, align 4
# |   store i32 %6, ptr %__s0, align 4
# |   %7 = load <4 x i32>
# | ...
# `---data was truncated (10240/22011) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005615eb93feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005615eb93ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005615eb94062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3763a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3763aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3763a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3763a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005615eb8d5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005615eb8d5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005615eb8ba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005615eb569e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005615eb569b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3763a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3763a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3763a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615eb569a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c (736 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldnf1_mf8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnf1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.ldnf1.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldnf1_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnf1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ldnf1.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.ldnf1.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ldnf1.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ldnf1.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ldnf1.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ldnf1.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldnf1_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnf1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ldnf1.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ldnf1.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ldnf1.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svldnf1_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.ldnf1.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ldnf1.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svldnf1_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.ldnf1.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ldnf1.nxv4f32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svldnf1_f64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.ldnf1.nxv2f64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ldnf1.nxv2f64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldnf1_vnum_mf8(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# | 
# | ...
# `---data was truncated (10240/22483) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c82d42ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c82d429e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c82d42d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc4ab933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc4ab98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc4ab933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc4ab91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c82d3c2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c82d3c2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c82d3a78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c82d056e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c82d056b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc4ab91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc4ab91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc4ab91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c82d056a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c (737 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfadd_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfadd_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfadd_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfadd_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfadd_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfadd_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range
# | ...
# `---data was truncated (10240/302397) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564caad5aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564caad57e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564caad5b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe849133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe84918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe849133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe84911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564caacf0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564caacf0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564caacd58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564caa984e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564caa984b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe84911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe84911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe84911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564caa984a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c (738 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrdiv_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrdiv_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfrdiv.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrdiv.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrdiv_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfrdiv.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrdiv.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrdiv_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfrdiv.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrdiv.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrdiv_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfrdiv.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrdiv.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrdiv_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfrdiv.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrdiv.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrdiv_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrdiv_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfrdiv.nxv2f32.f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrdiv.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrdiv_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vsc
# | ...
# `---data was truncated (10240/147382) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b33d1e0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b33d1dde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b33d1e162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8cb2133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8cb218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8cb2133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8cb211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b33d176bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b33d176a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b33d15b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b33ce0ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b33ce0ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8cb211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8cb211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8cb211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b33ce0aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c (739 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmand_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmand_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmand_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmand_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmand_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmand_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmand_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec766d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ec766d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ec766d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa629b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa629b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa629b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa629b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec7666ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ec7666ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ec766538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ec76302e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ec76302b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa629b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa629b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa629b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec76302a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c (740 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsadd_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsadd_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsadd_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsadd_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsadd_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsadd_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsadd_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsadd_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsadd_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op
# | ...
# `---data was truncated (10240/222917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555d81f80eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555d81f7de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555d81f8162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f008e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f008e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f008e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f008e71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555d81f16bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555d81f16a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555d81efb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555d81baae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555d81baab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f008e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f008e71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f008e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555d81baaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c (741 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredor_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredor_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredor_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.add
# | ...
# `---data was truncated (10240/94157) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005582d9079eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005582d9076e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005582d907a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ed601bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ed60725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ed601ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ed6003507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005582d900fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005582d900fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005582d8ff48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005582d8ca3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005582d8ca3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8ed6004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ed60050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ed60050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005582d8ca3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c (742 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svget2_s8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svget2_s16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svget2_s32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svget2_s64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 1
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svget2_u8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svget2_u16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svget2_u32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svget2_u64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 1
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svget2_f16(<vscale x 8 x half> %tuple.coerce0, <vscale x 8 x half> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %tuple.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %tuple, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svget2_f32(<vscale x 4 x float> %tuple.coerce0, <vscale x 4 x float> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %tuple.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %tuple, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | d
# | ...
# `---data was truncated (10240/14679) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055f0eb126eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f0eb123e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f0eb12762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f266961bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f26696725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f266961ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2669603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f0eb0bcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f0eb0bca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f0eb0a18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f0ead50e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f0ead50b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2669604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f26696050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f26696050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f0ead50a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c (743 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16mf4(ptr noundef %base, <vscale x 1 x i32> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16mf2(ptr noundef %base, <vscale x 2 x i32> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16m1(ptr noundef %base, <vscale x 4 x i32> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16m2(ptr noundef %base, <vscale x 8 x i32> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16m4(ptr noundef %base, <vscale x 16 x i32> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f32mf2(ptr noundef %base, <vscale x 1 x i32> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f32m1(ptr noundef %base, <vscale x 2 x i32> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f32m2(ptr noundef %base, <vscale x 4 x i32> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f32m4(ptr noundef %base, <vscale x 8 x i32> %bindex, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   re
# | ...
# `---data was truncated (10240/120915) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559217ebbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559217eb8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559217ebc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc53ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc53ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc53ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc53ed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559217e51bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559217e51a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559217e368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559217ae5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559217ae5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc53ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc53ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc53ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559217ae5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c (744 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vbrev_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vbrev_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vbrev.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vbrev.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vbrev_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vbrev.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vbrev.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vbrev_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vbrev.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vbrev.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vbrev_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vbrev.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vbrev.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vbrev_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vbrev.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vbrev.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vbrev_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vbrev.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vbrev.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vbrev_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vbrev.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vbrev.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vbrev_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vbrev.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vbrev.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vbrev_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vbrev.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vbrev.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | d
# | ...
# `---data was truncated (10240/95223) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dea78ddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dea78dae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dea78de62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ad0249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ad02a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ad0249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ad0231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dea7873bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dea7873a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dea78588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dea7507e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dea7507b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4ad0232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ad02330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ad02330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dea7507a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c (745 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563886dd2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563886dcfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563886dd362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f06d3d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f06d3d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f06d3d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f06d3ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563886d68bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563886d68a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563886d4d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005638869fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005638869fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f06d3ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f06d3cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f06d3cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005638869fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c (746 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16m1x2(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16m2x2(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16m4x2(ptr noundef %base, <vscale x 16 x i32> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f32m1x2(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f32m2x2(ptr noundef %base, <vscale x
# | ...
# `---data was truncated (10240/123663) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f3c9956eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f3c9953e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f3c995762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f37af133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f37af18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f37af133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f37af11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f3c98ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f3c98eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f3c98d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f3c9580e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f3c9580b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f37af11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f37af11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f37af11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f3c9580a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c (747 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmax_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmax_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmax_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmax_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmax_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmax_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmax_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmax_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmax_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/222475) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b34e489eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b34e486e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b34e48a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f187fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f187fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f187fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f187fb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b34e41fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b34e41fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b34e4048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b34e0b3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b34e0b3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f187fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f187fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f187fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b34e0b3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c (748 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmacc_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmacc_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmacc_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmacc_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmacc_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmacc_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmacc_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmacc_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7
# | ...
# `---data was truncated (10240/64374) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560ac5886eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560ac5883e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560ac588762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5c59b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5c59b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5c59b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5c59b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ac581cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560ac581ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560ac58018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560ac54b0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560ac54b0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5c59b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5c59b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5c59b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ac54b0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c (749 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svset4_b_0(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1, <vscale x 16 x i1> %tuple.coerce2, <vscale x 16 x i1> %tuple.coerce3, <vscale x 16 x i1> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %x.addr = alloca <vscale x 16 x i1>, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %1, <vscale x 16 x i1> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %tuple.coerce3, 3
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %3, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   store <vscale x 16 x i1> %x, ptr %x.addr, align 2
# |   %4 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %5 = load <vscale x 16 x i1>, ptr %x.addr, align 2
# |   %6 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %4, <vscale x 16 x i1> %5, 0
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svset4_b_1(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1, <vscale x 16 x i1> %tuple.coerce2, <vscale x 16 x i1> %tuple.coerce3, <vscale x 16 x i1> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %x.addr = alloca <vscale x 16 x i1>, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %1, <vscale x 16 x i1> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %tuple.coerce3, 3
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %3, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   store <vscale x 16 x i1> %x, ptr %x.addr, align 2
# |   %4 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %5 = load <vscale x 16 x i1>, ptr %x.addr, align 2
# |   %6 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %4, <vscale x 16 x i1> %5, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svset4_b_3(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1, <vscale x 16 x i1> %tuple.coerce2, <vscale x 16 x i1> %tuple.coerce3, <vscale x 16 x i1> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %x.addr = alloca <vscale x 16 x i1>, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %1, <vscale x 16 x i1> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %tuple.coerce3, 3
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %3, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   store <vscale x 16 x i1> %x, ptr %x.addr, align 2
# |   %4 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %5 = load <vscale x 16 x i1>, ptr %x.addr, align 2
# |   %6 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %4, <vscale x 16 x i1> %5, 3
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %6
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ced210feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ced210ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ced211062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcdb5649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcdb56a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcdb5649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcdb5631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ced20a5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ced20a5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ced208a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ced1d39e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ced1d39b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcdb5632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcdb56330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcdb56330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ced1d39a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c (750 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f16m1x7(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f32m1x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f64m1x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/69980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aadf95deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aadf95ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aadf95e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f38d1649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f38d16a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f38d1649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f38d1631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aadf8f3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aadf8f3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aadf8d88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aadf587e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aadf587b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f38d1632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f38d16330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f38d16330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aadf587a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c (751 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesef_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesef_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesef_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind w
# | ...
# `---data was truncated (10240/20198) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e8dc9c3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e8dc9c0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e8dc9c462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f68a7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f68a778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f68a7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f68a771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e8dc959bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e8dc959a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e8dc93e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e8dc5ede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e8dc5edb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f68a771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f68a771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f68a771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e8dc5eda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c (752 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef4_s8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svundef4_s16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svundef4_s32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svundef4_s64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef4_u8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svundef4_u16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svundef4_u32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svundef4_u64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svundef4_f16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svundef4_f32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @test_svundef4_f64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef4_mf8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svundef4_bf16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } undef
# | }
# | 
# | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | !llvm.errno.tbaa = !{!4}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# | !4 = !{!5, !6, i64 0}
# | !5 = !{!"__libc_errno", !6, i64 0}
# | !6 = !{!"int", !7, i64 0}
# | !7 = !{!"omnipotent char", !8, i64 0}
# | !8 = !{!"Simple C/C++ TBAA"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055b54885aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b548857e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b54885b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1ceaf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1ceaf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1ceaf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1ceaf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b5487f0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b5487f0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b5487d58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b548484e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b548484b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1ceaf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1ceaf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1ceaf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b548484a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c (753 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei8_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %m
# | ...
# `---data was truncated (10240/160133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a248650eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a24864de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a24865162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3090333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f309038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3090333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f309031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a2485e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a2485e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a2485cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a24827ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a24827ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f309031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f309031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f309031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a24827aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c (754 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vror_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vror_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vror_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vror_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vror_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vror_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vror_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vror_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vror_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %v
# | ...
# `---data was truncated (10240/222307) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056371415aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563714157e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056371415b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fed5e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fed5e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fed5e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fed5e431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005637140f0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005637140f0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005637140d58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563713d84e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563713d84b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fed5e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fed5e4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fed5e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563713d84a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c (755 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei64_v_i8mf8x6
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005634d28daeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005634d28d7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005634d28db62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa606305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa60635c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa606305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa6062ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005634d2870bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005634d2870a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005634d28558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005634d2504e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005634d2504b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa6062eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa6062ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa6062ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005634d2504a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c (756 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vncvt_x_x_w_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8>, <vscale x 32 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 
# | ...
# `---data was truncated (10240/126436) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f46b0f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f46b0efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f46b0f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6689e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6689ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6689e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6689e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f46b088bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f46b088a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f46b06d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f46ad1ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f46ad1cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6689e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6689e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6689e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f46ad1ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/neon-misc-constrained.c (757 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-misc-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon   -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vrndaq_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrnda.i = bitcast <16 x i8> %1 to <2 x double>
# |   %vrnda1.i = call <2 x double> @llvm.round.v2f64(<2 x double> %vrnda.i)
# |   store <2 x double> %vrnda1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <2 x double>, ptr %ref.tmp.i, align 16
# |   store <2 x double> %2, ptr %__ret.i, align 16
# |   %3 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vrndpq_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrndp.i = bitcast <16 x i8> %1 to <2 x double>
# |   %vrndp1.i = call <2 x double> @llvm.ceil.v2f64(<2 x double> %vrndp.i)
# |   store <2 x double> %vrndp1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <2 x double>, ptr %ref.tmp.i, align 16
# |   store <2 x double> %2, ptr %__ret.i, align 16
# |   %3 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vsqrtq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <4 x float>
# |   %vsqrt.i = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %2)
# |   store <4 x float> %vsqrt.i, ptr %ref.tmp.i, align 16
# |   %3 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %3, ptr %__ret.i, align 16
# |   %4 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vcvt_f16_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <4 x float>
# |   %3 = fptrunc <4 x float> %2 to <4 x half>
# |   store <4 x half> %3, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vcvt_high_f16_f32(<4 x half> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <4 x half>, align 8
# |   %__p1.addr.i2 = alloca <4 x half>, align 8
# |   %__ret.i3 = alloca <8 x half>, align 16
# |   %__p0.addr.i.i = alloca <4 x float>, align 16
# |   %__ret.i.i = alloca <4 x half>, align 8
# |   %ref.tmp.i.i = alloca <8 x i8>, align 8
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x float>, align 16
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <4 x half>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x float>, ptr %__p1.addr.i, align 16
# |   store <4 x float> %3, ptr %__p0.addr.i.i, align 16
# |   %4 = load <16 x i8>, ptr %__p0.addr.i.i, align 16
# |   %5 = bitcast <16 x i8> %4 to <4 x float>
# |   %6 = fptrunc <4 x float> %5 to <4 x half>
# |   store <4 x half> %6, ptr %ref.tmp.i.i, align 8
# |   %7 = load <4 x half>, ptr %ref.tmp.i.i, align 8
# |   store <4 x half> %7, ptr %__ret.i.i, align 8
# |   %8 = load <4 x half>, ptr %__ret.i.i, align 8
# |   store <4 x half> %2, ptr %__p0.addr.i1, align 8
# |   store <4 x half> %8, ptr %__p1.addr.i2, align 8
# |   %9 = load <4 x half>, ptr %__p0.addr.i1, align 8
# |   %10 = load <4 x half>, ptr %__p1.addr.i2, align 8
# |   %shuffle.i = shufflevector <4 x half> %9, <4 x half> %10, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x half> %shuffle.i, ptr %__ret.i3, align 16
# |   %11 = load <8 x half>, ptr %__ret.i3, align 16
# |   store <8 x half> %11, ptr %__ret.i, align 16
# |   %12 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vcvt_f32_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fpext <4 x half> %2 to <4 x float>
# |   store <4 x float> %3, ptr %ref.tmp.i, align 16
# |   %4 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %4, ptr %__ret.i, align 16
# |   %5 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vcvt_high_f32_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <8 x half>, align 16
# |   %__ret.i2 = alloca <4 x half>, align 8
# |   %__p0.addr.i.i = alloca <4 x half>, align 8
# |   %__ret.i.i = alloca <4 x float>, align 16
# |   %ref.tmp.i.i = alloca <16 x i8>, align 16
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x half>, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p0.addr.i1, align 16
# |   %2 = load <8 x half>, ptr %__p0.addr.i1, align 16
# |   %3 = load <8 x half>, ptr %__p0.addr.i1, align 16
# |   %shuffle.i = shufflevector <8 x half> %2, <8 x half> %3, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
# |   store <4 x half> %shuffle.i, ptr %__ret.i2, align 8
# |   %4 = load <4 x half>, ptr %__ret.i2, align 8
# |   store <4 x half> %4, ptr %__p0.addr.i.i, align 8
# |   %5 = load <8 x i8>, ptr %__p0.addr.i.i, align 8
# |   %6 = bitcast <8 x i8> %5 to <4 x half>
# |   %7 = fpext <4 x half> %6 to <4 x float>
# |   store <4 x float> %7, ptr %ref.tmp.i.i, align 16
# |   %8 = load <4 x float>, ptr %ref.tmp.i.i, align 16
# |   store <4 x float> %8, ptr %__ret.i.i, align 16
# |   %9 = load <4 x float>, ptr %__ret.i.i, align 16
# |   store <4 x float> %9, ptr %__ret.i, align 16
# |   %10 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %10
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <2 x double> @llvm.round.v2f64(<2 x double>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <2 x double> @llvm.ceil.v2f64(<2 x double>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000562c79c76eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562c79c73e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562c79c7762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f93d6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f93d6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f93d6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f93d6b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c79c0cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562c79c0ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562c79bf18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562c798a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562c798a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f93d6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f93d6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f93d6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c798a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c (758 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c3728f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c3728f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c3728f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a92b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a92b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a92b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a92b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c37288ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c37288ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c3728738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c372522e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c372522b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2a92b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a92b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a92b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c372522a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c (759 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnot_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnot_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnot_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnot_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnot_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vnot_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vnot_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vnot_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 -1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vnot_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 -1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vnot_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 -1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16.i6
# | ...
# `---data was truncated (10240/182165) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005615cce24eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005615cce21e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005615cce2562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4c72133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4c7218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4c72133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4c7211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005615ccdbabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005615ccdbaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005615ccd9f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005615cca4ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005615cca4eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4c7211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4c7211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4c7211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615cca4ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c (760 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vv_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vv_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vf_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofre
# | ...
# `---data was truncated (10240/183431) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ef2a26eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ef2a26be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ef2a26f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbe9fc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbe9fc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbe9fc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbe9fc03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ef2a204bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ef2a204a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ef2a1e98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ef29e98e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ef29e98b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbe9fc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbe9fc050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbe9fc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ef29e98a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c (761 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_x_f_qf_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %1, <vscale x 1 x float> %2, float %3, <vscale x 1 x i1> %0, i64 2, i64 %4, i64 2)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %1, <vscale x 2 x float> %2, float %3, <vscale x 2 x i1> %0, i64 2, i64 %4, i64 2)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load 
# | ...
# `---data was truncated (10240/26710) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562715b98eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562715b95e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562715b9962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f25e1b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f25e1b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f25e1b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f25e1aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562715b2ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562715b2ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562715b138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005627157c2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005627157c2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f25e1aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f25e1aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f25e1aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005627157c2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c (762 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_e4m3_e4m3_w4_f8e4m3m8_f8e4m3m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563d364f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563d364f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563d364fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff545d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff545d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff545d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff545d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d3648fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563d3648fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563d364748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563d36123e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563d36123b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff545d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff545d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff545d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d36123a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c (763 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclipu_wv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclipu_wx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclipu_wv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclipu_wx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclipu_wv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclipu_wx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclipu_wv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclipu_wx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test
# | ...
# `---data was truncated (10240/156773) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fbfaafdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fbfaafae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fbfaafe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee04e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee04e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee04e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee04e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fbfaa93bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fbfaa93a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fbfaa788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fbfa727e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fbfa727b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fee04e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee04e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee04e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fbfa727a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c (764 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf4_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf4_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vzext_vf4_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vzext_vf4_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf4_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf4_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf4_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf4_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i32> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call
# | ...
# `---data was truncated (10240/39914) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d8180a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d81809fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d8180a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f983621bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f98362725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f983621ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9836203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d818038bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d818038a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d81801d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d817ccce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d817cccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9836204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f98362050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f98362050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d817ccca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/neon-fma.c (765 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-fma.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vmla_n_f32(<2 x float> noundef %a, <2 x float> noundef %b, float noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__p2.addr.i = alloca float, align 4
# |   %__ret.i = alloca <2 x float>, align 8
# |   %.compoundliteral.i = alloca <2 x float>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %c.addr = alloca float, align 4
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   store float %c, ptr %c.addr, align 4
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   %2 = load float, ptr %c.addr, align 4
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   store float %2, ptr %__p2.addr.i, align 4
# |   %3 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %4 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %5 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit.i = insertelement <2 x float> poison, float %5, i32 0
# |   %6 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit1.i = insertelement <2 x float> %vecinit.i, float %6, i32 1
# |   store <2 x float> %vecinit1.i, ptr %.compoundliteral.i, align 8
# |   %7 = load <2 x float>, ptr %.compoundliteral.i, align 8
# |   %mul.i = fmul <2 x float> %4, %7
# |   %add.i = fadd <2 x float> %3, %mul.i
# |   store <2 x float> %add.i, ptr %__ret.i, align 8
# |   %8 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmlaq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__p2.addr.i = alloca float, align 4
# |   %__ret.i = alloca <4 x float>, align 16
# |   %.compoundliteral.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   %c.addr = alloca float, align 4
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   store float %c, ptr %c.addr, align 4
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   %2 = load float, ptr %c.addr, align 4
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   store float %2, ptr %__p2.addr.i, align 4
# |   %3 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %4 = load <4 x float>, ptr %__p1.addr.i, align 16
# |   %5 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit.i = insertelement <4 x float> poison, float %5, i32 0
# |   %6 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit1.i = insertelement <4 x float> %vecinit.i, float %6, i32 1
# |   %7 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %7, i32 2
# |   %8 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %8, i32 3
# |   store <4 x float> %vecinit3.i, ptr %.compoundliteral.i, align 16
# |   %9 = load <4 x float>, ptr %.compoundliteral.i, align 16
# |   %mul.i = fmul <4 x float> %4, %9
# |   %add.i = fadd <4 x float> %3, %mul.i
# |   store <4 x float> %add.i, ptr %__ret.i, align 16
# |   %10 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmlsq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__p2.addr.i = alloca float, align 4
# |   %__ret.i = alloca <4 x float>, align 16
# |   %.compoundliteral.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   %c.addr = alloca float, align 4
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   store float %c, ptr %c.addr, align 4
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   %2 = load float, ptr %c.addr, align 4
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   store float %2, ptr %__p2.addr.i, align 4
# |   %3 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %4 = load <4 x float>, ptr %__p1.addr.i, align 16
# |   %5 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit.i = insertelement <4 x float> poison, float %5, i32 0
# |   %6 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit1.i = insertelement <4 x float> %vecinit.i, float %6, i32 1
# |   %7 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %7, i32 2
# |   %8 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %8, i32 3
# |   store <4 x float> %vecinit3.i, ptr %.compoundliteral.i, align 16
# |   %9 = load <4 x float>, ptr %.compoundliteral.i, align 16
# |   %mul.i = fmul <4 x float> %4, %9
# |   %sub.i = fsub <4 x float> %3, %mul.i
# |   store <4 x float> %sub.i, ptr %__ret.i, align 16
# |   %10 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vmls_n_f32(<2 x float> noundef %a, <2 x float> noundef %b, float noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__p2.addr.i = alloca float, align 4
# |   %__ret.i = alloca <2 x float>, align 8
# |   %.compoundliteral.i = alloca <2 x float>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %c.addr = alloca float, align 4
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   store float %c, ptr %c.addr, align 4
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   %2 = load float, ptr %c.addr, align 4
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   store float %2, ptr %__p2.addr.i, align 4
# |   %3 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %4 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %5 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit.i = insertelement <2 x float> poison, float %5, i32 0
# |   %6 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit1.i = insertelement <2 x float> %vecinit.i, float %6, i32 1
# |   store <2 x float> %vecinit1.i, ptr %.compoundliteral.i, align 8
# |   %7 = load <2 x float>, ptr %.compoundliteral.i, align 8
# |   %mul.i = fmul <2 x float> %4, %7
# |   %sub.i = fsub <2 x float> %3, %mul.i
# |   store <2 x float> %sub.i, ptr %__ret.i, align 8
# |   %8 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vmla_lane_f32_0(<2 x float> noundef %a, <2 x float> noundef %b, <2 x float> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %v.addr = alloca <2 x float>, align 8
# |   %__ret_68 = alloca <2 x float>, align 8
# |   %__s0_68 = alloca <2 x float>, align 8
# |   %__s1_68 = alloca <2 x float>, align 8
# |   %__s2_68 = alloca <2 x float>, align 8
# |   %__ret = alloca <2 x float>, align 8
# |   %__s0 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x float>, align 8
# |   %tmp1 = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   store <2 x float> %v, ptr %v.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__s0_68, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %1, ptr %__s1_68, align 8
# |   %2 = load <2 x float>, ptr %v.addr, align 8
# |   store <2 x float> %2, ptr %__s2_68, align 8
# |   %3 = load <2 x float>, ptr %__s0_68, align 8
# |   %4 = load <2 x float>, ptr %__s1_68, align 8
# |   %5 = load <2 x float>, ptr %__s2_68, align 8
# |   store <2 x float> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x float>
# |   %lane = shufflevector <2 x float> %7, <2 x float> %7, <2 x i32> zeroinitializer
# |   store <2 x float> %lane, ptr %ref.tmp, align 8
# |   %8 = load <2 x float>, ptr %ref.tmp, align 8
# |   store <2 x float> %8, ptr %__ret, align 8
# |   %9 = load <2 x float>, ptr %__ret, align 8
# |   store <2 x float> %9, ptr %tmp, align 8
# |   %10 = load <2 x float>, ptr %tmp, align 8
# |   %mul = fmul <2 x float> %4, %10
# |   %add = fadd <2 x float> %3, %mul
# |   store <2 x float> %add, ptr %__ret_68, align 8
# |   %11 = load <2 x float>, ptr %__ret_68, align 8
# |   store <2 x float> %11, ptr %tmp1, align 8
# |   %12 = load <2 x float>, ptr %tmp1, align 8
# |   ret <2 x float> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmlaq_lane_f32_0(<4 x float> noundef %a, <4 x float> noundef %b, <2 x float> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   %v.addr = alloca <2 x float>, align 8
# |   %__ret_58 = alloca <4 x float>, align 16
# |   %__s0_58 = alloca <4 x float>, align 16
# |   %__s1_58 = alloca <4 x float>, align 16
# |   %__s2_58 = alloca <2 x float>, align 8
# |   %__ret = alloca <4 x float>, align 16
# |   %__s0 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x float>, align 16
# |   %tmp1 = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   store <2 x float> %v, ptr %v.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__s0_58, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x float> %1, ptr %__s1_58, align 16
# |   %2 = load <2 x float>, ptr %v.addr, align 8
# |   store <2 x float> %2, ptr %__s2_58, align 8
# |   %3 = load <4 x float>, ptr %__s0_58, align 16
# |   %4 = load <4 x float>, ptr %__s1_58, align 16
# |   %5 = load <2 x float>, ptr %__s2_58, align 8
# |   store <2 x f
# | ...
# `---data was truncated (10240/44730) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005652d10afeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005652d10ace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005652d10b062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3325f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3325f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3325f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3325f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005652d1045bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005652d1045a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005652d102a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005652d0cd9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005652d0cd9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3325f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3325f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3325f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005652d0cd9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c (766 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f16m1x7(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f32m1x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f64m1x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i16> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563d1cb62eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563d1cb5fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563d1cb6362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdfa9e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdfa9ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdfa9e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdfa9e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d1caf8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563d1caf8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563d1cadd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563d1c78ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563d1c78cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdfa9e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdfa9e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdfa9e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d1c78ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c (767 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005556b601deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005556b601ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005556b601e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f22f8c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f22f8ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f22f8c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f22f8c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005556b5fb3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005556b5fb3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005556b5f988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005556b5c47e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005556b5c47b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f22f8c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f22f8c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f22f8c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005556b5c47a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c (768 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vcompress_vm_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %src, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vcompress_vm_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %src, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vcompress_vm_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %src, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vcompress_vm_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %src, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vcompress_vm_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %src, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vcompress_vm_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %src, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i1> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vcompress_vm_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %src, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vcompress_vm_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %src, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vcompress.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind 
# | ...
# `---data was truncated (10240/77062) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055853e49feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055853e49ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055853e4a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1ef5049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1ef50a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1ef5049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1ef5031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055853e435bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055853e435a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055853e41a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055853e0c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055853e0c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1ef5032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1ef50330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1ef50330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055853e0c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c (769 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8_v_i8mf8x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8_v_i8mf4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8_v_i8mf2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8_v_i8m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8_v_i8m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8_v_i8m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8_v_u8mf8x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8_v_u8mf4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8_v_u8mf2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8_v_u8m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8_v_u8m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8_v_u8m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vect
# | ...
# `---data was truncated (10240/24229) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559cbcc2ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559cbcc29e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559cbcc2d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f11b2d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f11b2d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f11b2d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f11b2d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559cbcbc2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559cbcbc2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559cbcba78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559cbc856e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559cbc856b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f11b2d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f11b2d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f11b2d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559cbc856a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c (770 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei16_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/14613) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005643f1e10eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005643f1e0de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005643f1e1162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa0ffb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa0ffb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa0ffb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa0ffb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005643f1da6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005643f1da6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005643f1d8b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005643f1a3ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005643f1a3ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa0ffb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa0ffb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa0ffb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005643f1a3aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c (771 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vf_f32mf2_tu(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vf_f32m1_tu(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vf_f32m2_tu(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vf_f32m4_tu(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(
# | ...
# `---data was truncated (10240/179185) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005574159d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005574159d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005574159d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb234d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb234d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb234d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb234d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055741596cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055741596ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005574159518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557415600e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557415600b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb234d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb234d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb234d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557415600a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c (772 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16mf4x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16mf2x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16m1x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005608f2bfeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005608f2bfbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005608f2bff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1329449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13294a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1329449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1329431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005608f2b94bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005608f2b94a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005608f2b798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005608f2828e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005608f2828b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1329432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13294330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13294330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005608f2828a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c (773 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64ff_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(<vscale x 1 x double> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(<vscale x 1 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64ff_v_f64m2_tu(<vscale x 2 x double> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(<vscale x 2 x double> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(<vscale x 2 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vle64ff_v_f64m4_tu(<vscale x 4 x double> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(<vscale x 4 x double> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(<vscale x 4 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vle64ff_v_f64m8_tu(<vscale x 8 x double> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(<vscale x 8 x double> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(<vscale x 8 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64ff_v_i64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(<vscale x 1 x i64> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(<vscale x 1 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64ff_v_i64m2_tu(<vscale x 2 x i64> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(<vscale x 2 x i64> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(<vscale x 2 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64ff_v_i64m4_tu(<vscale x 4 x i64> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(<vscale x 4 x i64> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(<vscale x 4 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64ff_v_i64m8_tu(<vscale x 8 x i64> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x i64>, i64 } @llvm.riscv.vleff.nxv8i64.i64.p0(<vscale x 8 x i64> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x i64>, i64 } @l
# | ...
# `---data was truncated (10240/62760) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562eb010beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562eb0108e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562eb010c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5875105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f587515c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5875105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f58750ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562eb00a1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562eb00a1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562eb00868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562eafd35e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562eafd35b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f58750eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f58750ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f58750ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562eafd35a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c (774 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_s32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 4 x i32> %2 to <vscale x 4 x i16>
# |   call void @llvm.aarch64.sve.st1.nxv4i16.p0(<vscale x 4 x i16> %4, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv4i16.p0(<vscale x 4 x i16>, <vscale x 4 x i1>, ptr captures(none)) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 2 x i64> %2 to <vscale x 2 x i16>
# |   call void @llvm.aarch64.sve.st1.nxv2i16.p0(<vscale x 2 x i16> %4, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv2i16.p0(<vscale x 2 x i16>, <vscale x 2 x i1>, ptr captures(none)) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_u32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 4 x i32> %2 to <vscale x 4 x i16>
# |   call void @llvm.aarch64.sve.st1.nxv4i16.p0(<vscale x 4 x i16> %4, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 2 x i64> %2 to <vscale x 2 x i16>
# |   call void @llvm.aarch64.sve.st1.nxv2i16.p0(<vscale x 2 x i16> %4, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 4 x i32> %3 to <vscale x 4 x i16>
# |   call void @llvm.aarch64.sve.st1.nxv4i16.p0(<vscale x 4 x i16> %6, <vscale x 4 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 2 x i64> %3 to <vscale x 2 x i16>
# |   call void @llvm.aarch64.sve.st1.nxv2i16.p0(<vscale x 2 x i16> %6, <vscale x 2 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 4 x i32> %3 to <vscale x 4 x i16>
# |   call void @llvm.aarch64.sve.st1.nxv4i16.p0(<vscale x 4 x i16> %6, <vscale x 4 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 2 x i64> %3 to <vscale x 2 x i16>
# |   call void @llvm.aarch64.sve.st1.nxv2i16.p0(<vscale x 2 x i16> %6, <vscale x 2 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_scatter_u32base_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = trunc <vscale x 4 x i32> %2 to <vscale x 4 x i16>
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i16> %3, <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, i64 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i16>, <vscale x 4 x i1>, <vscale x 4 x i32>, i64) #
# | ...
# `---data was truncated (10240/43213) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x0000556c319faeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556c319f7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556c319fb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2de4849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2de48a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2de4849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2de4831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556c31990bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556c31990a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556c319758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556c31624e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556c31624b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2de4832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2de48330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2de48330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556c31624a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c (775 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei32_v_f16mf4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei32_v_f16mf2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei32_v_f16m1(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei32_v_f16m2(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei32_v_f16m4(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei32_v_f32mf2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei32_v_f32m1(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei32_v_f32m2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei32_v_f32m4(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vloxei32_v_f32m8(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.p0.nxv16i32.i64(<vscale x 16 x float> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.p0.nxv16i32.i64(<vscal
# | ...
# `---data was truncated (10240/107872) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d1d9355eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d1d9352e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d1d935662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc926b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc926b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc926b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc926b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d1d92ebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d1d92eba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d1d92d08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d1d8f7fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d1d8f7fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc926b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc926b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc926b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d1d8f7fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c (776 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vor_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vor_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vor_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vor_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vor_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vor_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vor_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vor_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vor_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr
# | ...
# `---data was truncated (10240/424049) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005643d1ca2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005643d1c9fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005643d1ca362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f874b21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f874b2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f874b21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f874b203507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005643d1c38bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005643d1c38a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005643d1c1d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005643d18cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005643d18ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f874b204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f874b2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f874b2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005643d18cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c (777 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056314455aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563144557e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056314455b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6668c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6668ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6668c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6668c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005631444f0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005631444f0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005631444d58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563144184e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563144184b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6668c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6668c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6668c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563144184a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/2008-07-17-no-emit-on-error.c (778 of 27911)
******************** TEST 'Clang :: CodeGen/2008-07-17-no-emit-on-error.c' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 1
rm -f /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc
# executed command: rm -f /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -DPASS /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2008-07-17-no-emit-on-error.c -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -DPASS /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2008-07-17-no-emit-on-error.c -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc -disable-output
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc -disable-output
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc -disable-output
# |  #0 0x00005612d2941eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005612d293ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005612d294262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa181b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa181b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa181b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa181b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005612d28d7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005612d28d7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005612d28bc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005612d256be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005612d256bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa181b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa181b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa181b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005612d256ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c (779 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmul_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmul_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmul_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmul_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmul_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmul_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmul_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmul_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range
# | ...
# `---data was truncated (10240/302397) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555854971eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055585496ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055585497262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f62f8649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f62f86a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f62f8649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f62f8631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555854907bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555854907a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005558548ec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055585459be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055585459bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f62f8632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f62f86330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f62f86330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055585459ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/reinterpret.c (780 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/reinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c --check-prefix=BOTH --check-prefix=LE
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x i16> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x i32> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_s64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = bitcast <2 x i64> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x i16> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x i32> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_u64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = bitcast <2 x i64> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x i16> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x i32> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_s64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = bitcast <2 x i64> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x i16> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x i32> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_u64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = bitcast <2 x i64> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x i32> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_s64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = bitcast <2 x i64> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   ret <8 x i16> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x i32> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_u64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = bitcast <2 x i64> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vreinterpretq_s32_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <4 x i32>
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vreinterpretq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vreinterpretq_s32_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align
# | ...
# `---data was truncated (10240/30281) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>'
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<>
# |  #0 0x000055d664b42eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d664b3fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d664b4362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe6f6533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe6f658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe6f6533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe6f651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d664ad8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d664ad8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d664abd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d66476ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d66476cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe6f651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe6f651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe6f651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d66476ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c --check-prefix=BOTH --check-prefix=LE
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c --check-prefix=BOTH --check-prefix=LE
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c (781 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmnor_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmnor.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmnor.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmnor_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmnor.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmnor.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmnor_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmnor.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmnor.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmnor_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmnor.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmnor.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmnor_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmnor.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmnor.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmnor_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmnor.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmnor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmnor_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmnor.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmnor.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dbde9b4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dbde9b1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dbde9b562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0face49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0facea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0face49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0face31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dbde94abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dbde94aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dbde92f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dbde5dee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dbde5deb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0face32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0face330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0face330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dbde5dea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c (782 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredxor_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredxor_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredxor_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 
# | ...
# `---data was truncated (10240/94379) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558bad3e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558bad3e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558bad3ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa41241bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa4124725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa41241ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa412403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558bad37fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558bad37fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558bad3648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558bad013e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558bad013b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa412404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4124050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4124050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558bad013a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c (783 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f16m1x5(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f32m1x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f64m1x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i64> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555b72534eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555b72531e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555b7253562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0d5ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0d5ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0d5ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0d5ad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b724cabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555b724caa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555b724af8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555b7215ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555b7215eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0d5ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0d5ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0d5ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b7215ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c (784 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svbrkpb_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.brkpb.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.brkpb.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000561ea4a5feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561ea4a5ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561ea4a6062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb36c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb36ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb36c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb36c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561ea49f5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561ea49f5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561ea49da8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561ea4689e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561ea4689b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feb36c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb36c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb36c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561ea4689a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c (785 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16m1x2(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16m2x2(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16m4x2(ptr noundef %base, <vscale x 16 x i8> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f32m1x2(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f32m2x2(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>,
# | ...
# `---data was truncated (10240/128444) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f97920eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564f9791de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564f9792162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcf32333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcf3238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcf32333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcf3231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f978b6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564f978b6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564f9789b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564f9754ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564f9754ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcf3231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcf3231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcf3231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f9754aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c (786 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadc_vvm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadc_vxm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadc_vvm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadc_vxm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadc_vvm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadc_vxm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadc_vvm_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 8 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Functi
# | ...
# `---data was truncated (10240/116949) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bc01131eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bc0112ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bc0113262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f771b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f771b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f771b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f771b231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bc010c7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bc010c7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bc010ac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bc00d5be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bc00d5bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f771b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f771b2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f771b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bc00d5ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c (787 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f16m1x5(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f32m1x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f64m1x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei32_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564607159eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564607156e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056460715a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f89e7049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f89e70a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f89e7049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f89e7031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005646070efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005646070efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005646070d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564606d83e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564606d83b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f89e7032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f89e70330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f89e70330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564606d83a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c (788 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vslide1up_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vslide1up_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vslide1up_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vslide1up_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vslide1up_vx_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vslide1up_vx_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vslide1up_vx_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vslide1up_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i16, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vslide1up_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = 
# | ...
# `---data was truncated (10240/210435) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005605a2e0ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005605a2e09e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005605a2e0d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd6dd905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd6dd95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd6dd905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd6dd8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005605a2da2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005605a2da2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005605a2d878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005605a2a36e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005605a2a36b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd6dd8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd6dd8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd6dd8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005605a2a36a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c (789 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16mf4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16mf2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m1_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m8_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff
# | ...
# `---data was truncated (10240/44185) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055929388beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559293888e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055929388c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f15b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f15b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f15b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f15b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559293821bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559293821a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005592938068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005592934b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005592934b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1f15b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f15b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f15b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005592934b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c (790 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_tu(<vscale x 1
# | ...
# `---data was truncated (10240/295853) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aa04849eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aa04846e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aa0484a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f39ab61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f39ab6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f39ab61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f39ab603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa047dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aa047dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aa047c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aa04473e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aa04473b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f39ab604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f39ab6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f39ab6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa04473a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c (791 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_i16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_i16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_i16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_lo
# | ...
# `---data was truncated (10240/70863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cf44ea1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cf44e9ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cf44ea262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f8bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f8bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f8bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f8bd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf44e37bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cf44e37a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cf44e1c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cf44acbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cf44acbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4f8bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f8bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f8bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf44acba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c (792 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564c7eeefeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564c7eeece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564c7eef062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f162df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f162df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f162df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f162df1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c7ee85bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564c7ee85a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564c7ee6a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564c7eb19e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564c7eb19b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f162df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f162df1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f162df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c7eb19a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c (793 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredand_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredand_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredand_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   stor
# | ...
# `---data was truncated (10240/94371) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b65e99aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b65e997e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b65e99b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb90f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb90f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb90f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb90f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b65e930bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b65e930a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b65e9158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b65e5c4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b65e5c4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feb90f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb90f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb90f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b65e5c4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c (794 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i32> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i
# | ...
# `---data was truncated (10240/15699) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005556bc9e7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005556bc9e4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005556bc9e862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f907c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f907c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f907c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f907c031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005556bc97dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005556bc97da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005556bc9628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005556bc611e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005556bc611b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f907c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f907c0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f907c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005556bc611a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c (795 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfneg_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfneg_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfneg_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfneg_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfneg_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfneg_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfneg_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfneg_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfneg_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfneg_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x float> %o
# | ...
# `---data was truncated (10240/70102) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005596eaf56eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005596eaf53e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005596eaf5762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdaa2333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdaa238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdaa2333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdaa231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005596eaeecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005596eaeeca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005596eaed18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005596eab80e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005596eab80b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdaa231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdaa231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdaa231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005596eab80a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c (796 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f16m1x4(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_f16m2x4(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f32m1x4(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_f32m2x4(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f64m1x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.
# | ...
# `---data was truncated (10240/87884) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056091477deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056091477ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056091477e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fea72a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fea72aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fea72a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fea72a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560914713bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560914713a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005609146f88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005609143a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005609143a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fea72a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fea72a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fea72a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005609143a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c (797 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f16m1x4(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_f16m2x4(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f32m1x4(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_f32m2x4(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f64m1x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), p
# | ...
# `---data was truncated (10240/87316) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d24156feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d24156ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d24157062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4660649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f46606a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4660649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4660631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d241505bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d241505a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d2414ea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d241199e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d241199b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4660632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f46606330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f46606330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d241199a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c (798 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulsu_vv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulsu_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulsu_vv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulsu_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulsu_vv_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulsu_vx_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulsu_vv_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulsu_vx_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulsu_vv_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr =
# | ...
# `---data was truncated (10240/154509) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056087877eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056087877be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056087877f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0a13a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0a13aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0a13a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0a13a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560878714bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560878714a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005608786f98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005608783a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005608783a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0a13a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0a13a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0a13a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005608783a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c (799 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willret
# | ...
# `---data was truncated (10240/365423) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559628609eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559628606e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055962860a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fef8a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fef8a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fef8a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fef8a431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055962859fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055962859fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005596285848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559628233e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559628233b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fef8a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fef8a4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fef8a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559628233a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c (800 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei8_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei8_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei8_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei8_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei8_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i8> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vluxei8_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, <vscale x 32 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i8> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei8_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei8_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei8_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = a
# | ...
# `---data was truncated (10240/288050) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e294dd8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e294dd5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e294dd962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1315b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1315b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1315b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1315b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e294d6ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e294d6ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e294d538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e294a02e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e294a02b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1315b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1315b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1315b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e294a02a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c (801 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f16m1x8(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f32m1x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f64m1x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei8_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none
# | ...
# `---data was truncated (10240/61673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d2fcd38eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d2fcd35e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d2fcd3962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa84cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa84cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa84cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa84cc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d2fcccebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d2fcccea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d2fccb38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d2fc962e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d2fc962b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa84cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa84cc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa84cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d2fc962a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c (802 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_i32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_i32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_u32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_u32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_f32mf2x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedof
# | ...
# `---data was truncated (10240/40734) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560cbc250eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560cbc24de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560cbc25162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8755933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f875598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8755933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f875591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560cbc1e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560cbc1e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560cbc1cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560cbbe7ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560cbbe7ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f875591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f875591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f875591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560cbbe7aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c (803 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u8mf8(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvw.se.i32.nxv1i16.nxv1i8.nxv1i8.i32(i32 3, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv1i16.nxv1i8.nxv1i8.i32(i32 immarg, <vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u8mf4(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvw.se.i32.nxv2i16.nxv2i8.nxv2i8.i32(i32 3, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv2i16.nxv2i8.nxv2i8.i32(i32 immarg, <vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u8mf2(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvw.se.i32.nxv4i16.nxv4i8.nxv4i8.i32(i32 3, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv4i16.nxv4i8.nxv4i8.i32(i32 immarg, <vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u8m1(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvw.se.i32.nxv8i16.nxv8i8.nxv8i8.i32(i32 3, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv8i16.nxv8i8.nxv8i8.i32(i32 immarg, <vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u8m2(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 16 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvw.se.i32.nxv16i16.nxv16i8.nxv16i8.i32(i32 3, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv16i16.nxv16i8.nxv16i8.i32(i32 immarg, <vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u8m4(<vscale x 32 x i16> %vd, <vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 32 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 32 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvw.se.i32.nxv32i16.nxv32i8.nxv32i8.i32(i32 3, <vscale x 32 x i16> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv32i16.nxv32i8.nxv32i8.i32(i32 immarg, <vscale x 32 x i16>, <vscale x 32 x i8>, <vscale x 32 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u16mf4(<vscale x 1 x i32> %vd, <vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvw.se.i32.nxv1i32.nxv1i16.nxv1i16.i32(i32 3, <vscale x 1 x i32> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv1i32.nxv1i16.nxv1i16.i32(i32 immarg, <vscale x 1 x i32>, <vscale x 1 x i16>, <vscale x 1 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u16mf2(<vscale x 2 x i32> %vd, <vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvw.se.i32.nxv2i32.nxv2i16.nxv2i16.i32(i32 3, <vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv2i32.nxv2i16.nxv2i16.i32(i32 immarg, <vscale x 2 x i32>, <vscale x 2 x i16>, <vscale x 2 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u16m1(<vscale x 4 x i32> %vd, <vscale x 4 x i16> %vs2, <vscale x 4 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void
# | ...
# `---data was truncated (10240/179328) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557e87f5feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557e87f5ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557e87f6062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f849321bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f84932725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f849321ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8493203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e87ef5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557e87ef5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557e87eda8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557e87b89e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557e87b89b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8493204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f84932050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f84932050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e87b89a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c (804 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m1_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m8_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   
# | ...
# `---data was truncated (10240/81304) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055863027aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558630277e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055863027b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f18c6333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f18c638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f18c6333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f18c631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558630210bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558630210a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005586301f58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055862fea4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055862fea4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f18c631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f18c631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f18c631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055862fea4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c (805 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclip_wv_i8mf8(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclip_wx_i8mf8(<vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclip_wv_i8mf4(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclip_wx_i8mf4(<vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclip_wv_i8mf2(<vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclip_wx_i8mf2(<vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclip_wv_i8m1(<vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclip_wx_i8m1(<vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclip_wv_i8m2(<vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclip_wx_i8m2(<vscale x 16 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 %1, i64 0,
# | ...
# `---data was truncated (10240/69839) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aedea68eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aedea65e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aedea6962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc50333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc5038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc50333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc5031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aede9febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aede9fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aede9e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aede692e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aede692b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efc5031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc5031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc5031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aede692a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c (806 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_f16mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_f16mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_f16m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_f16m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_i16mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_i16mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_i16m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_i16m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_u16mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | ent
# | ...
# `---data was truncated (10240/31706) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560cd7e94eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560cd7e91e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560cd7e9562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6fbe049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6fbe0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6fbe049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6fbe031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560cd7e2abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560cd7e2aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560cd7e0f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560cd7abee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560cd7abeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6fbe032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6fbe0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6fbe0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560cd7abea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c (807 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvt1_bf16_mf8(<vscale x 16 x i8> %zn, i64 noundef %fpm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvt1.nxv8bf16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvt1.nxv8bf16(<vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvt2_bf16_mf8(<vscale x 16 x i8> %zn, i64 noundef %fpm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvt2.nxv8bf16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvt2.nxv8bf16(<vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvtlt1_bf16_mf8(<vscale x 16 x i8> %zn, i64 noundef %fpm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvtlt1.nxv8bf16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvtlt1.nxv8bf16(<vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvtlt2_bf16_mf8(<vscale x 16 x i8> %zn, i64 noundef %fpm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvtlt2.nxv8bf16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvtlt2.nxv8bf16(<vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcvt1_f16_mf8(<vscale x 16 x i8> %zn, i64 noundef %fpm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvt1.nxv8f16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvt1.nxv8f16(<vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcvt2_f16_mf8(<vscale x 16 x i8> %zn, i64 noundef %fpm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvt2.nxv8f16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvt2.nxv8f16(<vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcvtlt1_f16_mf8(<vscale x 16 x i8> %zn, i64 noundef %fpm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvtlt1.nxv8f16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvtlt1.nxv8f16(<vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcvtlt2_f16_mf8(<vscale x 16 x i8> %zn, i64 noundef %fpm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvtlt2.nxv8f16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvtlt2.nxv8f16(<vscale x 16 x i8>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp8,+sve,+sve2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005612eb8e1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005612eb8dee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005612eb8e262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f10e0505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f10e055c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f10e0505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f10e04ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005612eb877bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005612eb877a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005612eb85c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005612eb50be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005612eb50bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f10e04eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f10e04ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f10e04ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005612eb50ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c (808 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsub_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsub_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsub_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsub_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsub_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsub_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsub_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsub_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.r
# | ...
# `---data was truncated (10240/65582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c5ef136eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c5ef133e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c5ef13762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1ca2449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1ca24a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1ca2449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1ca2431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c5ef0ccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c5ef0cca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c5ef0b18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c5eed60e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c5eed60b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1ca2432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1ca24330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1ca24330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c5eed60a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c (809 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_vv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_vx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_wv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_wx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_vv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_vx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_wv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_wx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwaddu_vv_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.ad
# | ...
# `---data was truncated (10240/306619) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055997c250eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055997c24de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055997c25162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4064f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4064f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4064f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4064f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055997c1e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055997c1e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055997c1cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055997be7ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055997be7ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4064f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4064f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4064f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055997be7aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c (810 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei16_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei16_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei16_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei16_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei16_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vloxei16_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, <vscale x 32 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei16_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei16_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei16_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %
# | ...
# `---data was truncated (10240/280171) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560ea569ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560ea5699e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560ea569d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5792449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57924a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5792449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5792431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ea5632bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560ea5632a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560ea56178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560ea52c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560ea52c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5792432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57924330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57924330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ea52c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c (811 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16mf4(ptr noundef %base, <vscale x 1 x i8> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16mf2(ptr noundef %base, <vscale x 2 x i8> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16m1(ptr noundef %base, <vscale x 4 x i8> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16m2(ptr noundef %base, <vscale x 8 x i8> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16m4(ptr noundef %base, <vscale x 16 x i8> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16m8(ptr noundef %base, <vscale x 32 x i8> %bindex, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> %2, ptr %0, <vscale x 32 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f32mf2(ptr noundef %base, <vscale x 1 x i8> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f32m1(ptr noundef %base, <vscale x 2 x i8> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f32m2(ptr noundef %base, <vscale x 4 x i8> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretur
# | ...
# `---data was truncated (10240/136005) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e0969dbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e0969d8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e0969dc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f08f5d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f08f5d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f08f5d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f08f5d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e096971bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e096971a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e0969568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e096605e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e096605b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f08f5d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f08f5d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f08f5d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e096605a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c (812 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmacc_vv_i16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmacc_vx_i16mf4_tu(<vscale x 1 x i16> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmacc_vv_i16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmacc_vx_i16mf2_tu(<vscale x 2 x i16> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmacc_vv_i16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmacc_vx_i16m1_tu(<vscale x 4 x i16> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmacc_vv_i16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmacc_vx_i16m2_tu(<vscale x 8 x i16> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmacc_vv_i16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, alig
# | ...
# `---data was truncated (10240/150641) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c7dd14ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c7dd149e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c7dd14d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd19d41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd19d4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd19d41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd19d403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c7dd0e2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c7dd0e2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c7dd0c78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c7dcd76e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c7dcd76b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd19d404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd19d4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd19d4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c7dcd76a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c (813 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_xu_f_qf_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %1, <vscale x 1 x float> %2, float %3, <vscale x 1 x i1> %0, i64 2, i64 %4, i64 2)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %1, <vscale x 2 x float> %2, float %3, <vscale x 2 x i1> %0, i64 2, i64 %4, i64 2)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, alig
# | ...
# `---data was truncated (10240/26754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056034daf1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056034daeee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056034daf262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4794933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f479498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4794933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f479491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056034da87bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056034da87a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056034da6c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056034d71be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056034d71bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f479491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f479491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f479491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056034d71ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c (814 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintx_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintx.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frintx.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintx_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintx.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frintx.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintx_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintx.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frintx.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintx_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.frintx.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintx_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frintx.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintx_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frintx.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintx_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintx.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintx_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintx.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintx_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintx.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000558811b8beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558811b88e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558811b8c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2231e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2231ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2231e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2231e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558811b21bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558811b21a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558811b068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005588117b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005588117b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2231e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2231e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2231e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005588117b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c (815 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmax_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmax_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmax_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmax_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmax_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmax_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmax_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmax_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmax_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmax_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16
# | ...
# `---data was truncated (10240/69305) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560a0b704eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560a0b701e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560a0b70562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa4aae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa4aaea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa4aae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa4aae31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a0b69abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560a0b69aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560a0b67f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560a0b32ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560a0b32eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa4aae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4aae330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4aae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a0b32ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c (816 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557615497eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557615494e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055761549862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3e5af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3e5af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3e5af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3e5af1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055761542dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055761542da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005576154128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005576150c1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005576150c1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3e5af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3e5af1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3e5af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005576150c1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c (817 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmul_vv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmul_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmul_vv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmul_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmul_vv_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmul_vx_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmul_vv_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmul_vx_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmul_vv_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = allo
# | ...
# `---data was truncated (10240/153905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f0d68daeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f0d68d7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f0d68db62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b45649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b456a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b45649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b45631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f0d6870bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f0d6870a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f0d68558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f0d6504e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f0d6504b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5b45632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b456330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b456330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f0d6504a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c (818 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevh_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevh_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevh_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevh_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevh_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevh_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevh_u32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevh_u64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevh_s32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevh_s64_x(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevh_u32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   
# | ...
# `---data was truncated (10240/11488) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005586e422aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005586e4227e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005586e422b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa3faf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa3faf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa3faf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa3faf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005586e41c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005586e41c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005586e41a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005586e3e54e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005586e3e54b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa3faf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa3faf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa3faf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005586e3e54a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminnmq.c (819 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminnmq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.minnum.v8f16(<8 x half> %0, <8 x half> %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.minnum.v8f16(<8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = call <4 x float> @llvm.minnum.v4f32(<4 x float> %0, <4 x float> %1)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x half>, ptr %inactive.addr, align 8
# |   %6 = call <8 x half> @llvm.arm.mve.min.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> %5)
# |   ret <8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.min.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>, <8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x float>, ptr %inactive.addr, align 8
# |   %6 = call <4 x float> @llvm.arm.mve.min.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.min.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>, <4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x half> @llvm.arm.mve.min.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> undef)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmq_x_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x float> @llvm.arm.mve.min.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> undef)
# |   ret <4 x float> %5
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056428bca0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056428bc9de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056428bca162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f10bfa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f10bfaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f10bfa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f10bfa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056428bc36bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056428bc36a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056428bc1b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056428b8cae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056428b8cab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f10bfa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f10bfa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f10bfa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056428b8caa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/2005-09-24-AsmUserPrefix.c (820 of 27911)
******************** TEST 'Clang :: CodeGen/2005-09-24-AsmUserPrefix.c' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-09-24-AsmUserPrefix.c -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 | llc |     not grep _foo2
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-09-24-AsmUserPrefix.c -emit-llvm -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-09-24-AsmUserPrefix.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-09-24-AsmUserPrefix.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @bar() #0 {
# | entry:
# |   call void @foo2()
# |   ret void
# | }
# | 
# | declare void @foo2() #1
# | 
# | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3
# |  #0 0x000056434956beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564349568e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056434956c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb34ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb34ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb34ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb34ab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564349501bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564349501a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005643494e68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564349195e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564349195b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb34ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb34ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb34ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564349195a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: llc
# executed command: not grep _foo2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c (821 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei32_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale
# | ...
# `---data was truncated (10240/32108) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e4100dceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e4100d9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e4100dd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdff8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdff878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdff8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdff871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e410072bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e410072a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e4100578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e40fd06e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e40fd06b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdff871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdff871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdff871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e40fd06a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c (822 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svld2_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld2.sret.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld2.sret.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svld2_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld2.sret.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld2.sret.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svld2_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld2.sret.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld2.sret.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svld2_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld2.sret.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld2.sret.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svld2_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld2.sret.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svld2_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld2.sret.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svld2_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld2.sret.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svld2_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld2.sret.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svld2_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld2.sret.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld2.sret.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svld2_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld2.sret.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld2.sret.nxv4f32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double> } @test_svld2_f64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.ld2.sret.nxv2f64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x double>, <vscale x 2 x double> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm
# | ...
# `---data was truncated (10240/24404) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c2ddc04eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c2ddc01e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c2ddc0562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3c68733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3c6878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3c68733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3c6871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c2ddb9abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c2ddb9aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c2ddb7f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c2dd82ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c2dd82eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3c6871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3c6871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3c6871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c2dd82ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c (823 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.
# | ...
# `---data was truncated (10240/18498) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ebc79aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ebc79a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ebc79ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdfe9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdfe9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdfe9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdfe9f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ebc7942bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ebc7942a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ebc79278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ebc75d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ebc75d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdfe9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdfe9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdfe9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ebc75d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c (824 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vand_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vand_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vand_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vand_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vand_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vand_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vand_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vand_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vand_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/424835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d572c43eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d572c40e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d572c4462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ff6733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ff678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ff6733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ff671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d572bd9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d572bd9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d572bbe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d57286de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d57286db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3ff671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ff671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ff671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d57286da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c (825 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsplice_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.splice.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.splice.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsplice_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.splice.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.splice.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsplice_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.splice.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.splice.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svsplice_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.splice.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.splice.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsplice_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.splice.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsplice_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.splice.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsplice_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.splice.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svsplice_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.splice.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svsplice_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.splice.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.splice.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x 
# | ...
# `---data was truncated (10240/14328) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000556cdac6aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556cdac67e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556cdac6b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feea4649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feea46a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feea4649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feea4631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556cdac00bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556cdac00a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556cdabe58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556cda894e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556cda894b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feea4632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feea46330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feea46330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556cda894a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c (826 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f16m1x5(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f32m1x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f64m1x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i16> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005637ecc14eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005637ecc11e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005637ecc1562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f48b4649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f48b46a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f48b4649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f48b4631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005637ecbaabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005637ecbaaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005637ecb8f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005637ec83ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005637ec83eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f48b4632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f48b46330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f48b46330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005637ec83ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c (827 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557cc7cb7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557cc7cb4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557cc7cb862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff065d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff065d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff065d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff065d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557cc7c4dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557cc7c4da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557cc7c328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557cc78e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557cc78e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff065d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff065d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff065d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557cc78e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c (828 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei32_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>,
# | ...
# `---data was truncated (10240/284336) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee30475eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ee30472e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ee3047662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa541d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa541d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa541d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa541ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee3040bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ee3040ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ee303f08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ee3009fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ee3009fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa541ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa541cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa541cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee3009fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c (829 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsbf_m_b1_mu(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %maskedoff, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %2, <vscale x 64 x i1> %0, i64 %3)
# |   ret <vscale x 64 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsbf_m_b2_mu(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %maskedoff, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %2, <vscale x 32 x i1> %0, i64 %3)
# |   ret <vscale x 32 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsbf_m_b4_mu(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %maskedoff, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %2, <vscale x 16 x i1> %0, i64 %3)
# |   ret <vscale x 16 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsbf_m_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %2, <vscale x 8 x i1> %0, i64 %3)
# |   ret <vscale x 8 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbf_m_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %2, <vscale x 4 x i1> %0, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbf_m_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %2, <vscale x 2 x i1> %0, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbf_m_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1.i64(<vscale x 1 x i1> %1, <vscale x 1 x i1> %2, <vscale x 1 x i1> %0, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a90f1f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a90f1eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a90f1f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f663ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f663eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f663ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f663ea31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a90f187bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a90f187a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a90f16c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a90ee1be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a90ee1bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f663ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f663ea330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f663ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a90ee1ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c (830 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsac_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsac_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsac_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsac_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsac_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsac_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsac_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsac_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bflo
# | ...
# `---data was truncated (10240/34364) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005614d8f39eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005614d8f36e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005614d8f3a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca66249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca662a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca66249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca66231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005614d8ecfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005614d8ecfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005614d8eb48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005614d8b63e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005614d8b63b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fca66232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca662330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca662330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005614d8b63a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c (831 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldff1_mf8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldff1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.ldff1.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldff1_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldff1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ldff1.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.ldff1.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ldff1.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ldff1.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ldff1.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ldff1.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldff1_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldff1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ldff1.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ldff1.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ldff1.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svldff1_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.ldff1.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ldff1.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svldff1_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.ldff1.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ldff1.nxv4f32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svldff1_f64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.ldff1.nxv2f64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ldff1.nxv2f64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldff1_vnum_mf8(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# | 
# | ...
# `---data was truncated (10240/64727) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c43db7beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c43db78e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c43db7c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ef641bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ef64725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ef641ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ef6403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c43db11bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c43db11a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c43daf68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c43d7a5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c43d7a5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8ef6404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ef64050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ef64050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c43d7a5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c (832 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_i16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_i16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_i16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_u16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, ali
# | ...
# `---data was truncated (10240/60543) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cb19beaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cb19be7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cb19beb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f364a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f364a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f364a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f364a91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb19b80bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cb19b80a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cb19b658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cb19814e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cb19814b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f364a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f364a91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f364a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb19814a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve/orn.c (833 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/orn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svorn_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.orn.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.orn.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x0000565490bd6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565490bd3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000565490bd762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3229333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f322938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3229333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f322931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565490b6cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565490b6ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000565490b518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565490800e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565490800b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f322931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f322931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f322931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565490800a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/arm-neon-directed-rounding.c (834 of 27911)
******************** TEST 'Clang :: CodeGen/arm-neon-directed-rounding.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57      -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c -o - |      /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8-unknown-linux-gnueabihf"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrnda_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrnda_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrnda_v1.i = call <2 x float> @llvm.round.v2f32(<2 x float> %vrnda_v.i)
# |   %vrnda_v2.i = bitcast <2 x float> %vrnda_v1.i to <8 x i8>
# |   store <8 x i8> %vrnda_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndaq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndaq_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndaq_v1.i = call <4 x float> @llvm.round.v4f32(<4 x float> %vrndaq_v.i)
# |   %vrndaq_v2.i = bitcast <4 x float> %vrndaq_v1.i to <16 x i8>
# |   store <16 x i8> %vrndaq_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrndm_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndm_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrndm_v1.i = call <2 x float> @llvm.floor.v2f32(<2 x float> %vrndm_v.i)
# |   %vrndm_v2.i = bitcast <2 x float> %vrndm_v1.i to <8 x i8>
# |   store <8 x i8> %vrndm_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndmq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndmq_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndmq_v1.i = call <4 x float> @llvm.floor.v4f32(<4 x float> %vrndmq_v.i)
# |   %vrndmq_v2.i = bitcast <4 x float> %vrndmq_v1.i to <16 x i8>
# |   store <16 x i8> %vrndmq_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrndn_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndn_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrndn_v1.i = call <2 x float> @llvm.roundeven.v2f32(<2 x float> %vrndn_v.i)
# |   %vrndn_v2.i = bitcast <2 x float> %vrndn_v1.i to <8 x i8>
# |   store <8 x i8> %vrndn_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndnq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndnq_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndnq_v1.i = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %vrndnq_v.i)
# |   %vrndnq_v2.i = bitcast <4 x float> %vrndnq_v1.i to <16 x i8>
# |   store <16 x i8> %vrndnq_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrndp_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndp_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrndp_v1.i = call <2 x float> @llvm.ceil.v2f32(<2 x float> %vrndp_v.i)
# |   %vrndp_v2.i = bitcast <2 x float> %vrndp_v1.i to <8 x i8>
# |   store <8 x i8> %vrndp_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndpq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndpq_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndpq_v1.i = call <4 x float> @llvm.ceil.v4f32(<4 x float> %vrndpq_v.i)
# |   %vrndpq_v2.i = bitcast <4 x float> %vrndpq_v1.i to <16 x i8>
# |   store <16 x i8> %vrndpq_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrndx_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndx_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrndx_v1.i = call <2 x float> @llvm.rint.v2f32(<2 x float> %vrndx_v.i)
# |   %vrndx_v2.i = bitcast <2 x float> %vrndx_v1.i to <8 x i8>
# |   store <8 x i8> %vrndx_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndxq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndxq_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndxq_v1.i = call <4 x float> @llvm.rint.v4f32(<4 x float> %vrndxq_v.i)
# |   %vrndxq_v2.i = bitcast <4 x float> %vrndxq_v1.i to <16 x i8>
# |   store <16 x i8> %vrndxq_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrnd_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrnd_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrnd_v1.i = call <2 x float> @llvm.trunc.v2f32(<2 x float> %vrnd_v.i)
# |   %vrnd_v2.i = bitcast <2 x float> %vrnd_v1.i to <8 x i8>
# |   store <8 x i8> %vrnd_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x
# | ...
# `---data was truncated (10240/16447) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000563760abbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563760ab8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563760abc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6fb9449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6fb94a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6fb9449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6fb9431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563760a51bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563760a51a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563760a368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005637606e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005637606e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6fb9432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6fb94330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6fb94330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005637606e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c (835 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f16m1x8(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f32m1x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f64m1x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei8_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none
# | ...
# `---data was truncated (10240/61673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dbdc8d1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dbdc8cee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dbdc8d262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0259e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0259ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0259e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0259e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dbdc867bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dbdc867a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dbdc84c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dbdc4fbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dbdc4fbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0259e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0259e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0259e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dbdc4fba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c (836 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vv_f32mf2(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vf_f32mf2(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wv_f32mf2(<vscale x 1 x float> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wf_f32mf2(<vscale x 1 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vv_f32m1(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vf_f32m1(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wv_f32m1(<vscale x 2 x float> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wf_f32m1(<vscale x 2 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwadd_vv_f32m2(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwadd_vf_f32m2(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/151903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e9cbe1aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e9cbe17e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e9cbe1b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcca9c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcca9c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcca9c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcca9c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e9cbdb0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e9cbdb0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e9cbd958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e9cba44e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e9cba44b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcca9c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcca9c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcca9c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e9cba44a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c (837 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsmul_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsmul_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsmul_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsmul_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsmul_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsmul_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsmul_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsmul_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsmul_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, al
# | ...
# `---data was truncated (10240/225213) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556446be1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556446bdee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556446be262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f96c6849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f96c68a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f96c6849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f96c6831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556446b77bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556446b77a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556446b5c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055644680be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055644680bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f96c6832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f96c68330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f96c68330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055644680ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c (838 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3e
# | ...
# `---data was truncated (10240/228857) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056265bebaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056265beb7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056265bebb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f501de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f501dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f501de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f501de31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056265be50bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056265be50a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056265be358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056265bae4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056265bae4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f501de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f501de330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f501de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056265bae4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c (839 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsne_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsne_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsne_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsne_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsne_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsne_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsne_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsne_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsne_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsne_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsne_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> %0, 
# | ...
# `---data was truncated (10240/171381) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005584ed216eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005584ed213e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005584ed21762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9fb4649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9fb46a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9fb4649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9fb4631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005584ed1acbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005584ed1aca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005584ed1918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005584ece40e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005584ece40b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9fb4632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9fb46330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9fb46330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005584ece40a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c (840 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdivu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdivu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdivu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdivu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdivu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdivu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdivu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdivu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdivu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x
# | ...
# `---data was truncated (10240/222925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed55667eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ed55664e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ed5566862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f55fce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f55fcea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f55fce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f55fce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed555fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ed555fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ed555e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ed55291e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ed55291b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f55fce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f55fce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f55fce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed55291a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c (841 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei8_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %m
# | ...
# `---data was truncated (10240/160133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d1b455eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558d1b452e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558d1b45662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb7abe1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb7abe725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb7abe1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb7abe03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d1b3ebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558d1b3eba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558d1b3d08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558d1b07fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558d1b07fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb7abe04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb7abe050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb7abe050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d1b07fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c (842 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgather_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %index.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgather_vx_f16mf4(<vscale x 1 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgather_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %index.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgather_vx_f16mf2(<vscale x 2 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgather_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %index.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgather_vx_f16m1(<vscale x 4 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgather_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgather_vx_f16m2(<vscale x 8 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgather_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vrgather.vv.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vrgather.vv.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgather_vx_f16m4(<vscale x 16 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vrgather.vx.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willre
# | ...
# `---data was truncated (10240/273697) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555889797eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555889794e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055588979862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc3df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc3df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc3df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc3df1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055588972dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055588972da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005558897128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005558893c1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005558893c1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdc3df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc3df1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc3df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005558893c1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c (843 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_i16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_i16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_i16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_u16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, ali
# | ...
# `---data was truncated (10240/60543) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561f932d7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561f932d4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561f932d862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d81649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d816a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d81649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d81631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f9326dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561f9326da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561f932528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561f92f01e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561f92f01b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8d81632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d816330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d816330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f92f01a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c (844 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558b0af26eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558b0af23e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558b0af2762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc16ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc16cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc16ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc16ce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558b0aebcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558b0aebca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558b0aea18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558b0ab50e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558b0ab50b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc16ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc16ce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc16ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558b0ab50a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c (845 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlse16_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16.p0.i64(<vscale x 1 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlse16_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16.p0.i64(<vscale x 2 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlse16_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16.p0.i64(<vscale x 4 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlse16_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16.p0.i64(<vscale x 8 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlse16_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16.p0.i64(<vscale x 16 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlse16_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16.p0.i64(<vscale x 32 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vlse16_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16.p0.i64(<vscale x 1 x i16> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vlse16_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16.p0.i64(<vscale x 2 x i16> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vlse16_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vlse.nxv4i16.p0.i64(<vscale x 4 x i16> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i16> @llvm.riscv.vlse.nx
# | ...
# `---data was truncated (10240/83629) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563cee341eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563cee33ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563cee34262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2715b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2715b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2715b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2715b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563cee2d7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563cee2d7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563cee2bc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563cedf6be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563cedf6bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2715b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2715b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2715b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563cedf6ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c (846 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4r_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4r.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4r.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4r_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4r_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4r_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm4r_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4r_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4r_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv
# | ...
# `---data was truncated (10240/20082) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bcbf001eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bcbeffee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bcbf00262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff15c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff15c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff15c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff15c51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bcbef97bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bcbef97a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bcbef7c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bcbec2be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bcbec2bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff15c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff15c51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff15c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bcbec2ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c (847 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_f32mf2x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_f32m1x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_f32m2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_f32m4x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_i32mf2x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_i32m1x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_i32m2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_i32m4x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_u32mf2x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_u32m1x2_m(<vscale x 2 x i1> %mask,
# | ...
# `---data was truncated (10240/13544) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558931754eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558931751e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055893175562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f57a1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57a1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f57a1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f57a1d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589316eabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005589316eaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005589316cf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055893137ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055893137eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f57a1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57a1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57a1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055893137ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c (848 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_u16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_u16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_u16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_u16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_u16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfclass_v_u16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfclass_v_u32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfclass_v_u32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfclass_v_u32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfclass_v_u32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8f32.i64(<vscale x 8 x i32> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8f32.i64(<vscale x 8 x i32>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfclass_v_u32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vfclass.nxv16f32.i64(<vscale x 16 x i32> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vfclass.nxv16f32.i64(<vscale x 16 x i32>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vfclass_v_u64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vfclass.nxv1f64.i64(<vscale x 1 x i64> poison, <vscale x 1 x double> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vfclass.nxv1f64.i64(<vscale x 1 x i64>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vfclass_v_u64m2(<vscale x 2 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <v
# | ...
# `---data was truncated (10240/28691) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560cc7fe9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560cc7fe6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560cc7fea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efe6a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efe6a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efe6a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efe6a431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560cc7f7fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560cc7f7fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560cc7f648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560cc7c13e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560cc7c13b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efe6a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efe6a4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efe6a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560cc7c13a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c (849 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh    -target-feature +xsfvfexpa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexpa_v_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexpa_v_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexpa_v_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexpa_v_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexpa_v_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vfexpa_v_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 32 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexpa_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexpa_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexpa_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexpa_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32.i64(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>
# | ...
# `---data was truncated (10240/47764) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557df080beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557df0808e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557df080c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3262133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f326218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3262133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f326211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557df07a1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557df07a1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557df07868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557df0435e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557df0435b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f326211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f326211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f326211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557df0435a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c (850 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesef_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesef_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesef_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretur
# | ...
# `---data was truncated (10240/20190) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558f5498eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558f5498be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558f5498f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff030933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff03098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff030933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff03091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f54924bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558f54924a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558f549098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558f545b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558f545b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff03091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff03091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff03091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f545b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c (851 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vv_bf16mf4_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vf_bf16mf4_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vv_bf16mf2_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vf_bf16mf2_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vv_bf16m1_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vf_bf16m1_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vv_bf16m2_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vf_bf16m2_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.bf16.nxv8bf16.i6
# | ...
# `---data was truncated (10240/51694) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561b2ea6ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561b2ea69e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561b2ea6d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f788f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f788f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f788f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f788f31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561b2ea02bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561b2ea02a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561b2e9e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561b2e696e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561b2e696b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f788f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f788f31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f788f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561b2e696a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c (852 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve-b16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve-b16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_bf16(<vscale x 8 x bfloat> %acc, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) #0 {
# | entry:
# |   %acc.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %a.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %b.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %acc, ptr %acc.addr, align 16
# |   store <vscale x 8 x bfloat> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x bfloat> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %acc.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %a.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %b.addr, align 16
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmmla.nxv8bf16.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmmla.nxv8bf16.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16mm" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000563047984eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563047981e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056304798562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1909d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1909d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1909d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1909d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056304791abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056304791aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005630478ff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005630475aee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005630475aeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1909d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1909d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1909d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005630475aea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c (853 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature -fullfp16 -target-feature +v8a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature -fullfp16 -target-feature +v8a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | %struct.float16x4x2_t = type { [2 x <4 x half>] }
# | %struct.float16x8x2_t = type { [2 x <8 x half>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vbsl_f16(<4 x i16> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vbsl.i = bitcast <8 x i8> %3 to <4 x i16>
# |   %vbsl1.i = bitcast <8 x i8> %4 to <4 x i16>
# |   %vbsl2.i = bitcast <8 x i8> %5 to <4 x i16>
# |   %vbsl3.i = and <4 x i16> %vbsl.i, %vbsl1.i
# |   %6 = xor <4 x i16> %vbsl.i, splat (i16 -1)
# |   %vbsl4.i = and <4 x i16> %6, %vbsl2.i
# |   %vbsl5.i = or <4 x i16> %vbsl3.i, %vbsl4.i
# |   %7 = bitcast <4 x i16> %vbsl5.i to <4 x half>
# |   store <4 x half> %7, ptr %ref.tmp.i, align 8
# |   %8 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %8, ptr %__ret.i, align 8
# |   %9 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vbslq_f16(<8 x i16> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vbsl.i = bitcast <16 x i8> %3 to <8 x i16>
# |   %vbsl1.i = bitcast <16 x i8> %4 to <8 x i16>
# |   %vbsl2.i = bitcast <16 x i8> %5 to <8 x i16>
# |   %vbsl3.i = and <8 x i16> %vbsl.i, %vbsl1.i
# |   %6 = xor <8 x i16> %vbsl.i, splat (i16 -1)
# |   %vbsl4.i = and <8 x i16> %6, %vbsl2.i
# |   %vbsl5.i = or <8 x i16> %vbsl3.i, %vbsl4.i
# |   %7 = bitcast <8 x i16> %vbsl5.i to <8 x half>
# |   store <8 x half> %7, ptr %ref.tmp.i, align 16
# |   %8 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %8, ptr %__ret.i, align 16
# |   %9 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float16x4x2_t @test_vzip_f16(<4 x half> noundef %a, <4 x half> noundef %b) #0 {
# | entry:
# |   %retval.i = alloca %struct.float16x4x2_t, align 8
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %retval = alloca %struct.float16x4x2_t, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = bitcast <8 x i8> %2 to <4 x half>
# |   %5 = bitcast <8 x i8> %3 to <4 x half>
# |   %vzip.i = shufflevector <4 x half> %4, <4 x half> %5, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
# |   store <4 x half> %vzip.i, ptr %retval.i, align 8
# |   %6 = getelementptr inbounds <4 x half>, ptr %retval.i, i32 1
# |   %vzip1.i = shufflevector <4 x half> %4, <4 x half> %5, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
# |   store <4 x half> %vzip1.i, ptr %6, align 8
# |   %7 = load %struct.float16x4x2_t, ptr %retval.i, align 8
# |   %8 = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %retval, i32 0, i32 0
# |   %9 = extractvalue %struct.float16x4x2_t %7, 0
# |   store [2 x <4 x half>] %9, ptr %8, align 8
# |   %10 = load %struct.float16x4x2_t, ptr %retval, align 8
# |   ret %struct.float16x4x2_t %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float16x8x2_t @test_vzipq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %retval.i = alloca %struct.float16x8x2_t, align 16
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %retval = alloca %struct.float16x8x2_t, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %4 = bitcast <16 x i8> %2 to <8 x half>
# |   %5 = bitcast <16 x i8> %3 to <8 x half>
# |   %vzip.i = shufflevector <8 x half> %4, <8 x half> %5, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
# |   store <8 x half> %vzip.i, ptr %retval.i, align 16
# |   %6 = getelementptr inbounds <8 x half>, ptr %retval.i, i32 1
# |   %vzip1.i = shufflevector <8 x half> %4, <8 x half> %5, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
# |   store <8 x half> %vzip1.i, ptr %6, align 16
# |   %7 = load %struct.float16x8x2_t, ptr %retval.i, align 16
# |   %8 = getelementptr inbounds nuw %struct.float16x8x2_t, ptr %retval, i32 0, i32 0
# |   %9 = extractvalue %struct.float16x8x2_t %7, 0
# |   store [2 x <8 x half>] %9, ptr %8, align 16
# |   %10 = load %struct.float16x8x2_t, ptr %retval, align 16
# |   ret %struct.float16x8x2_t %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float16x4x2_t @test_vuzp_f16(<4 x half> noundef %a, <4 x half> noundef %b) #0 {
# | entry:
# |   %retval.i = alloca %struct.float16x4x2_t, align 8
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %retval = alloca %struct.float16x4x2_t, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = bitcast <8 x i8> %2 to <4 x half>
# |   %5 = bitcast <8 x i8> %3 to <4 x half>
# |   %vuzp.i = shufflevector <4 x half> %4, <4 x half> %5, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
# |   store <4 x half> %vuzp.i, ptr %retval.i, align 8
# |   %6 = getelementptr inbounds <4 x half>, ptr %retval.i, i32 1
# |   %vuzp1.i = shufflevector <4 x half> %4, <4 x half> %5, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
# |   store <4 x half> %vuzp1.i, ptr %6, align 8
# |   %7 = load %struct.float16x4x2_t, ptr %retval.i, align 8
# |   %8 = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %retval, i32 0, i32 0
# |   %9 = extractvalue %struct.float16x4x2_t %7, 0
# |   store [2 x <4 x half>] %9, ptr %8, align 8
# |   %10 = load %struct.float16x4x2_t, ptr %retval, align 8
# |   ret %struct.float16x4x2_t %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float16x8x2_t @test_vuzpq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %retval.i = alloca %struct.float16x8x2_t, align 16
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %retval = alloca %struct.float16x8x2_t, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %4 = bitcast <16 x i8> %2 to <8 x half>
# |   %5 = bitcast <16 x i8> %3 to <8 x half>
# |   %vuzp.i = shufflevector <8 x half> %4, <8 x half> %5, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
# |   store <8 x half> %vuzp.i, ptr %retval.i, align 16
# |   %6 = getelementptr inbounds <8 x half>, ptr %retval.i, i32 1
# |   %vuzp1.i = shufflevector <8 x half> %4, <8 x half> %5, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
# |   store <8 x half> %vuzp1.i, ptr %6, align 16
# |   %7 = load %struct.float16x8x2_t, ptr %retval.i, align 16
# |   %8 = getelementptr inbounds nuw %struct.float16x8x2_t, ptr %retval, i32 0, i32 0
# |   %9 = extractvalue %struct.float16x8x2_t %7, 0
# |   store [2 x <8 x half>] %9, ptr %8, align 16
# |   %10 = load %struct.float16x8x2_t, ptr %retval, align 16
# |   ret %struct.float16x8x2_t %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float16x4x2_t @test_vtrn_f16(<4 x half> noundef %a, <4 x half> noundef 
# | ...
# `---data was truncated (10240/31986) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055c11f2eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c11f2ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c11f2ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff46ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff46ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff46ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff46ed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c11f284bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c11f284a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c11f2698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c11ef18e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c11ef18b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff46ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff46ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff46ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c11ef18a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c (854 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f16m1x4(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f16m2x4(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f32m1x4(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f32m2x4(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f64m1x4(ptr noundef %base, <vscale x 1 x i64
# | ...
# `---data was truncated (10240/94235) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005637834edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005637834eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005637834ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff801e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff801ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff801e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff801e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563783483bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563783483a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005637834688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563783117e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563783117b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff801e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff801e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff801e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563783117a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c (855 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f16m1x3(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_f16m2x3(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f32m1x3(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_f32m2x3(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f64m1x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.
# | ...
# `---data was truncated (10240/82975) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560432a86eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560432a83e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560432a8762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f50c3d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f50c3d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f50c3d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f50c3d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560432a1cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560432a1ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560432a018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005604326b0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005604326b0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f50c3d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f50c3d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f50c3d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005604326b0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c (856 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnj_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnj_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnj_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnj_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnj_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnj_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnj_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnj_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnj_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnj.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnj.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnj_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnj.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale 
# | ...
# `---data was truncated (10240/69495) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c3cc62eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563c3cc5fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563c3cc6362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa3eaf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa3eaf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa3eaf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa3eaf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c3cbf8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563c3cbf8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563c3cbdd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563c3c88ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563c3c88cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa3eaf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa3eaf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa3eaf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c3c88ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c (857 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svaclt_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.facgt.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %2, <vscale x 8 x half> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.facgt.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svaclt_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.facgt.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %2, <vscale x 4 x float> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.facgt.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svaclt_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.facgt.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %2, <vscale x 2 x double> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.facgt.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svaclt_n_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, float noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca float, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store float %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 4 x float> poison, float %2, i64 0
# |   %.splat = shufflevector <vscale x 4 x float> %.splatinsert, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.facgt.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %.splat, <vscale x 4 x float> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svaclt_n_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, double noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca double, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store double %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load double, ptr %op2.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 2 x double> poison, double %2, i64 0
# |   %.splat = shufflevector <vscale x 2 x double> %.splatinsert, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.facgt.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %.splat, <vscale x 2 x double> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c262b38eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c262b35e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c262b3962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fde3c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fde3c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fde3c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fde3c831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c262acebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c262acea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c262ab38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c262762e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c262762b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fde3c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fde3c8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fde3c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c262762a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c (858 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmmla_s32(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.smmla.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.smmla.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmmla_u32(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ummla.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ummla.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svusmmla_s32(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usmmla.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.usmmla.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+i8mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005584e7595eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005584e7592e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005584e759662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f77a4c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f77a4ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f77a4c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f77a4c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005584e752bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005584e752ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005584e75108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005584e71bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005584e71bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f77a4c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f77a4c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f77a4c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005584e71bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c (859 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565331dd2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565331dcfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000565331dd362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff40fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff40fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff40fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff40fb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565331d68bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565331d68a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000565331d4d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005653319fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005653319fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff40fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff40fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff40fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005653319fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c (860 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs1, <vsc
# | ...
# `---data was truncated (10240/148835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560b527eaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560b527e7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560b527eb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f084f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f084f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f084f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f084f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b52780bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560b52780a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560b527658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560b52414e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560b52414b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f084f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f084f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f084f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b52414a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c (861 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svget3_s8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %tuple.coerce2) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %tuple.coerce2, 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svget3_s16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %tuple.coerce2) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %tuple.coerce2, 2
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   %3 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, 2
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svget3_s32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1, <vscale x 4 x i32> %tuple.coerce2) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %tuple.coerce2, 2
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   %3 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 1
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svget3_s64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1, <vscale x 2 x i64> %tuple.coerce2) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, <vscale x 2 x i64> %tuple.coerce2, 2
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %tuple1, ptr %tuple.addr, align 16
# |   %3 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple.addr, align 16
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 0
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svget3_u8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %tuple.coerce2) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %tuple.coerce2, 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 2
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svget3_u16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %tuple.coerce2) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %tuple.coerce2, 2
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   %3 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, 1
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svget3_u32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1, <vscale x 4 x i32> %tuple.coerce2) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %tuple.coerce2, 2
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   %3 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 0
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svget3_u64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1, <vscale x 2 x i64> %tuple.coerce2) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   %2 = insertvalue 
# | ...
# `---data was truncated (10240/21007) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000563033763eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563033760e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056303376462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f16add33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f16add8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f16add33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f16add1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005630336f9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005630336f9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005630336de8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056303338de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056303338db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f16add1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f16add1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f16add1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056303338da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c (862 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f20ca9aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f20ca97e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f20ca9b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2441333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f244138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2441333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f244131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f20ca30bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f20ca30a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f20ca158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f20c6c4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f20c6c4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f244131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f244131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f244131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f20c6c4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c (863 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svget4_s8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %tuple.coerce2, <vscale x 16 x i8> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %tuple.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svget4_s16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %tuple.coerce2, <vscale x 8 x i16> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %tuple.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   %4 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 2
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svget4_s32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1, <vscale x 4 x i32> %tuple.coerce2, <vscale x 4 x i32> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %tuple.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 2
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svget4_s64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1, <vscale x 2 x i64> %tuple.coerce2, <vscale x 2 x i64> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, <vscale x 2 x i64> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %tuple.coerce3, 3
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %tuple1, ptr %tuple.addr, align 16
# |   %4 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple.addr, align 16
# |   %5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 3
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svget4_u8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %tuple.coerce2, <vscale x 16 x i8> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %tuple.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svget4_u16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %tuple.coerce2, <vscale x 8 x i16> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %tuple.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.a
# | ...
# `---data was truncated (10240/28771) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005560878f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005560878f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005560878fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0ca0b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0ca0b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0ca0b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0ca0aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055608788fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055608788fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005560878748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556087523e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556087523b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0ca0aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0ca0aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0ca0aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556087523a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c (864 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsll_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsll_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsll_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsll_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsll_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsll_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsll_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsll_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsll_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 
# | ...
# `---data was truncated (10240/427575) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555e5861ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555e58619e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555e5861d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f89df533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f89df58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f89df533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f89df51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555e585b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555e585b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555e585978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555e58246e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555e58246b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f89df51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f89df51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f89df51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555e58246a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c (865 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclip_wv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclip_wx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclip_wv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclip_wx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclip_wv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclip_wx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclip_wv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclip_wx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclip_wv_i8m2_tu(<vscale
# | ...
# `---data was truncated (10240/156471) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563985043eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563985040e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056398504462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa0c3649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa0c36a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa0c3649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa0c3631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563984fd9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563984fd9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563984fbe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563984c6de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563984c6db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa0c3632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa0c36330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa0c36330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563984c6da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c (866 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqinch_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqinch.n32(i32 %0, i32 31, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqinch.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqinch_n_s32_1(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqinch.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqinch_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqinch.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqinch.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqinch_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqinch.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqinch.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqinch_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqinch.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uqinch.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqinch_pat_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqinch.n32(i32 %0, i32 30, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqinch_pat_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqinch.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqinch_pat_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqinch.n32(i32 %0, i32 0, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqinch_pat_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqinch.n64(i64 %0, i32 1, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqinch_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqinch.nxv8i16(<vscale x 8 x i16> %0, i32 31, i32 16)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqinch.nxv8i16(<vscale x 8 x i16>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqinch_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqinch.nxv8i16(<vscale x 8 x i16> %0, i32 31, i32 1)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqinch.nxv8i16(<vscale x 8 x i16>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqinch_pat_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqinch.nxv8i16(<vscale x 8 x i16> %0, i32 2, i32 16)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqinch_pat_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqinch.nxv8i16(<vscale x 8 x i16> %0, i32 3, i32 1)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055595f7b8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055595f7b5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055595f7b962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8affe1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8affe725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8affe1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8affe03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055595f74ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055595f74ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055595f7338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055595f3e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055595f3e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8affe04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8affe050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8affe050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055595f3e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c (867 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vf_f32mf2_tu(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vf_f32m1_tu(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vf_f32m2_tu(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vf_f32m4_tu(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsa
# | ...
# `---data was truncated (10240/179511) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f0060d4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f0060d1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f0060d562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb98db05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb98db5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb98db05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb98daed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f00606abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f00606aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f00604f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f005cfee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f005cfeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb98daeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb98daef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb98daef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f005cfea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c (868 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svunpkhi_s16(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.sunpkhi.nxv8i16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sunpkhi.nxv8i16(<vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svunpkhi_s32(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.sunpkhi.nxv4i32(<vscale x 8 x i16> %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sunpkhi.nxv4i32(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svunpkhi_s64(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.sunpkhi.nxv2i64(<vscale x 4 x i32> %0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sunpkhi.nxv2i64(<vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svunpkhi_u16(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.uunpkhi.nxv8i16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uunpkhi.nxv8i16(<vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svunpkhi_u32(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.uunpkhi.nxv4i32(<vscale x 8 x i16> %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uunpkhi.nxv4i32(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svunpkhi_u64(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.uunpkhi.nxv2i64(<vscale x 4 x i32> %0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uunpkhi.nxv2i64(<vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svunpkhi_b(<vscale x 16 x i1> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.punpkhi.nxv16i1(<vscale x 16 x i1> %0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.punpkhi.nxv16i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055f93d339eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f93d336e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f93d33a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f52ba333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f52ba38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f52ba333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f52ba31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f93d2cfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f93d2cfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f93d2b48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f93cf63e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f93cf63b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f52ba31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f52ba31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f52ba31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f93cf63a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c (869 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16m1x2(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16m2x2(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16m4x2(ptr noundef %base, <vscale x 16 x i32> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f32m1x2(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f32m2x2(ptr noundef %base, <vscale x
# | ...
# `---data was truncated (10240/123663) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558f1f1d0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558f1f1cde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558f1f1d162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc396533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc39658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc396533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc39651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f1f166bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558f1f166a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558f1f14b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558f1edfae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558f1edfab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc39651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc39651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc39651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f1edfaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c (870 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei8_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_f32m1x2_tu(target("riscv
# | ...
# `---data was truncated (10240/295533) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e5f103beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e5f1038e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e5f103c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc4de933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc4de98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc4de933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc4de91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e5f0fd1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e5f0fd1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e5f0fb68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e5f0c65e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e5f0c65b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc4de91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc4de91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc4de91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e5f0c65a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c (871 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabdu_vv_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabdu_vx_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabdu_vv_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabdu_vx_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabdu_vv_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabdu_vx_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabdu_vv_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabdu_vx_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabdu_vv_u8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i
# | ...
# `---data was truncated (10240/215478) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c157b16eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c157b13e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c157b1762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f48b1f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f48b1f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f48b1f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f48b1f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c157aacbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c157aaca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c157a918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c157740e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c157740b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f48b1f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f48b1f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f48b1f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c157740a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c (872 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vpairo_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vpairo.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vpairo.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vpairo_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vpairo.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vpairo.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vpairo_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vpairo.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vpairo.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vpairo_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vpairo.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vpairo.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vpairo_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vpairo.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vpairo.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vpairo_vv_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vpairo.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vpairo.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vpairo_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vpairo.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vpairo.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vpairo_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vpairo.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vpairo.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vpairo_vv_f32m2_tu
# | ...
# `---data was truncated (10240/288275) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564970653eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564970650e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056497065462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcebf933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcebf98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcebf933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcebf91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005649705e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005649705e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005649705ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056497027de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056497027db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcebf91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcebf91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcebf91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056497027da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c (873 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willr
# | ...
# `---data was truncated (10240/44361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556606e51eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556606e4ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556606e5262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd23b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd23b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd23b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd23b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556606de7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556606de7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556606dcc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556606a7be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556606a7bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbd23b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd23b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd23b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556606a7ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c (874 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsadd_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsadd_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsadd_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsadd_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsadd_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsadd_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsadd_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsadd_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsadd_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x
# | ...
# `---data was truncated (10240/222925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b48786ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b487869e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b48786d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f94ee049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f94ee0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f94ee049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f94ee031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b487802bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b487802a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b4877e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b487496e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b487496b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f94ee032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f94ee0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f94ee0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b487496a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c (875 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_vv_i16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_vx_i16mf4(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_wv_i16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_wx_i16mf4(<vscale x 1 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_vv_i16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_vx_i16mf2(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_wv_i16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_wx_i16mf2(<vscale x 2 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsub_vv_i16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsub_vx_i16m1(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsub_wv_i16m1(<vscal
# | ...
# `---data was truncated (10240/134557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556ce5a9aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556ce5a97e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556ce5a9b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe6cbd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe6cbd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe6cbd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe6cbd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ce5a30bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556ce5a30a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556ce5a158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556ce56c4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556ce56c4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe6cbd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe6cbd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe6cbd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556ce56c4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c (876 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei8_v_f16mf4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei8_v_f16mf2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei8_v_f16m1(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei8_v_f16m2(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei8_v_f16m4(ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vluxei8_v_f16m8(ptr noundef %base, <vscale x 32 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> poison, ptr %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei8_v_f32mf2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei8_v_f32m1(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei8_v_f32m2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei8_v_f32m4(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i8.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i8.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vsc
# | ...
# `---data was truncated (10240/121179) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055846cfc4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055846cfc1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055846cfc562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa576c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa576ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa576c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa576c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055846cf5abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055846cf5aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055846cf3f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055846cbeee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055846cbeeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa576c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa576c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa576c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055846cbeea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/arm-v8.6a-neon-intrinsics.c (877 of 27911)
******************** TEST 'Clang :: CodeGen/arm-v8.6a-neon-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.6a-arm-none-eabi -target-feature +neon -target-feature +fullfp16 -target-feature +i8mm  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.6a-arm-none-eabi -target-feature +neon -target-feature +fullfp16 -target-feature +i8mm -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8.6a-arm-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmmlaq_s32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 8
# |   %__p1.addr.i = alloca <16 x i8>, align 8
# |   %__p2.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %r.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <4 x i32> %r, ptr %r.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %r.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 8
# |   %vmmla.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vmmla1.i = call <4 x i32> @llvm.arm.neon.smmla.v4i32.v16i8(<4 x i32> %vmmla.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vmmla1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmmlaq_u32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 8
# |   %__p1.addr.i = alloca <16 x i8>, align 8
# |   %__p2.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %r.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <4 x i32> %r, ptr %r.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %r.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 8
# |   %vmmla.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vmmla1.i = call <4 x i32> @llvm.arm.neon.ummla.v4i32.v16i8(<4 x i32> %vmmla.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vmmla1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vusmmlaq_s32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 8
# |   %__p1.addr.i = alloca <16 x i8>, align 8
# |   %__p2.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %r.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <4 x i32> %r, ptr %r.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %r.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 8
# |   %vusmmla.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vusmmla1.i = call <4 x i32> @llvm.arm.neon.usmmla.v4i32.v16i8(<4 x i32> %vusmmla.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vusmmla1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vusdot_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x i32>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <2 x i32> %r, ptr %r.addr, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %r.addr, align 8
# |   %1 = load <8 x i8>, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %b.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vusdot.i = bitcast <8 x i8> %3 to <2 x i32>
# |   %vusdot1.i = call <2 x i32> @llvm.arm.neon.usdot.v2i32.v8i8(<2 x i32> %vusdot.i, <8 x i8> %4, <8 x i8> %5)
# |   store <2 x i32> %vusdot1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vusdot_lane_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x i32>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret_845 = alloca <2 x i32>, align 8
# |   %__s0_845 = alloca <2 x i32>, align 8
# |   %__s1_845 = alloca <8 x i8>, align 8
# |   %__s2_845 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <2 x i32>, align 8
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp1 = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   %tmp2 = alloca <2 x i32>, align 8
# |   store <2 x i32> %r, ptr %r.addr, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %r.addr, align 8
# |   store <2 x i32> %0, ptr %__s0_845, align 8
# |   %1 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %1, ptr %__s1_845, align 8
# |   %2 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %2, ptr %__s2_845, align 8
# |   %3 = load <2 x i32>, ptr %__s0_845, align 8
# |   %4 = load <8 x i8>, ptr %__s1_845, align 8
# |   %5 = load <2 x i32>, ptr %__s2_845, align 8
# |   store <2 x i32> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x i32>
# |   %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> zeroinitializer
# |   store <2 x i32> %lane, ptr %ref.tmp1, align 8
# |   %8 = load <2 x i32>, ptr %ref.tmp1, align 8
# |   store <2 x i32> %8, ptr %__ret, align 8
# |   %9 = load <2 x i32>, ptr %__ret, align 8
# |   store <2 x i32> %9, ptr %tmp, align 8
# |   %10 = load <2 x i32>, ptr %tmp, align 8
# |   store <2 x i32> %10, ptr %ref.tmp, align 8
# |   %11 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <2 x i32> %3, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %4, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %11, ptr %__p2.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %14 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vusdot.i = bitcast <8 x i8> %12 to <2 x i32>
# |   %vusdot1.i = call <2 x i32> @llvm.arm.neon.usdot.v2i32.v8i8(<2 x i32> %vusdot.i, <8 x i8> %13, <8 x i8> %14)
# |   store <2 x i32> %vusdot1.i, ptr %ref.tmp.i, align 8
# |   %15 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %15, ptr %__ret.i, align 8
# |   %16 = load <2 x i32>, ptr %__ret.i, align 8
# |   store <2 x i32> %16, ptr %__ret_845, align 8
# |   %17 = load <2 x i32>, ptr %__ret_845, align 8
# |   store <2 x i32> %17, ptr %tmp2, align 8
# |   %18 = load <2 x i32>, ptr %tmp2, align 8
# |   ret <2 x i32> %18
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vsudot_lane_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x i32>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret_841 = alloca <2 x i32>, align 8
# |   %__s0_841 = alloca <2 x i32>, align 8
# |   %__s1_841 = alloca <8 x i8>, align 8
# |   %__s2_841 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <2 x i32>, align 8
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp1 = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   %tmp2 = alloca <2 x i32>, align 8
# |   store <2 x i32> %r, ptr %r.addr, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %r.addr, align 8
# |   store <2 x i32> %0, ptr %__s0_841, align 8
# |   %1 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %1, ptr %__s1_841, align 8
# |   %2 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %2, ptr %__s2_841, align 8
# |   %3 = load <2 x i32>, ptr %__s0_841, align 8
# |   %4 = load <2 x i32>, ptr %__s2_841, align 8
# |   store <2 x i32> %4, ptr %__s0, align 8
# |   %5 = load <8 x i8>, ptr %__s0, align 8
# |   %6 = bitcast <8 x i8> %5 to <2 x i32>
# |   %lane = shufflevector <2 x i32> %6, <2 x i32> %6, <2 
# | ...
# `---data was truncated (10240/18482) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055b38d94eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b38d94be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b38d94f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0da1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0da178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0da1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0da171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b38d8e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b38d8e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b38d8c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b38d578e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b38d578b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0da171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0da171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0da171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b38d578a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/arm-mfp8.c (878 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mfp8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -emit-llvm -triple aarch64-arm-none-eabi -target-feature -fp8 -target-feature +neon -disable-O0-optnone -o -        /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c --check-prefixes=CHECK-C
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -emit-llvm -triple aarch64-arm-none-eabi -target-feature -fp8 -target-feature +neon -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-arm-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_ret_mfloat8x16_t(<16 x i8> %v) #0 {
# | entry:
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   ret <16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_ret_mfloat8x8_t(<8 x i8> %v) #0 {
# | entry:
# |   %v.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %v, ptr %v.addr, align 8
# |   %0 = load <8 x i8>, ptr %v.addr, align 8
# |   ret <8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i8> @func1n(<1 x i8> %mfp8) #0 {
# | entry:
# |   %mfp8.addr = alloca <1 x i8>, align 1
# |   %f1n = alloca [10 x <1 x i8>], align 1
# |   store <1 x i8> %mfp8, ptr %mfp8.addr, align 1
# |   %0 = load <1 x i8>, ptr %mfp8.addr, align 1
# |   %arrayidx = getelementptr inbounds [10 x <1 x i8>], ptr %f1n, i64 0, i64 2
# |   store <1 x i8> %0, ptr %arrayidx, align 1
# |   %arrayidx1 = getelementptr inbounds [10 x <1 x i8>], ptr %f1n, i64 0, i64 2
# |   %1 = load <1 x i8>, ptr %arrayidx1, align 1
# |   ret <1 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i8> @test_extract_element(<16 x i8> %x, i32 noundef %i) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   %i.addr = alloca i32, align 4
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   store i32 %i, ptr %i.addr, align 4
# |   %0 = load <16 x i8>, ptr %x.addr, align 16
# |   %1 = load i32, ptr %i.addr, align 4
# |   %vecext = extractelement <16 x i8> %0, i32 %1
# |   %mfp8ext = insertelement <1 x i8> poison, i8 %vecext, i64 0
# |   ret <1 x i8> %mfp8ext
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_insert_element(<16 x i8> %x, i32 noundef %i, <1 x i8> %v) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   %i.addr = alloca i32, align 4
# |   %v.addr = alloca <1 x i8>, align 1
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   store i32 %i, ptr %i.addr, align 4
# |   store <1 x i8> %v, ptr %v.addr, align 1
# |   %0 = load <1 x i8>, ptr %v.addr, align 1
# |   %1 = load i32, ptr %i.addr, align 4
# |   %2 = load <16 x i8>, ptr %x.addr, align 16
# |   %3 = bitcast <1 x i8> %0 to i8
# |   %vecins = insertelement <16 x i8> %2, i8 %3, i32 %1
# |   store <16 x i8> %vecins, ptr %x.addr, align 16
# |   %4 = load <16 x i8>, ptr %x.addr, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon,-fp8" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=mem2reg
# |  #0 0x00005589f91deeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005589f91dbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005589f91df62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcdc8105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcdc815c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcdc8105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcdc80ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589f9174bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005589f9174a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005589f91598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005589f8e08e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005589f8e08b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcdc80eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcdc80ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcdc80ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005589f8e08a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c --check-prefixes=CHECK-C
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c --check-prefixes=CHECK-C
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c (879 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmacc_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmacc_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmacc_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmacc_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmacc_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmacc_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmacc_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmacc_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# | ...
# `---data was truncated (10240/34438) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564a82cf5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564a82cf2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564a82cf662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce35e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce35ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce35e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce35e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564a82c8bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564a82c8ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564a82c708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564a8291fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564a8291fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fce35e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce35e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce35e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564a8291fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c (880 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_viota_m_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_viota_m_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_viota_m_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_viota_m_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_viota_m_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_viota_m_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_viota_m_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_viota_m_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_viota_m_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_viota_m_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_viota
# | ...
# `---data was truncated (10240/94681) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055595f6ffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055595f6fce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055595f70062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc4c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc4c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc4c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc4c631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055595f695bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055595f695a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055595f67a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055595f329e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055595f329b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcc4c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc4c6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc4c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055595f329a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c (881 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmacc_2x8x2_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmacc_2x8x2_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmacc_2x8x2_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmacc_2x8x2_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005615e00c5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005615e00c2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005615e00c662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee0f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee0f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee0f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee0f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005615e005bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005615e005ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005615e00408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005615dfcefe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005615dfcefb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fee0f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee0f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee0f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615dfcefa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c (882 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svscale_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fscale.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fscale.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svscale_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fscale.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svscale_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fscale.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svscale_n_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, i16 noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca i16, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store i16 %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load i16, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fscale.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svscale_n_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, i16 noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca i16, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store i16 %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load i16, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fscale.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svscale_n_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, i16 noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca i16, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store i16 %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load i16, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fscale.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-bfscale" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000564ad73a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564ad73a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564ad73a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2829533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f282958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2829533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f282951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ad733dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564ad733da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564ad73228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564ad6fd1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564ad6fd1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f282951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f282951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f282951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ad6fd1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c (883 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_q_f8e4m3mf8(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf8(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_q_f8e4m3mf4(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf4(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_q_f8e4m3mf2(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf2(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_f_f_q_f8e4m3m1(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_sat_f_f_q_f8e4m3m1(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_f_f_q_f8e4m3m2(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_sat_f_f_q_f8e4m3m2(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_q_f8e4m3mf8_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf8_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, ali
# | ...
# `---data was truncated (10240/69542) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562820c55eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562820c52e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562820c5662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff9bec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff9beca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff9bec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff9bec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562820bebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562820beba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562820bd08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056282087fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056282087fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff9bec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff9bec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff9bec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056282087fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c (884 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vf_f32mf2(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vf_f32m1(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vf_f32m2(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vf_f32m4(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.f16.nx
# | ...
# `---data was truncated (10240/90875) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c6c8dd7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c6c8dd4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c6c8dd862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0be7f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0be7f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0be7f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0be7f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c6c8d6dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c6c8d6da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c6c8d528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c6c8a01e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c6c8a01b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0be7f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0be7f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0be7f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c6c8a01a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c (885 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vle32_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vle.nxv1f32.p0.i64(<vscale x 1 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x float> @llvm.riscv.vle.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vle32_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vle.nxv2f32.p0.i64(<vscale x 2 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x float> @llvm.riscv.vle.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vle32_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vle.nxv4f32.p0.i64(<vscale x 4 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.riscv.vle.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vle32_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vle.nxv8f32.p0.i64(<vscale x 8 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x float> @llvm.riscv.vle.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vle32_v_f32m8_tu(<vscale x 16 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.p0.i64(<vscale x 16 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.p0.i64(<vscale x 1 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.p0.i64(<vscale x 2 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.p0.i64(<vscale x 4 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vle32_v_i32m4_tu(<vscale x 8 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32.p0.i64(<vscale x 8 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vle32_v_i32m8_tu(<vscale x 16 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.p0.i64(<vscale x 16 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.p0.i64(<vscale x 16 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32_v_u32mf2_tu(<vscale x 1 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, 
# | ...
# `---data was truncated (10240/60217) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561964530eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056196452de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056196453162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd85cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd85cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd85cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd85cd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005619644c6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005619644c6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005619644ab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056196415ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056196415ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd85cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd85cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd85cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056196415aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c (886 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfge_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfge_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfge_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64
# | ...
# `---data was truncated (10240/66565) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559c922bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559c922b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559c922bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8be8249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8be82a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8be8249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8be8231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c92252bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559c92252a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559c922378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559c91ee6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559c91ee6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8be8232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8be82330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8be82330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c91ee6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c (887 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_u16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_u16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_u16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_u16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_u16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfclass_v_u16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfclass_v_u32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfclass_v_u32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfclass_v_u32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfclass_v_u32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8f32.i64(<vscale x 8 x i32> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8f32.i64(<vscale x 8 x i32>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfclass_v_u32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vfclass.nxv16f32.i64(<vscale x 16 x i32> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vfclass.nxv16f32.i64(<vscale x 16 x i32>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vfclass_v_u64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vfclass.nxv1f64.i64(<vscale x 1 x i64> poison, <vscale x 1 x double> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vfclass.nxv1f64.i64(<vscale x 1 x i64>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vfclass_v_u64m2(<vscale x 2 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 
# | ...
# `---data was truncated (10240/28683) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558263e92eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558263e8fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558263e9362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3609449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f36094a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3609449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3609431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558263e28bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558263e28a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558263e0d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558263abce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558263abcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3609432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f36094330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f36094330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558263abca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c (888 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrem_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrem_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrem_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrem_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrem_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrem_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrem_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrem_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrem_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/222483) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055991bb1beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055991bb18e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055991bb1c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0822733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f082278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0822733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f082271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055991bab1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055991bab1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055991ba968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055991b745e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055991b745b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f082271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f082271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f082271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055991b745a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c (889 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjn_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjn_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjn_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjn_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjn_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjn_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjn_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjn_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjn_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjn_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretur
# | ...
# `---data was truncated (10240/69677) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a850f34eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a850f31e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a850f3562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce08049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce080a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce08049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce08031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a850ecabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a850ecaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a850eaf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a850b5ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a850b5eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fce08032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce080330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce080330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a850b5ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c (890 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005619ef2e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005619ef2e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005619ef2ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa002305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa00235c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa002305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa0022ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005619ef27fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005619ef27fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005619ef2648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005619eef13e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005619eef13b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa0022eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa0022ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa0022ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005619eef13a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c (891 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vxor_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vxor_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vxor_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vxor_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vxor_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vxor_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vxor_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vxor_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vxor_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/424843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f025180eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f02517de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f02518162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4bcf133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4bcf18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4bcf133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4bcf11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f025116bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f025116a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f0250fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f024daae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f024daab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4bcf11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4bcf11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4bcf11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f024daaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c (892 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_f32mf2x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_f32m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_i32mf2x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_i32m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_u32mf2x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_u32m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_i32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_i32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_u32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8
# | ...
# `---data was truncated (10240/12059) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561e5994aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561e59947e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561e5994b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7ab7249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7ab72a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7ab7249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7ab7231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561e598e0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561e598e0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561e598c58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561e59574e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561e59574b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7ab7232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7ab72330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7ab72330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561e59574a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c (893 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f16m1x8(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f32m1x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f64m1x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558057087eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558057084e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055805708862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ac9e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ac9ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ac9e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ac9e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055805701dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055805701da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005580570028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558056cb1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558056cb1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4ac9e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ac9e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ac9e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558056cb1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c (894 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_tu(<vs
# | ...
# `---data was truncated (10240/295861) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b3b98cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b3b98c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b3b98cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6402733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f640278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6402733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f640271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b3b9861bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b3b9861a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b3b98468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b3b94f5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b3b94f5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f640271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f640271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f640271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b3b94f5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c (895 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmacc_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmacc_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmacc_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmacc_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmacc_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmacc_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmacc_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmacc_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 
# | ...
# `---data was truncated (10240/64244) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d762ed1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d762ecee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d762ed262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc81249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc812a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc81249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc81231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d762e67bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d762e67a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d762e4c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d762afbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d762afbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcc81232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc812330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc812330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d762afba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c (896 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16mf4x8(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16mf2x8(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16m1x8(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d3e93e0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d3e93dde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d3e93e162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f00b6c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f00b6ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f00b6c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f00b6c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d3e9376bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d3e9376a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d3e935b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d3e900ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d3e900ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f00b6c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f00b6c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f00b6c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d3e900aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c (897 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vv_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vv_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vf_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync
# | ...
# `---data was truncated (10240/183423) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ce7b168eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ce7b165e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ce7b16962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb4f7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb4f778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb4f7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb4f771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ce7b0febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ce7b0fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ce7b0e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ce7ad92e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ce7ad92b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb4f771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb4f771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb4f771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ce7ad92a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c (898 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_f16mf4x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_f16mf2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_f16m1x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_f16m2x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_i16mf4x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_i16mf2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_i16m1x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tu
# | ...
# `---data was truncated (10240/17844) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563e52e00eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563e52dfde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563e52e0162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb529449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb5294a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb529449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb529431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e52d96bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563e52d96a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563e52d7b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563e52a2ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563e52a2ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb529432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb5294330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb5294330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e52a2aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c (899 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecd_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecd.n32(i32 %0, i32 31, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqdecd.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecd_n_s32_1(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecd.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecd_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqdecd.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqdecd.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecd_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqdecd.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqdecd.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecd_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqdecd.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uqdecd.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecd_pat_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecd.n32(i32 %0, i32 4, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecd_pat_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqdecd.n64(i64 %0, i32 5, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecd_pat_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqdecd.n32(i32 %0, i32 6, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecd_pat_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqdecd.n64(i64 %0, i32 7, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqdecd_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.sqdecd.nxv2i64(<vscale x 2 x i64> %0, i32 31, i32 16)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sqdecd.nxv2i64(<vscale x 2 x i64>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqdecd_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.uqdecd.nxv2i64(<vscale x 2 x i64> %0, i32 31, i32 1)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uqdecd.nxv2i64(<vscale x 2 x i64>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqdecd_pat_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.sqdecd.nxv2i64(<vscale x 2 x i64> %0, i32 8, i32 16)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqdecd_pat_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.uqdecd.nxv2i64(<vscale x 2 x i64> %0, i32 9, i32 1)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560047792eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056004778fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056004779362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f02de649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f02de6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f02de649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f02de631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560047728bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560047728a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056004770d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005600473bce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005600473bcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f02de632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f02de6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f02de6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005600473bca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c (900 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_x_f_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_x_f_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_x_f_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_x_f_v_i32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_x_f_v_i32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_xu_f_v_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_xu_f_v_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_xu_f_v_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_xu_f_v_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_xu_f_v_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |  
# | ...
# `---data was truncated (10240/81507) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563ac66e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563ac66e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563ac66e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f758d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f758d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f758d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f758d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ac6679bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563ac6679a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563ac665e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563ac630de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563ac630db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f758d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f758d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f758d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ac630da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c (901 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmax_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmax_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmax_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmax_bf16_n_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmax_bf16_n_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmax_bf16_n_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055eb04ca5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eb04ca2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eb04ca662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbe6ae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbe6aea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbe6ae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbe6ae31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb04c3bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eb04c3ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eb04c208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eb048cfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eb048cfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbe6ae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbe6ae330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbe6ae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb048cfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/neon-intrinsics-constrained.c (902 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-intrinsics-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon      -disable-O0-optnone   -flax-vector-conversions=none -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vadd_f32(<2 x float> noundef %v1, <2 x float> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %v1.addr = alloca <2 x float>, align 8
# |   %v2.addr = alloca <2 x float>, align 8
# |   store <2 x float> %v1, ptr %v1.addr, align 8
# |   store <2 x float> %v2, ptr %v2.addr, align 8
# |   %0 = load <2 x float>, ptr %v1.addr, align 8
# |   %1 = load <2 x float>, ptr %v2.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %add.i = fadd <2 x float> %2, %3
# |   store <2 x float> %add.i, ptr %__ret.i, align 8
# |   %4 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vaddq_f32(<4 x float> noundef %v1, <4 x float> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %v1.addr = alloca <4 x float>, align 16
# |   %v2.addr = alloca <4 x float>, align 16
# |   store <4 x float> %v1, ptr %v1.addr, align 16
# |   store <4 x float> %v2, ptr %v2.addr, align 16
# |   %0 = load <4 x float>, ptr %v1.addr, align 16
# |   %1 = load <4 x float>, ptr %v2.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %3 = load <4 x float>, ptr %__p1.addr.i, align 16
# |   %add.i = fadd <4 x float> %2, %3
# |   store <4 x float> %add.i, ptr %__ret.i, align 16
# |   %4 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vsub_f32(<2 x float> noundef %v1, <2 x float> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %v1.addr = alloca <2 x float>, align 8
# |   %v2.addr = alloca <2 x float>, align 8
# |   store <2 x float> %v1, ptr %v1.addr, align 8
# |   store <2 x float> %v2, ptr %v2.addr, align 8
# |   %0 = load <2 x float>, ptr %v1.addr, align 8
# |   %1 = load <2 x float>, ptr %v2.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %sub.i = fsub <2 x float> %2, %3
# |   store <2 x float> %sub.i, ptr %__ret.i, align 8
# |   %4 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vsubq_f32(<4 x float> noundef %v1, <4 x float> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %v1.addr = alloca <4 x float>, align 16
# |   %v2.addr = alloca <4 x float>, align 16
# |   store <4 x float> %v1, ptr %v1.addr, align 16
# |   store <4 x float> %v2, ptr %v2.addr, align 16
# |   %0 = load <4 x float>, ptr %v1.addr, align 16
# |   %1 = load <4 x float>, ptr %v2.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %3 = load <4 x float>, ptr %__p1.addr.i, align 16
# |   %sub.i = fsub <4 x float> %2, %3
# |   store <4 x float> %sub.i, ptr %__ret.i, align 16
# |   %4 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vsubq_f64(<2 x double> noundef %v1, <2 x double> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__p1.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %v1.addr = alloca <2 x double>, align 16
# |   %v2.addr = alloca <2 x double>, align 16
# |   store <2 x double> %v1, ptr %v1.addr, align 16
# |   store <2 x double> %v2, ptr %v2.addr, align 16
# |   %0 = load <2 x double>, ptr %v1.addr, align 16
# |   %1 = load <2 x double>, ptr %v2.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   store <2 x double> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <2 x double>, ptr %__p0.addr.i, align 16
# |   %3 = load <2 x double>, ptr %__p1.addr.i, align 16
# |   %sub.i = fsub <2 x double> %2, %3
# |   store <2 x double> %sub.i, ptr %__ret.i, align 16
# |   %4 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vmul_f32(<2 x float> noundef %v1, <2 x float> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %v1.addr = alloca <2 x float>, align 8
# |   %v2.addr = alloca <2 x float>, align 8
# |   store <2 x float> %v1, ptr %v1.addr, align 8
# |   store <2 x float> %v2, ptr %v2.addr, align 8
# |   %0 = load <2 x float>, ptr %v1.addr, align 8
# |   %1 = load <2 x float>, ptr %v2.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %mul.i = fmul <2 x float> %2, %3
# |   store <2 x float> %mul.i, ptr %__ret.i, align 8
# |   %4 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmulq_f32(<4 x float> noundef %v1, <4 x float> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %v1.addr = alloca <4 x float>, align 16
# |   %v2.addr = alloca <4 x float>, align 16
# |   store <4 x float> %v1, ptr %v1.addr, align 16
# |   store <4 x float> %v2, ptr %v2.addr, align 16
# |   %0 = load <4 x float>, ptr %v1.addr, align 16
# |   %1 = load <4 x float>, ptr %v2.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %3 = load <4 x float>, ptr %__p1.addr.i, align 16
# |   %mul.i = fmul <4 x float> %2, %3
# |   store <4 x float> %mul.i, ptr %__ret.i, align 16
# |   %4 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vmulq_f64(<2 x double> noundef %v1, <2 x double> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__p1.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %v1.addr = alloca <2 x double>, align 16
# |   %v2.addr = alloca <2 x double>, align 16
# |   store <2 x double> %v1, ptr %v1.addr, align 16
# |   store <2 x double> %v2, ptr %v2.addr, align 16
# |   %0 = load <2 x double>, ptr %v1.addr, align 16
# |   %1 = load <2 x double>, ptr %v2.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   store <2 x double> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <2 x double>, ptr %__p0.addr.i, align 16
# |   %3 = load <2 x double>, ptr %__p1.addr.i, align 16
# |   %mul.i = fmul <2 x double> %2, %3
# |   store <2 x double> %mul.i, ptr %__ret.i, align 16
# |   %4 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vmla_f32(<2 x float> noundef %v1, <2 x float> noundef %v2, <2 x float> noundef %v3) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__p2.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %v1.addr = alloca <2 x float>, align 8
# |   %v2.addr = alloca <2 x float>, align 8
# |   %v3.addr = alloca <2 x float>, align 8
# |   store <2 x float> %v1, ptr %v1.addr, align 8
# |   store <2 x float> %v2, ptr %v2.addr, align 8
# |   store <2 x float> %v3, ptr %v3.addr, align 8
# |   %0 = load <2 x float>, ptr %v1.addr, align 8
# |   %1 = load <2 x float>, ptr %v2.addr, align 8
# |   %2 = load <2 x float>, ptr %v3.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   store <2 x float> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %4 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %5 = load <2 x float>, ptr %__p2.addr.i, align 8
# |   %mul.i = fmul <2 x float> %4, %5
# |   %add.i = fadd <2 x float> %3, %mul.i
# |   store <2 x float> %add.i, ptr %__ret.i, align 8
# |   %6 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmlaq_f32(<4 x float> noundef %v1, <4 x float> noundef %v2, <4 x float> noundef %v3) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__p2.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %v1.addr = alloca <4 x float>, align 16
# |   %v2.addr = alloca <4 x float>, align 16
# |   %v3.addr = alloca <4 x float>, align 16
# |   store <4 x float> %v1, ptr %v1.addr, align 16
# |   store <4 x float> %v2, ptr %v2.addr, align 16
# |   store <4 x float> %v3, ptr %v3.addr, align 16
# |   %0 = load <4 x float>, ptr %v1.addr, align 16
# |   %1 = load <4 x float>, ptr %v2.addr, align 16
# |   %2 = load <4 x float>, ptr %v3.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   store <4 x float> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %4 = load <4 x float>, ptr %__p1.addr.i, align 16
# |   %5 = load <4 x float>, ptr %__p2.addr.i, align 16
# |   %mul.i = fmul <4 x float> %4, %5
# |   %add.i = fadd <4 x float> %3, %mul.i
# |   store <4 x float> %add.i, ptr %__ret.i, align 16
# |   %6 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %6
# | }
# | 
# | ; F
# | ...
# `---data was truncated (10240/91378) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055c2a4642eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c2a463fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c2a464362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f831b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f831b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f831b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f831b91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c2a45d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c2a45d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c2a45bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c2a426ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c2a426cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f831b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f831b91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f831b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c2a426ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c (903 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f16m1x3(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f16m2x3(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f32m1x3(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f32m2x3(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f64m1x3(ptr noundef %base, <vscale x 1 x i64> %binde
# | ...
# `---data was truncated (10240/94227) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557417648eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557417645e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055741764962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7083733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f708378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7083733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f708371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005574175debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005574175dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005574175c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557417272e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557417272b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f708371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f708371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f708371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557417272a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c (904 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vv_f32mf2(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vf_f32mf2(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wv_f32mf2(<vscale x 1 x float> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wf_f32mf2(<vscale x 1 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vv_f32m1(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vf_f32m1(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wv_f32m1(<vscale x 2 x float> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wf_f32m1(<vscale x 2 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwadd_vv_f32m2(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwadd_vf_f32m2(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2
# | ...
# `---data was truncated (10240/151911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559413b19eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559413b16e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559413b1a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1824305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f182435c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1824305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f18242ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559413aafbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559413aafa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559413a948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559413743e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559413743b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f18242eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f18242ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f18242ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559413743a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c (905 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16m1x2(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16m2x2(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16m4x2(ptr noundef %base, <vscale x 16 x i16> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f32m1x2(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f32m2x2(ptr noundef %base, <vscale x 4 x i16
# | ...
# `---data was truncated (10240/129182) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e950e67eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e950e64e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e950e6862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa938049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa9380a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa938049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa938031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e950dfdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e950dfda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e950de28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e950a91e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e950a91b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa938032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa9380330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa9380330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e950a91a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c (906 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst3_s8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data.coerce0, <vscale x 16 x i8> %data.coerce1, <vscale x 16 x i8> %data.coerce2) #0 {
# | entry:
# |   %data = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %data.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %data.coerce2, 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, ptr %data, align 16
# |   %data1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %data1, ptr %data.addr, align 16
# |   %3 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %4 = load ptr, ptr %base.addr, align 8
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %data.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 2
# |   call void @llvm.aarch64.sve.st3.nxv16i8.p0(<vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8, <vscale x 16 x i1> %3, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st3.nxv16i8.p0(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst3_s16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data.coerce0, <vscale x 8 x i16> %data.coerce1, <vscale x 8 x i16> %data.coerce2) #0 {
# | entry:
# |   %data = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %data.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %data.coerce2, 2
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, ptr %data, align 16
# |   %data1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %data1, ptr %data.addr, align 16
# |   %3 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %4 = load ptr, ptr %base.addr, align 8
# |   %5 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %data.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 1
# |   %8 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 2
# |   %9 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %3)
# |   call void @llvm.aarch64.sve.st3.nxv8i16.p0(<vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %8, <vscale x 8 x i1> %9, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st3.nxv8i16.p0(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst3_s32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data.coerce0, <vscale x 4 x i32> %data.coerce1, <vscale x 4 x i32> %data.coerce2) #0 {
# | entry:
# |   %data = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %data.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %data.coerce2, 2
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, ptr %data, align 16
# |   %data1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %data1, ptr %data.addr, align 16
# |   %3 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %4 = load ptr, ptr %base.addr, align 8
# |   %5 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %data.addr, align 16
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 0
# |   %7 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 1
# |   %8 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 2
# |   %9 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %3)
# |   call void @llvm.aarch64.sve.st3.nxv4i32.p0(<vscale x 4 x i32> %6, <vscale x 4 x i32> %7, <vscale x 4 x i32> %8, <vscale x 4 x i1> %9, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st3.nxv4i32.p0(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst3_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data.coerce0, <vscale x 2 x i64> %data.coerce1, <vscale x 2 x i64> %data.coerce2) #0 {
# | entry:
# |   %data = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %data.coerce1, 1
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, <vscale x 2 x i64> %data.coerce2, 2
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %2, ptr %data, align 16
# |   %data1 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %data1, ptr %data.addr, align 16
# |   %3 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %4 = load ptr, ptr %base.addr, align 8
# |   %5 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %data.addr, align 16
# |   %6 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5, 0
# |   %7 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5, 1
# |   %8 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5, 2
# |   %9 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %3)
# |   call void @llvm.aarch64.sve.st3.nxv2i64.p0(<vscale x 2 x i64> %6, <vscale x 2 x i64> %7, <vscale x 2 x i64> %8, <vscale x 2 x i1> %9, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st3.nxv2i64.p0(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst3_u8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data.coerce0, <vscale x 16 x i8> %data.coerce1, <vscale x 16 x i8> %data.coerce2) #0 {
# | entry:
# |   %data = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = al
# | ...
# `---data was truncated (10240/58378) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005642f0b8deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005642f0b8ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005642f0b8e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7a7d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7a7d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7a7d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7a7d71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005642f0b23bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005642f0b23a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005642f0b088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005642f07b7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005642f07b7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7a7d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7a7d71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7a7d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005642f07b7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c (907 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vid_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8.i64(<vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8.i64(<vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vid_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8.i64(<vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8.i64(<vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vid_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8.i64(<vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8.i64(<vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vid_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8.i64(<vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8.i64(<vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vid_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8.i64(<vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8.i64(<vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vid_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8.i64(<vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8.i64(<vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vid_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vid.nxv64i8.i64(<vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vid.nxv64i8.i64(<vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vid_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16.i64(<vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16.i64(<vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vid_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16.i64(<vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16.i64(<vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vid_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16.i64(<vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16.i64(<vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vid_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16.i64(<vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16.i64(<vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vid_v_u16m4_tu(<vscale x 16 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16.i64(<vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16.i64(<vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vid_v_u16m8_tu(<vscale x 32 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16.i64(<vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16.i64(<vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vid_v_u32mf2_tu(<vscale x 1 x i32> %maske
# | ...
# `---data was truncated (10240/75397) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559e6f2e8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559e6f2e5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559e6f2e962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5e19133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5e1918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5e19133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5e1911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e6f27ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559e6f27ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559e6f2638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559e6ef12e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559e6ef12b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5e1911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5e1911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5e1911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e6ef12a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c (908 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgtu_vv_u8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgtu_vx_u8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgtu_vv_u8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgtu_vx_u8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgtu_vv_u8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgtu_vx_u8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgtu_vv_u8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgtu_vx_u8m1_b8(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgtu_vv_u8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgtu_vx_u8m2_b4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsgtu_vv_u8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.nxv32i8.n
# | ...
# `---data was truncated (10240/95347) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ab32ea2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ab32e9fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ab32ea362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcfea333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcfea38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcfea333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcfea31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ab32e38bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ab32e38a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ab32e1d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ab32acce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ab32accb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcfea31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcfea31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcfea31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ab32acca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c (909 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e6dfc29eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e6dfc26e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e6dfc2a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f038f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f038f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f038f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f038f031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e6dfbbfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e6dfbbfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e6dfba48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e6df853e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e6df853b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f038f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f038f0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f038f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e6df853a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c (910 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei32_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei32_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei32_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei32_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei32_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei32_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei32_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei32_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei32_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, <vsc
# | ...
# `---data was truncated (10240/255546) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558ff2f02eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558ff2effe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558ff2f0362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa122249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa1222a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa122249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa122231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558ff2e98bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558ff2e98a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558ff2e7d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558ff2b2ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558ff2b2cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa122232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa1222330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa1222330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558ff2b2ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c (911 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_i64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_u64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_f64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_i64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_u64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vsca
# | ...
# `---data was truncated (10240/20895) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562be22a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562be22a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562be22a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7faeb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7faeb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7faeb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7faeb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562be223dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562be223da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562be22228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562be1ed1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562be1ed1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7faeb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7faeb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7faeb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562be1ed1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c (912 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llv
# | ...
# `---data was truncated (10240/101576) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d132e3eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d132e3be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d132e3f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fda89333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fda8938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fda89333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fda8931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d132dd4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d132dd4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d132db98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d132a68e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d132a68b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fda8931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fda8931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fda8931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d132a68a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c (913 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005650a478deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005650a478ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005650a478e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5e47733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5e4778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5e47733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5e4771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005650a4723bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005650a4723a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005650a47088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005650a43b7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005650a43b7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5e4771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5e4771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5e4771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005650a43b7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c (914 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f16m1x7(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f32m1x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f64m1x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei16_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b93fd3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563b93fd0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563b93fd462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb1da1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb1da725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb1da1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb1da03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b93f69bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563b93f69a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563b93f4e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563b93bfde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563b93bfdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feb1da04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb1da050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb1da050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b93bfda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c (915 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccus_vx_i16mf4(<vscale x 1 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccus_vx_i16mf2(<vscale x 2 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccus_vx_i16m1(<vscale x 4 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccus_vx_i16m2(<vscale x 8 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccus_vx_i16m4(<vscale x 16 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16>, i8, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwmaccus_vx_i16m8(<vscale x 32 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 32 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16>, i8, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwmaccus_vx_i32mf2(<vscale x 1 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32>, i16, <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwmaccus_vx_i32m1(<vscale x 2 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32>, i16, <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwmaccus_vx_i32m2(<vscale x 4 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 =
# | ...
# `---data was truncated (10240/39218) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564d19016eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564d19013e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564d1901762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff4da333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff4da38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff4da333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff4da31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d18facbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564d18faca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564d18f918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564d18c40e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564d18c40b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff4da31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff4da31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff4da31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d18c40a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c (916 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnj_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnj_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnj_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnj_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnj_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnj_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnj_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnj_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnj_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> 
# | ...
# `---data was truncated (10240/157475) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e01cf5aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e01cf57e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e01cf5b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd829049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd8290a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd829049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd829031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e01cef0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e01cef0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e01ced58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e01cb84e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e01cb84b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd829032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd8290330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd8290330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e01cb84a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c (917 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_i64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_i64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_u64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_u64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056313c79feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056313c79ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056313c7a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4780333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f478038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4780333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f478031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056313c735bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056313c735a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056313c71a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056313c3c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056313c3c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f478031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f478031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f478031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056313c3c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c (918 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei64_v_i8mf8x5
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556a532c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556a532bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556a532c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8f96733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8f9678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8f96733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8f9671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556a53256bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556a53256a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556a5323b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556a52eeae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556a52eeab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8f9671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8f9671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8f9671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556a52eeaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c (919 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti4_lane_zt_u8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti4_lane_zt_s8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti4_lane_zt_mf8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svluti4_lane_zt_u16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8i16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svluti4_lane_zt_s16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svluti4_lane_zt_f16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8f16(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8f16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svluti4_lane_zt_bf16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8bf16(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8bf16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svluti4_lane_zt_u32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4i32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svluti4_lane_zt_s32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svluti4_lane_zt_f32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4f32(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4f32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000561c40e8ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561c40e89e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561c40e8d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f695de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f695dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f695de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f695de31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561c40e22bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561c40e22a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561c40e078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561c40ab6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561c40ab6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f695de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f695de330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f695de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561c40ab6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c (920 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdivu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdivu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdivu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdivu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdivu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdivu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdivu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdivu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdivu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op
# | ...
# `---data was truncated (10240/222917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558182c26eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558182c23e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558182c2762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efec1533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efec158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efec1533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efec151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558182bbcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558182bbca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558182ba18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558182850e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558182850b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efec151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efec151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efec151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558182850a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp (921 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2    -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @in_zt0() #0 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @out_zt0() #1 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @inout_zt0() #2 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @preserves_zt0() #3 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @new_zt0() #4 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @in_za_zt0() #5 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @out_za_zt0() #6 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @inout_za_zt0() #7 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @preserves_za_zt0() #8 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @new_za_zt0() #9 {
# | entry:
# |   ret void
# | }
# | 
# | attributes #0 = { mustprogress noinline nounwind "aarch64_in_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { mustprogress noinline nounwind "aarch64_out_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #2 = { mustprogress noinline nounwind "aarch64_inout_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #3 = { mustprogress noinline nounwind "aarch64_preserves_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #4 = { mustprogress noinline nounwind "aarch64_new_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #5 = { mustprogress noinline nounwind "aarch64_in_za" "aarch64_in_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #6 = { mustprogress noinline nounwind "aarch64_out_za" "aarch64_out_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #7 = { mustprogress noinline nounwind "aarch64_inout_za" "aarch64_inout_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #8 = { mustprogress noinline nounwind "aarch64_preserves_za" "aarch64_preserves_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #9 = { mustprogress noinline nounwind "aarch64_new_za" "aarch64_new_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056275259beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562752598e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056275259c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4947e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4947e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4947e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4947e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562752531bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562752531a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005627525168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005627521c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005627521c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4947e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4947e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4947e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005627521c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline
# |  #0 0x0000562bcef48eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562bcef45e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562bcef4962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc1c8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc1c878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc1c8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc1c871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562bceedebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562bceedea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562bceec38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562bceb72e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562bceb72b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc1c871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc1c871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc1c871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562bceb72a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/neon/fused-multiply.c (922 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/fused-multiply.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vfma_f32(<2 x float> noundef %a, <2 x float> noundef %b, <2 x float> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__p2.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %c.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   store <2 x float> %c, ptr %c.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   %2 = load <2 x float>, ptr %c.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   store <2 x float> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %6 = bitcast <8 x i8> %3 to <2 x float>
# |   %7 = bitcast <8 x i8> %4 to <2 x float>
# |   %8 = bitcast <8 x i8> %5 to <2 x float>
# |   %9 = call <2 x float> @llvm.fma.v2f32(<2 x float> %7, <2 x float> %8, <2 x float> %6)
# |   store <2 x float> %9, ptr %ref.tmp.i, align 8
# |   %10 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %10, ptr %__ret.i, align 8
# |   %11 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vfma_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__p1.addr.i = alloca <1 x double>, align 8
# |   %__p2.addr.i = alloca <1 x double>, align 8
# |   %__ret.i = alloca <1 x double>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %c.addr = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   store <1 x double> %c, ptr %c.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   %1 = load <1 x double>, ptr %b.addr, align 8
# |   %2 = load <1 x double>, ptr %c.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   store <1 x double> %1, ptr %__p1.addr.i, align 8
# |   store <1 x double> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %6 = bitcast <8 x i8> %3 to <1 x double>
# |   %7 = bitcast <8 x i8> %4 to <1 x double>
# |   %8 = bitcast <8 x i8> %5 to <1 x double>
# |   %9 = call <1 x double> @llvm.fma.v1f64(<1 x double> %7, <1 x double> %8, <1 x double> %6)
# |   store <1 x double> %9, ptr %ref.tmp.i, align 8
# |   %10 = load <1 x double>, ptr %ref.tmp.i, align 8
# |   store <1 x double> %10, ptr %__ret.i, align 8
# |   %11 = load <1 x double>, ptr %__ret.i, align 8
# |   ret <1 x double> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vfmaq_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__p2.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   %c.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   store <4 x float> %c, ptr %c.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   %2 = load <4 x float>, ptr %c.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   store <4 x float> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %6 = bitcast <16 x i8> %3 to <4 x float>
# |   %7 = bitcast <16 x i8> %4 to <4 x float>
# |   %8 = bitcast <16 x i8> %5 to <4 x float>
# |   %9 = call <4 x float> @llvm.fma.v4f32(<4 x float> %7, <4 x float> %8, <4 x float> %6)
# |   store <4 x float> %9, ptr %ref.tmp.i, align 16
# |   %10 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %10, ptr %__ret.i, align 16
# |   %11 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vfmaq_f64(<2 x double> noundef %a, <2 x double> noundef %b, <2 x double> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__p1.addr.i = alloca <2 x double>, align 16
# |   %__p2.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   %b.addr = alloca <2 x double>, align 16
# |   %c.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   store <2 x double> %c, ptr %c.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   %1 = load <2 x double>, ptr %b.addr, align 16
# |   %2 = load <2 x double>, ptr %c.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   store <2 x double> %1, ptr %__p1.addr.i, align 16
# |   store <2 x double> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %6 = bitcast <16 x i8> %3 to <2 x double>
# |   %7 = bitcast <16 x i8> %4 to <2 x double>
# |   %8 = bitcast <16 x i8> %5 to <2 x double>
# |   %9 = call <2 x double> @llvm.fma.v2f64(<2 x double> %7, <2 x double> %8, <2 x double> %6)
# |   store <2 x double> %9, ptr %ref.tmp.i, align 16
# |   %10 = load <2 x double>, ptr %ref.tmp.i, align 16
# |   store <2 x double> %10, ptr %__ret.i, align 16
# |   %11 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vfma_lane_f32(<2 x float> noundef %a, <2 x float> noundef %b, <2 x float> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %v.addr = alloca <2 x float>, align 8
# |   %__ret = alloca <2 x float>, align 8
# |   %__s0 = alloca <2 x float>, align 8
# |   %__s1 = alloca <2 x float>, align 8
# |   %__s2 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   store <2 x float> %v, ptr %v.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__s0, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %1, ptr %__s1, align 8
# |   %2 = load <2 x float>, ptr %v.addr, align 8
# |   store <2 x float> %2, ptr %__s2, align 8
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <8 x i8>, ptr %__s2, align 8
# |   %6 = bitcast <8 x i8> %5 to <2 x float>
# |   %lane = shufflevector <2 x float> %6, <2 x float> %6, <2 x i32> <i32 1, i32 1>
# |   %fmla = bitcast <8 x i8> %4 to <2 x float>
# |   %fmla1 = bitcast <8 x i8> %3 to <2 x float>
# |   %fmla2 = call <2 x float> @llvm.fma.v2f32(<2 x float> %fmla, <2 x float> %lane, <2 x float> %fmla1)
# |   store <2 x float> %fmla2, ptr %ref.tmp, align 8
# |   %7 = load <2 x float>, ptr %ref.tmp, align 8
# |   store <2 x float> %7, ptr %__ret, align 8
# |   %8 = load <2 x float>, ptr %__ret, align 8
# |   store <2 x float> %8, ptr %tmp, align 8
# |   %9 = load <2 x float>, ptr %tmp, align 8
# |   ret <2 x float> %9
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vfma_lane_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <1 x double>, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %v.addr = alloca <1 x double>, align 8
# |   %__ret = alloca <1 x double>, align 8
# |   %__s0 = alloca <1 x double>, align 8
# |   %__s1 = alloca <1 x double>, align 8
# |   %__s2 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   store <1 x double> %v, ptr %v.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__s0, align 8
# |   %1 = load <1 x double>, ptr %b.addr, align 8
# |   store <1 x double> %1, ptr %__s1, align 8
# |   %2 = load <1 x double>, ptr %v.addr, align 8
# |   store <1 x double> %2, ptr %__s2, align 8
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <8 x i8>, ptr %__s2, align 8
# |   %6 = bitcast <8 x i8> %5 to <1 x double>
# |   %lane = shufflevector <1 x double> %6, <1 x double> %6, <1 x i32> zeroinitializer
# |   %fmla = bitcast <8 x i8> %4 to <1 x double>
# |   %fmla1 = bitcast <8 x i8> %3 to <1 x double>
# |   %fmla2 = call <1 x double> @llvm.fma.v1f64(<1 x double> %fmla, <1 x double> %lane, <1 x double> %fmla1)
# |   store <1 x double> %fmla2, ptr %ref.tmp, align 8
# |   %7 = load <1 x double>, ptr %ref.tmp, align 8
# |   store <1 x double> %7, ptr %__ret, align 8
# |   %8 = load <1 x double>, ptr %__ret, align 8
# |   store <1 x double> %8, ptr %tmp, align 8
# |   %9 = load <1 x double>, ptr %tmp, align 8
# |   ret <1 x double> %9
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <1 x double> @llvm.fma.v1f64(<1 x double>, <1 x double>, <1 x double>) #1
# | 
# | ; Functio
# | ...
# `---data was truncated (10240/80179) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000562cbf1aeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562cbf1abe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562cbf1af62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5800449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f58004a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5800449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5800431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562cbf144bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562cbf144a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562cbf1298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562cbedd8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562cbedd8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5800432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f58004330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f58004330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562cbedd8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c (923 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpfirst_b(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.pfirst.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.pfirst.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055fd2e336eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fd2e333e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fd2e33762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7b40105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7b4015c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7b40105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7b400ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd2e2ccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fd2e2cca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fd2e2b18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fd2df60e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fd2df60b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7b400eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7b400ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7b400ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd2df60a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c (924 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdiv_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdiv_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdiv_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdiv_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdiv_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdiv_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdiv_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdiv_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdiv_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vdiv.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vdiv.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdiv_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vdiv.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vdiv.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vdiv_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/97639) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005589d7559eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005589d7556e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005589d755a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ebf049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ebf0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ebf049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ebf031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589d74efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005589d74efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005589d74d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005589d7183e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005589d7183b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3ebf032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ebf0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ebf0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005589d7183a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c (925 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei32_v_i8mf8x8
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d34ccc1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d34ccbee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d34ccc262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0ec1e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0ec1ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0ec1e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0ec1e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d34cc57bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d34cc57a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d34cc3c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d34c8ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d34c8ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0ec1e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0ec1e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0ec1e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d34c8eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c (926 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_f16mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_f16mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_f16m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_i16mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_i16mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_i16m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_u16mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_u16mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_u16m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, pt
# | ...
# `---data was truncated (10240/24016) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b91d809eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b91d806e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b91d80a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdb5ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdb5ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdb5ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdb5ff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b91d79fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b91d79fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b91d7848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b91d433e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b91d433b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdb5ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdb5ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdb5ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b91d433a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c (927 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_v
# | ...
# `---data was truncated (10240/253156) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564fbce2ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564fbce29e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564fbce2d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe13d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe13d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe13d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe13d831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564fbcdc2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564fbcdc2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564fbcda78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564fbca56e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564fbca56b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe13d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe13d8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe13d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564fbca56a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c (928 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei32_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei32_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   
# | ...
# `---data was truncated (10240/25616) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de03aaaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055de03aa7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055de03aab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc18c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc18ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc18c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc18c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de03a40bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055de03a40a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055de03a258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055de036d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055de036d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efc18c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc18c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc18c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de036d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c (929 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_bf16mf4x5(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_bf16mf2x5(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_bf16m1x5(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005607fe400eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005607fe3fde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005607fe40162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb5cb649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb5cb6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb5cb649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb5cb631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607fe396bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005607fe396a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005607fe37b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005607fe02ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005607fe02ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb5cb632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb5cb6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb5cb6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607fe02aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c (930 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmul_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmul_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmul_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmul_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmul_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmul_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmul_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmul_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmul_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmul.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmul.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmul_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmul.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, ha
# | ...
# `---data was truncated (10240/125649) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560fa3d54eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560fa3d51e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560fa3d5562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1273049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f12730a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1273049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1273031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560fa3ceabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560fa3ceaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560fa3ccf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560fa397ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560fa397eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1273032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f12730330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f12730330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560fa397ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c (931 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjx_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjx_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjx_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjx_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjx_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjx_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjx_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjx_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjx_vv_f16m4_tu(<vscale x 16 x half> %maske
# | ...
# `---data was truncated (10240/157777) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055af8f25beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055af8f258e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055af8f25c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f72aaa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f72aaaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f72aaa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f72aaa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055af8f1f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055af8f1f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055af8f1d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055af8ee85e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055af8ee85b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f72aaa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f72aaa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f72aaa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055af8ee85a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c (932 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16mf4x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16mf2x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16m1x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cfd8a3beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cfd8a38e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cfd8a3c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f409d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f409d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f409d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f409d431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cfd89d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cfd89d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cfd89b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cfd8665e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cfd8665b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f409d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f409d4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f409d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cfd8665a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c (933 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsbc_vvm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsbc_vxm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsbc_vvm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsbc_vxm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsbc_vvm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsbc_vxm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsbc_vvm_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 8 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <
# | ...
# `---data was truncated (10240/117389) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d563f1beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d563f18e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d563f1c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcb12449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcb124a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcb12449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcb12431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d563eb1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d563eb1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d563e968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d563b45e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d563b45b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcb12432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcb124330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcb124330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d563b45a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c (934 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasubu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasubu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasubu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasubu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasubu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasubu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasubu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasubu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasubu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.ad
# | ...
# `---data was truncated (10240/225647) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005563efbeceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005563efbe9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005563efbed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fea37849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fea378a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fea37849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fea37831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005563efb82bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005563efb82a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005563efb678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005563ef816e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005563ef816b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fea37832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fea378330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fea378330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005563ef816a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c (935 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsac_vv_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsac_vx_i8mf8_tu(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsac_vv_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsac_vx_i8mf4_tu(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsac_vv_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsac_vx_i8mf2_tu(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsac_vv_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsac_vx_i8m1_tu(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnmsac_vv_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   
# | ...
# `---data was truncated (10240/415319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b8b6b1aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b8b6b17e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b8b6b1b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7605249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f76052a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7605249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7605231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b8b6ab0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b8b6ab0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b8b6a958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b8b6744e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b8b6744b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7605232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f76052330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f76052330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b8b6744a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c (936 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei32_v_i8mf8x6
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561c2211feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561c2211ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561c2212062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7921049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f79210a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7921049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7921031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561c220b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561c220b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561c2209a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561c21d49e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561c21d49b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7921032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f79210330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f79210330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561c21d49a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c (937 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei64_v_i8mf8x6
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005572f8072eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005572f806fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005572f807362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff209533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff20958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff209533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff20951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005572f8008bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005572f8008a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005572f7fed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005572f7c9ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005572f7c9cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff20951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff20951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff20951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005572f7c9ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c (938 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_i64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_u64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_f64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_i64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_u64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple
# | ...
# `---data was truncated (10240/20903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562144f2feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562144f2ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562144f3062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2041905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f204195c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2041905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f20418ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562144ec5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562144ec5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562144eaa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562144b59e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562144b59b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f20418eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f20418ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f20418ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562144b59a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c (939 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsll_vv_u16mf4(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsll_vx_u16mf4(<vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsll_vv_u16mf2(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsll_vx_u16mf2(<vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsll_vv_u16m1(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsll_vx_u16m1(<vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vwsll_vv_u16m2(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vwsll_vx_u16m2(<vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vwsll_vv_u16m4(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vwsll_vx_u16m4(<vscale x 16 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.i64.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.i64.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vsca
# | ...
# `---data was truncated (10240/68133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005617e5539eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005617e5536e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005617e553a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff77ee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff77eea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff77ee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff77ee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005617e54cfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005617e54cfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005617e54b48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005617e5163e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005617e5163b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff77ee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff77ee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff77ee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005617e5163a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c (940 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_bf16m1x
# | ...
# `---data was truncated (10240/25695) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559cfcd7feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559cfcd7ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559cfcd8062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efd85133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efd8518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efd85133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efd8511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559cfcd15bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559cfcd15a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559cfccfa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559cfc9a9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559cfc9a9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efd8511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efd8511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efd8511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559cfc9a9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c (941 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpuo_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.fcmpuo.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.fcmpuo.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpuo_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.fcmpuo.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.fcmpuo.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpuo_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.fcmpuo.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.fcmpuo.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpuo_n_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, half noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca half, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store half %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x half> poison, half %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x half> %.splatinsert, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.fcmpuo.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %.splat)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpuo_n_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, float noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca float, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store float %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 4 x float> poison, float %2, i64 0
# |   %.splat = shufflevector <vscale x 4 x float> %.splatinsert, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.fcmpuo.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %.splat)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpuo_n_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, double noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca double, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store double %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load double, ptr %op2.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 2 x double> poison, double %2, i64 0
# |   %.splat = shufflevector <vscale x 2 x double> %.splatinsert, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.fcmpuo.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %.splat)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c6894b2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c6894afe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c6894b362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe329333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe32938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe329333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe32931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c689448bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c689448a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c68942d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c6890dce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c6890dcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe32931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe32931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe32931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c6890dca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c (942 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055829b402eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055829b3ffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055829b40362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa810d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa810d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa810d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa810ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055829b398bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055829b398a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055829b37d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055829b02ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055829b02cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa810ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa810cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa810cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055829b02ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c (943 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f16m1x4(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f16m2x4(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f32m1x4(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f32m2x4(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f64m1x4(ptr noundef %base, <vscale x 1 x i16> %binde
# | ...
# `---data was truncated (10240/99754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556b3c9daeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556b3c9d7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556b3c9db62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd74f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd74f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd74f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd74eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b3c970bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556b3c970a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556b3c9558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556b3c604e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556b3c604b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbd74eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd74eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd74eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b3c604a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c (944 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8_v_i8mf8x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8_v_i8mf4x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8_v_i8mf2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8_v_i8m1x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8_v_i8m2x2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8_v_i8m4x2_m(<vscale x 32 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv32i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 32 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv32i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8_v_u8mf8x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8_v_u8mf4x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8_v_u8mf2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align
# | ...
# `---data was truncated (10240/14145) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d174550eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d17454de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d17455162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc9eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc9eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc9eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc9eb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d1744e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d1744e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d1744cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d17417ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d17417ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcc9eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc9eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc9eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d17417aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c (945 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005620765ddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005620765dae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005620765de62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2ab4d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2ab4d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2ab4d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2ab4d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562076573bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562076573a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005620765588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562076207e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562076207b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2ab4d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2ab4d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2ab4d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562076207a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c (946 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16mf4(ptr noundef %base, <vscale x 1 x i8> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16mf2(ptr noundef %base, <vscale x 2 x i8> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16m1(ptr noundef %base, <vscale x 4 x i8> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16m2(ptr noundef %base, <vscale x 8 x i8> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16m4(ptr noundef %base, <vscale x 16 x i8> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16m8(ptr noundef %base, <vscale x 32 x i8> %bindex, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> %2, ptr %0, <vscale x 32 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f32mf2(ptr noundef %base, <vscale x 1 x i8> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f32m1(ptr noundef %base, <vscale x 2 x i8> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f32m2(ptr noundef %base, <vscale x 4 x i8> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretur
# | ...
# `---data was truncated (10240/136005) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005629de98feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005629de98ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005629de99062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe5cf533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe5cf58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe5cf533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe5cf51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005629de925bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005629de925a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005629de90a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005629de5b9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005629de5b9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe5cf51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe5cf51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe5cf51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005629de5b9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c (947 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulsu_vv_i16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulsu_vx_i16mf4(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulsu_vv_i16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulsu_vx_i16mf2(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulsu_vv_i16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulsu_vx_i16m1(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulsu_vv_i16m2(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulsu_vx_i16m2(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulsu_vv_i16m4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulsu_vx_i16m4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) 
# | ...
# `---data was truncated (10240/68437) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005560d169beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005560d1698e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005560d169c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7257849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f72578a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7257849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7257831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005560d1631bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005560d1631a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005560d16168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005560d12c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005560d12c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7257832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f72578330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f72578330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005560d12c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c (948 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsltu_vv_u8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsltu_vx_u8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsltu_vv_u8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsltu_vx_u8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsltu_vv_u8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsltu_vx_u8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsltu_vv_u8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsltu_vx_u8m1_b8(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsltu_vv_u8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsltu_vx_u8m2_b4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsltu_vv_u8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsltu.n
# | ...
# `---data was truncated (10240/95355) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cda4387eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cda4384e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cda438862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f071d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f071d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f071d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f071d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cda431dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cda431da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cda43028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cda3fb1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cda3fb1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f071d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f071d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f071d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cda3fb1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvp-intrinsics.c (949 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvp-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +experimental-p    -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c --check-prefixes=CHECK,RV32
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +experimental-p -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_cls_32(i32 noundef %a) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   %1 = load i32, ptr %__rs1.addr.i, align 4
# |   %isneg.i = icmp slt i32 %1, 0
# |   %not.i = xor i32 %1, -1
# |   %2 = select i1 %isneg.i, i32 %not.i, i32 %1
# |   %3 = call i32 @llvm.ctlz.i32(i32 %2, i1 false)
# |   %4 = sub nuw i32 %3, 1
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_rev_32(i32 noundef %a) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   %1 = load i32, ptr %__rs1.addr.i, align 4
# |   %2 = call i32 @llvm.bitreverse.i32(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_slx_32(i32 noundef %rd, i32 noundef %rs1, i32 noundef %shamt) #0 {
# | entry:
# |   %__rd.addr.i = alloca i32, align 4
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__shamt.addr.i = alloca i32, align 4
# |   %rd.addr = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %shamt.addr = alloca i32, align 4
# |   store i32 %rd, ptr %rd.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %shamt, ptr %shamt.addr, align 4
# |   %0 = load i32, ptr %rd.addr, align 4
# |   %1 = load i32, ptr %rs1.addr, align 4
# |   %2 = load i32, ptr %shamt.addr, align 4
# |   store i32 %0, ptr %__rd.addr.i, align 4
# |   store i32 %1, ptr %__rs1.addr.i, align 4
# |   store i32 %2, ptr %__shamt.addr.i, align 4
# |   %3 = load i32, ptr %__rd.addr.i, align 4
# |   %4 = load i32, ptr %__rs1.addr.i, align 4
# |   %5 = load i32, ptr %__shamt.addr.i, align 4
# |   %6 = call i32 @llvm.fshl.i32(i32 %3, i32 %4, i32 %5)
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_srx_32(i32 noundef %rd, i32 noundef %rs1, i32 noundef %shamt) #0 {
# | entry:
# |   %__rd.addr.i = alloca i32, align 4
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__shamt.addr.i = alloca i32, align 4
# |   %rd.addr = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %shamt.addr = alloca i32, align 4
# |   store i32 %rd, ptr %rd.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %shamt, ptr %shamt.addr, align 4
# |   %0 = load i32, ptr %rd.addr, align 4
# |   %1 = load i32, ptr %rs1.addr, align 4
# |   %2 = load i32, ptr %shamt.addr, align 4
# |   store i32 %0, ptr %__rd.addr.i, align 4
# |   store i32 %1, ptr %__rs1.addr.i, align 4
# |   store i32 %2, ptr %__shamt.addr.i, align 4
# |   %3 = load i32, ptr %__rs1.addr.i, align 4
# |   %4 = load i32, ptr %__rd.addr.i, align 4
# |   %5 = load i32, ptr %__shamt.addr.i, align 4
# |   %6 = call i32 @llvm.fshr.i32(i32 %3, i32 %4, i32 %5)
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_aadd_i32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.aadd.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_aaddu_u32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.aaddu.u32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_asub_i32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.asub.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_asubu_u32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.asubu.u32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_sadd_i32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %elt.sat.i = call i32 @llvm.sadd.sat.i32(i32 %2, i32 %3)
# |   ret i32 %elt.sat.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_saddu_u32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %elt.sat.i = call i32 @llvm.uadd.sat.i32(i32 %2, i32 %3)
# |   ret i32 %elt.sat.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ssub_i32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %elt.sat.i = call i32 @llvm.ssub.sat.i32(i32 %2, i32 %3)
# |   ret i32 %elt.sat.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ssubu_u32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %elt.sat.i = call i32 @llvm.usub.sat.i32(i32 %2, i32 %3)
# |   ret i32 %elt.sat.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_abs_u32(i32 noundef %a) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   %1 = load i32, ptr %__rs1.addr.i, align 4
# |   %elt.abs.i = call i32 @llvm.abs.i32(i32 %1, i1 false)
# |   ret i32 %elt.abs.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_sati_i32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call i32 @llvm.riscv.sati.i32(i32 %0, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sati.i32(i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_usati_u32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call i32 @llvm.riscv.usati.i32(i32 %0, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.usati.i32(i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_mulh_i32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %4 = call i32 @llvm.smulh.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function At
# | ...
# `---data was truncated (10240/1228637) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine
# |  #0 0x000055920618aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559206187e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055920618b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f70f0933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f70f098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f70f0933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f70f091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559206120bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559206120a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005592061058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559205db4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559205db4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f70f091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f70f091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f70f091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559205db4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c --check-prefixes=CHECK,RV32
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c --check-prefixes=CHECK,RV32
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c (950 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vf_f32mf2(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vf_f32m1(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vf_f32m2(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vf_f32m4(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x fl
# | ...
# `---data was truncated (10240/90693) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056080252feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056080252ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056080253062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2eb7449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2eb74a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2eb7449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2eb7431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005608024c5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005608024c5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005608024aa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560802159e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560802159b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2eb7432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2eb74330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2eb74330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560802159a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c (951 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste64_f64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.sf.vste64.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste64_i64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste64_u64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056540632eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056540632be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056540632f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc79ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc79ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc79ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc79ed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005654062c4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005654062c4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005654062a98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565405f58e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565405f58b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc79ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc79ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc79ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565405f58a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c (952 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmacc_vv_i8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmacc_vx_i8mf8(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmacc_vv_i8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmacc_vx_i8mf4(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmacc_vv_i8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmacc_vx_i8mf2(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmacc_vv_i8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmacc_vx_i8m1(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmacc_vv_i8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, a
# | ...
# `---data was truncated (10240/207757) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ce6c165eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ce6c162e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ce6c16662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1be5705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1be575c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1be5705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1be56ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ce6c0fbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ce6c0fba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ce6c0e08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ce6bd8fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ce6bd8fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1be56eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1be56ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1be56ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ce6bd8fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c (953 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgatherei16_vv_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgatherei16_vv_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgatherei16_vv_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vrgatherei16_vv_bf16m8(<vscale x 32 x bfloat> %vs2, <vscale x 32 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgatherei16_vv_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x
# | ...
# `---data was truncated (10240/15375) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb8fe98eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fb8fe95e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fb8fe9962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6be5e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6be5e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6be5e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6be5e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb8fe2ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fb8fe2ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fb8fe138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fb8fac2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fb8fac2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6be5e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6be5e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6be5e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb8fac2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c (954 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbc_vvm_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbc_vxm_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbc_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbc_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbc_vvm_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbc_vxm_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbc_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbc_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbc_vvm_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbc_vxm_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# | ...
# `---data was truncated (10240/170489) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ead6c52eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ead6c4fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ead6c5362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe57ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe57eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe57ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe57ea31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ead6be8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ead6be8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ead6bcd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ead687ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ead687cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe57ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe57ea330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe57ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ead687ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c (955 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_f16m1x2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_f16m2x2(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_f16m4x2(ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_f32m1x2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_f32m2x2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple
# | ...
# `---data was truncated (10240/113757) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d2850b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d2850b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d2850b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f925121bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f92512725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f925121ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9251203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d28504bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d28504ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d2850308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d284cdfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d284cdfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9251204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f92512050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f92512050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d284cdfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c (956 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e22bba7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e22bba4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e22bba862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe089733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe08978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe089733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe08971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e22bb3dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e22bb3da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e22bb228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e22b7d1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e22b7d1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe08971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe08971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe08971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e22b7d1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c (957 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f16m1x6(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f32m1x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f64m1x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d4174feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558d4174ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558d4175062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f00c7933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f00c798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f00c7933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f00c791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d416e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558d416e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558d416ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558d41379e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558d41379b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f00c791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f00c791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f00c791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d41379a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/neon/intrinsics-constrained.c (958 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/intrinsics-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=maytrap -DEXCEPT=1 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c --check-prefix=LLVM --implicit-check-not=fpexcept.maytrap --implicit-check-not=' @llvm.sqrt.'
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=maytrap -DEXCEPT=1 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <4 x half> @test_vsqrt_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %vsqrt.i = call <4 x half> @llvm.experimental.constrained.sqrt.v4f16(<4 x half> %2, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <4 x half> %vsqrt.i, ptr %ref.tmp.i, align 8
# |   %3 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %3, ptr %__ret.i, align 8
# |   %4 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <8 x half> @test_vsqrtq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %vsqrt.i = call <8 x half> @llvm.experimental.constrained.sqrt.v8f16(<8 x half> %2, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <8 x half> %vsqrt.i, ptr %ref.tmp.i, align 16
# |   %3 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %3, ptr %__ret.i, align 16
# |   %4 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <2 x double> @test_vsqrtq_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <2 x double>
# |   %vsqrt.i = call <2 x double> @llvm.experimental.constrained.sqrt.v2f64(<2 x double> %2, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <2 x double> %vsqrt.i, ptr %ref.tmp.i, align 16
# |   %3 = load <2 x double>, ptr %ref.tmp.i, align 16
# |   store <2 x double> %3, ptr %__ret.i, align 16
# |   %4 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare <4 x half> @llvm.experimental.constrained.sqrt.v4f16(<4 x half>, metadata, metadata) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare <8 x half> @llvm.experimental.constrained.sqrt.v8f16(<8 x half>, metadata, metadata) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare <2 x double> @llvm.experimental.constrained.sqrt.v2f64(<2 x double>, metadata, metadata) #1
# | 
# | attributes #0 = { noinline nounwind strictfp "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon" }
# | attributes #1 = { nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) }
# | attributes #2 = { strictfp }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005607ff9f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005607ff9efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005607ff9f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe4cf449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe4cf4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe4cf449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe4cf431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607ff988bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005607ff988a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005607ff96d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005607ff61ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005607ff61cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe4cf432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe4cf4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe4cf4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607ff61ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c --check-prefix=LLVM --implicit-check-not=fpexcept.maytrap '--implicit-check-not= @llvm.sqrt.'
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c --check-prefix=LLVM --implicit-check-not=fpexcept.maytrap --implicit-check-not= @llvm.sqrt.
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c (959 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtbl_s8(<vscale x 16 x i8> %data, <vscale x 16 x i8> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   %indices.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   store <vscale x 16 x i8> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.tbl.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.tbl.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtbl_s16(<vscale x 8 x i16> %data, <vscale x 8 x i16> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   %indices.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   store <vscale x 8 x i16> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.tbl.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.tbl.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtbl_s32(<vscale x 4 x i32> %data, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.tbl.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.tbl.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtbl_s64(<vscale x 2 x i64> %data, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.tbl.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.tbl.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtbl_u8(<vscale x 16 x i8> %data, <vscale x 16 x i8> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   %indices.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   store <vscale x 16 x i8> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.tbl.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtbl_u16(<vscale x 8 x i16> %data, <vscale x 8 x i16> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   %indices.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   store <vscale x 8 x i16> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.tbl.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtbl_u32(<vscale x 4 x i32> %data, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.tbl.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtbl_u64(<vscale x 2 x i64> %data, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.tbl.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtbl_f16(<vscale x 8 x half> %data, <vscale x 8 x i16> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 8 x half>, align 16
# |   %indices.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x half> %data, ptr %data.addr, align 16
# |   store <vscale x 8 x i16> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %data.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.tbl.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.tbl.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtbl_f32(<vscale x 4 x float> %data, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 4 x float>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x float> %data, ptr %data.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %data.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.tbl.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.tbl.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtbl_f64(<vscale x 2 x double> %data, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 2 x double>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x double> %data, ptr %data.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %data.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.tbl.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.tbl.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svtbl_bf16(<vscale x 8 x bfloat> %data, <vscale x 8 x i16> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %indices.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x bfloat> %data, ptr %data.addr, align 16
# |   store <vscale x 8 x i16> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %data.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.tbl.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.tbl.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x i16>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptra
# | ...
# `---data was truncated (10240/10361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000558ab8743eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558ab8740e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558ab874462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa9efa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa9efaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa9efa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa9efa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558ab86d9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558ab86d9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558ab86be8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558ab836de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558ab836db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa9efa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa9efa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa9efa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558ab836da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c (960 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulu_vv_u16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulu_vx_u16mf4(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulu_vv_u16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulu_vx_u16mf2(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulu_vv_u16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulu_vx_u16m1(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulu_vv_u16m2(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulu_vx_u16m2(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulu_vv_u16m4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulu_vx_u16m4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind 
# | ...
# `---data was truncated (10240/68247) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f43511feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f43511ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f43512062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b3d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b3d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b3d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b3d91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f4350b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f4350b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f43509a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f434d49e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f434d49b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5b3d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b3d91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b3d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f434d49a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c (961 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_i8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_i8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8_v_i8m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_u8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_u8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_u8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8_v_u8m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_i8mf8x6_tum(<vscale x 1 x 
# | ...
# `---data was truncated (10240/43119) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056371565eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056371565be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056371565f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff9e9649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff9e96a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff9e9649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff9e9631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005637155f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005637155f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005637155d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563715288e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563715288b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff9e9632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff9e96330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff9e96330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563715288a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c (962 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_i16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_i16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8
# | ...
# `---data was truncated (10240/80508) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005624da969eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005624da966e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005624da96a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f11f8649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f11f86a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f11f8649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f11f8631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005624da8ffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005624da8ffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005624da8e48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005624da593e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005624da593b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f11f8632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f11f86330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f11f86330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005624da593a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c (963 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_w_bf16mf4_f8e4m3mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_w_bf16mf4_f8e4m3mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_w_bf16mf2_f8e4m3mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_w_bf16mf2_f8e4m3mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_w_bf16m1_f8e4m3mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_sat_f_f_w_bf16m1_f8e4m3mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_f_f_w_bf16m2_f8e4m3m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_sat_f_f_w_bf16m2_f8e4m3m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_f_f_w_bf16m4_f8e4m3m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_sat_f_f_w_bf16m4_f8e4m3m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_f_f_w_bf16m8_f8e4m3m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.f.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> poison, <vscale x 32 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.f.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_sat_f_f_w_bf16m8_f8e4m3m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <
# | ...
# `---data was truncated (10240/84810) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055da6d5a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055da6d5a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055da6d5a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2ff1933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2ff198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2ff1933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2ff191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da6d53cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055da6d53ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055da6d5218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055da6d1d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055da6d1d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2ff191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2ff191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2ff191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da6d1d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c (964 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3e
# | ...
# `---data was truncated (10240/228857) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b074077eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b074074e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b07407862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fddf9649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fddf96a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fddf9649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fddf9631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b07400dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b07400da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b073ff28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b073ca1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b073ca1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fddf9632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fddf96330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fddf96330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b073ca1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c (965 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtrn2_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.trn2q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.trn2q.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtrn2_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.trn2q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.trn2q.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtrn2_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.trn2q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.trn2q.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtrn2_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.trn2q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.trn2q.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtrn2_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.trn2q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtrn2_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.trn2q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtrn2_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.trn2q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtrn2_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.trn2q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtrn2_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.trn2q.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.trn2q.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtrn2_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.trn2q.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.trn2q.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtrn2_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.trn2q.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.trn2q.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svtrn2_bf16(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.trn2q.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.trn2q.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000561ea3707eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561ea3704e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561ea370862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2974d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2974d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2974d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2974d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561ea369dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561ea369da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561ea36828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561ea3331e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561ea3331b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2974d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2974d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2974d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561ea3331a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c (966 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vslideup_vx_f16mf4_tu(<vscale x 1 x half> %dest, <vscale x 1 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vslideup_vx_f16mf2_tu(<vscale x 2 x half> %dest, <vscale x 2 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vslideup_vx_f16m1_tu(<vscale x 4 x half> %dest, <vscale x 4 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vslideup_vx_f16m2_tu(<vscale x 8 x half> %dest, <vscale x 8 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vslideup_vx_f16m4_tu(<vscale x 16 x half> %dest, <vscale x 16 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vslideup_vx_f16m8_tu(<vscale x 32 x half> %dest, <vscale x 32 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vslideup_vx_f32mf2_tu(<vscale x 1 x float> %dest, <vscale x 1 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vslideup_vx_f32m1_tu(<vscale x 2 x float> %dest, <vscale x 2 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vslideup_vx_f32m2_tu(<vscale x 4 x float> %dest, <vscale x 4 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %dest, ptr %dest.addr, ali
# | ...
# `---data was truncated (10240/280217) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d67980ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d679809e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d67980d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d2ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d2ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d2ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d2ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d6797a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d6797a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d6797878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d679436e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d679436b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4d2ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d2ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d2ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d679436a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c (967 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesz_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesz_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesz_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesz_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesz_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesz_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesz_vs_u32m1_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32m2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback 
# | ...
# `---data was truncated (10240/15245) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a7a8a15eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a7a8a12e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a7a8a1662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd92a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd92aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd92a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd92a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a7a89abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a7a89aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a7a89908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a7a863fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a7a863fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbd92a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd92a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd92a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a7a863fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c (968 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vset_v_bf16m1_bf16m2(<vscale x 8 x bfloat> %dest, i64 noundef %index, <vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 0)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vset_v_bf16m1_bf16m4(<vscale x 16 x bfloat> %dest, i64 noundef %index, <vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 0)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vset_v_bf16m2_bf16m4(<vscale x 16 x bfloat> %dest, i64 noundef %index, <vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 0)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vset_v_bf16m1_bf16m8(<vscale x 32 x bfloat> %dest, i64 noundef %index, <vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 0)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vset_v_bf16m2_bf16m8(<vscale x 32 x bfloat> %dest, i64 noundef %index, <vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 0)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat>, <vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vset_v_bf16m4_bf16m8(<vscale x 32 x bfloat> %dest, i64 noundef %index, <vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv16bf16(<vscale x 32 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 0)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv16bf16(<vscale x 32 x bfloat>, <vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vset_v_bf16mf4_bf16mf4x2(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %dest, i64 noundef %index, <vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_2t.nxv1bf16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, <vscale x 1 x bfloat> %1, i32 0)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_2t.nxv1bf16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), <vscale x 1 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vset_v_bf16mf4_bf16mf4x3(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %dest, i64 noundef %index, <vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_3t.nxv1bf16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, <vscale x 1 x bfloat> %1, i32 0)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_3t.nxv1bf16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), <vscale x 1 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vset_v_bf16mf4_bf16mf4x4(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %dest, i64 noundef %index, <vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %2 = call target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/41659) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005559a4e4feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005559a4e4ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005559a4e5062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1ec0b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1ec0b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1ec0b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1ec0b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005559a4de5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005559a4de5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005559a4dca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005559a4a79e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005559a4a79b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1ec0b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1ec0b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1ec0b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005559a4a79a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c (969 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559a5da0deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559a5da0ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559a5da0e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff802733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff80278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff802733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff80271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a5d9a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559a5d9a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559a5d9888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559a5d637e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559a5d637b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff80271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff80271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff80271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a5d637a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c (970 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmin_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmin_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmin_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmin_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmin_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmin_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmin_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmin_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmin_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfmin.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmin.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmin_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %o
# | ...
# `---data was truncated (10240/29054) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555b18935eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555b18932e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555b1893662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4050849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f40508a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4050849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4050831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b188cbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555b188cba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555b188b08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555b1855fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555b1855fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4050832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f40508330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f40508330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b1855fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c (971 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vunzipo_v_f16mf4(<vscale x 2 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(<vscale x 1 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(<vscale x 1 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vunzipo_v_f16mf2(<vscale x 4 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(<vscale x 2 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(<vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vunzipo_v_f16m1(<vscale x 8 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vunzipo_v_f16m2(<vscale x 16 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(<vscale x 8 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(<vscale x 8 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vunzipo_v_f16m4(<vscale x 32 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(<vscale x 16 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(<vscale x 16 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vunzipo_v_f32mf2(<vscale x 2 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(<vscale x 1 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(<vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vunzipo_v_f32m1(<vscale x 4 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vunzipo_v_f32m2(<vscale x 8 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(<vscale x 4 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(<vscale x 4 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vunzipo_v_f32m4(<vscale x 16 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(<vscale x 8 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(<vscale x 8 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vunzipo_v_f64m1(<vscale x 2 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64(<vscale x 1 x double>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vunzipo_v_f64m2(<vscale x 4 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.vunzipo.nxv2f64.nxv4f64.i64(<vscale x 2 x double> poison, <vscale x 4 x double> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vunzipo.nxv2f64.nxv4f64.i64(<vscale x 2 x double>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vunzipo_v_f64m4(<vscale x 8 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.vunzipo.nxv4f64.nxv8f64.i64(<vscale x 4 x double> poison, <vscale x 8 x double> %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.vunzipo.nxv4f64.nxv8f64.i64(<vscale x 4 x double>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1
# | ...
# `---data was truncated (10240/35782) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005613c5d38eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005613c5d35e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005613c5d3962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fda01049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fda010a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fda01049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fda01031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005613c5ccebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005613c5ccea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005613c5cb38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005613c5962e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005613c5962b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fda01032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fda010330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fda010330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005613c5962a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c (972 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_bf16mf4x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_bf16mf2x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_bf16m1x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16ff_v_bf16m2x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16ff_v_bf16m4x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x
# | ...
# `---data was truncated (10240/15718) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055719c1b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055719c1b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055719c1b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbfe0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbfe08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbfe0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbfe0831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055719c14bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055719c14ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055719c1308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055719bddfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055719bddfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbfe0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbfe08330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbfe08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055719bddfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c (973 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmacc_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmacc_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmacc_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmacc_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmacc_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmacc_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmacc_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmacc_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <v
# | ...
# `---data was truncated (10240/64252) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056515cca5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056515cca2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056515cca662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6ae6733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6ae678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6ae6733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6ae671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056515cc3bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056515cc3ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056515cc208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056515c8cfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056515c8cfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6ae671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6ae671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6ae671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056515c8cfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c (974 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_tu(<vscale x 16 x half> %vd, <vsc
# | ...
# `---data was truncated (10240/295319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005598cccb1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005598cccaee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005598cccb262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc010533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc01058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc010533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc01051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005598ccc47bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005598ccc47a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005598ccc2c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005598cc8dbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005598cc8dbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc01051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc01051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc01051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005598cc8dba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c (975 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8ff_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8ff_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(<vscale x 2 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8ff_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(<vscale x 4 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8ff_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(<vscale x 8 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8ff_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(<vscale x 16 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 16 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8ff_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(<vscale x 32 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 32 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 32 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8ff_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(<vscale x 64 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 64 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 64 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 64 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8ff_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8ff_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, a
# | ...
# `---data was truncated (10240/71115) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561009509eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561009506e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056100950a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e9c81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e9c8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e9c81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e9c803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056100949fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056100949fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005610094848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561009133e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561009133b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6e9c804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e9c8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e9c8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561009133a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c (976 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsac_vv_i8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsac_vx_i8mf8(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsac_vv_i8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsac_vx_i8mf4(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsac_vv_i8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsac_vx_i8mf2(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsac_vv_i8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsac_vx_i8m1(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnmsac_vv_i8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x
# | ...
# `---data was truncated (10240/208199) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005589de76eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005589de76be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005589de76f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007facd5049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007facd50a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007facd5049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007facd5031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589de704bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005589de704a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005589de6e98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005589de398e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005589de398b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007facd5032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007facd50330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007facd50330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005589de398a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c (977 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgeu_vv_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgeu_vx_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgeu_vv_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgeu_vx_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgeu_vv_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgeu_vx_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgeu_vv_u8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vsca
# | ...
# `---data was truncated (10240/63705) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555fdb231eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555fdb22ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555fdb23262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f8be1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f8be725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f8be1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f8be03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555fdb1c7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555fdb1c7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555fdb1ac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555fdae5be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555fdae5bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1f8be04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f8be050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f8be050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555fdae5ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c (978 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vremu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vremu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vremu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vremu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vremu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vremu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vremu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vremu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vremu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vremu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vremu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vremu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vremu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vremu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vremu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr
# | ...
# `---data was truncated (10240/97905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558ca27aeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558ca27abe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558ca27af62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9ad4f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9ad4f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9ad4f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9ad4f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558ca2744bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558ca2744a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558ca27298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558ca23d8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558ca23d8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9ad4f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9ad4f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9ad4f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558ca23d8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c (979 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsrl_wv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsrl_wx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsrl_wv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsrl_wx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsrl_wv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsrl_wx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsrl_wv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsrl_wx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsrl_wv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = allo
# | ...
# `---data was truncated (10240/154609) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a91d49beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a91d498e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a91d49c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feaaac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feaaaca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feaaac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feaaac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a91d431bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a91d431a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a91d4168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a91d0c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a91d0c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feaaac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feaaac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feaaac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a91d0c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c (980 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vzext_vf2_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vzext_vf2_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vzext_vf2_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vzext_vf2_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vzext_vf2_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vzext_vf2_u16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf2_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf2_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf2_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vzext_vf2_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: n
# | ...
# `---data was truncated (10240/66036) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005631d5ebaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005631d5eb7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005631d5ebb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efd88d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efd88d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efd88d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efd88d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005631d5e50bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005631d5e50a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005631d5e358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005631d5ae4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005631d5ae4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efd88d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efd88d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efd88d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005631d5ae4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/arm-neon-vld.c (981 of 27911)
******************** TEST 'Clang :: CodeGen/arm-neon-vld.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon      -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |      /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | %struct.float16x4x2_t = type { [2 x <4 x half>] }
# | %struct.float16x4x3_t = type { [3 x <4 x half>] }
# | %struct.float16x4x4_t = type { [4 x <4 x half>] }
# | %struct.float32x2x2_t = type { [2 x <2 x float>] }
# | %struct.float32x2x3_t = type { [3 x <2 x float>] }
# | %struct.float32x2x4_t = type { [4 x <2 x float>] }
# | %struct.poly16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.poly16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.poly16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.poly8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.poly8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.poly8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.int16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.int16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.int16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.int32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.int32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.int32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.int64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.int64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.int64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.int8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.int8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.int8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.uint16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.uint16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.uint16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.uint32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.uint32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.uint32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.uint64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.uint64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.uint64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.uint8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.uint8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.uint8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.float16x8x2_t = type { [2 x <8 x half>] }
# | %struct.float16x8x3_t = type { [3 x <8 x half>] }
# | %struct.float16x8x4_t = type { [4 x <8 x half>] }
# | %struct.float32x4x2_t = type { [2 x <4 x float>] }
# | %struct.float32x4x3_t = type { [3 x <4 x float>] }
# | %struct.float32x4x4_t = type { [4 x <4 x float>] }
# | %struct.poly16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.poly16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.poly16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.poly8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.poly8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.poly8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.int16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.int16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.int16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.int32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.int32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.int32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.int64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.int64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.int64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.int8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.int8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.int8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.uint16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.uint16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.uint16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.uint32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.uint32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.uint32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.uint64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.uint64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.uint64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.uint8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.uint8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.uint8x16x4_t = type { [4 x <16 x i8>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float16x4x2_t @test_vld1_f16_x2(ptr noundef %a) #0 {
# | entry:
# |   %retval = alloca %struct.float16x4x2_t, align 8
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca %struct.float16x4x2_t, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %vld1xN = call { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x2.v4f16.p0(ptr %0)
# |   store { <4 x half>, <4 x half> } %vld1xN, ptr %__ret, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 16, i1 false)
# |   %1 = load %struct.float16x4x2_t, ptr %retval, align 8
# |   ret %struct.float16x4x2_t %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x2.v4f16.p0(ptr) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.memcpy.p0.p0.i64(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i64, i1 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float16x4x3_t @test_vld1_f16_x3(ptr noundef %a) #0 {
# | entry:
# |   %retval = alloca %struct.float16x4x3_t, align 8
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca %struct.float16x4x3_t, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %vld1xN = call { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x3.v4f16.p0(ptr %0)
# |   store { <4 x half>, <4 x half>, <4 x half> } %vld1xN, ptr %__ret, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 24, i1 false)
# |   %1 = load %struct.float16x4x3_t, ptr %retval, align 8
# |   ret %struct.float16x4x3_t %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x3.v4f16.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float16x4x4_t @test_vld1_f16_x4(ptr noundef %a) #0 {
# | entry:
# |   %retval = alloca %struct.float16x4x4_t, align 8
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca %struct.float16x4x4_t, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %vld1xN = call { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x4.v4f16.p0(ptr %0)
# |   store { <4 x half>, <4 x half>, <4 x half>, <4 x half> } %vld1xN, ptr %__ret, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 32, i1 false)
# |   %1 = load %struct.float16x4x4_t, ptr %retval, align 8
# |   ret %struct.float16x4x4_t %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x4.v4f16.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float32x2x2_t @test_vld1_f32_x2(ptr noundef %a) #0 {
# | entry:
# |   %retval = alloca %struct.float32x2x2_t, align 8
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca %struct.float32x2x2_t, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %vld1xN = call { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x2.v2f32.p0(ptr %0)
# |   store { <2 x float>, <2 x float> } %vld1xN, ptr %__ret, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 16, i1 false)
# |   %1 = load %struct.float32x2x2_t, ptr %retval, align 8
# |   ret %struct.float32x2x2_t %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x2.v2f32.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float32x2x3_t @test_vld1_f32_x3(ptr noundef %a) #0 {
# | entry:
# |   %retval = alloca %struct.float32x2x3_t, align 8
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca %struct.float32x2x3_t, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %vld1xN = call { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x3.v2f32.p0(ptr %0)
# |   store { <2 x float>, <2 x float>, <2 x float> } %vld1xN, ptr %__ret, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 24, i1 false)
# |   %1 = load %struct.float32x2x3_t, ptr %retval, align 8
# |   ret %struct.float32x2x3_t %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x3.v2f32.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float32x2x4_t @test_vld1_f32_x4(ptr noundef %a) #0 {
# | entry:
# |   %retval = alloca %struct.float32x2x4_t, align 8
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca %struct.float32x2x4_t, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %vld1xN = call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x4.v2f32.p0(ptr %0)
# |   store { <2 x float>, <2 x float>, <2 x float>, <2 x float> } %vld1xN, ptr %__ret, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 32, i1 false)
# |   %1 = load %struct.float32x2x4_t, ptr %retval, align 8
# |   ret %struct.float32x2x4_t %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x4.v2f32.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.poly16x4x2_t @test_vld1_p16_x2(ptr noundef %a) #0 {
# | entry:
# |   %retval = alloca %struct.poly16x4x2_t, align 8
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca %struct.poly16x4x2_t, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %vld1xN = call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x2.v4i16.p0(ptr %0)
# |   store { <4 x i16>, <4 x i16> } %vld1xN, ptr %__ret, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 16, i1 false)
# |   %1 = load %struct.poly16x4x2_t, ptr %retval, align 8
# |   ret %struct.poly16x4x2_t %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x2.v4i16.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.poly16x4x3_t @test_vld1_p16_x3(ptr noundef %a) #0 {
# | entry:
# |   %retval = alloca %struct.poly16x4x3_t, align 8
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca %struct.poly16
# | ...
# `---data was truncated (10240/109928) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005645a639deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005645a639ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005645a639e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007effa0b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007effa0b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007effa0b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007effa0b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005645a6333bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005645a6333a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005645a63188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005645a5fc7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005645a5fc7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007effa0b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007effa0b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007effa0b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005645a5fc7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c (982 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4(<vscale x 16 x half> %
# | ...
# `---data was truncated (10240/149145) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b94b35beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b94b358e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b94b35c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdbb3e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdbb3ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdbb3e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdbb3e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b94b2f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b94b2f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b94b2d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b94af85e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b94af85b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdbb3e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdbb3e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdbb3e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b94af85a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c (983 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f16m1x3(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f16m2x3(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f32m1x3(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f32m2x3(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f64m1x3(ptr noundef %base, <vscale x 1 x i32
# | ...
# `---data was truncated (10240/99762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b49c3b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b49c3b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b49c3b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcf3af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcf3af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcf3af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcf3af1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b49c349bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b49c349a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b49c32e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b49bfdde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b49bfddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcf3af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcf3af1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcf3af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b49bfdda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c (984 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf4(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf2(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvt_rod_f_f_w_bf16m1(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvt_rod_f_f_w_bf16m2(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvt_rod_f_f_w_bf16m4(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvt_rod_f_f_w_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvt_rod_f_f_w_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvt_rod_f_f_w_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_ran
# | ...
# `---data was truncated (10240/10878) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a73b6c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a73b6c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a73b6c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa34ce1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa34ce725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa34ce1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa34ce03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a73b65abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a73b65aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a73b63f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a73b2eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a73b2eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa34ce04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa34ce050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa34ce050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a73b2eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c (985 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8ff_v_i8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.mask.nxv1i8.i64.p0(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.mask.nxv1i8.i64.p0(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8ff_v_i8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.mask.nxv2i8.i64.p0(<vscale x 2 x i8> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 2 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.mask.nxv2i8.i64.p0(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8ff_v_i8mf2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.mask.nxv4i8.i64.p0(<vscale x 4 x i8> poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 4 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.mask.nxv4i8.i64.p0(<vscale x 4 x i8>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8ff_v_i8m1_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.mask.nxv8i8.i64.p0(<vscale x 8 x i8> poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 8 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.mask.nxv8i8.i64.p0(<vscale x 8 x i8>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8ff_v_i8m2_m(<vscale x 16 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.mask.nxv16i8.i64.p0(<vscale x 16 x i8> poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 16 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.mask.nxv16i8.i64.p0(<vscale x 16 x i8>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8ff_v_i8m4_m(<vscale x 32 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.mask.nxv32i8.i64.p0(<vscale x 32 x i8> poison, ptr %1, <vscale x 32 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 32 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 32 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.mask.nxv32i8.i64.p0(<vscale x 32 x i8>, ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8ff_v_i8m8_m(<vscale x 64 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.mask.nxv64i8.i64.p0(<vscale x 64 x i8> poison, ptr %1, <vscale x 64 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 64 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 64 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 64 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.mask.nxv64i8.i64.p0(<vscale x 64 x i8>, ptr captures(none), <vscale x 64 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8ff_v_u8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.mask.nxv1i8.i64.p0(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   
# | ...
# `---data was truncated (10240/17236) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555f18f25eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555f18f22e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555f18f2662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0c92d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0c92d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0c92d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0c92d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f18ebbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555f18ebba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555f18ea08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555f18b4fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555f18b4fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0c92d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0c92d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0c92d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f18b4fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c (986 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulsu_vv_i16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulsu_vx_i16mf4(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulsu_vv_i16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulsu_vx_i16mf2(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulsu_vv_i16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulsu_vx_i16m1(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulsu_vv_i16m2(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulsu_vx_i16m2(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulsu_vv_i16m4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulsu_vx_i16m4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Fu
# | ...
# `---data was truncated (10240/68429) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d1d298feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d1d298ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d1d299062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f99adb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f99adb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f99adb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f99adb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d1d2925bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d1d2925a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d1d290a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d1d25b9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d1d25b9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f99adb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f99adb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f99adb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d1d25b9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c (987 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f16m1x6(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f32m1x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f64m1x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei64_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005601b0ddfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005601b0ddce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005601b0de062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f242961bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f24296725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f242961ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2429603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005601b0d75bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005601b0d75a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005601b0d5a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005601b0a09e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005601b0a09b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2429604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f24296050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f24296050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005601b0a09a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c (988 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16mf4x3(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16mf2x3(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16m1x3(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16m2x3(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale
# | ...
# `---data was truncated (10240/10790) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560e7d107eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560e7d104e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560e7d10862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb2da133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb2da18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb2da133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb2da11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e7d09dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560e7d09da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560e7d0828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560e7cd31e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560e7cd31b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb2da11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb2da11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb2da11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e7cd31a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c (989 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei64_v_i8mf8x8
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055729827feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055729827ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055729828062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f46f4649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f46f46a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f46f4649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f46f4631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557298215bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557298215a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005572981fa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557297ea9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557297ea9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f46f4632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f46f46330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f46f46330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557297ea9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c (990 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564b52143eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564b52140e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564b5214462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f132481bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13248725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f132481ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1324803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564b520d9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564b520d9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564b520be8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564b51d6de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564b51d6db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1324804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13248050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13248050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564b51d6da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c (991 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei64_v_i8mf8x7
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f9561faeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f9561f7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f9561fb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f129101bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f12910725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f129101ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1291003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f956190bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f956190a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f9561758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f955e24e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f955e24b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1291004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f12910050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f12910050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f955e24a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c (992 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_bf16m1x3_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function 
# | ...
# `---data was truncated (10240/22115) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dd7f737eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dd7f734e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dd7f73862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efef4533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efef458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efef4533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efef451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd7f6cdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dd7f6cda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dd7f6b28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dd7f361e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dd7f361b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efef451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efef451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efef451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd7f361a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c (993 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vv_bf16mf4_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vf_bf16mf4_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vv_bf16mf2_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vf_bf16mf2_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vv_bf16m1_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vf_bf16m1_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vv_bf16m2_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vf_bf16m2_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.bf16.nxv
# | ...
# `---data was truncated (10240/51702) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056071abd5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056071abd2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056071abd662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4316d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4316d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4316d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4316d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056071ab6bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056071ab6ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056071ab508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056071a7ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056071a7ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4316d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4316d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4316d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056071a7ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c (994 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwcvt_x_x_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwcvt_x_x_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwcvt_x_x_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwcvt_x_x_v_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwcvt_x_x_v_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwcvt_x_x_v_i16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwcvt_x_x_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwcvt_x_x_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwcvt_x_x_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vwcvt_x_x_v_i32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <
# | ...
# `---data was truncated (10240/66998) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f1405eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f1405ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f1405ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efdb3849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efdb38a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efdb3849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efdb3831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f140584bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f140584a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f1405698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f140218e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f140218b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efdb3832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efdb38330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efdb38330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f140218a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/packed-structure.c (995 of 27911)
******************** TEST 'Clang :: CodeGen/packed-structure.c' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/packed-structure.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=strip -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/packed-structure.c.tmp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/packed-structure.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/packed-structure.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/packed-structure.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64"
# | 
# | %struct.s0 = type { i32, i32 }
# | %struct.s1 = type { i32, i32 }
# | %struct.s2 = type { i32, i32 }
# | %struct.s3 = type <{ i16, i32, [10 x i8] }>
# | 
# | @s0_align_x = global i32 4, align 4
# | @s0_align_y = global i32 1, align 4
# | @s0_align = global i32 4, align 4
# | @s1_align_x = global i32 1, align 4
# | @s1_align_y = global i32 1, align 4
# | @s1_align = global i32 1, align 4
# | @s2_align_x = global i32 2, align 4
# | @s2_align_y = global i32 2, align 4
# | @s2_align = global i32 2, align 4
# | @s3_1 = global i32 1, align 4
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @s0_load_x(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %x = getelementptr inbounds nuw %struct.s0, ptr %0, i32 0, i32 0
# |   %1 = load i32, ptr %x, align 4
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @s0_load_y(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %y = getelementptr inbounds nuw %struct.s0, ptr %0, i32 0, i32 1
# |   %1 = load i32, ptr %y, align 4
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @s0_copy(ptr noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 8
# |   %0 = load ptr, ptr %b.addr, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 4 %0, ptr align 4 %1, i64 8, i1 false)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.memcpy.p0.p0.i64(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i64, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @s1_load_x(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %x = getelementptr inbounds nuw %struct.s1, ptr %0, i32 0, i32 0
# |   %1 = load i32, ptr %x, align 1
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @s1_load_y(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %y = getelementptr inbounds nuw %struct.s1, ptr %0, i32 0, i32 1
# |   %1 = load i32, ptr %y, align 1
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @s1_copy(ptr noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 8
# |   %0 = load ptr, ptr %b.addr, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 1 %0, ptr align 1 %1, i64 8, i1 false)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @s2_load_x(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %x = getelementptr inbounds nuw %struct.s2, ptr %0, i32 0, i32 0
# |   %1 = load i32, ptr %x, align 2
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @s2_load_y(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %y = getelementptr inbounds nuw %struct.s2, ptr %0, i32 0, i32 1
# |   %1 = load i32, ptr %y, align 2
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @s2_copy(ptr noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 8
# |   %0 = load ptr, ptr %b.addr, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 2 %0, ptr align 2 %1, i64 8, i1 false)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @test3(ptr noundef %ptr) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %anInt = getelementptr inbounds nuw %struct.s3, ptr %0, i32 0, i32 1
# |   %1 = load i32, ptr %anInt, align 2
# |   ret i32 %1
# | }
# | 
# | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=strip -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/packed-structure.c.tmp
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=strip -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/packed-structure.c.tmp
# |  #0 0x0000563247ab4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563247ab1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563247ab562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb342b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb342b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb342b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb342aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563247a4abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563247a4aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563247a2f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005632476dee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005632476deb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb342aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb342aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb342aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005632476dea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c (996 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei8_v_f16mf4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei8_v_f16mf2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei8_v_f16m1(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei8_v_f16m2(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei8_v_f16m4(ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vloxei8_v_f16m8(ptr noundef %base, <vscale x 32 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> poison, ptr %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei8_v_f32mf2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei8_v_f32m1(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei8_v_f32m2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei8_v_f32m4(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i8.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i8.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline noun
# | ...
# `---data was truncated (10240/121187) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562cac6e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562cac6e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562cac6e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8923849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f89238a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8923849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8923831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562cac679bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562cac679a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562cac65e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562cac30de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562cac30db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8923832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f89238330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f89238330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562cac30da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c (997 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vf_f32mf2_tu(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vf_f32m1_tu(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vf_f32m2_tu(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vf_f32m4_tu(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(<vscale 
# | ...
# `---data was truncated (10240/179177) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b7c99a8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b7c99a5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b7c99a962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7963c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7963ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7963c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7963c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b7c993ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b7c993ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b7c99238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b7c95d2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b7c95d2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7963c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7963c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7963c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b7c95d2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c (998 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f16m1x7(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f32m1x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f64m1x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef
# | ...
# `---data was truncated (10240/69988) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564e51e6ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564e51e69e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564e51e6d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8a53733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8a5378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8a53733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8a5371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564e51e02bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564e51e02a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564e51de78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564e51a96e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564e51a96b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8a5371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8a5371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8a5371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564e51a96a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c (999 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_f64m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_f64m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_f64m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_i64m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_i64m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_i64m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_u64m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_u64m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_u64m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_f64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_f64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_f64m4x2_m(<vscale x 4
# | ...
# `---data was truncated (10240/17583) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005645964baeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005645964b7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005645964bb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9021b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9021b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9021b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9021b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564596450bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564596450a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005645964358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005645960e4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005645960e4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9021b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9021b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9021b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005645960e4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-vls-subscript-ops.c (1000 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-subscript-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d  -target-feature +f -target-feature +d -disable-O0-optnone  -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c |  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local signext i8 @subscript_int8(<vscale x 8 x i8> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <32 x i8> %0, i64 %1
# |   ret i8 %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local zeroext i8 @subscript_uint8(<vscale x 8 x i8> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <32 x i8> %0, i64 %1
# |   ret i8 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local signext i16 @subscript_int16(<vscale x 4 x i16> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <16 x i16> %0, i64 %1
# |   ret i16 %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local zeroext i16 @subscript_uint16(<vscale x 4 x i16> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <16 x i16> %0, i64 %1
# |   ret i16 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local signext i32 @subscript_int32(<vscale x 2 x i32> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <8 x i32> %0, i64 %1
# |   ret i32 %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local signext i32 @subscript_uint32(<vscale x 2 x i32> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <8 x i32> %0, i64 %1
# |   ret i32 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local i64 @subscript_int64(<vscale x 1 x i64> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i64>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %a.coerce, i64 0)
# |   store <4 x i64> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <4 x i64>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <4 x i64> %0, i64 %1
# |   ret i64 %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local i64 @subscript_uint64(<vscale x 1 x i64> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i64>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %a.coerce, i64 0)
# |   store <4 x i64> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <4 x i64>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <4 x i64> %0, i64 %1
# |   ret i64 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local float @subscript_float32(<vscale x 2 x float> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x float>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <8 x float> @llvm.vector.extract.v8f32.nxv2f32(<vscale x 2 x float> %a.coerce, i64 0)
# |   store <8 x float> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <8 x float>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <8 x float> %0, i64 %1
# |   ret float %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x float> @llvm.vector.extract.v8f32.nxv2f32(<vscale x 2 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local double @subscript_float64(<vscale x 1 x double> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x double>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <4 x double> @llvm.vector.extract.v4f64.nxv1f64(<vscale x 1 x double> %a.coerce, i64 0)
# |   store <4 x double> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <4 x double>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <4 x double> %0, i64 %1
# |   ret double %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x double> @llvm.vector.extract.v4f64.nxv1f64(<vscale x 1 x double>, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,4) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x0000555f6bce5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555f6bce2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555f6bce662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1246733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f124678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1246733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f124671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f6bc7bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555f6bc7ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555f6bc608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555f6b90fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555f6b90fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f124671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f124671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f124671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f6b90fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c (1001 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1(<vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vx_u64m1(<vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmulh_vv_u64m2(<vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmulh_vx_u64m2(<vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmulh_vv_u64m4(<vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmulh_vx_u64m4(<vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmulh_vv_u64m8(<vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmulh_vx_u64m8(<vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vx_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   
# | ...
# `---data was truncated (10240/18925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ee3a56eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564ee3a53e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564ee3a5762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f020f61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f020f6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f020f61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f020f603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ee39ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564ee39eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564ee39d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564ee3680e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564ee3680b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f020f604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f020f6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f020f6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ee3680a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/get-set-lane.c (1002 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/get-set-lane.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc half @test_vgetq_lane_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = extractelement <8 x half> %0, i32 2
# |   ret half %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc float @test_vgetq_lane_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = extractelement <4 x float> %0, i32 3
# |   ret float %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc signext i16 @test_vgetq_lane_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = extractelement <8 x i16> %0, i32 4
# |   ret i16 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vgetq_lane_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = extractelement <4 x i32> %0, i32 0
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vgetq_lane_s64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = extractelement <2 x i64> %0, i32 0
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc signext i8 @test_vgetq_lane_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = extractelement <16 x i8> %0, i32 10
# |   ret i8 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vgetq_lane_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = extractelement <8 x i16> %0, i32 3
# |   ret i16 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vgetq_lane_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = extractelement <4 x i32> %0, i32 3
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vgetq_lane_u64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = extractelement <2 x i64> %0, i32 1
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vgetq_lane_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = extractelement <16 x i8> %0, i32 1
# |   ret i8 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vsetq_lane_f16(half noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca <8 x half>, align 8
# |   store half %a, ptr %a.addr, align 2
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %b.addr, align 8
# |   %1 = load half, ptr %a.addr, align 2
# |   %2 = insertelement <8 x half> %0, half %1, i32 4
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vsetq_lane_f32(float noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca float, align 4
# |   %b.addr = alloca <4 x float>, align 8
# |   store float %a, ptr %a.addr, align 4
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %b.addr, align 8
# |   %1 = load float, ptr %a.addr, align 4
# |   %2 = insertelement <4 x float> %0, float %1, i32 2
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vsetq_lane_s8(i8 noundef signext %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %b.addr, align 8
# |   %1 = load i8, ptr %a.addr, align 1
# |   %2 = insertelement <16 x i8> %0, i8 %1, i32 12
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vsetq_lane_s16(i16 noundef signext %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = load i16, ptr %a.addr, align 2
# |   %2 = insertelement <8 x i16> %0, i16 %1, i32 6
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsetq_lane_s32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = load i32, ptr %a.addr, align 4
# |   %2 = insertelement <4 x i32> %0, i32 %1, i32 2
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vsetq_lane_s64(i64 noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <2 x i64>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i64>, ptr %b.addr, align 8
# |   %1 = load i64, ptr %a.addr, align 8
# |   %2 = insertelement <2 x i64> %0, i64 %1, i32 0
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vsetq_lane_u8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %b.addr, align 8
# |   %1 = load i8, ptr %a.addr, align 1
# |   %2 = insertelement <16 x i8> %0, i8 %1, i32 2
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vsetq_lane_u16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = load i16, ptr %a.addr, align 2
# |   %2 = insertelement <8 x i16> %0, i16 %1, i32 7
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsetq_lane_u32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = load i32, ptr %a.addr, align 4
# |   %2 = insertelement <4 x i32> %0, i32 %1, i32 0
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vsetq_lane_u64(i64 noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <2 x i64>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i64>, ptr %b.addr, align 8
# |   %1 = load i64, ptr %a.addr, align 8
# |   %2 = insertelement <2 x i64> %0, i64 %1, i32 1
# |   ret <2 x i64> %2
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>'
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<>
# |  #0 0x000055efefde1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055efefddee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055efefde262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2160449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f21604a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2160449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2160431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055efefd77bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055efefd77a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055efefd5c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055efefa0be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055efefa0bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2160432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f21604330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f21604330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055efefa0ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c (1003 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llv
# | ...
# `---data was truncated (10240/101576) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b99be77eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b99be74e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b99be7862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0b98f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0b98f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0b98f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0b98f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b99be0dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b99be0da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b99bdf28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b99baa1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b99baa1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0b98f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0b98f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0b98f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b99baa1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c (1004 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563e72d99eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563e72d96e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563e72d9a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbee8c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbee8ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbee8c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbee8c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e72d2fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563e72d2fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563e72d148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563e729c3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563e729c3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbee8c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbee8c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbee8c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e729c3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c (1005 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac43fabeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ac43fa8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ac43fac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa432933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa43298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa432933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa43291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac43f41bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ac43f41a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ac43f268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ac43bd5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ac43bd5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa43291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa43291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa43291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac43bd5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c (1006 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_x_f_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_x_f_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_x_f_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_x_f_v_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_x_f_v_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_x_f_v_i16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> %0, <vscale x 32 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_xu_f_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_xu_f_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_xu_f_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_xu_f_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x hal
# | ...
# `---data was truncated (10240/514165) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555f68ec2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555f68ebfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555f68ec362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9e08e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9e08ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9e08e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9e08e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f68e58bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555f68e58a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555f68e3d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555f68aece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555f68aecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9e08e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9e08e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9e08e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f68aeca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c (1007 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f16m1x7(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f32m1x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f64m1x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei8_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none
# | ...
# `---data was truncated (10240/61673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055611128beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556111288e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055611128c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc5ce449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5ce4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc5ce449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc5ce431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556111221bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556111221a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005561112068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556110eb5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556110eb5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc5ce432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5ce4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5ce4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556110eb5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c (1008 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabdau_vv_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabdau_vx_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabdau_vv_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabdau_vx_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabdau_vv_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabdau_vx_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabdau_vv_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabdau_vx_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwabdau_vv_u16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vsc
# | ...
# `---data was truncated (10240/110284) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c51ffb9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c51ffb6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c51ffba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdfd6a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdfd6aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdfd6a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdfd6a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c51ff4fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c51ff4fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c51ff348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c51fbe3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c51fbe3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdfd6a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdfd6a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdfd6a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c51fbe3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c (1009 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei8_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_f32m1x2_tu(target("riscv.vector.
# | ...
# `---data was truncated (10240/295525) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557d49245eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557d49242e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557d4924662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb6b641bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb6b64725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb6b641ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb6b6403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557d491dbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557d491dba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557d491c08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557d48e6fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557d48e6fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb6b6404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb6b64050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb6b64050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557d48e6fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c (1010 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8ff_v_i8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8ff_v_i8mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8ff_v_i8mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8ff_v_i8m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8ff_v_i8m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8ff_v_i8m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { targe
# | ...
# `---data was truncated (10240/81756) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560c3c48beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560c3c488e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560c3c48c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbfb8c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbfb8c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbfb8c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbfb8c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c3c421bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560c3c421a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560c3c4068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560c3c0b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560c3c0b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbfb8c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbfb8c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbfb8c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c3c0b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c (1011 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnot_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnot_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnot_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnot_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnot_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vnot_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vnot_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vnot_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 -1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vnot_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 -1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vnot_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 -1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i1
# | ...
# `---data was truncated (10240/182173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056365590deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056365590ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056365590e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc616133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc61618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc616133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc61611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005636558a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005636558a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005636558888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563655537e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563655537b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc61611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc61611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc61611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563655537a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c (1012 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfneg_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfneg_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfneg_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfneg_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfneg_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfneg_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfneg_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfneg_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfneg_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfneg_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x f
# | ...
# `---data was truncated (10240/70110) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa0be8feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fa0be8ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fa0be9062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff1dfb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff1dfb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff1dfb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff1dfaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa0be25bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fa0be25a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fa0be0a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fa0bab9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fa0bab9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff1dfaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff1dfaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff1dfaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa0bab9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c (1013 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3e
# | ...
# `---data was truncated (10240/216250) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055556cafbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055556caf8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055556cafc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d5e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d5e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d5e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d5e431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055556ca91bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055556ca91a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055556ca768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055556c725e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055556c725b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1d5e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d5e4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d5e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055556c725a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c (1014 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsle_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsle_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsle_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsle_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsle_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsle_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsle_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsle_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsle_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsle_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsle_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsle.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> %0, 
# | ...
# `---data was truncated (10240/95081) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559c27304eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559c27301e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559c2730562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f720e705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f720e75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f720e705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f720e6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c2729abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559c2729aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559c2727f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559c26f2ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559c26f2eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f720e6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f720e6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f720e6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c26f2ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c (1015 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_f32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_f32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_f32m2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_i32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_i32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_i32m2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_u32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_u32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_u32m2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0
# | ...
# `---data was truncated (10240/10425) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560ea42e2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560ea42dfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560ea42e362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc5e5e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5e5ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc5e5e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc5e5e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ea4278bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560ea4278a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560ea425d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560ea3f0ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560ea3f0cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc5e5e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5e5e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5e5e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ea3f0ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/cx-complex-range-real.c (1016 of 27911)
******************** TEST 'Clang :: CodeGen/cx-complex-range-real.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c -O0 -disable-O0-optnone -emit-llvm -triple x86_64-unknown-unknown  -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c --check-prefix=FULL
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c -O0 -disable-O0-optnone -emit-llvm -triple x86_64-unknown-unknown -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-unknown"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @mulaf(<2 x float> noundef %a.coerce, float noundef %b) #0 {
# | entry:
# |   %retval = alloca { float, float }, align 4
# |   %a = alloca { float, float }, align 4
# |   %b.addr = alloca float, align 4
# |   store <2 x float> %a.coerce, ptr %a, align 4
# |   store float %b, ptr %b.addr, align 4
# |   %a.realp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 0
# |   %a.real = load float, ptr %a.realp, align 4
# |   %a.imagp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 1
# |   %a.imag = load float, ptr %a.imagp, align 4
# |   %0 = load float, ptr %b.addr, align 4
# |   %mul.rl = fmul float %a.real, %0
# |   %mul.il = fmul float %a.imag, %0
# |   %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0
# |   %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1
# |   store float %mul.rl, ptr %retval.realp, align 4
# |   store float %mul.il, ptr %retval.imagp, align 4
# |   %1 = load <2 x float>, ptr %retval, align 4
# |   ret <2 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @mulassignf(ptr noundef %a, float noundef %b) #1 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca float, align 4
# |   store ptr %a, ptr %a.addr, align 8
# |   store float %b, ptr %b.addr, align 4
# |   %0 = load float, ptr %b.addr, align 4
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %.realp = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 0
# |   %.real = load float, ptr %.realp, align 4
# |   %.imagp = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 1
# |   %.imag = load float, ptr %.imagp, align 4
# |   %mul.rl = fmul float %.real, %0
# |   %mul.il = fmul float %.imag, %0
# |   %.realp1 = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 0
# |   %.imagp2 = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 1
# |   store float %mul.rl, ptr %.realp1, align 4
# |   store float %mul.il, ptr %.imagp2, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @mulbf(float noundef %a, <2 x float> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca { float, float }, align 4
# |   %b = alloca { float, float }, align 4
# |   %a.addr = alloca float, align 4
# |   store <2 x float> %b.coerce, ptr %b, align 4
# |   store float %a, ptr %a.addr, align 4
# |   %0 = load float, ptr %a.addr, align 4
# |   %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0
# |   %b.real = load float, ptr %b.realp, align 4
# |   %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1
# |   %b.imag = load float, ptr %b.imagp, align 4
# |   %mul.rl = fmul float %0, %b.real
# |   %mul.ir = fmul float %0, %b.imag
# |   %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0
# |   %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1
# |   store float %mul.rl, ptr %retval.realp, align 4
# |   store float %mul.ir, ptr %retval.imagp, align 4
# |   %1 = load <2 x float>, ptr %retval, align 4
# |   ret <2 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @divf(<2 x float> noundef %a.coerce, float noundef %b) #0 {
# | entry:
# |   %retval = alloca { float, float }, align 4
# |   %a = alloca { float, float }, align 4
# |   %b.addr = alloca float, align 4
# |   store <2 x float> %a.coerce, ptr %a, align 4
# |   store float %b, ptr %b.addr, align 4
# |   %a.realp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 0
# |   %a.real = load float, ptr %a.realp, align 4
# |   %a.imagp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 1
# |   %a.imag = load float, ptr %a.imagp, align 4
# |   %0 = load float, ptr %b.addr, align 4
# |   %1 = fdiv float %a.real, %0
# |   %2 = fdiv float %a.imag, %0
# |   %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0
# |   %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1
# |   store float %1, ptr %retval.realp, align 4
# |   store float %2, ptr %retval.imagp, align 4
# |   %3 = load <2 x float>, ptr %retval, align 4
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @divassignf(ptr noundef %a, float noundef %b) #1 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca float, align 4
# |   store ptr %a, ptr %a.addr, align 8
# |   store float %b, ptr %b.addr, align 4
# |   %0 = load float, ptr %b.addr, align 4
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %.realp = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 0
# |   %.real = load float, ptr %.realp, align 4
# |   %.imagp = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 1
# |   %.imag = load float, ptr %.imagp, align 4
# |   %2 = fdiv float %.real, %0
# |   %3 = fdiv float %.imag, %0
# |   %.realp1 = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 0
# |   %.imagp2 = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 1
# |   store float %2, ptr %.realp1, align 4
# |   store float %3, ptr %.imagp2, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local { double, double } @divd(double noundef %a.coerce0, double noundef %a.coerce1, double noundef %b) #1 {
# | entry:
# |   %retval = alloca { double, double }, align 8
# |   %a = alloca { double, double }, align 8
# |   %b.addr = alloca double, align 8
# |   %0 = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 0
# |   store double %a.coerce0, ptr %0, align 8
# |   %1 = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 1
# |   store double %a.coerce1, ptr %1, align 8
# |   store double %b, ptr %b.addr, align 8
# |   %a.realp = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 0
# |   %a.real = load double, ptr %a.realp, align 8
# |   %a.imagp = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 1
# |   %a.imag = load double, ptr %a.imagp, align 8
# |   %2 = load double, ptr %b.addr, align 8
# |   %3 = fdiv double %a.real, %2
# |   %4 = fdiv double %a.imag, %2
# |   %retval.realp = getelementptr inbounds nuw { double, double }, ptr %retval, i32 0, i32 0
# |   %retval.imagp = getelementptr inbounds nuw { double, double }, ptr %retval, i32 0, i32 1
# |   store double %3, ptr %retval.realp, align 8
# |   store double %4, ptr %retval.imagp, align 8
# |   %5 = load { double, double }, ptr %retval, align 8
# |   ret { double, double } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @divbd(double noundef %a, double noundef %b.coerce0, double noundef %b.coerce1) #0 {
# | entry:
# |   %retval = alloca { float, float }, align 4
# |   %b = alloca { double, double }, align 8
# |   %a.addr = alloca double, align 8
# |   %0 = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 0
# |   store double %b.coerce0, ptr %0, align 8
# |   %1 = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 1
# |   store double %b.coerce1, ptr %1, align 8
# |   store double %a, ptr %a.addr, align 8
# |   %2 = load double, ptr %a.addr, align 8
# |   %b.realp = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 0
# |   %b.real = load double, ptr %b.realp, align 8
# |   %b.imagp = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 1
# |   %b.imag = load double, ptr %b.imagp, align 8
# |   %call = call { double, double } @__divdc3(double noundef %2, double noundef 0.000000e+00, double noundef %b.real, double noundef %b.imag) #2
# |   %3 = extractvalue { double, double } %call, 0
# |   %4 = extractvalue { double, double } %call, 1
# |   %conv = fptrunc double %3 to float
# |   %conv1 = fptrunc double %4 to float
# |   %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0
# |   %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1
# |   store float %conv, ptr %retval.realp, align 4
# |   store float %conv1, ptr %retval.imagp, align 4
# |   %5 = load <2 x float>, ptr %retval, align 4
# |   ret <2 x float> %5
# | }
# | 
# | declare { double, double } @__divdc3(double, double, double, double)
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @divassignd(ptr noundef %a, double noundef %b) #1 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca double, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store double %b, ptr %b.addr, align 8
# |   %0 = load double, ptr %b.addr, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %.realp = getelementptr inbounds nuw { double, double }, ptr %1, i32 0, i32 0
# |   %.real = load double, ptr %.realp, align 8
# |   %.imagp = getelementptr inbounds nuw { double, double }, ptr %1, i32 0, i32 1
# |   %.imag = load double, ptr %.imagp, align 8
# |   %2 = fdiv double %.real, %0
# |   %3 = fdiv double %.imag, %0
# |   %.realp1 = getelementptr inbounds nuw { double, double }, ptr %1, i32 0, i32 0
# |   %.imagp2 = getelementptr inbounds nuw { double, double }, ptr %1, i32 0, i32 1
# |   store double %2, ptr %.realp1, align 8
# |   store double %3, ptr %.imagp2, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local { x86_fp80, x86_fp80 } @divld(ptr noundef byval({ x86_fp80, x86_fp80 }) align 16 %a, x86_fp80 noundef %b) #1 {
# | entry:
# |   %retval = alloca { x86_fp80, x86_fp80 }, align 16
# |   %b.addr = alloca x86_fp80, align 16
# |   store x86_fp80 %b, ptr %b.addr, align 16
# |   %a.realp = getelementptr inbounds nuw { x86_fp80, x86_fp80 }, ptr %a, i32 0, i32 0
# |   %a.real = load x86_fp80, ptr %a.realp, align 16
# |   %a.imagp = getelementptr inbounds nuw { x86_fp80, x86_fp80 }, ptr %a, i32 0, i32 1
# |   %a.imag = load x86_fp80, ptr %a.imagp, align 16
# |   %0 = load x86_fp80, ptr %b.addr, align 16
# |   %1 = fdiv x86_fp80 %a.real, %0
# |   %2 = fdiv x86_fp80 %a.imag, %0
# |   %retval.realp = getelementptr inbounds nuw { x86_fp80, x86_fp80 }, ptr %retval, i32 0, i32 0
# |   %retval.imagp = getelementptr inbounds nuw { x86_fp80, x86_fp80 }, ptr %retval, i32 0, i32 1
# |   store x86_fp80 %1, ptr %retval.realp, align 16
# |   store x86_fp80 %2, ptr %retval.imagp, align 16
# |   %3 = load { x86_fp80, x86_fp80 }, ptr %retval, align 16
# |   ret { x86_fp80, x86_fp80 } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @divassignld(ptr noundef %a, x86_fp80 noundef %b) #1 {
# | entry:
# |   %a.addr 
# | ...
# `---data was truncated (10240/11567) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055f2e6204eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f2e6201e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f2e620562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f581b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f581b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f581b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f581b231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f2e619abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f2e619aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f2e617f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f2e5e2ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f2e5e2eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f581b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f581b2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f581b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f2e5e2ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c --check-prefix=FULL
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c --check-prefix=FULL
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c (1017 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16m1x2(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16m2x2(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16m4x2(ptr noundef %base, <vscale x 16 x i16> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f32m1x2(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f32m2x2(ptr noundef %base, <vscale x
# | ...
# `---data was truncated (10240/129190) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d9a20f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d9a20f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d9a20f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab8ae1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab8ae725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab8ae1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab8ae03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d9a208ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d9a208ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d9a20738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d9a1d22e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d9a1d22b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fab8ae04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab8ae050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab8ae050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d9a1d22a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c (1018 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_i32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_i32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_u32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_u32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_f32mf2x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_f32m1x6_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("ri
# | ...
# `---data was truncated (10240/32023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005561e3c0feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005561e3c0ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005561e3c1062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe18fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe18faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe18fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe18fa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005561e3ba5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005561e3ba5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005561e3b8a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005561e3839e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005561e3839b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe18fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe18fa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe18fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005561e3839a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c (1019 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056290f0a8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056290f0a5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056290f0a962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f91c2c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f91c2ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f91c2c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f91c2c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056290f03ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056290f03ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056290f0238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056290ecd2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056290ecd2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f91c2c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f91c2c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f91c2c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056290ecd2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c (1020 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincd_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincd.n32(i32 %0, i32 31, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqincd.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincd_n_s32_1(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincd.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincd_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqincd.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqincd.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincd_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqincd.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqincd.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincd_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqincd.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uqincd.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincd_pat_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincd.n32(i32 %0, i32 9, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincd_pat_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqincd.n64(i64 %0, i32 10, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincd_pat_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqincd.n32(i32 %0, i32 11, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincd_pat_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqincd.n64(i64 %0, i32 12, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqincd_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.sqincd.nxv2i64(<vscale x 2 x i64> %0, i32 31, i32 16)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sqincd.nxv2i64(<vscale x 2 x i64>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqincd_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.uqincd.nxv2i64(<vscale x 2 x i64> %0, i32 31, i32 1)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uqincd.nxv2i64(<vscale x 2 x i64>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqincd_pat_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.sqincd.nxv2i64(<vscale x 2 x i64> %0, i32 13, i32 16)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqincd_pat_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.uqincd.nxv2i64(<vscale x 2 x i64> %0, i32 29, i32 1)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c7d763aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c7d7637e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c7d763b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1b31c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1b31c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1b31c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1b31c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c7d75d0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c7d75d0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c7d75b58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c7d7264e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c7d7264b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1b31c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1b31c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1b31c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c7d7264a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c (1021 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsac_vv_i8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsac_vx_i8mf8(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsac_vv_i8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsac_vx_i8mf4(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsac_vv_i8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsac_vx_i8mf2(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsac_vv_i8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsac_vx_i8m1(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnmsac_vv_i8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8
# | ...
# `---data was truncated (10240/208191) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005583d3b61eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005583d3b5ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005583d3b6262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb33ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb33ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb33ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb33ff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005583d3af7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005583d3af7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005583d3adc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005583d378be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005583d378bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb33ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb33ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb33ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005583d378ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c (1022 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8ff_v_i8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8ff_v_i8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8ff_v_i8m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_u8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8ff_v_u8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8ff_v_u8mf2
# | ...
# `---data was truncated (10240/54694) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055864befceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055864bef9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055864befd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2bd4d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2bd4d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2bd4d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2bd4d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055864be92bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055864be92a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055864be778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055864bb26e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055864bb26b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2bd4d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2bd4d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2bd4d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055864bb26a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c (1023 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4(<vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2(<vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1(<vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfneg_v_bf16m2(<vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfneg_v_bf16m4(<vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfneg_v_bf16m8(<vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfneg_v_bf16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscal
# | ...
# `---data was truncated (10240/13282) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055db87bf6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055db87bf3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055db87bf762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe1d5933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe1d598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe1d5933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe1d591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055db87b8cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055db87b8ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055db87b718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055db87820e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055db87820b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe1d591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe1d591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe1d591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055db87820a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c (1024 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_f16m1x2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_f16m2x2(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei8_v_f16m4x2(ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_f32m1x2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_f32m2x2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8
# | ...
# `---data was truncated (10240/113011) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561848580eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056184857de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056184858162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2865649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f28656a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2865649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2865631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561848516bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561848516a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005618484fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005618481aae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005618481aab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2865632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f28656330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f28656330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005618481aaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/neon-misc.c (1025 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-misc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon   -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vcgez_s8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = icmp sge <8 x i8> %1, zeroinitializer
# |   %vcgez.i = sext <8 x i1> %2 to <8 x i8>
# |   store <8 x i8> %vcgez.i, ptr %ref.tmp.i, align 8
# |   %3 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %3, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcgez_s16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x i16>
# |   %3 = icmp sge <4 x i16> %2, zeroinitializer
# |   %vcgez.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vcgez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vcgez_s32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <2 x i32>
# |   %3 = icmp sge <2 x i32> %2, zeroinitializer
# |   %vcgez.i = sext <2 x i1> %3 to <2 x i32>
# |   store <2 x i32> %vcgez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %4, ptr %__ret.i, align 8
# |   %5 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vcgez_s64(<1 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <1 x i64>
# |   %3 = icmp sge <1 x i64> %2, zeroinitializer
# |   %vcgez.i = sext <1 x i1> %3 to <1 x i64>
# |   store <1 x i64> %vcgez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <1 x i64>, ptr %ref.tmp.i, align 8
# |   store <1 x i64> %4, ptr %__ret.i, align 8
# |   %5 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vcgezq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = icmp sge <16 x i8> %1, zeroinitializer
# |   %vcgez.i = sext <16 x i1> %2 to <16 x i8>
# |   store <16 x i8> %vcgez.i, ptr %ref.tmp.i, align 16
# |   %3 = load <16 x i8>, ptr %ref.tmp.i, align 16
# |   store <16 x i8> %3, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcgezq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x i16>
# |   %3 = icmp sge <8 x i16> %2, zeroinitializer
# |   %vcgez.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vcgez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcgezq_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <4 x i32>
# |   %3 = icmp sge <4 x i32> %2, zeroinitializer
# |   %vcgez.i = sext <4 x i1> %3 to <4 x i32>
# |   store <4 x i32> %vcgez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %4, ptr %__ret.i, align 16
# |   %5 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vcgezq_s64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <2 x i64>
# |   %3 = icmp sge <2 x i64> %2, zeroinitializer
# |   %vcgez.i = sext <2 x i1> %3 to <2 x i64>
# |   store <2 x i64> %vcgez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <2 x i64>, ptr %ref.tmp.i, align 16
# |   store <2 x i64> %4, ptr %__ret.i, align 16
# |   %5 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vcgez_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <2 x float>
# |   %3 = fcmp oge <2 x float> %2, zeroinitializer
# |   %vcgez.i = sext <2 x i1> %3 to <2 x i32>
# |   store <2 x i32> %vcgez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %4, ptr %__ret.i, align 8
# |   %5 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vcgez_f64(<1 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <1 x double>
# |   %3 = fcmp oge <1 x double> %2, zeroinitializer
# |   %vcgez.i = sext <1 x i1> %3 to <1 x i64>
# |   store <1 x i64> %vcgez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <1 x i64>, ptr %ref.tmp.i, align 8
# |   store <1 x i64> %4, ptr %__ret.i, align 8
# |   %5 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcgezq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <4 x float>
# |   %3 = fcmp oge <4 x float> %2, zeroinitializer
# |   %vcgez.i = sext <4 x i1> %3 to <4 x i32>
# |   store <4 x i32> %vcgez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %4, ptr %__ret.i, align 16
# |   %5 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vcgezq_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <2 x double>
# |   %3 = fcmp oge <2 x double> %2, zeroinitializer
# |   %vcgez.i = sext <2 x i1> %3 to <2 x i64>
# |   store <2 x i64> %vcgez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <2 x i64>, ptr %ref.tmp.i, align 16
# |   store <2 x i64> %4, ptr %__ret.i, align 16
# |   %5 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vclez_s8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, ali
# | ...
# `---data was truncated (10240/217310) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005589cd377eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005589cd374e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005589cd37862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9ad1f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9ad1f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9ad1f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9ad1f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589cd30dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005589cd30da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005589cd2f28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005589ccfa1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005589ccfa1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9ad1f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9ad1f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9ad1f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005589ccfa1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c (1026 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2p2 -target-feature +f16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2p2 -target-feature +f16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_f16(<vscale x 8 x half> %acc, <vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
# | entry:
# |   %acc.addr = alloca <vscale x 8 x half>, align 16
# |   %a.addr = alloca <vscale x 8 x half>, align 16
# |   %b.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %acc, ptr %acc.addr, align 16
# |   store <vscale x 8 x half> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %acc.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %a.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %b.addr, align 16
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.fmmla.nxv8f16.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fmmla.nxv8f16.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f16mm,+sve,+sve2p2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560956440eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056095643de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056095644162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa6c761bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa6c76725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa6c761ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa6c7603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005609563d6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005609563d6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005609563bb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056095606ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056095606ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa6c7604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa6c76050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa6c76050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056095606aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c (1027 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei64_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ca039c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ca039c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ca039c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0d30049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0d300a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0d30049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0d30031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ca0395ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ca0395ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ca039438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ca035f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ca035f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0d30032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0d300330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0d300330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ca035f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c (1028 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee6f640eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ee6f63de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ee6f64162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff446533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff44658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff446533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff44651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee6f5d6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ee6f5d6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ee6f5bb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ee6f26ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ee6f26ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff44651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff44651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff44651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee6f26aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c (1029 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmflt_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmflt_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmflt_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64
# | ...
# `---data was truncated (10240/66565) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cf8daa1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cf8da9ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cf8daa262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3a78449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3a784a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3a78449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3a78431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf8da37bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cf8da37a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cf8da1c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cf8d6cbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cf8d6cbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3a78432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3a784330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3a784330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf8d6cba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c (1030 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1(<vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vx_u64m1(<vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmul_vv_u64m2(<vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmul_vx_u64m2(<vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmul_vv_u64m4(<vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmul_vx_u64m4(<vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmul_vv_u64m8(<vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmul_vx_u64m8(<vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vx_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |  
# | ...
# `---data was truncated (10240/18867) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056311ea1ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056311ea19e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056311ea1d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f54fab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54fab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f54fab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f54fab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056311e9b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056311e9b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056311e9978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056311e646e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056311e646b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f54fab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54fab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54fab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056311e646a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c (1031 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfwcvt_f_x_v_f16mf4(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfwcvt_f_x_v_f16mf2(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfwcvt_f_x_v_f16m1(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfwcvt_f_x_v_f16m2(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfwcvt_f_x_v_f16m4(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfwcvt_f_x_v_f16m8(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfwcvt_f_xu_v_f16mf4(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfwcvt_f_xu_v_f16mf2(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfwcvt_f_xu_v_f16m1(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfwcvt_f_xu_v_f16m2(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfwcvt_f_xu_v_f16m4(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfwcvt_f_xu_v_f16m8(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_x_f_v_i32mf2(<vscale x
# | ...
# `---data was truncated (10240/119289) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dee323feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dee323ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dee324062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac3681bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac368725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac3681ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac36803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dee31d5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dee31d5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dee31ba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dee2e69e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dee2e69b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fac36804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac368050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac368050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dee2e69a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c (1032 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulu_vv_u16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulu_vx_u16mf4(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulu_vv_u16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulu_vx_u16mf2(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulu_vv_u16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulu_vx_u16m1(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulu_vv_u16m2(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulu_vx_u16m2(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulu_vv_u16m4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulu_vx_u16m4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline n
# | ...
# `---data was truncated (10240/68255) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055da4a6e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055da4a6e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055da4a6e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa5dbd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa5dbd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa5dbd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa5dbd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da4a67abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055da4a67aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055da4a65f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055da4a30ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055da4a30eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa5dbd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa5dbd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa5dbd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da4a30ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/neon-vget-hilo.c (1033 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-vget-hilo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon   -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vget_high_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vget_high_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vget_high_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <4 x i32> %1, <4 x i32> %2, <2 x i32> <i32 2, i32 3>
# |   store <2 x i32> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vget_high_s64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> <i32 1>
# |   store <1 x i64> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vget_high_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vget_high_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vget_high_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <4 x i32> %1, <4 x i32> %2, <2 x i32> <i32 2, i32 3>
# |   store <2 x i32> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vget_high_u64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> <i32 1>
# |   store <1 x i64> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vget_high_p64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> <i32 1>
# |   store <1 x i64> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vget_high_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <4 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x half>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x half>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x half> %1, <8 x half> %2, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
# |   store <4 x half> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vget_high_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <4 x float> %1, <4 x float> %2, <2 x i32> <i32 2, i32 3>
# |   store <2 x float> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vget_high_p8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vget_high_p16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vget_high_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <1 x double>, align 8
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x double>, ptr %__p0.addr.i, align 16
# |   %2 = load <2 x double>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <2 x double> %1, <2 x double> %2, <1 x i32> <i32 1>
# |   store <1 x double> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <1 x double>, ptr %__ret.i, align 8
# |   ret <1 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vget_low_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = allo
# | ...
# `---data was truncated (10240/20383) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a5ca12feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a5ca12ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a5ca13062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f50f0b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f50f0b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f50f0b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f50f0b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a5ca0c5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a5ca0c5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a5ca0aa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a5c9d59e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a5c9d59b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f50f0b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f50f0b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f50f0b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a5c9d59a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c (1034 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16m1x2(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16m2x2(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16m4x2(ptr noundef %base, <vscale x 16 x i32> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f32m1x2(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f32m2x2(ptr noundef %base, <vscale x 4 x i32
# | ...
# `---data was truncated (10240/123655) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559c098bdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559c098bae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559c098be62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0d54933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0d5498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0d54933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0d5491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c09853bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559c09853a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559c098388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559c094e7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559c094e7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0d5491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0d5491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0d5491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c094e7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c (1035 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16ff_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16ff_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_i16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = e
# | ...
# `---data was truncated (10240/100513) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559494b17eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559494b14e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559494b1862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbdcee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbdceea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbdcee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbdcee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559494aadbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559494aada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559494a928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559494741e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559494741b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbdcee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbdcee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbdcee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559494741a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c (1036 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_f32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_f32m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_f32m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_f32m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_i32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_i32m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_i32m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_i32m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_u32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# | ...
# `---data was truncated (10240/30866) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005608337b0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005608337ade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005608337b162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba65e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba65ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba65e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba65e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560833746bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560833746a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056083372b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005608333dae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005608333dab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fba65e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba65e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba65e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005608333daa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c (1037 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_q_f8e4m3mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_q_f8e4m3mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_q_f8e4m3mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_f_f_q_f8e4m3m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_sat_f_f_q_f8e4m3m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_f_f_q_f8e4m3m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_sat_f_f_q_f8e4m3m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv
# | ...
# `---data was truncated (10240/165238) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a20ffc7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a20ffc4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a20ffc862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb196333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb19638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb196333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb19631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a20ff5dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a20ff5da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a20ff428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a20fbf1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a20fbf1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb19631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb19631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb19631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a20fbf1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c (1038 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_x_f_w_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_x_f_w_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_x_f_w_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_x_f_w_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_x_f_w_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_x_f_w_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_xu_f_w_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_xu_f_w_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_xu_f_w_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_xu_f_w_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = loa
# | ...
# `---data was truncated (10240/135111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056179f7e6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056179f7e3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056179f7e762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5a2d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5a2d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5a2d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5a2d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056179f77cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056179f77ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056179f7618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056179f410e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056179f410b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5a2d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5a2d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5a2d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056179f410a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c (1039 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 8 x i64>, ptr %rs2.addr
# | ...
# `---data was truncated (10240/20623) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a3c8b2feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a3c8b2ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a3c8b3062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6fc0249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6fc02a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6fc0249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6fc0231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a3c8ac5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a3c8ac5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a3c8aaa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a3c8759e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a3c8759b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6fc0232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6fc02330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6fc02330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a3c8759a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c (1040 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vxor_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vxor_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vxor_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vxor_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vxor_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vxor_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vxor_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vxor_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vxor_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vxor_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vxor_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/175155) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055baf009eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055baf009be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055baf009f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f89d4249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f89d42a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f89d4249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f89d4231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055baf0034bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055baf0034a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055baf00198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055baefcc8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055baefcc8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f89d4232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f89d42330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f89d42330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055baefcc8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/scalar-shifts.c (1041 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/scalar-shifts.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_asrl(i64 noundef %value, i32 noundef %shift) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   %shift.addr = alloca i32, align 4
# |   store i64 %value, ptr %value.addr, align 8
# |   store i32 %shift, ptr %shift.addr, align 4
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load i32, ptr %shift.addr, align 4
# |   %5 = call { i32, i32 } @llvm.arm.mve.asrl(i32 %3, i32 %2, i32 %4)
# |   %6 = extractvalue { i32, i32 } %5, 1
# |   %7 = zext i32 %6 to i64
# |   %8 = shl i64 %7, 32
# |   %9 = extractvalue { i32, i32 } %5, 0
# |   %10 = zext i32 %9 to i64
# |   %11 = or i64 %8, %10
# |   ret i64 %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.asrl(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_lsll(i64 noundef %value, i32 noundef %shift) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   %shift.addr = alloca i32, align 4
# |   store i64 %value, ptr %value.addr, align 8
# |   store i32 %shift, ptr %shift.addr, align 4
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load i32, ptr %shift.addr, align 4
# |   %5 = call { i32, i32 } @llvm.arm.mve.lsll(i32 %3, i32 %2, i32 %4)
# |   %6 = extractvalue { i32, i32 } %5, 1
# |   %7 = zext i32 %6 to i64
# |   %8 = shl i64 %7, 32
# |   %9 = extractvalue { i32, i32 } %5, 0
# |   %10 = zext i32 %9 to i64
# |   %11 = or i64 %8, %10
# |   ret i64 %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.lsll(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_sqrshr(i32 noundef %value, i32 noundef %shift) #0 {
# | entry:
# |   %value.addr = alloca i32, align 4
# |   %shift.addr = alloca i32, align 4
# |   store i32 %value, ptr %value.addr, align 4
# |   store i32 %shift, ptr %shift.addr, align 4
# |   %0 = load i32, ptr %value.addr, align 4
# |   %1 = load i32, ptr %shift.addr, align 4
# |   %2 = call i32 @llvm.arm.mve.sqrshr(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.sqrshr(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_sqrshrl(i64 noundef %value, i32 noundef %shift) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   %shift.addr = alloca i32, align 4
# |   store i64 %value, ptr %value.addr, align 8
# |   store i32 %shift, ptr %shift.addr, align 4
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load i32, ptr %shift.addr, align 4
# |   %5 = call { i32, i32 } @llvm.arm.mve.sqrshrl(i32 %3, i32 %2, i32 %4, i32 64)
# |   %6 = extractvalue { i32, i32 } %5, 1
# |   %7 = zext i32 %6 to i64
# |   %8 = shl i64 %7, 32
# |   %9 = extractvalue { i32, i32 } %5, 0
# |   %10 = zext i32 %9 to i64
# |   %11 = or i64 %8, %10
# |   ret i64 %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.sqrshrl(i32, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_sqrshrl_sat48(i64 noundef %value, i32 noundef %shift) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   %shift.addr = alloca i32, align 4
# |   store i64 %value, ptr %value.addr, align 8
# |   store i32 %shift, ptr %shift.addr, align 4
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load i32, ptr %shift.addr, align 4
# |   %5 = call { i32, i32 } @llvm.arm.mve.sqrshrl(i32 %3, i32 %2, i32 %4, i32 48)
# |   %6 = extractvalue { i32, i32 } %5, 1
# |   %7 = zext i32 %6 to i64
# |   %8 = shl i64 %7, 32
# |   %9 = extractvalue { i32, i32 } %5, 0
# |   %10 = zext i32 %9 to i64
# |   %11 = or i64 %8, %10
# |   ret i64 %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_sqshl(i32 noundef %value) #0 {
# | entry:
# |   %value.addr = alloca i32, align 4
# |   store i32 %value, ptr %value.addr, align 4
# |   %0 = load i32, ptr %value.addr, align 4
# |   %1 = call i32 @llvm.arm.mve.sqshl(i32 %0, i32 2)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.sqshl(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_sqshll(i64 noundef %value) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   store i64 %value, ptr %value.addr, align 8
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = call { i32, i32 } @llvm.arm.mve.sqshll(i32 %3, i32 %2, i32 17)
# |   %5 = extractvalue { i32, i32 } %4, 1
# |   %6 = zext i32 %5 to i64
# |   %7 = shl i64 %6, 32
# |   %8 = extractvalue { i32, i32 } %4, 0
# |   %9 = zext i32 %8 to i64
# |   %10 = or i64 %7, %9
# |   ret i64 %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.sqshll(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_srshr(i32 noundef %value) #0 {
# | entry:
# |   %value.addr = alloca i32, align 4
# |   store i32 %value, ptr %value.addr, align 4
# |   %0 = load i32, ptr %value.addr, align 4
# |   %1 = call i32 @llvm.arm.mve.srshr(i32 %0, i32 6)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.srshr(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_srshrl(i64 noundef %value) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   store i64 %value, ptr %value.addr, align 8
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = call { i32, i32 } @llvm.arm.mve.srshrl(i32 %3, i32 %2, i32 26)
# |   %5 = extractvalue { i32, i32 } %4, 1
# |   %6 = zext i32 %5 to i64
# |   %7 = shl i64 %6, 32
# |   %8 = extractvalue { i32, i32 } %4, 0
# |   %9 = zext i32 %8 to i64
# |   %10 = or i64 %7, %9
# |   ret i64 %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.srshrl(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_uqrshl(i32 noundef %value, i32 noundef %shift) #0 {
# | entry:
# |   %value.addr = alloca i32, align 4
# |   %shift.addr = alloca i32, align 4
# |   store i32 %value, ptr %value.addr, align 4
# |   store i32 %shift, ptr %shift.addr, align 4
# |   %0 = load i32, ptr %value.addr, align 4
# |   %1 = load i32, ptr %shift.addr, align 4
# |   %2 = call i32 @llvm.arm.mve.uqrshl(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.uqrshl(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_uqrshll(i64 noundef %value, i32 noundef %shift) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   %shift.addr = alloca i32, align 4
# |   store i64 %value, ptr %value.addr, align 8
# |   store i32 %shift, ptr %shift.addr, align 4
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load i32, ptr %shift.addr, align 4
# |   %5 = call { i32, i32 } @llvm.arm.mve.uqrshll(i32 %3, i32 %2, i32 %4, i32 64)
# |   %6 = extractvalue { i32, i32 } %5, 1
# |   %7 = zext i32 %6 to i64
# |   %8 = shl i64 %7, 32
# |   %9 = extractvalue { i32, i32 } %5, 0
# |   %10 = zext i32 %9 to i64
# |   %11 = or i64 %8, %10
# |   ret i64 %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.uqrshll(i32, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_uqrshll_sat48(i64 noundef %value, i32 noundef %shift) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   %shift.addr = alloca i32, align 4
# |   store i64 %value, ptr %value.addr, align 8
# |   store i32 %shift, ptr %shift.addr, align 4
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load i32, ptr %shift.addr, align 4
# |   %5 = call { i32, i32 } @llvm.arm.mve.uqrshll(i32 %3, i32 %2, i32 %4, i32 48)
# |   %6 = extractvalue { i32, i32 } %5, 1
# |   %7 = zext i32 %6 to i64
# |   %8 = shl i64 %7, 32
# |   %9 = extractvalue { i32, i32 } %5, 0
# |   %10 = zext i32 %9 to i64
# |   %11 = or i64 %8, %10
# |   ret i64 %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_uqshl(i32 noundef %value) #0 {
# | entry:
# |   %value.addr = alloca i32, align 4
# |   store i32 %value, ptr %value.addr, align 4
# |   %0 = load i32, ptr %value.addr, align 4
# |   %1 = call i32 @llvm.arm.mve.uqshl(i32 %0, i32 21)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.uqshl(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_uqshll(i64 noundef %value) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   store i64 %value, ptr %value.addr, align 8
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = call { i32, i32 } @llvm.arm.mve.uqshll(i32 %3, i32 %2, i32 16)
# |   %5 = extractvalue { i32, i32 } %4, 1
# |   %6 = zext i32 %5 to i64
# |   %7 = shl i64 %6, 32
# |   %8 = extractvalue { i32, i32 } %4, 0
# |   %9 = zext i32 %8 to i64
# |   %10 = or i64 %7, %9
# |   ret i64 %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.uqshll(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_urshr(i32 noundef %value) #0 {
# | entry:
# |   %value.addr = alloca i32, align 4
# |   store i32 %value, ptr %value.addr, align 4
# |   %0 = load i32, ptr %value.addr, align 4
# |   %1 = call i32 @llvm.arm.mve.urshr(i32 %0, i32 22)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nos
# | ...
# `---data was truncated (10240/11578) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005634e6989eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005634e6986e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005634e698a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6770b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6770b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6770b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6770b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005634e691fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005634e691fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005634e69048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005634e65b3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005634e65b3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6770b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6770b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6770b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005634e65b3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c (1042 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vzip_vv_f16mf2(<vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vzip_vv_f16m1(<vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vzip_vv_f16m2(<vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vzip_vv_f16m4(<vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vzip_vv_f16m8(<vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vzip_vv_f32m1(<vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vzip_vv_f32m2(<vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vzip_vv_f32m4(<vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vzip_vv_f32m8(<vscale x 8 x float> %vs2, <vscale x 8 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vzip.nxv16f32.nxv8f32.i64(<vscale x 16 x float> poison, <vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vzip.nxv16f32.nxv8f32.i64(<vscale x 16 x float>, <vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vzip_vv_f64m2(<vscale x 1 x double> %vs2, <vscale x 1 x double> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vs1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x double> %vs1, ptr %vs1.addr, align 8
# |   sto
# | ...
# `---data was truncated (10240/102864) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005594a55d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005594a55d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005594a55d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f79a6e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f79a6ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f79a6e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f79a6e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005594a556cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005594a556ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005594a55518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005594a5200e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005594a5200b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f79a6e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f79a6e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f79a6e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005594a5200a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c (1043 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_f16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_f16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_f16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_i16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_i16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_i16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_u16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_u16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_u16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale 
# | ...
# `---data was truncated (10240/23357) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c801d0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562c801cde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562c801d162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0d68849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0d688a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0d68849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0d68831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c80166bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562c80166a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562c8014b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562c7fdfae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562c7fdfab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0d68832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0d688330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0d688330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c7fdfaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c (1044 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrev8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrev8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrev8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrev8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrev8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrev8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrev8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrev8_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrev8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrev8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrev8_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrev8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrev8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vrev8_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vrev8.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrev8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vrev8_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vrev8.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrev8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vrev8_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vrev8.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrev8.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vrev8_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vrev8.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrev8.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vrev8_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vrev8.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrev8.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | d
# | ...
# `---data was truncated (10240/95223) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f3f8962eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f3f895fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f3f896362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f38d2933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f38d298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f38d2933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f38d291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f3f88f8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f3f88f8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f3f88dd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f3f858ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f3f858cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f38d291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f38d291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f38d291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f3f858ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c (1045 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f16m1x4(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f16m2x4(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f32m1x4(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f32m2x4(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f64m1x4(ptr noundef %base, <vscale x 1 x i64> %binde
# | ...
# `---data was truncated (10240/94227) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005612b3465eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005612b3462e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005612b346662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f01933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f0198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f01933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f0191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005612b33fbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005612b33fba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005612b33e08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005612b308fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005612b308fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6f0191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f0191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f0191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005612b308fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c (1046 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_4x8x4_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_4x8x4_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_4x8x4_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_4x8x4_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a52284feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a52284ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a52285062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f62d6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f62d6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f62d6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f62d6b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a5227e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a5227e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a5227ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a522479e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a522479b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f62d6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f62d6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f62d6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a522479a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c (1047 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_vv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_wv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_wx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_vv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_wv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_wx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsub_vv_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i
# | ...
# `---data was truncated (10240/306017) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555c39176eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555c39173e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555c3917762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff00c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff00ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff00c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff00c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555c3910cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555c3910ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555c390f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555c38da0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555c38da0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007eff00c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff00c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff00c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555c38da0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c (1048 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_i16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_i16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_i16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_u16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca 
# | ...
# `---data was truncated (10240/60551) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d84ad87eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d84ad84e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d84ad8862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f57e8c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57e8c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f57e8c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f57e8c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d84ad1dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d84ad1da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d84ad028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d84a9b1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d84a9b1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f57e8c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57e8c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57e8c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d84a9b1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c (1049 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f16m1x5(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f32m1x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f64m1x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef
# | ...
# `---data was truncated (10240/69988) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bad52a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bad52a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bad52a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2132b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2132b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2132b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2132aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bad523bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bad523ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bad52208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bad4ecfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bad4ecfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2132aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2132aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2132aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bad4ecfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c (1050 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f16m1x6(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f32m1x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f64m1x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i16> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c35dee6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c35dee3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c35dee762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f74ab933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f74ab98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f74ab933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f74ab91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c35de7cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c35de7ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c35de618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c35db10e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c35db10b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f74ab91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f74ab91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f74ab91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c35db10a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c (1051 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf8_u16m1(<vscale x 1 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> poison, <vscale x 1 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16>, <vscale x 1 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf4_u16m1(<vscale x 2 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> poison, <vscale x 2 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16>, <vscale x 2 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf2_u16m1(<vscale x 4 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m1_u16m1(<vscale x 8 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> poison, <vscale x 8 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16>, <vscale x 8 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m2_u16m1(<vscale x 16 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> poison, <vscale x 16 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16>, <vscale x 16 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m4_u16m1(<vscale x 32 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> poison, <vscale x 32 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16>, <vscale x 32 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m8_u16m1(<vscale x 64 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> poison, <vscale x 64 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16>, <vscale x 64 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsumu_vs_u16mf4_u32m1(<vscale x 1 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv1i16.i64(<vscale x 2 x i32> poison, <vscale x 1 x i16> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv1i16.i64(<vscale x 2 x i32>, <vscale x 1 x i16>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsumu_vs_u16mf2_u32m1(<vscale x 2 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsumu_vs_u16m1_u32m1(<vscale x 4 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 
# | ...
# `---data was truncated (10240/43617) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555a5ab90eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555a5ab8de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555a5ab9162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f82ada49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f82adaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f82ada49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f82ada31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555a5ab26bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555a5ab26a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555a5ab0b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555a5a7bae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555a5a7bab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f82ada32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f82ada330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f82ada330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555a5a7baa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c (1052 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f16m1x8(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f32m1x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f64m1x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei8_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vsca
# | ...
# `---data was truncated (10240/61665) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055726c995eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055726c992e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055726c99662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3bf861bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3bf86725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3bf861ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3bf8603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055726c92bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055726c92ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055726c9108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055726c5bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055726c5bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3bf8604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3bf86050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3bf86050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055726c5bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c (1053 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e807e01eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e807dfee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e807e0262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f66fd449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f66fd4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f66fd449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f66fd431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e807d97bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e807d97a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e807d7c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e807a2be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e807a2bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f66fd432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f66fd4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f66fd4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e807a2ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c (1054 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_f32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_f32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_i32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_i32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_u32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_u32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vsca
# | ...
# `---data was truncated (10240/15944) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005556ff15feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005556ff15ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005556ff16062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbb8f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbb8f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbb8f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbb8f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005556ff0f5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005556ff0f5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005556ff0da8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005556fed89e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005556fed89b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbb8f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbb8f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbb8f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005556fed89a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c (1055 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulh_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulh_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulh_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulh_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulh_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulh_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulh_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulh_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulh_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulh_vx_i8m4(<vscale x 32 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 64 x i8> @test_vmulh_vv_i8m8(<vscale x 64 x i8> %op1, <vscale x 64 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vsc
# | ...
# `---data was truncated (10240/65701) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055db68fd5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055db68fd2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055db68fd662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6b9dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6b9dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6b9dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6b9dc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055db68f6bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055db68f6ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055db68f508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055db68bffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055db68bffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6b9dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6b9dc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6b9dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055db68bffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c (1056 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vid_v_u8mf8(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8.i64(<vscale x 1 x i8> poison, i64 %0)
# |   ret <vscale x 1 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8.i64(<vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vid_v_u8mf4(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8.i64(<vscale x 2 x i8> poison, i64 %0)
# |   ret <vscale x 2 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8.i64(<vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vid_v_u8mf2(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8.i64(<vscale x 4 x i8> poison, i64 %0)
# |   ret <vscale x 4 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8.i64(<vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vid_v_u8m1(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8.i64(<vscale x 8 x i8> poison, i64 %0)
# |   ret <vscale x 8 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8.i64(<vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vid_v_u8m2(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8.i64(<vscale x 16 x i8> poison, i64 %0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8.i64(<vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vid_v_u8m4(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8.i64(<vscale x 32 x i8> poison, i64 %0)
# |   ret <vscale x 32 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8.i64(<vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vid_v_u8m8(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 64 x i8> @llvm.riscv.vid.nxv64i8.i64(<vscale x 64 x i8> poison, i64 %0)
# |   ret <vscale x 64 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vid.nxv64i8.i64(<vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vid_v_u16mf4(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16.i64(<vscale x 1 x i16> poison, i64 %0)
# |   ret <vscale x 1 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16.i64(<vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vid_v_u16mf2(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16.i64(<vscale x 2 x i16> poison, i64 %0)
# |   ret <vscale x 2 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16.i64(<vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vid_v_u16m1(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16.i64(<vscale x 4 x i16> poison, i64 %0)
# |   ret <vscale x 4 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16.i64(<vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vid_v_u16m2(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16.i64(<vscale x 8 x i16> poison, i64 %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16.i64(<vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vid_v_u16m4(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16.i64(<vscale x 16 x i16> poison, i64 %0)
# |   ret <vscale x 16 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16.i64(<vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vid_v_u16m8(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16.i64(<vscale x 32 x i16> poison, i64 %0)
# |   ret <vscale x 32 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16.i64(<vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vid_v_u32mf2(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 1 x i32> @llvm.riscv.vid.nxv1i32.i64(<vscale x 1 x i32> poison, i64 %0)
# |   ret <vscale x 1 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vid.nxv1i32.i64(<vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vid_v_u32m1(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 2 x i32> @llvm.riscv.vid.nxv2i32.i64(<vscale x 2 x i32> poison, i64 %0)
# |   ret <vscale x 2 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vid.nxv2i32.i64(<vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vid_v_u32m2(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 4 x i32> @llvm.riscv.vid.nxv4i32.i64(<vscale x 4 x i32> poison, i64 %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vid.nxv4i32.i64(<vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vid_v_u32m4(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 8 x i32> @llvm.riscv.vid.nxv8i32.i64(<vscale x 8 x i32> poison, i64 %0)
# |   ret <vscale x 8 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vid.nxv8i32.i64(<vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vid_v_u32m8(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 16 x i32> @llvm.riscv.vid.nxv16i32.i64(<vscale x 16 x i32> poison, i64 %0)
# |   ret <vscale x 16 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vid.nxv16i32.i64(<vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vid_v_u64m1(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align
# | ...
# `---data was truncated (10240/30303) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b7ed500eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b7ed4fde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b7ed50162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6540133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f654018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6540133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f654011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b7ed496bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b7ed496a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b7ed47b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b7ed12ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b7ed12ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f654011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f654011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f654011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b7ed12aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c (1057 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vneg_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vneg_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vneg_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vneg_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vneg_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vneg_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vneg_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vneg_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vneg_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vneg_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vr
# | ...
# `---data was truncated (10240/96265) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b781117eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b781114e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b78111862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd9c7249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd9c72a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd9c7249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd9c7231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b7810adbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b7810ada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b7810928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b780d41e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b780d41b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd9c7232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd9c72330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd9c72330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b780d41a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c (1058 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei8_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %m
# | ...
# `---data was truncated (10240/160133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cbbd6d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cbbd6d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cbbd6d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f64c6f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f64c6f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f64c6f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f64c6f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cbbd66cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cbbd66ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cbbd6518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cbbd300e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cbbd300b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f64c6f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f64c6f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f64c6f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cbbd300a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c (1059 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e32_v_f32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e32_v_f32m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_i32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_i32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e32_v_i32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,
# | ...
# `---data was truncated (10240/70979) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555d4411ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555d44119e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555d4411d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f019461bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f01946725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f019461ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0194603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555d440b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555d440b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555d440978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555d43d46e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555d43d46b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0194604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f01946050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f01946050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555d43d46a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c (1060 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svmov_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.and.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.and.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e4b806aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e4b8067e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e4b806b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0970533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f097058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0970533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f097051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e4b8000bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e4b8000a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e4b7fe58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e4b7c94e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e4b7c94b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f097051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f097051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f097051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e4b7c94a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c (1061 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnj_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnj_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnj_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnj_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnj_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnj_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnj_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnj_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnj_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnj.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnj.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnj_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnj.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x h
# | ...
# `---data was truncated (10240/69487) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005571105d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005571105d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005571105d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1b70d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1b70d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1b70d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1b70d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055711056cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055711056ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005571105518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557110200e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557110200b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1b70d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1b70d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1b70d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557110200a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c (1062 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsbc_vvm_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsbc_vxm_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsbc_vvm_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsbc_vxm_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsbc_vvm_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsbc_vxm_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsbc_vvm_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsbc_vxm_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, <vscale x 8 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsbc_vvm_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |  
# | ...
# `---data was truncated (10240/98589) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e1260a3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e1260a0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e1260a462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0a7c41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0a7c4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0a7c41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0a7c403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e126039bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e126039a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e12601e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e125ccde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e125ccdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0a7c404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0a7c4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0a7c4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e125ccda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c (1063 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4e
# | ...
# `---data was truncated (10240/228857) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c93ce2ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c93ce29e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c93ce2d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f32c1933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f32c198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f32c1933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f32c191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c93cdc2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c93cdc2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c93cda78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c93ca56e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c93ca56b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f32c191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f32c191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f32c191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c93ca56a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c (1064 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +v8.5a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +v8.5a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_rint32zf(float noundef %a) #0 {
# | entry:
# |   %__a.addr.i = alloca float, align 4
# |   %a.addr = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__a.addr.i, align 4
# |   %1 = load float, ptr %__a.addr.i, align 4
# |   %frint32z.i = call float @llvm.aarch64.frint32z.f32(float %1)
# |   ret float %frint32z.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_rint32z(double noundef %a) #0 {
# | entry:
# |   %__a.addr.i = alloca double, align 8
# |   %a.addr = alloca double, align 8
# |   store double %a, ptr %a.addr, align 8
# |   %0 = load double, ptr %a.addr, align 8
# |   store double %0, ptr %__a.addr.i, align 8
# |   %1 = load double, ptr %__a.addr.i, align 8
# |   %frint32z.i = call double @llvm.aarch64.frint32z.f64(double %1)
# |   ret double %frint32z.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_rint64zf(float noundef %a) #0 {
# | entry:
# |   %__a.addr.i = alloca float, align 4
# |   %a.addr = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__a.addr.i, align 4
# |   %1 = load float, ptr %__a.addr.i, align 4
# |   %frint64z.i = call float @llvm.aarch64.frint64z.f32(float %1)
# |   ret float %frint64z.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_rint64z(double noundef %a) #0 {
# | entry:
# |   %__a.addr.i = alloca double, align 8
# |   %a.addr = alloca double, align 8
# |   store double %a, ptr %a.addr, align 8
# |   %0 = load double, ptr %a.addr, align 8
# |   store double %0, ptr %__a.addr.i, align 8
# |   %1 = load double, ptr %__a.addr.i, align 8
# |   %frint64z.i = call double @llvm.aarch64.frint64z.f64(double %1)
# |   ret double %frint64z.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_rint32xf(float noundef %a) #0 {
# | entry:
# |   %__a.addr.i = alloca float, align 4
# |   %a.addr = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__a.addr.i, align 4
# |   %1 = load float, ptr %__a.addr.i, align 4
# |   %frint32x.i = call float @llvm.aarch64.frint32x.f32(float %1)
# |   ret float %frint32x.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_rint32x(double noundef %a) #0 {
# | entry:
# |   %__a.addr.i = alloca double, align 8
# |   %a.addr = alloca double, align 8
# |   store double %a, ptr %a.addr, align 8
# |   %0 = load double, ptr %a.addr, align 8
# |   store double %0, ptr %__a.addr.i, align 8
# |   %1 = load double, ptr %__a.addr.i, align 8
# |   %frint32x.i = call double @llvm.aarch64.frint32x.f64(double %1)
# |   ret double %frint32x.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_rint64xf(float noundef %a) #0 {
# | entry:
# |   %__a.addr.i = alloca float, align 4
# |   %a.addr = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__a.addr.i, align 4
# |   %1 = load float, ptr %__a.addr.i, align 4
# |   %frint64x.i = call float @llvm.aarch64.frint64x.f32(float %1)
# |   ret float %frint64x.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_rint64x(double noundef %a) #0 {
# | entry:
# |   %__a.addr.i = alloca double, align 8
# |   %a.addr = alloca double, align 8
# |   store double %a, ptr %a.addr, align 8
# |   %0 = load double, ptr %a.addr, align 8
# |   store double %0, ptr %__a.addr.i, align 8
# |   %1 = load double, ptr %__a.addr.i, align 8
# |   %frint64x.i = call double @llvm.aarch64.frint64x.f64(double %1)
# |   ret double %frint64x.i
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.frint32z.f32(float) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.frint32z.f64(double) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.frint64z.f32(float) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.frint64z.f64(double) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.frint32x.f32(float) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.frint32x.f64(double) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.frint64x.f32(float) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.frint64x.f64(double) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+jsconv,+lse,+neon,+pauth,+predres,+ras,+rcpc,+rdm,+sb,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8a" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d0c8b76eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d0c8b73e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d0c8b7762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efd67b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efd67b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efd67b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efd67b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0c8b0cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d0c8b0ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d0c8af18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d0c87a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d0c87a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efd67b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efd67b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efd67b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d0c87a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c (1065 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16m1x2(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16m2x2(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16m4x2(ptr noundef %base, <vscale x 16 x i8> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f32m1x2(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f32m2x2(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_t
# | ...
# `---data was truncated (10240/128436) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f1cc46ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f1cc469e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f1cc46d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2003533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f200358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2003533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f200351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f1cc402bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f1cc402a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f1cc3e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f1cc096e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f1cc096b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f200351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f200351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f200351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f1cc096a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c (1066 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564c6247deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564c6247ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564c6247e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f06d2505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f06d255c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f06d2505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f06d24ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c62413bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564c62413a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564c623f88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564c620a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564c620a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f06d24eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f06d24ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f06d24ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c620a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c (1067 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f16m1x6(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f32m1x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f64m1x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055834edf7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055834edf4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055834edf862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f52f4849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f52f48a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f52f4849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f52f4831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055834ed8dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055834ed8da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055834ed728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055834ea21e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055834ea21b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f52f4832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f52f48330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f52f48330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055834ea21a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c (1068 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei8_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8
# | ...
# `---data was truncated (10240/160141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056121162aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561211627e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056121162b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa19e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa19e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa19e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa19e431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005612115c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005612115c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005612115a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561211254e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561211254b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa19e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa19e4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa19e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561211254a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c (1069 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasub_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasub_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasub_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasub_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasub_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasub_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasub_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasub_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasub_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, al
# | ...
# `---data was truncated (10240/225213) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cc7f041eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cc7f03ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cc7f04262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5e32b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5e32b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5e32b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5e32b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc7efd7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cc7efd7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cc7efbc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cc7ec6be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cc7ec6bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5e32b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5e32b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5e32b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc7ec6ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c (1070 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_i32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_i32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_u32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_u32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_f32mf2x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple"
# | ...
# `---data was truncated (10240/35929) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005608fd611eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005608fd60ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005608fd61262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa942249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa9422a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa942249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa942231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005608fd5a7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005608fd5a7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005608fd58c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005608fd23be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005608fd23bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa942232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa9422330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa9422330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005608fd23ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vldr.c (1071 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vldr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrwq_gather_base_wb_s32(ptr noundef %addr) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = load <4 x i32>, ptr %0, align 8
# |   %2 = call { <4 x i32>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4i32.v4i32(<4 x i32> %1, i32 80)
# |   %3 = extractvalue { <4 x i32>, <4 x i32> } %2, 1
# |   store <4 x i32> %3, ptr %0, align 8
# |   %4 = extractvalue { <4 x i32>, <4 x i32> } %2, 0
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare { <4 x i32>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4i32.v4i32(<4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vldrwq_gather_base_wb_f32(ptr noundef %addr) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = load <4 x i32>, ptr %0, align 8
# |   %2 = call { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4f32.v4i32(<4 x i32> %1, i32 64)
# |   %3 = extractvalue { <4 x float>, <4 x i32> } %2, 1
# |   store <4 x i32> %3, ptr %0, align 8
# |   %4 = extractvalue { <4 x float>, <4 x i32> } %2, 0
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4f32.v4i32(<4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vldrdq_gather_base_wb_z_u64(ptr noundef %addr, i16 noundef zeroext %p) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %addr, ptr %addr.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = load <2 x i64>, ptr %0, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3)
# |   %5 = call { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v2i64.v2i64.v2i1(<2 x i64> %1, i32 656, <2 x i1> %4)
# |   %6 = extractvalue { <2 x i64>, <2 x i64> } %5, 1
# |   store <2 x i64> %6, ptr %0, align 8
# |   %7 = extractvalue { <2 x i64>, <2 x i64> } %5, 0
# |   ret <2 x i64> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v2i64.v2i64.v2i1(<2 x i64>, i32, <2 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dd16f17eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dd16f14e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dd16f1862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe386533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe38658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe386533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe38651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd16eadbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dd16eada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dd16e928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dd16b41e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dd16b41b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe38651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe38651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe38651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd16b41a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/distributed-thin-lto/backend-skip.ll (1072 of 27911)
******************** TEST 'Clang :: CodeGen/distributed-thin-lto/backend-skip.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 6
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/backend-skip.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/backend-skip.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/backend-skip.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/backend-skip.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/backend-skip.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/backend-skip.ll
# |  #0 0x000055ac2bf64eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ac2bf61e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ac2bf6562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fda5a105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fda5a15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fda5a105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fda5a0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac2befabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ac2befaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ac2bedf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ac2bb8ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ac2bb8eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fda5a0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fda5a0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fda5a0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac2bb8ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c (1073 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f16m1x8(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f32m1x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f64m1x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556539e37eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556539e34e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556539e3862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbbe7133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbbe718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbbe7133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbbe711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556539dcdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556539dcda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556539db28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556539a61e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556539a61b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbbe711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbbe711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbbe711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556539a61a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c (1074 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f16m1x4(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_f16m2x4(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f32m1x4(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_f32m2x4(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f64m1x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/87892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056137992aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561379927e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056137992b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f241b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f241b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f241b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f241b231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005613798c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005613798c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005613798a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561379554e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561379554b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f241b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f241b2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f241b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561379554a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c (1075 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8mf8x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_u8mf8x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_u8mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_u8mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_u8m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, a
# | ...
# `---data was truncated (10240/26721) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557acc4f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557acc4f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557acc4f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd631f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd631f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd631f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd631f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557acc48abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557acc48aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557acc46f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557acc11ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557acc11eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd631f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd631f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd631f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557acc11ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c (1076 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgtu_vv_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgtu_vx_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgtu_vv_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgtu_vx_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgtu_vv_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgtu_vx_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgtu_vv_u8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vsca
# | ...
# `---data was truncated (10240/63705) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557fbf346eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557fbf343e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557fbf34762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f701a41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f701a4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f701a41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f701a403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557fbf2dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557fbf2dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557fbf2c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557fbef70e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557fbef70b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f701a404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f701a4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f701a4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557fbef70a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/neon-vcmla.c (1077 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-vcmla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64 -target-feature +neon         -target-feature +v8.3a         -target-feature +fullfp16         -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes="mem2reg,instsimplify,sroa" | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64 -target-feature +neon -target-feature +v8.3a -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vcmla_f16(<4 x half> noundef %acc, <4 x half> noundef %lhs, <4 x half> noundef %rhs) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %acc.addr = alloca <4 x half>, align 8
# |   %lhs.addr = alloca <4 x half>, align 8
# |   %rhs.addr = alloca <4 x half>, align 8
# |   store <4 x half> %acc, ptr %acc.addr, align 8
# |   store <4 x half> %lhs, ptr %lhs.addr, align 8
# |   store <4 x half> %rhs, ptr %rhs.addr, align 8
# |   %0 = load <4 x half>, ptr %acc.addr, align 8
# |   %1 = load <4 x half>, ptr %lhs.addr, align 8
# |   %2 = load <4 x half>, ptr %rhs.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vcmla_f16.i = bitcast <8 x i8> %3 to <4 x half>
# |   %vcmla_f161.i = bitcast <8 x i8> %4 to <4 x half>
# |   %vcmla_f162.i = bitcast <8 x i8> %5 to <4 x half>
# |   %vcmla_f163.i = call <4 x half> @llvm.aarch64.neon.vcmla.rot0.v4f16(<4 x half> %vcmla_f16.i, <4 x half> %vcmla_f161.i, <4 x half> %vcmla_f162.i)
# |   %vcmla_f164.i = bitcast <4 x half> %vcmla_f163.i to <8 x i8>
# |   store <8 x i8> %vcmla_f164.i, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vcmla_f32(<2 x float> noundef %acc, <2 x float> noundef %lhs, <2 x float> noundef %rhs) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__p2.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %acc.addr = alloca <2 x float>, align 8
# |   %lhs.addr = alloca <2 x float>, align 8
# |   %rhs.addr = alloca <2 x float>, align 8
# |   store <2 x float> %acc, ptr %acc.addr, align 8
# |   store <2 x float> %lhs, ptr %lhs.addr, align 8
# |   store <2 x float> %rhs, ptr %rhs.addr, align 8
# |   %0 = load <2 x float>, ptr %acc.addr, align 8
# |   %1 = load <2 x float>, ptr %lhs.addr, align 8
# |   %2 = load <2 x float>, ptr %rhs.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   store <2 x float> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vcmla_f32.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vcmla_f321.i = bitcast <8 x i8> %4 to <2 x float>
# |   %vcmla_f322.i = bitcast <8 x i8> %5 to <2 x float>
# |   %vcmla_f323.i = call <2 x float> @llvm.aarch64.neon.vcmla.rot0.v2f32(<2 x float> %vcmla_f32.i, <2 x float> %vcmla_f321.i, <2 x float> %vcmla_f322.i)
# |   %vcmla_f324.i = bitcast <2 x float> %vcmla_f323.i to <8 x i8>
# |   store <8 x i8> %vcmla_f324.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vcmlaq_f16(<8 x half> noundef %acc, <8 x half> noundef %lhs, <8 x half> noundef %rhs) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %acc.addr = alloca <8 x half>, align 16
# |   %lhs.addr = alloca <8 x half>, align 16
# |   %rhs.addr = alloca <8 x half>, align 16
# |   store <8 x half> %acc, ptr %acc.addr, align 16
# |   store <8 x half> %lhs, ptr %lhs.addr, align 16
# |   store <8 x half> %rhs, ptr %rhs.addr, align 16
# |   %0 = load <8 x half>, ptr %acc.addr, align 16
# |   %1 = load <8 x half>, ptr %lhs.addr, align 16
# |   %2 = load <8 x half>, ptr %rhs.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vcmlaq_f16.i = bitcast <16 x i8> %3 to <8 x half>
# |   %vcmlaq_f161.i = bitcast <16 x i8> %4 to <8 x half>
# |   %vcmlaq_f162.i = bitcast <16 x i8> %5 to <8 x half>
# |   %vcmlaq_f163.i = call <8 x half> @llvm.aarch64.neon.vcmla.rot0.v8f16(<8 x half> %vcmlaq_f16.i, <8 x half> %vcmlaq_f161.i, <8 x half> %vcmlaq_f162.i)
# |   %vcmlaq_f164.i = bitcast <8 x half> %vcmlaq_f163.i to <16 x i8>
# |   store <16 x i8> %vcmlaq_f164.i, ptr %ref.tmp.i, align 16
# |   %6 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %6, ptr %__ret.i, align 16
# |   %7 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vcmlaq_f32(<4 x float> noundef %acc, <4 x float> noundef %lhs, <4 x float> noundef %rhs) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__p2.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %acc.addr = alloca <4 x float>, align 16
# |   %lhs.addr = alloca <4 x float>, align 16
# |   %rhs.addr = alloca <4 x float>, align 16
# |   store <4 x float> %acc, ptr %acc.addr, align 16
# |   store <4 x float> %lhs, ptr %lhs.addr, align 16
# |   store <4 x float> %rhs, ptr %rhs.addr, align 16
# |   %0 = load <4 x float>, ptr %acc.addr, align 16
# |   %1 = load <4 x float>, ptr %lhs.addr, align 16
# |   %2 = load <4 x float>, ptr %rhs.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   store <4 x float> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vcmlaq_f32.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vcmlaq_f321.i = bitcast <16 x i8> %4 to <4 x float>
# |   %vcmlaq_f322.i = bitcast <16 x i8> %5 to <4 x float>
# |   %vcmlaq_f323.i = call <4 x float> @llvm.aarch64.neon.vcmla.rot0.v4f32(<4 x float> %vcmlaq_f32.i, <4 x float> %vcmlaq_f321.i, <4 x float> %vcmlaq_f322.i)
# |   %vcmlaq_f324.i = bitcast <4 x float> %vcmlaq_f323.i to <16 x i8>
# |   store <16 x i8> %vcmlaq_f324.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vcmlaq_f64(<2 x double> noundef %acc, <2 x double> noundef %lhs, <2 x double> noundef %rhs) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__p1.addr.i = alloca <2 x double>, align 16
# |   %__p2.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %acc.addr = alloca <2 x double>, align 16
# |   %lhs.addr = alloca <2 x double>, align 16
# |   %rhs.addr = alloca <2 x double>, align 16
# |   store <2 x double> %acc, ptr %acc.addr, align 16
# |   store <2 x double> %lhs, ptr %lhs.addr, align 16
# |   store <2 x double> %rhs, ptr %rhs.addr, align 16
# |   %0 = load <2 x double>, ptr %acc.addr, align 16
# |   %1 = load <2 x double>, ptr %lhs.addr, align 16
# |   %2 = load <2 x double>, ptr %rhs.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   store <2 x double> %1, ptr %__p1.addr.i, align 16
# |   store <2 x double> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vcmlaq_f64.i = bitcast <16 x i8> %3 to <2 x double>
# |   %vcmlaq_f641.i = bitcast <16 x i8> %4 to <2 x double>
# |   %vcmlaq_f642.i = bitcast <16 x i8> %5 to <2 x double>
# |   %vcmlaq_f643.i = call <2 x double> @llvm.aarch64.neon.vcmla.rot0.v2f64(<2 x double> %vcmlaq_f64.i, <2 x double> %vcmlaq_f641.i, <2 x double> %vcmlaq_f642.i)
# |   %vcmlaq_f644.i = bitcast <2 x double> %vcmlaq_f643.i to <16 x i8>
# |   store <16 x i8> %vcmlaq_f644.i, ptr %ref.tmp.i, align 16
# |   %6 = load <2 x double>, ptr %ref.tmp.i, align 16
# |   store <2 x double> %6, ptr %__ret.i, align 16
# |   %7 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vcmla_rot90_f16(<4 x half> noundef %acc, <4 x half> noundef %lhs, <4 x half> noundef %rhs) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %acc.addr = alloca <4 x half>, align 8
# |   %lhs.addr = alloca <4 x half>, align 8
# |   %rhs.addr = alloca <4 x half>, align 8
# |   store <4 x half> %acc, ptr %acc.addr, align 8
# |   store <4 x half> %lhs, ptr %lhs.addr, align 8
# |   store <4 x half> %rhs, ptr %rhs.addr, align 8
# |   %0 = load <4 x half>, ptr %acc.addr, align 8
# |   %1 = load <4 x half>, ptr %lhs.addr, align 8
# |   %2 = load <4 x half>, ptr %rhs.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vcmla_rot90_f16.i = bitcast <8 x i8> %3 to <4 x half>
# |   %vcmla_rot90_f161.i = bitcast <8 x i8> %4 to <4 x half>
# |   %vcmla_rot90_f162.i = bitcast <8 x i8> %5 to <4 x half>
# |   %vcmla_rot90_f163.i = call <4 x half> @llvm.aarch64.neon.vcmla.rot90.v
# | ...
# `---data was truncated (10240/166298) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instsimplify,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instsimplify,sroa
# |  #0 0x000055cc863d2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cc863cfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cc863d362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd255133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd25518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd255133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd25511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc86368bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cc86368a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cc8634d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cc85ffce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cc85ffcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd25511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd25511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd25511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc85ffca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c (1078 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f16m1x8(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f32m1x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f64m1x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei64_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557e9130ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557e91309e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557e9130d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9f6a61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9f6a6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9f6a61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9f6a603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e912a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557e912a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557e912878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557e90f36e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557e90f36b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9f6a604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9f6a6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9f6a6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e90f36a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c (1079 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_vv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_vx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_wv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_wx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_vv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_vx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_wv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_wx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsubu_vv_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.ad
# | ...
# `---data was truncated (10240/306619) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056511da72eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056511da6fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056511da7362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb8e4b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb8e4b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb8e4b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb8e4b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056511da08bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056511da08a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056511d9ed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056511d69ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056511d69cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb8e4b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb8e4b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb8e4b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056511d69ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c (1080 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv1i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv1i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8ff_v_i8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8ff_v_i8mf2x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8ff_v_i8m1x6_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_u8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv1i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8ff_v_u8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8ff_v_u8mf2x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>,
# | ...
# `---data was truncated (10240/12668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cec70d3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cec70d0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cec70d462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce98505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce9855c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce98505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce984ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cec7069bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cec7069a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cec704e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cec6cfde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cec6cfdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fce984eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce984ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce984ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cec6cfda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c (1081 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvsintload -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vlnu8_v_u8m1_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.nds.vlnu.mask.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vlnu.mask.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vlnu8_v_u8m2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.nds.vlnu.mask.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.nds.vlnu.mask.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i8> @test_nds_vlnu8_v_u8m4_m(<vscale x 32 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.nds.vlnu.mask.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %1, <vscale x 32 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.nds.vlnu.mask.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_nds_vlnu8_v_u8m8_m(<vscale x 64 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.nds.vlnu.mask.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %1, <vscale x 64 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.nds.vlnu.mask.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), <vscale x 64 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xandesvsintload,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xandesvsintload5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ecdf493eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ecdf490e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ecdf49462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb718d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb718d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb718d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb718d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ecdf429bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ecdf429a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ecdf40e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ecdf0bde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ecdf0bdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb718d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb718d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb718d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ecdf0bda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c (1082 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055975c5f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055975c5efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055975c5f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f44f1333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f44f138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f44f1333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f44f131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055975c588bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055975c588a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055975c56d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055975c21ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055975c21cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f44f131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44f131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44f131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055975c21ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c (1083 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb1d19ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fb1d199e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fb1d19d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f151af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f151af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f151af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f151af1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb1d132bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fb1d132a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fb1d1178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fb1cdc6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fb1cdc6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f151af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f151af1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f151af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb1cdc6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c (1084 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwi
# | ...
# `---data was truncated (10240/44369) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d33a2d0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d33a2cde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d33a2d162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f26f3e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f26f3ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f26f3e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f26f3e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d33a266bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d33a266a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d33a24b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d339efae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d339efab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f26f3e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f26f3e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f26f3e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d339efaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c (1085 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.
# | ...
# `---data was truncated (10240/16808) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005618de8dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005618de8dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005618de8e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3fcbb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3fcbb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3fcbb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3fcbb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005618de875bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005618de875a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005618de85a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005618de509e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005618de509b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3fcbb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3fcbb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3fcbb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005618de509a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/mozilla-ms-inline-asm.c (1086 of 27911)
******************** TEST 'Clang :: CodeGen/mozilla-ms-inline-asm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c -triple i386-apple-darwin10 -fasm-blocks -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=strip -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c -triple i386-apple-darwin10 -fasm-blocks -emit-llvm -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c"
# | target datalayout = "e-m:o-p:32:32-p270:32:32-p271:32:32-p272:64:64-i128:128-f64:32:64-f80:128-n8:16:32-S128"
# | target triple = "i386-apple-darwin10"
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define void @invoke_copy_to_stack() #0 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define void @invoke(ptr noundef %that, i32 noundef %methodIndex, i32 noundef %paramCount, ptr noundef %params) #0 {
# | entry:
# |   %that.addr = alloca ptr, align 4
# |   %methodIndex.addr = alloca i32, align 4
# |   %paramCount.addr = alloca i32, align 4
# |   %params.addr = alloca ptr, align 4
# |   store ptr %that, ptr %that.addr, align 4
# |   store i32 %methodIndex, ptr %methodIndex.addr, align 4
# |   store i32 %paramCount, ptr %paramCount.addr, align 4
# |   store ptr %params, ptr %params.addr, align 4
# |   call void asm sideeffect inteldialect "mov edx,$1\0A\09test edx,edx\0A\09jz L__MSASMLABEL_.${:uid}__noparams\0A\09mov eax,edx\0A\09shl eax,$$3\0A\09sub esp,eax\0A\09mov ecx,esp\0A\09push $0\0A\09call ${2:P}\0A\09L__MSASMLABEL_.${:uid}__noparams:\0A\09mov ecx,$3\0A\09push ecx\0A\09mov edx,[ecx]\0A\09mov eax,$4\0A\09call dword ptr[edx + eax * $$4]\0A\09mov esp,ebp\0A\09pop ebp\0A\09ret", "=*m,*m,*m,*m,*m,~{eax},~{ebp},~{ecx},~{edx},~{flags},~{esp},~{dirflag},~{fpsr},~{flags}"(ptr elementtype(ptr) %params.addr, ptr elementtype(i32) %paramCount.addr, ptr elementtype(void (...)) @invoke_copy_to_stack, ptr elementtype(ptr) %that.addr, ptr elementtype(i32) %methodIndex.addr) #1, !srcloc !2
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+x87" }
# | attributes #1 = { nounwind }
# | 
# | !llvm.module.flags = !{!0}
# | !llvm.ident = !{!1}
# | 
# | !0 = !{i32 1, !"NumRegisterParameters", i32 0}
# | !1 = !{!"clang version 24.0.0"}
# | !2 = !{i64 1623}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=strip -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=strip -S
# |  #0 0x000055c1d0f4ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c1d0f49e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c1d0f4d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7ebc933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7ebc98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7ebc933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7ebc91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c1d0ee2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c1d0ee2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c1d0ec78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c1d0b76e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c1d0b76b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7ebc91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7ebc91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7ebc91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c1d0b76a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c (1087 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgather_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %index.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgather_vx_f16mf4(<vscale x 1 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgather_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %index.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgather_vx_f16mf2(<vscale x 2 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgather_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %index.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgather_vx_f16m1(<vscale x 4 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgather_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgather_vx_f16m2(<vscale x 8 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgather_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vrgather.vv.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vrgather.vv.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgather_vx_f16m4(<vscale x 16 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vrgather.vx.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwin
# | ...
# `---data was truncated (10240/273705) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562f57084eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562f57081e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562f5708562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3f10f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3f10f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3f10f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3f10f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562f5701abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562f5701aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562f56fff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562f56caee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562f56caeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3f10f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3f10f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3f10f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562f56caea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c (1088 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsadd_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsadd_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsadd_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsadd_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsadd_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsadd_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsadd_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsadd_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsadd_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsadd_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsadd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsadd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsadd_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/97913) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563d9ab0deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563d9ab0ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563d9ab0e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa6ba733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa6ba78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa6ba733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa6ba71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d9aaa3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563d9aaa3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563d9aa888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563d9a737e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563d9a737b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa6ba71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa6ba71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa6ba71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d9a737a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c (1089 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vsext_vf2_i16mf4(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vsext_vf2_i16mf2(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vsext_vf2_i16m1(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vsext_vf2_i16m2(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vsext_vf2_i16m4(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vsext_vf2_i16m8(<vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf2_i32mf2(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf2_i32m1(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf2_i32m2(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vsext_vf2_i32m4(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vsext_vf2_i32m8(<vscale x 16 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf2_i64m1(<vscale x 1 x i32> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf2_i64m2(<vscale x 2 x i32> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>,
# | ...
# `---data was truncated (10240/28571) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563a769e8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563a769e5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563a769e962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9ed1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9ed1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9ed1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9ed1b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a7697ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563a7697ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563a769638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563a76612e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563a76612b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9ed1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9ed1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9ed1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a76612a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c (1090 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrem_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrem_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrem_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrem_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrem_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrem_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrem_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrem_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrem_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/222475) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056336e2e0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056336e2dde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056336e2e162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe796b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe796b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe796b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe796b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056336e276bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056336e276a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056336e25b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056336df0ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056336df0ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe796b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe796b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe796b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056336df0aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c (1091 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4e
# | ...
# `---data was truncated (10240/228857) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c37495ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c374959e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c37495d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1b11d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1b11d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1b11d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1b11d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c3748f2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c3748f2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c3748d78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c374586e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c374586b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1b11d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1b11d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1b11d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c374586a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c (1092 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> %0, <vscale x 32 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale
# | ...
# `---data was truncated (10240/410383) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005557766a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005557766a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005557766a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efd85b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efd85b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efd85b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efd85b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055577663cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055577663ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005557766218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005557762d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005557762d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efd85b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efd85b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efd85b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005557762d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c (1093 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsub_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.sub.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.sub.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsub_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.sub.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sub.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsub_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.sub.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sub.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svsub_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.sub.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sub.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsub_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.sub.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsub_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.sub.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsub_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.sub.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svsub_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.sub.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsub_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, pt
# | ...
# `---data was truncated (10240/72449) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005588dcf90eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005588dcf8de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005588dcf9162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6bd0049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6bd00a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6bd0049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6bd0031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005588dcf26bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005588dcf26a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005588dcf0b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005588dcbbae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005588dcbbab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6bd0032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6bd00330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6bd00330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005588dcbbaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c (1094 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvpackfph -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadb_vf_f16mf4(<vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadb_vf_f16mf2(<vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadb_vf_f16m1(<vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadb_vf_f16m2(<vscale x 8 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half>, <vscale x 8 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_nds_vfpmadb_vf_f16m4(<vscale x 16 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half>, <vscale x 16 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_nds_vfpmadb_vf_f16m8(<vscale x 32 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half>, <vscale x 32 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadb_vf_f16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %1, float %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadb_vf_f16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %1, float %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadb_vf_f16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %1, float %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadb_vf_f16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x half> %op1, fl
# | ...
# `---data was truncated (10240/25099) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565101c2aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565101c27e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000565101c2b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e04505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e0455c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e04505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e044ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565101bc0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565101bc0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000565101ba58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565101854e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565101854b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8e044eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e044ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e044ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565101854a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c (1095 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vx_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmulh_vv_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmulh_vx_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmulh_vv_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmulh_vx_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmulh_vv_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmulh_vx_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %m
# | ...
# `---data was truncated (10240/41661) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557bbbc8ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557bbbc89e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557bbbc8d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa27d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa27d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa27d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa27d831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557bbbc22bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557bbbc22a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557bbbc078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557bbb8b6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557bbb8b6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa27d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa27d8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa27d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557bbb8b6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c (1096 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c0152aeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c0152abe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c0152af62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4a5bc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4a5bca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4a5bc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4a5bc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c015244bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c015244a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c0152298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c014ed8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c014ed8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4a5bc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4a5bc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4a5bc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c014ed8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c (1097 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_i32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_i32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_u32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_u32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_f32mf2x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedof
# | ...
# `---data was truncated (10240/40734) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005611a0888eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005611a0885e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005611a088962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f07b6505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f07b655c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f07b6505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f07b64ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005611a081ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005611a081ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005611a08038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005611a04b2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005611a04b2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f07b64eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f07b64ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f07b64ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005611a04b2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c (1098 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsac_vv_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsac_vx_i8mf8_tu(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsac_vv_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsac_vx_i8mf4_tu(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsac_vv_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsac_vx_i8mf2_tu(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsac_vv_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsac_vx_i8m1_tu(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnmsac_vv_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = loa
# | ...
# `---data was truncated (10240/415311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557b0582beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557b05828e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557b0582c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffbdcd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffbdcd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffbdcd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffbdcd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b057c1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557b057c1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557b057a68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557b05455e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557b05455b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffbdcd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffbdcd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffbdcd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b05455a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c (1099 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fc765c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fc765bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fc765c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ec7649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ec76a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ec7649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ec7631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fc76558bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fc76558a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fc7653d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fc761ece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fc761ecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8ec7632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ec76330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ec76330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fc761eca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c (1100 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_x_f_v_i16mf4(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_x_f_v_i16mf2(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_x_f_v_i16m1(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_x_f_v_i16m2(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_x_f_v_i16m4(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_x_f_v_i16m8(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_xu_f_v_u16mf4(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_xu_f_v_u16mf2(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_xu_f_v_u16m1(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_xu_f_v_u16m2(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_xu_f_v_u16m4(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_xu_f_v_u16m8(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willr
# | ...
# `---data was truncated (10240/205805) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556a8e5a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556a8e5a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556a8e5a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3c44a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3c44a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3c44a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3c44a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556a8e53bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556a8e53ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556a8e5208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556a8e1cfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556a8e1cfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3c44a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3c44a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3c44a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556a8e1cfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c (1101 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaeskf1_vi_u32mf2(<vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i64.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaeskf1_vi_u32m1(<vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i64.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaeskf1_vi_u32m2(<vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i64.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaeskf1_vi_u32m4(<vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i64.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaeskf1_vi_u32m8(<vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i64.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056478e609eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056478e606e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056478e60a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f006df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f006df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f006df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f006df1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056478e59fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056478e59fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056478e5848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056478e233e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056478e233b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f006df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f006df1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f006df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056478e233a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c (1102 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvtbf16_f_f_v_f32mf2(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvtbf16_f_f_v_f32m1(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvtbf16_f_f_v_f32m2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvtbf16_f_f_v_f32m4(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvtbf16_f_f_v_f32m8(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvtbf16_f_f_v_f32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvtbf16_f_f_v_f32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvtbf16_f_f_v_f32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvtbf16_f_f_v_f32m4_m(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvtbf16_f_f_v_f32m8_m(<vscale x 16 x i1> %vm, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_ran
# | ...
# `---data was truncated (10240/10777) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ab75fa6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ab75fa3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ab75fa762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7d27b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7d27b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7d27b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7d27b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ab75f3cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ab75f3ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ab75f218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ab75bd0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ab75bd0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7d27b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7d27b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7d27b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ab75bd0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c (1103 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssubu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssubu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssubu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssubu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssubu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssubu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssubu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssubu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssubu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, ali
# | ...
# `---data was truncated (10240/223367) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558a99ce5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558a99ce2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558a99ce662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff87dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff87dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff87dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff87dd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a99c7bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558a99c7ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558a99c608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558a9990fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558a9990fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff87dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff87dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff87dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a9990fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/riscv-xandesbfhcvt.c (1104 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesbfhcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesbfhcvt -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c -o -    -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesbfhcvt -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_fcvt_s_bf16(bfloat noundef %bf) #0 {
# | entry:
# |   %bf.addr = alloca bfloat, align 2
# |   store bfloat %bf, ptr %bf.addr, align 2
# |   %0 = load bfloat, ptr %bf.addr, align 2
# |   %1 = fpext bfloat %0 to float
# |   ret float %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local bfloat @test_fcvt_bf16_s(float noundef %sf) #0 {
# | entry:
# |   %sf.addr = alloca float, align 4
# |   store float %sf, ptr %sf.addr, align 4
# |   %0 = load float, ptr %sf.addr, align 4
# |   %1 = fptrunc float %0 to bfloat
# |   ret bfloat %1
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+f,+i,+xandesbfhcvt,+zicsr" }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_f2p2_zicsr2p0_xandesbfhcvt5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558e873ddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558e873dae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558e873de62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e42b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e42b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e42b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e42b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558e87373bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558e87373a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558e873588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558e87007e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558e87007b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7e42b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e42b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e42b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558e87007a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c (1105 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvt_f_f_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvt_f_f_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvt_f_f_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvt_f_f_v_f32m8_tu(<vscale x 16 x float> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwcvt_f_f_v_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vfwcvt_f_f_v_f64m2_tu(<vscale x 2 x double> %maskedoff, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x double>, align 8
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vfwcvt_f_f_v_f64m4_tu(<vscale x 4 x double> %maskedoff, <vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x double>, align 8
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vfwcvt_f_f_v_f64m8_tu(<vscale x 8 x double> %maskedoff, <vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x double>, align 8
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2_tum(<vscale x 1 x i1> %mask, <vscale x 1 x float> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.a
# | ...
# `---data was truncated (10240/41678) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564350305eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564350302e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056435030662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd7cd133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd7cd18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd7cd133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd7cd11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056435029bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056435029ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005643502808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056434ff2fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056434ff2fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd7cd11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd7cd11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd7cd11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056434ff2fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c (1106 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vslide1up_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vslide1up_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vslide1up_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vslide1up_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vslide1up_vx_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vslide1up_vx_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vslide1up_vx_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vslide1up_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i16, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vslide1up_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vs
# | ...
# `---data was truncated (10240/210427) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fc281e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fc281e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fc281e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efe76c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efe76ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efe76c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efe76c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fc28179bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fc28179a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fc2815e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fc27e0de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fc27e0db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efe76c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efe76c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efe76c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fc27e0da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c (1107 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssra_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssra_vx_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssra_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssra_vx_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssra_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssra_vx_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssra_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssra_vx_i8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssra_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssra_vx_i8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function
# | ...
# `---data was truncated (10240/100281) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559b21f93eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559b21f90e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559b21f9462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdaa8a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdaa8aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdaa8a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdaa8a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559b21f29bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559b21f29a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559b21f0e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559b21bbde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559b21bbdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdaa8a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdaa8a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdaa8a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559b21bbda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c (1108 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_tu(<vs
# | ...
# `---data was truncated (10240/295861) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557c71240eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557c7123de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557c7124162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e7db05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e7db5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e7db05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e7daed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557c711d6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557c711d6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557c711bb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557c70e6ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557c70e6ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1e7daeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e7daef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e7daef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557c70e6aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c (1109 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmerge_vvm_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmerge_vxm_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmerge_vvm_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmerge_vxm_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmerge_vvm_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmerge_vxm_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmerge_vvm_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmerge_vxm_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmerge_vvm_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca 
# | ...
# `---data was truncated (10240/124506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560dbac6deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560dbac6ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560dbac6e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f941fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f941fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f941fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f941fc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560dbac03bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560dbac03a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560dbabe88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560dba897e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560dba897b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f941fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f941fc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f941fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560dba897a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c (1110 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vsext_vf2_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vsext_vf2_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vsext_vf2_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vsext_vf2_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vsext_vf2_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vsext_vf2_i16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf2_i32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf2_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf2_i32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vsext_vf2_i32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: n
# | ...
# `---data was truncated (10240/66036) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564bce8c6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564bce8c3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564bce8c762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7fadf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7fadf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7fadf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7fadf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564bce85cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564bce85ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564bce8418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564bce4f0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564bce4f0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7fadf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7fadf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7fadf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564bce4f0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c (1111 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgatherei16_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgatherei16_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgatherei16_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgatherei16_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgatherei16_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, <vscale x 16 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vrgatherei16_vv_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, <vscale x 32 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 32 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vrgatherei16_vv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, <vscale x 1 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 1 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vrgatherei16_vv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, <vscale x 2 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 2 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vrgatherei16.vv.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x 
# | ...
# `---data was truncated (10240/292007) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005625d35a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005625d35a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005625d35a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5bfee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5bfeea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5bfee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5bfee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005625d353cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005625d353ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005625d35218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005625d31d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005625d31d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5bfee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5bfee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5bfee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005625d31d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c (1112 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecb_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecb.n32(i32 %0, i32 31, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqdecb.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecb_n_s32_1(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecb.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecb_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqdecb.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqdecb.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecb_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqdecb.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqdecb.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecb_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqdecb.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uqdecb.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecb_pat_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecb.n32(i32 %0, i32 0, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecb_pat_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqdecb.n64(i64 %0, i32 1, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecb_pat_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqdecb.n32(i32 %0, i32 2, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecb_pat_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqdecb.n64(i64 %0, i32 3, i32 1)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e107c6feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e107c6ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e107c7062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe8d2133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe8d218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe8d2133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe8d211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e107c05bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e107c05a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e107bea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e107899e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e107899b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe8d211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe8d211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe8d211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e107899a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c (1113 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei8_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei8_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei8_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei8_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei8_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vluxei8_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> poison, ptr %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei8_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei8_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei8_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei8_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vs
# | ...
# `---data was truncated (10240/14201) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed5bac4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ed5bac1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ed5bac562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffa8f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffa8f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffa8f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffa8f631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed5ba5abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ed5ba5aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ed5ba3f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ed5b6eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ed5b6eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffa8f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffa8f6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffa8f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed5b6eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c (1114 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svqadd_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.sqadd.x.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.sqadd.x.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqadd_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqadd.x.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqadd.x.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqadd_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.sqadd.x.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sqadd.x.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqadd_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.sqadd.x.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sqadd.x.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svqadd_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uqadd.x.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uqadd.x.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqadd_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqadd.x.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqadd.x.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqadd_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uqadd.x.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uqadd.x.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqadd_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uqadd.x.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uqadd.x.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svqadd_n_s8(<vscale x 16 x i8> %op1, i8 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca i8, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store i8 %op2, ptr %op2.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.sqadd.x.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqadd_n_s16(<vscale x 8 x i16> %op1, i16 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca i16, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store i16 %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqadd.x.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqadd_n_s32(<vscale x 4 x i32> %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca i32, align 4
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %.splatinsert = insertelement <vscale x 4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <vscale x 4 x i32> %.splatinsert, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.sqadd.x.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %.splat)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqadd_n_s64(<vscale x 2 x i64> %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %.splatinsert = insertelement <vscale x 2 x i64> poison, i64 %1, i64 0
# |   %.splat = shufflevector <vscale x 2 x i64> %.splatinsert, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.sqadd.x.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %.splat)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_l
# | ...
# `---data was truncated (10240/13780) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c13c8d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c13c8d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c13c8d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f60ee333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f60ee38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f60ee333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f60ee31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c13c86cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c13c86ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c13c8518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c13c500e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c13c500b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f60ee31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f60ee31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f60ee31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c13c500a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c (1115 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4(<vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2(<vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslidedown_vx_bf16m1(<vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslidedown_vx_bf16m2(<vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vslidedown_vx_bf16m4(<vscale x 16 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vslidedown_vx_bf16m8(<vscale x 32 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslidedown.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslidedown_vx_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vslidedown.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslidedown.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslidedown_vx_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vs2, i64 noundef
# | ...
# `---data was truncated (10240/14333) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055792d578eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055792d575e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055792d57962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd4e8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd4e878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd4e8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd4e871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055792d50ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055792d50ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055792d4f38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055792d1a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055792d1a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd4e871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd4e871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd4e871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055792d1a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c (1116 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssrl_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssrl_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssrl_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssrl_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssrl_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssrl_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssrl_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssrl_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssrl_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/226585) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005610eaa51eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005610eaa4ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005610eaa5262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fea5721bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fea572725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fea5721ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fea57203507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005610ea9e7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005610ea9e7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005610ea9cc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005610ea67be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005610ea67bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fea57204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fea572050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fea572050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005610ea67ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c (1117 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4(<vscale x 16 x half> %
# | ...
# `---data was truncated (10240/149145) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056120b5dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056120b5dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056120b5e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd35a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd35a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd35a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd35a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056120b575bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056120b575a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056120b55a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056120b209e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056120b209b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd35a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd35a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd35a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056120b209a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c (1118 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei32_v_f16mf4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei32_v_f16mf2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei32_v_f16m1(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei32_v_f16m2(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei32_v_f16m4(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei32_v_f32mf2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei32_v_f32m1(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei32_v_f32m2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei32_v_f32m4(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vloxei32_v_f32m8(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.p0.nxv16i32.i64(<vscale x 16 x float> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.p0.nxv16i32.i64(<vscale x 16 x
# | ...
# `---data was truncated (10240/107864) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564a3dedfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564a3dedce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564a3dee062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e6f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e6f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e6f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e6f91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564a3de75bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564a3de75a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564a3de5a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564a3db09e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564a3db09b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6e6f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e6f91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e6f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564a3db09a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c (1119 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vzip_vv_f16mf2(<vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vzip_vv_f16m1(<vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vzip_vv_f16m2(<vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vzip_vv_f16m4(<vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vzip_vv_f16m8(<vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vzip_vv_f32m1(<vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vzip_vv_f32m2(<vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vzip_vv_f32m4(<vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vzip_vv_f32m8(<vscale x 8 x float> %vs2, <vscale x 8 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vzip.nxv16f32.nxv8f32.i64(<vscale x 16 x float> poison, <vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vzip.nxv16f32.nxv8f32.i64(<vscale x 16 x float>, <vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vzip_vv_f64m2(<vscale x 1 x double> %vs2, <vscale x 1 x double> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vs1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x double> %vs1, ptr %vs1.addr, align
# | ...
# `---data was truncated (10240/102872) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e76ae3deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e76ae3ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e76ae3e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcdf301bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcdf30725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcdf301ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcdf3003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e76add3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e76add3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e76adb88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e76aa67e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e76aa67b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcdf3004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcdf30050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcdf30050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e76aa67a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c (1120 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpaire_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vpaire.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpaire.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpaire_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vpaire.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpaire.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpaire_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vpaire.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vpaire.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vpaire_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vpaire.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vpaire.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vpaire_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vpaire.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vpaire.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vpaire_vv_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, <vscale x 32 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vpaire.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vpaire.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpaire_vv_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vpaire.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpaire.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpaire_vv_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2
# | ...
# `---data was truncated (10240/32654) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005595e7b29eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005595e7b26e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005595e7b2a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb29af05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb29af5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb29af05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb29aeed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005595e7abfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005595e7abfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005595e7aa48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005595e7753e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005595e7753b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb29aeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb29aeef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb29aeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005595e7753a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c (1121 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svexpa_f16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x half> @llvm.aarch64.sve.fexpa.x.nxv8f16(<vscale x 8 x i16> %0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fexpa.x.nxv8f16(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svexpa_f32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x float> @llvm.aarch64.sve.fexpa.x.nxv4f32(<vscale x 4 x i32> %0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fexpa.x.nxv4f32(<vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svexpa_f64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x double> @llvm.aarch64.sve.fexpa.x.nxv2f64(<vscale x 2 x i64> %0)
# |   ret <vscale x 2 x double> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fexpa.x.nxv2f64(<vscale x 2 x i64>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560cf35c9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560cf35c6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560cf35ca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f859d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f859d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f859d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f859d031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560cf355fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560cf355fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560cf35448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560cf31f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560cf31f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f859d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f859d0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f859d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560cf31f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c (1122 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f0ba47deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f0ba47ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f0ba47e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd3d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd3d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd3d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd3d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f0ba413bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f0ba413a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f0ba3f88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f0ba0a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f0ba0a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdd3d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd3d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd3d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f0ba0a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c (1123 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_v
# | ...
# `---data was truncated (10240/216258) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005555810b2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005555810afe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005555810b362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1161b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1161b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1161b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1161b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555581048bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555581048a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055558102d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555580cdce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555580cdcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1161b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1161b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1161b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555580cdca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c (1124 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f16mf4(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f16mf2(ptr noundef %base, <vscale x 2 x i64> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f16m1(ptr noundef %base, <vscale x 4 x i64> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f16m2(ptr noundef %base, <vscale x 8 x i64> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f32mf2(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f32m1(ptr noundef %base, <vscale x 2 x i64> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f32m2(ptr noundef %base, <vscale x 4 x i64> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f32m4(ptr noundef %base, <vscale x 8 x i64> %bindex, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f64m1(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; F
# | ...
# `---data was truncated (10240/102296) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec2c208eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ec2c205e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ec2c20962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce46333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce4638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce46333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce4631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec2c19ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ec2c19ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ec2c1838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ec2be32e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ec2be32b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fce4631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce4631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce4631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec2be32a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c (1125 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsof_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsof_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsof_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsof_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsof_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsof_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsof_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsof_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1> poison, <vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsof_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1> poison, <vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsof_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1> poison, <vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsof_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1> poison, <vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsof_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1.i64(<vscale x 4 x i1> poison, <vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback n
# | ...
# `---data was truncated (10240/13031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bb02cf1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bb02ceee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bb02cf262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6119733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f611978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6119733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f611971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bb02c87bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bb02c87a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bb02c6c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bb0291be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bb0291bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f611971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f611971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f611971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bb0291ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c (1126 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei8_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %m
# | ...
# `---data was truncated (10240/160133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005587c94a1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005587c949ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005587c94a262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fafe7a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fafe7aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fafe7a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fafe7a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005587c9437bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005587c9437a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005587c941c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005587c90cbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005587c90cbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fafe7a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fafe7a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fafe7a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005587c90cba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c (1127 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_i16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_i16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_i16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_u16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_u16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_u16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("ri
# | ...
# `---data was truncated (10240/47480) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005606e80a1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005606e809ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005606e80a262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff2b1649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff2b16a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff2b1649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff2b1631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005606e8037bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005606e8037a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005606e801c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005606e7ccbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005606e7ccbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff2b1632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff2b16330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff2b16330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005606e7ccba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c (1128 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccsu_vv_i16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccsu_vx_i16mf4_tu(<vscale x 1 x i16> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccsu_vv_i16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccsu_vx_i16mf2_tu(<vscale x 2 x i16> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccsu_vv_i16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccsu_vx_i16m1_tu(<vscale x 4 x i16> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccsu_vv_i16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccsu_vx_i16m2_tu(<vscale x 8 x i16> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccsu_vv_i16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align
# | ...
# `---data was truncated (10240/151245) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005645a0d22eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005645a0d1fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005645a0d2362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1bd9305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1bd935c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1bd9305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1bd92ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005645a0cb8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005645a0cb8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005645a0c9d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005645a094ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005645a094cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1bd92eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1bd92ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1bd92ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005645a094ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c (1129 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwcvtu_x_x_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwcvtu_x_x_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwcvtu_x_x_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwcvtu_x_x_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwcvtu_x_x_v_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwcvtu_x_x_v_u16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwcvtu_x_x_v_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwcvtu_x_x_v_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwcvtu_x_x_v_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vwcvtu_x_x_v_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %
# | ...
# `---data was truncated (10240/67150) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a39b54feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a39b54ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a39b55062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e6261bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e626725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e6261ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e62603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a39b4e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a39b4e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a39b4ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a39b179e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a39b179b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8e62604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e626050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e626050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a39b179a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c (1130 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounw
# | ...
# `---data was truncated (10240/12658) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055626e1b1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055626e1aee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055626e1b262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd1bf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd1bf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd1bf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd1beed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055626e147bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055626e147a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055626e12c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055626dddbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055626dddbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbd1beeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd1beef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd1beef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055626dddba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c (1131 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vand_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vand_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vand_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vand_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vand_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vand_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vand_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vand_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vand_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/424843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f8bcac8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f8bcac5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f8bcac962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3833d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3833d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3833d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3833ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f8bca5ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f8bca5ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f8bca438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f8bc6f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f8bc6f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3833ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3833cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3833cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f8bc6f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/compare.c (1132 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/compare.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c --check-prefixes=CHECK,CHECK-NOSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = fcmp oeq <8 x half> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = fcmp oeq <4 x float> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = icmp eq <16 x i8> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = icmp eq <8 x i16> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = icmp eq <4 x i32> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = icmp eq <16 x i8> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = icmp eq <8 x i16> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = icmp eq <4 x i32> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_f16(<8 x half> noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca half, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load half, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x half> poison, half %1, i64 0
# |   %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
# |   %2 = fcmp oeq <8 x half> %0, %.splat
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_f32(<4 x float> noundef %a, float noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca float, align 4
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store float %b, ptr %b.addr, align 4
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load float, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x float> poison, float %1, i64 0
# |   %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer
# |   %2 = fcmp oeq <4 x float> %0, %.splat
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_s8(<16 x i8> noundef %a, i8 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = icmp eq <16 x i8> %0, %.splat
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = icmp eq <8 x i16> %0, %.splat
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = icmp eq <4 x i32> %0, %.splat
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = icmp eq <16 x i8> %0, %.splat
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = icmp eq <8 x i16> %0, %.splat
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = 
# | ...
# `---data was truncated (10240/125481) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055805d359eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055805d356e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055805d35a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb43a705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb43a75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb43a705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb43a6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055805d2efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055805d2efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055805d2d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055805cf83e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055805cf83b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb43a6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb43a6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb43a6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055805cf83a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c --check-prefixes=CHECK,CHECK-NOSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c --check-prefixes=CHECK,CHECK-NOSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c (1133 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f16m1x8(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f32m1x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f64m1x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef
# | ...
# `---data was truncated (10240/69988) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005618e5eb5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005618e5eb2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005618e5eb662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f164c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f164c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f164c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f164c31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005618e5e4bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005618e5e4ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005618e5e308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005618e5adfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005618e5adfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f164c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f164c31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f164c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005618e5adfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c (1134 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_f16mf4x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_f16mf2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_f16m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_f16m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_i16mf4x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_i16mf2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_i16m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_i16m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_u16mf4x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_u16mf2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_u16m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_u16m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_f16mf4x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = allo
# | ...
# `---data was truncated (10240/23031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005589a45b0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005589a45ade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005589a45b162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff2e8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff2e878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff2e8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff2e871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589a4546bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005589a4546a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005589a452b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005589a41dae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005589a41dab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff2e871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff2e871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff2e871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005589a41daa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c (1135 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b32_m(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nof
# | ...
# `---data was truncated (10240/11966) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bf86bbdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bf86bbae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bf86bbe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3301733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f330178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3301733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f330171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bf86b53bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bf86b53a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bf86b388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bf867e7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bf867e7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f330171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f330171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f330171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bf867e7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c (1136 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005564afc5eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005564afc5be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005564afc5f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efcd901bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efcd90725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efcd901ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efcd9003507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005564afbf4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005564afbf4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005564afbd98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005564af888e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005564af888b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efcd9004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efcd90050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efcd90050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005564af888a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c (1137 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmseq_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmseq_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmseq_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmseq_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmseq_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmseq_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmseq_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | 
# | ...
# `---data was truncated (10240/116259) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056136888beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561368888e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056136888c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f963e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f963e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f963e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f963e51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561368821bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561368821a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005613688068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005613684b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005613684b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f963e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f963e51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f963e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005613684b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c (1138 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vf_f32mf2(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vf_f32m1(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vf_f32m2(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vf_f32m4(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float>, ha
# | ...
# `---data was truncated (10240/90685) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f8abdc3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f8abdc0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f8abdc462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fde30c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fde30ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fde30c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fde30c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f8abd59bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f8abd59a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f8abd3e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f8ab9ede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f8ab9edb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fde30c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fde30c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fde30c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f8ab9eda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c (1139 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_f16m1x2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_f16m2x2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_f32m1x2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_f32m2x2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei64_v_f32m4x2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple
# | ...
# `---data was truncated (10240/96919) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564110b9beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564110b98e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564110b9c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5599449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f55994a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5599449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5599431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564110b31bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564110b31a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564110b168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005641107c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005641107c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5599432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f55994330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f55994330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005641107c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c (1140 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsqrt7_v_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsqrt7_v_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsqrt7_v_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsqrt7_v_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsqrt7_v_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrsqrt7_v_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsqrt7_v_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsqrt7_v_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsqrt7_v_bf16m1_tum(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.mask.
# | ...
# `---data was truncated (10240/28162) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564b9c47aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564b9c477e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564b9c47b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d9f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d9f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d9f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d9f831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564b9c410bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564b9c410a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564b9c3f58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564b9c0a4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564b9c0a4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8d9f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d9f8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d9f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564b9c0a4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c (1141 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556e62722eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556e6271fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556e6272362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c4b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c4b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c4b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c4b31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e626b8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556e626b8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556e6269d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556e6234ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556e6234cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1c4b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c4b31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c4b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e6234ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c (1142 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_vfmad_lane_f64(double noundef %a, double noundef %b, <1 x double> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca double, align 8
# |   %b.addr = alloca double, align 8
# |   %c.addr = alloca <1 x double>, align 8
# |   %__ret = alloca double, align 8
# |   %__s0 = alloca double, align 8
# |   %__s1 = alloca double, align 8
# |   %__s2 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca double, align 8
# |   %tmp = alloca double, align 8
# |   store double %a, ptr %a.addr, align 8
# |   store double %b, ptr %b.addr, align 8
# |   store <1 x double> %c, ptr %c.addr, align 8
# |   %0 = load double, ptr %a.addr, align 8
# |   store double %0, ptr %__s0, align 8
# |   %1 = load double, ptr %b.addr, align 8
# |   store double %1, ptr %__s1, align 8
# |   %2 = load <1 x double>, ptr %c.addr, align 8
# |   store <1 x double> %2, ptr %__s2, align 8
# |   %3 = load double, ptr %__s0, align 8
# |   %4 = load double, ptr %__s1, align 8
# |   %5 = load <1 x double>, ptr %__s2, align 8
# |   %extract = extractelement <1 x double> %5, i32 0
# |   %6 = call double @llvm.fma.f64(double %4, double %extract, double %3)
# |   store double %6, ptr %ref.tmp, align 8
# |   %7 = load double, ptr %ref.tmp, align 8
# |   store double %7, ptr %__ret, align 8
# |   %8 = load double, ptr %__ret, align 8
# |   store double %8, ptr %tmp, align 8
# |   %9 = load double, ptr %tmp, align 8
# |   ret double %9
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare double @llvm.fma.f64(double, double, double) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_vfmad_laneq_f64(double noundef %a, double noundef %b, <2 x double> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca double, align 8
# |   %b.addr = alloca double, align 8
# |   %c.addr = alloca <2 x double>, align 16
# |   %__ret = alloca double, align 8
# |   %__s0 = alloca double, align 8
# |   %__s1 = alloca double, align 8
# |   %__s2 = alloca <2 x double>, align 16
# |   %ref.tmp = alloca double, align 8
# |   %tmp = alloca double, align 8
# |   store double %a, ptr %a.addr, align 8
# |   store double %b, ptr %b.addr, align 8
# |   store <2 x double> %c, ptr %c.addr, align 16
# |   %0 = load double, ptr %a.addr, align 8
# |   store double %0, ptr %__s0, align 8
# |   %1 = load double, ptr %b.addr, align 8
# |   store double %1, ptr %__s1, align 8
# |   %2 = load <2 x double>, ptr %c.addr, align 16
# |   store <2 x double> %2, ptr %__s2, align 16
# |   %3 = load double, ptr %__s0, align 8
# |   %4 = load double, ptr %__s1, align 8
# |   %5 = load <2 x double>, ptr %__s2, align 16
# |   %extract = extractelement <2 x double> %5, i32 1
# |   %6 = call double @llvm.fma.f64(double %4, double %extract, double %3)
# |   store double %6, ptr %ref.tmp, align 8
# |   %7 = load double, ptr %ref.tmp, align 8
# |   store double %7, ptr %__ret, align 8
# |   %8 = load double, ptr %__ret, align 8
# |   store double %8, ptr %tmp, align 8
# |   %9 = load double, ptr %tmp, align 8
# |   ret double %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vfmss_lane_f32(float noundef %a, float noundef %b, <2 x float> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca float, align 4
# |   %b.addr = alloca float, align 4
# |   %c.addr = alloca <2 x float>, align 8
# |   %__ret_443 = alloca float, align 4
# |   %__s0_443 = alloca float, align 4
# |   %__s1_443 = alloca float, align 4
# |   %__s2_443 = alloca <2 x float>, align 8
# |   %__ret = alloca float, align 4
# |   %__s0 = alloca float, align 4
# |   %__s1 = alloca float, align 4
# |   %__s2 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca float, align 4
# |   %tmp = alloca float, align 4
# |   %tmp1 = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   store float %b, ptr %b.addr, align 4
# |   store <2 x float> %c, ptr %c.addr, align 8
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__s0_443, align 4
# |   %1 = load float, ptr %b.addr, align 4
# |   store float %1, ptr %__s1_443, align 4
# |   %2 = load <2 x float>, ptr %c.addr, align 8
# |   store <2 x float> %2, ptr %__s2_443, align 8
# |   %3 = load float, ptr %__s0_443, align 4
# |   store float %3, ptr %__s0, align 4
# |   %4 = load float, ptr %__s1_443, align 4
# |   %fneg = fneg float %4
# |   store float %fneg, ptr %__s1, align 4
# |   %5 = load <2 x float>, ptr %__s2_443, align 8
# |   store <2 x float> %5, ptr %__s2, align 8
# |   %6 = load float, ptr %__s0, align 4
# |   %7 = load float, ptr %__s1, align 4
# |   %8 = load <2 x float>, ptr %__s2, align 8
# |   %extract = extractelement <2 x float> %8, i32 1
# |   %9 = call float @llvm.fma.f32(float %7, float %extract, float %6)
# |   store float %9, ptr %ref.tmp, align 4
# |   %10 = load float, ptr %ref.tmp, align 4
# |   store float %10, ptr %__ret, align 4
# |   %11 = load float, ptr %__ret, align 4
# |   store float %11, ptr %tmp, align 4
# |   %12 = load float, ptr %tmp, align 4
# |   store float %12, ptr %__ret_443, align 4
# |   %13 = load float, ptr %__ret_443, align 4
# |   store float %13, ptr %tmp1, align 4
# |   %14 = load float, ptr %tmp1, align 4
# |   ret float %14
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare float @llvm.fma.f32(float, float, float) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vfma_lane_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <1 x double>, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %v.addr = alloca <1 x double>, align 8
# |   %__ret = alloca <1 x double>, align 8
# |   %__s0 = alloca <1 x double>, align 8
# |   %__s1 = alloca <1 x double>, align 8
# |   %__s2 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   store <1 x double> %v, ptr %v.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__s0, align 8
# |   %1 = load <1 x double>, ptr %b.addr, align 8
# |   store <1 x double> %1, ptr %__s1, align 8
# |   %2 = load <1 x double>, ptr %v.addr, align 8
# |   store <1 x double> %2, ptr %__s2, align 8
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <8 x i8>, ptr %__s2, align 8
# |   %6 = bitcast <8 x i8> %5 to <1 x double>
# |   %lane = shufflevector <1 x double> %6, <1 x double> %6, <1 x i32> zeroinitializer
# |   %fmla = bitcast <8 x i8> %4 to <1 x double>
# |   %fmla1 = bitcast <8 x i8> %3 to <1 x double>
# |   %fmla2 = call <1 x double> @llvm.fma.v1f64(<1 x double> %fmla, <1 x double> %lane, <1 x double> %fmla1)
# |   store <1 x double> %fmla2, ptr %ref.tmp, align 8
# |   %7 = load <1 x double>, ptr %ref.tmp, align 8
# |   store <1 x double> %7, ptr %__ret, align 8
# |   %8 = load <1 x double>, ptr %__ret, align 8
# |   store <1 x double> %8, ptr %tmp, align 8
# |   %9 = load <1 x double>, ptr %tmp, align 8
# |   ret <1 x double> %9
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <1 x double> @llvm.fma.v1f64(<1 x double>, <1 x double>, <1 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vfms_lane_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <1 x double>, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %v.addr = alloca <1 x double>, align 8
# |   %__ret_449 = alloca <1 x double>, align 8
# |   %__s0_449 = alloca <1 x double>, align 8
# |   %__s1_449 = alloca <1 x double>, align 8
# |   %__s2_449 = alloca <1 x double>, align 8
# |   %__ret = alloca <1 x double>, align 8
# |   %__s0 = alloca <1 x double>, align 8
# |   %__s1 = alloca <1 x double>, align 8
# |   %__s2 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x double>, align 8
# |   %tmp3 = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   store <1 x double> %v, ptr %v.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__s0_449, align 8
# |   %1 = load <1 x double>, ptr %b.addr, align 8
# |   store <1 x double> %1, ptr %__s1_449, align 8
# |   %2 = load <1 x double>, ptr %v.addr, align 8
# |   store <1 x double> %2, ptr %__s2_449, align 8
# |   %3 = load <1 x double>, ptr %__s0_449, align 8
# |   store <1 x double> %3, ptr %__s0, align 8
# |   %4 = load <1 x double>, ptr %__s1_449, align 8
# |   %fneg = fneg <1 x double> %4
# |   store <1 x double> %fneg, ptr %__s1, align 8
# |   %5 = load <1 x double>, ptr %__s2_449, align 8
# |   store <1 x double> %5, ptr %__s2, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = load <8 x i8>, ptr %__s1, align 8
# |   %8 = load <8 x i8>, ptr %__s2, align 8
# |   %9 = bitcast <8 x i8> %8 to <1 x double>
# |   %lane = shufflevector <1 x double> %9, <1 x double> %9, <1 x i32> zeroinitializer
# |   %fmla = bitcast <8 x i8> %7 to <1 x double>
# |   %fmla1 = bitcast <8 x i8> %6 to <1 x double>
# |   %fmla2 = call <1 x double> @llvm.fma.v1f64(<1 x double> %fmla, <1 x double> %lane, <1 x double> %fmla1)
# |   store <1 x double> %fmla2, ptr %ref.tmp, align 8
# |   %10 = load <1 x double>, ptr %ref.tmp, align 8
# |   store <1 x double> %10, ptr %__ret, align 8
# |   %11 = load <1 x double>, ptr %__ret, align 8
# |   store <1 x double> %11, ptr %tmp, align 8
# |   %12 = load <1 x double>, ptr %tmp, align 8
# |   store <1 x double> %12, ptr %__ret_449, align 8
# |   %13 = load <1 x double>, ptr %__ret_449, align 8
# |   store <1 x double> %13, ptr %tmp3, align 8
# |   %14 = load <1 x double>, ptr %tmp3, align 8
# |   ret <1 x double> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vfms_laneq_f64(<1 x double> noundef %a, <1 x double> noundef %b, <2 x double> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <1 x double>, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %v.addr = alloca <2 x double>, align 16
# |   %__ret_460 = alloca <1 x double>, align 8
# |   %__s0_460 = alloca <1 x double>, align 8
# |   %__s1_460 = alloca <1 x double>, align 8
# |   %__s2_460 = alloca <2 x double>, align 16
# |   %__ret = alloca <1 x double>, align 8
# |   %_
# | ...
# `---data was truncated (10240/12799) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005595b1450eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005595b144de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005595b145162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efe6e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efe6e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efe6e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efe6e631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005595b13e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005595b13e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005595b13cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005595b107ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005595b107ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efe6e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efe6e6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efe6e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005595b107aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c (1143 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmnot_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmnot_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmnot_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmnot_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmnot_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmnot_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmnot_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564d12a20eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564d12a1de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564d12a2162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc14bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc14bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc14bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc14bf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d129b6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564d129b6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564d1299b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564d1264ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564d1264ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc14bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc14bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc14bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d1264aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c (1144 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f16m1x2(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f16m2x2(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f32m1x2(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f32m2x2(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f32m4x2(ptr noundef %base, <vscale x 8 x i64> %binde
# | ...
# `---data was truncated (10240/110121) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558ed5203eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558ed5200e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558ed520462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f903bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f903bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f903bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f903bf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558ed5199bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558ed5199a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558ed517e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558ed4e2de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558ed4e2db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f903bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f903bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f903bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558ed4e2da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c (1145 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredsum_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor
# | ...
# `---data was truncated (10240/113039) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563d6dd26eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563d6dd23e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563d6dd2762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7ed5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7ed52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7ed5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7ed5231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d6dcbcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563d6dcbca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563d6dca18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563d6d950e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563d6d950b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7ed5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7ed52330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7ed52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d6d950a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c (1146 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei32_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>,
# | ...
# `---data was truncated (10240/284336) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ea68f3eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ea68f3be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ea68f3f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdb77f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdb77f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdb77f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdb77f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ea68ed4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ea68ed4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ea68eb98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ea68b68e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ea68b68b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdb77f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdb77f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdb77f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ea68b68a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c (1147 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmacc_vv_i16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmacc_vx_i16mf4(<vscale x 1 x i16> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmacc_vv_i16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmacc_vx_i16mf2(<vscale x 2 x i16> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmacc_vv_i16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmacc_vx_i16m1(<vscale x 4 x i16> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmacc_vv_i16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmacc_vx_i16m2(<vscale x 8 x i16> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmacc_vv_i16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store
# | ...
# `---data was truncated (10240/79497) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dab7023eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dab7020e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dab702462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3c2c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3c2c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3c2c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3c2c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dab6fb9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dab6fb9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dab6f9e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dab6c4de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dab6c4db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3c2c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3c2c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3c2c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dab6c4da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c (1148 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredand_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretu
# | ...
# `---data was truncated (10240/113047) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559b6a932eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559b6a92fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559b6a93362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f48ffa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f48ffaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f48ffa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f48ffa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559b6a8c8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559b6a8c8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559b6a8ad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559b6a55ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559b6a55cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f48ffa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f48ffa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f48ffa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559b6a55ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c (1149 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f16mf4(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f16mf2(ptr noundef %base, <vscale x 2 x i64> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f16m1(ptr noundef %base, <vscale x 4 x i64> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f16m2(ptr noundef %base, <vscale x 8 x i64> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f32mf2(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f32m1(ptr noundef %base, <vscale x 2 x i64> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f32m2(ptr noundef %base, <vscale x 4 x i64> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f32m4(ptr noundef %base, <vscale x 8 x i64> %bindex, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f64m1(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret voi
# | ...
# `---data was truncated (10240/102304) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005633dc2d2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005633dc2cfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005633dc2d362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc0d9333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc0d938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc0d9333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc0d931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005633dc268bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005633dc268a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005633dc24d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005633dbefce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005633dbefcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc0d931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc0d931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc0d931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005633dbefca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c (1150 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_f_f_w_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfncvt_f_f_w_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfncvt_f_f_w_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfncvt_f_f_w_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> %0, <vscale x 16 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfncvt_f_f_w_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfncvt_f_f_w_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> %0, <vscale x 2 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float>, <vscale x 2 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfncvt_f_f_w_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> %0, <vscale x 4 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float>, <vscale x 4 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfncvt_f_f_w_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> %0, <vscale x 8 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float>, <vscale x 8 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x half> %maskedoff, <vscale x 1 x float> %src, i64 nou
# | ...
# `---data was truncated (10240/78890) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055618b9dbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055618b9d8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055618b9dc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff23dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff23dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff23dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff23dc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055618b971bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055618b971a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055618b9568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055618b605e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055618b605b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff23dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff23dc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff23dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055618b605a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c (1151 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosy
# | ...
# `---data was truncated (10240/12666) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d9d8f83eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d9d8f80e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d9d8f8462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb4ce105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb4ce15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb4ce105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb4ce0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d9d8f19bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d9d8f19a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d9d8efe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d9d8bade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d9d8badb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb4ce0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb4ce0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb4ce0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d9d8bada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c (1152 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vf_f32mf2_tu(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vf_f32m1_tu(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vf_f32m2_tu(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vf_f32m4_tu(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(
# | ...
# `---data was truncated (10240/179185) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557fe0051eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557fe004ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557fe005262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f19c961bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f19c96725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f19c961ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f19c9603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557fdffe7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557fdffe7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557fdffcc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557fdfc7be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557fdfc7bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f19c9604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f19c96050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f19c96050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557fdfc7ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c (1153 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005583d8f81eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005583d8f7ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005583d8f8262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5191e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5191ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5191e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5191e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005583d8f17bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005583d8f17a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005583d8efc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005583d8babe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005583d8babb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5191e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5191e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5191e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005583d8baba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c (1154 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabda_vv_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabda_vx_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabda_vv_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabda_vx_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabda_vv_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabda_vx_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabda_vv_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabda_vx_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwabda_vv_u16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %v
# | ...
# `---data was truncated (10240/110062) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b5cd181eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b5cd17ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b5cd18262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f50a1a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f50a1aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f50a1a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f50a1a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b5cd117bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b5cd117a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b5cd0fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b5ccdabe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b5ccdabb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f50a1a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f50a1a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f50a1a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b5ccdaba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c (1155 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_s16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 8 x i16> %2 to <vscale x 8 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv8i8.p0(<vscale x 8 x i8> %4, <vscale x 8 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv8i8.p0(<vscale x 8 x i8>, <vscale x 8 x i1>, ptr captures(none)) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_s32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 4 x i32> %2 to <vscale x 4 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv4i8.p0(<vscale x 4 x i8> %4, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv4i8.p0(<vscale x 4 x i8>, <vscale x 4 x i1>, ptr captures(none)) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 2 x i64> %2 to <vscale x 2 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv2i8.p0(<vscale x 2 x i8> %4, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv2i8.p0(<vscale x 2 x i8>, <vscale x 2 x i1>, ptr captures(none)) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_u16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 8 x i16> %2 to <vscale x 8 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv8i8.p0(<vscale x 8 x i8> %4, <vscale x 8 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_u32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 4 x i32> %2 to <vscale x 4 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv4i8.p0(<vscale x 4 x i8> %4, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 2 x i64> %2 to <vscale x 2 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv2i8.p0(<vscale x 2 x i8> %4, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_vnum_s16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 8 x i16> %3 to <vscale x 8 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv8i8.p0(<vscale x 8 x i8> %6, <vscale x 8 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 4 x i32> %3 to <vscale x 4 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv4i8.p0(<vscale x 4 x i8> %6, <vscale x 4 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 2 x i8>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 2 x i64> %3 to <vscale x 2 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv2i8.p0(<vscale x 2 x i8> %6, <vscale x 2 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_vnum_u16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 8 x i16> %data) #0 {
# | e
# | ...
# `---data was truncated (10240/32866) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x0000562ecd597eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562ecd594e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562ecd59862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f21e7d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f21e7d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f21e7d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f21e7d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562ecd52dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562ecd52da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562ecd5128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562ecd1c1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562ecd1c1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f21e7d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f21e7d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f21e7d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562ecd1c1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c (1156 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrsub_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrsub_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrsub_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrsub_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrsub_vx_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vrsub_vx_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vrsub_vx_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vrsub_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i16, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vrsub_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i16, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = c
# | ...
# `---data was truncated (10240/207083) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055995fc92eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055995fc8fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055995fc9362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f28dd01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f28dd0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f28dd01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f28dd003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055995fc28bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055995fc28a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055995fc0d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055995f8bce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055995f8bcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f28dd004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f28dd0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f28dd0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055995f8bca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c (1157 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f16m1x8(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f32m1x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f64m1x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i16> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005614e5ea1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005614e5e9ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005614e5ea262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb8b9533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb8b958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb8b9533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb8b951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005614e5e37bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005614e5e37a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005614e5e1c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005614e5acbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005614e5acbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb8b951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb8b951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb8b951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005614e5acba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c (1158 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_gather_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_gather_u64base_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_gather_s64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = sext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1>, ptr, <vscale x 2 x i64>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_gather_s64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = sext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_gather_u64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = sext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_gather_u64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = sext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff
# | ...
# `---data was truncated (10240/18920) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055afca99feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055afca99ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055afca9a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc44d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc44d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc44d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc44d91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055afca935bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055afca935a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055afca91a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055afca5c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055afca5c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc44d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc44d91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc44d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055afca5c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c (1159 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -disable-O0-optnone -emit-llvm -Qn /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c -o -      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2 | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -disable-O0-optnone -emit-llvm -Qn /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @test_vlenb() #0 {
# | entry:
# |   %0 = call i32 @llvm.read_register.i32(metadata !4)
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare i32 @llvm.read_register.i32(metadata) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"vlenb"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2
# |  #0 0x00005629dee6ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005629dee69e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005629dee6d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f66a7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f66a778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f66a7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f66a771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005629dee02bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005629dee02a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005629dede78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005629dea96e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005629dea96b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f66a771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f66a771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f66a771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005629dea96a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c (1160 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_f16m1x2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_f16m2x2(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei8_v_f16m4x2(ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_f32m1x2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_f32m2x2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8
# | ...
# `---data was truncated (10240/113011) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561de38bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561de38b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561de38bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7cafc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7cafca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7cafc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7cafc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561de3851bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561de3851a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561de38368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561de34e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561de34e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7cafc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7cafc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7cafc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561de34e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c (1161 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_f32mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_f32m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_i32mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_i32m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_u32mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_u32m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_i32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_i32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/14010) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005619ef56beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005619ef568e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005619ef56c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f396fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f396fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f396fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f396fd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005619ef501bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005619ef501a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005619ef4e68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005619ef195e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005619ef195b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f396fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f396fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f396fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005619ef195a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/neon-3v.c (1162 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-3v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vand_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %and.i = and <8 x i8> %2, %3
# |   store <8 x i8> %and.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vandq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %and.i = and <16 x i8> %2, %3
# |   store <16 x i8> %and.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vand_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %and.i = and <4 x i16> %2, %3
# |   store <4 x i16> %and.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vandq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   %1 = load <8 x i16>, ptr %b.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %3 = load <8 x i16>, ptr %__p1.addr.i, align 16
# |   %and.i = and <8 x i16> %2, %3
# |   store <8 x i16> %and.i, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vand_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %and.i = and <2 x i32> %2, %3
# |   store <2 x i32> %and.i, ptr %__ret.i, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vandq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   %1 = load <4 x i32>, ptr %b.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <4 x i32> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %3 = load <4 x i32>, ptr %__p1.addr.i, align 16
# |   %and.i = and <4 x i32> %2, %3
# |   store <4 x i32> %and.i, ptr %__ret.i, align 16
# |   %4 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vand_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   %3 = load <1 x i64>, ptr %__p1.addr.i, align 8
# |   %and.i = and <1 x i64> %2, %3
# |   store <1 x i64> %and.i, ptr %__ret.i, align 8
# |   %4 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vandq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__p1.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %a.addr = alloca <2 x i64>, align 16
# |   %b.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %3 = load <2 x i64>, ptr %__p1.addr.i, align 16
# |   %and.i = and <2 x i64> %2, %3
# |   store <2 x i64> %and.i, ptr %__ret.i, align 16
# |   %4 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vand_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %and.i = and <8 x i8> %2, %3
# |   store <8 x i8> %and.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vandq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %and.i = and <16 x i8> %2, %3
# |   store <16 x i8> %and.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vand_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %and.i = and <4 x i16> %2, %3
# |   store <4 x i16> %and.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vandq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   %1 = load <8 x i16>, ptr %b.addr, al
# | ...
# `---data was truncated (10240/70553) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a0e4b4beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a0e4b48e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a0e4b4c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee8a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee8a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee8a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee8a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a0e4ae1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a0e4ae1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a0e4ac68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a0e4775e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a0e4775b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fee8a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee8a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee8a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a0e4775a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c (1163 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrsub_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrsub_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrsub_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrsub_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrsub_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vrsub_vx_i8m4(<vscale x 32 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vrsub_vx_i8m8(<vscale x 64 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vrsub_vx_i16mf4(<vscale x 1 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vrsub_vx_i16mf2(<vscale x 2 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vrsub_vx_i16m1(<vscale x 4 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vrsub_vx_i16m2(<vscale x 8 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vrsub.nxv8i16
# | ...
# `---data was truncated (10240/84971) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005629e8426eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005629e8423e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005629e842762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c2d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c2d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c2d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c2d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005629e83bcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005629e83bca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005629e83a18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005629e8050e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005629e8050b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8c2d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c2d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c2d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005629e8050a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c (1164 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnj_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnj_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnj_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnj_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnj_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnj_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnj_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnj_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnj_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnj.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnj.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnj_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load 
# | ...
# `---data was truncated (10240/29128) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055704bf29eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055704bf26e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055704bf2a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe09b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe09b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe09b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe09b11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055704bebfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055704bebfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055704bea48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055704bb53e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055704bb53b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe09b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe09b11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe09b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055704bb53a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c (1165 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei16_v_i8mf8x8
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561802fdbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561802fd8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561802fdc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff1f9333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff1f938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff1f9333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff1f931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561802f71bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561802f71a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561802f568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561802c05e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561802c05b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff1f931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff1f931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff1f931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561802c05a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c (1166 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfabs_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfabs_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfabs_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfabs_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfabs_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfabs_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfabs_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfabs_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfabs_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfabs_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x float> %o
# | ...
# `---data was truncated (10240/70102) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562e4c08ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562e4c089e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562e4c08d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec62049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec620a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec62049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec62031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562e4c022bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562e4c022a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562e4c0078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562e4bcb6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562e4bcb6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fec62032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec620330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec620330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562e4bcb6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c (1167 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_f32mf2_tu(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_f32m1_tu(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_f32m2_tu(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_f32m4_tu(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f3
# | ...
# `---data was truncated (10240/179503) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559b9fee9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559b9fee6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559b9feea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd678a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd678aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd678a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd678a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559b9fe7fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559b9fe7fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559b9fe648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559b9fb13e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559b9fb13b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd678a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd678a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd678a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559b9fb13a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c (1168 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_vv_i16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_vx_i16mf4(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_wv_i16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_wx_i16mf4(<vscale x 1 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_vv_i16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_vx_i16mf2(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_wv_i16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_wx_i16mf2(<vscale x 2 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwadd_vv_i16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwadd_vx_i16m1(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwadd_wv_i16m1(<vscal
# | ...
# `---data was truncated (10240/134557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055717e115eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055717e112e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055717e11662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa077c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa077ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa077c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa077c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055717e0abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055717e0aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055717e0908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055717dd3fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055717dd3fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa077c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa077c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa077c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055717dd3fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c (1169 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f16m1x4(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f16m2x4(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f32m1x4(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f32m2x4(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f64m1x4(ptr noundef %base, <vscale x 1 x i32> %binde
# | ...
# `---data was truncated (10240/99754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b0745a8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b0745a5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b0745a962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f138f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f138f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f138f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f138f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b07453ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b07453ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b0745238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b0741d2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b0741d2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f138f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f138f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f138f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b0741d2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c (1170 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8(<vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4(<vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2(<vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1(<vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_x_f_qf_i8m2(<vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function
# | ...
# `---data was truncated (10240/12439) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560031d2eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560031d2be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560031d2f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe4a1e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe4a1ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe4a1e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe4a1e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560031cc4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560031cc4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560031ca98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560031958e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560031958b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe4a1e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe4a1e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe4a1e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560031958a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c (1171 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4(<vscale x 16 x half> %vd, <vsc
# | ...
# `---data was truncated (10240/149137) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005622bf138eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005622bf135e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005622bf13962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe10e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe10e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe10e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe10e91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005622bf0cebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005622bf0cea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005622bf0b38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005622bed62e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005622bed62b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe10e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe10e91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe10e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005622bed62a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c (1172 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1f32.p0.i64(<vscale x 1 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32m1(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2f32.p0.i64(<vscale x 2 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32m2(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4f32.p0.i64(<vscale x 4 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32m4(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8f32.p0.i64(<vscale x 8 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32m8(ptr noundef %base, i64 noundef %bstride, <vscale x 16 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 16 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 16 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv16f32.p0.i64(<vscale x 16 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i32.p0.i64(<vscale x 1 x i32> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32m1(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i32.p0.i64(<vscale x 2 x i32> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32m2(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i32.p0.i64(<vscale x 4 x i32> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32m4(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8i32.p0.i64(<vscale x 8 x i32> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32m8(ptr noundef %base, i64 noundef %bstride, <vscale x 16 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 16 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.a
# | ...
# `---data was truncated (10240/33190) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005609a9ee7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005609a9ee4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005609a9ee862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f13c0049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13c00a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f13c0049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f13c0031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005609a9e7dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005609a9e7da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005609a9e628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005609a9b11e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005609a9b11b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f13c0032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13c00330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13c00330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005609a9b11a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c (1173 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8ff_v_i8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8ff_v_i8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8ff_v_i8mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8ff_v_i8m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8ff_v_i8m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8ff_v_u8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv
# | ...
# `---data was truncated (10240/68225) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005629ff228eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005629ff225e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005629ff22962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb8921bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb892725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb8921ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb89203507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005629ff1bebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005629ff1bea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005629ff1a38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005629fee52e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005629fee52b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffb89204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb892050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb892050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005629fee52a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c (1174 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf4(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf2(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvtbf16_f_f_w_bf16m1(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvtbf16_f_f_w_bf16m2(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvtbf16_f_f_w_bf16m4(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvtbf16_f_f_w_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %1, <vscale x 4 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvtbf16_f_f_w_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %1, <vscale x 8 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, <vscale x 8 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvtbf16_f_f_w_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %1, <vscale x 16 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.ris
# | ...
# `---data was truncated (10240/18562) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558b39244eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558b39241e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558b3924562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7a6c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7a6c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7a6c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7a6c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558b391dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558b391daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558b391bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558b38e6ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558b38e6eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7a6c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7a6c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7a6c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558b38e6ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c (1175 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f16m1x4(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f16m2x4(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f32m1x4(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f32m2x4(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f64m1x4(ptr noundef %base, <vscale x 1 x i64> %binde
# | ...
# `---data was truncated (10240/94227) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555a3df3eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555a3df3be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555a3df3f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4314733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f431478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4314733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f431471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555a3ded4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555a3ded4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555a3deb98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555a3db68e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555a3db68b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f431471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f431471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f431471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555a3db68a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_index.c (1176 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_index.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svindex_s8(i8 noundef %base, i8 noundef %step) #0 {
# | entry:
# |   %base.addr = alloca i8, align 1
# |   %step.addr = alloca i8, align 1
# |   store i8 %base, ptr %base.addr, align 1
# |   store i8 %step, ptr %step.addr, align 1
# |   %0 = load i8, ptr %base.addr, align 1
# |   %1 = load i8, ptr %step.addr, align 1
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.index.nxv16i8(i8 %0, i8 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.index.nxv16i8(i8, i8) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svindex_s16(i16 noundef %base, i16 noundef %step) #0 {
# | entry:
# |   %base.addr = alloca i16, align 2
# |   %step.addr = alloca i16, align 2
# |   store i16 %base, ptr %base.addr, align 2
# |   store i16 %step, ptr %step.addr, align 2
# |   %0 = load i16, ptr %base.addr, align 2
# |   %1 = load i16, ptr %step.addr, align 2
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.index.nxv8i16(i16 %0, i16 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.index.nxv8i16(i16, i16) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svindex_s32(i32 noundef %base, i32 noundef %step) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   %step.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   store i32 %step, ptr %step.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = load i32, ptr %step.addr, align 4
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.index.nxv4i32(i32 %0, i32 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.index.nxv4i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svindex_s64(i64 noundef %base, i64 noundef %step) #0 {
# | entry:
# |   %base.addr = alloca i64, align 8
# |   %step.addr = alloca i64, align 8
# |   store i64 %base, ptr %base.addr, align 8
# |   store i64 %step, ptr %step.addr, align 8
# |   %0 = load i64, ptr %base.addr, align 8
# |   %1 = load i64, ptr %step.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.index.nxv2i64(i64 %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.index.nxv2i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svindex_u8(i8 noundef %base, i8 noundef %step) #0 {
# | entry:
# |   %base.addr = alloca i8, align 1
# |   %step.addr = alloca i8, align 1
# |   store i8 %base, ptr %base.addr, align 1
# |   store i8 %step, ptr %step.addr, align 1
# |   %0 = load i8, ptr %base.addr, align 1
# |   %1 = load i8, ptr %step.addr, align 1
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.index.nxv16i8(i8 %0, i8 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svindex_u16(i16 noundef %base, i16 noundef %step) #0 {
# | entry:
# |   %base.addr = alloca i16, align 2
# |   %step.addr = alloca i16, align 2
# |   store i16 %base, ptr %base.addr, align 2
# |   store i16 %step, ptr %step.addr, align 2
# |   %0 = load i16, ptr %base.addr, align 2
# |   %1 = load i16, ptr %step.addr, align 2
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.index.nxv8i16(i16 %0, i16 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svindex_u32(i32 noundef %base, i32 noundef %step) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   %step.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   store i32 %step, ptr %step.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = load i32, ptr %step.addr, align 4
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.index.nxv4i32(i32 %0, i32 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svindex_u64(i64 noundef %base, i64 noundef %step) #0 {
# | entry:
# |   %base.addr = alloca i64, align 8
# |   %step.addr = alloca i64, align 8
# |   store i64 %base, ptr %base.addr, align 8
# |   store i64 %step, ptr %step.addr, align 8
# |   %0 = load i64, ptr %base.addr, align 8
# |   %1 = load i64, ptr %step.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.index.nxv2i64(i64 %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e904026eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e904023e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e90402762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe407c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe407ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe407c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe407c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e903fbcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e903fbca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e903fa18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e903c50e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e903c50b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe407c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe407c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe407c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e903c50a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c (1177 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64ff_v_f64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.mask.nxv1f64.i64.p0(<vscale x 1 x double> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.mask.nxv1f64.i64.p0(<vscale x 1 x double>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64ff_v_f64m2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.mask.nxv2f64.i64.p0(<vscale x 2 x double> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 2 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.mask.nxv2f64.i64.p0(<vscale x 2 x double>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vle64ff_v_f64m4_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.mask.nxv4f64.i64.p0(<vscale x 4 x double> poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 4 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.mask.nxv4f64.i64.p0(<vscale x 4 x double>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vle64ff_v_f64m8_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.mask.nxv8f64.i64.p0(<vscale x 8 x double> poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 8 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.mask.nxv8f64.i64.p0(<vscale x 8 x double>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64ff_v_i64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.mask.nxv1i64.i64.p0(<vscale x 1 x i64> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.mask.nxv1i64.i64.p0(<vscale x 1 x i64>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64ff_v_i64m2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.mask.nxv2i64.i64.p0(<vscale x 2 x i64> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 2 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.mask.nxv2i64.i64.p0(<vscale x 2 x i64>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64ff_v_i64m4_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.mask.nxv4i64.i64.p0(<vscale x 4 x i64> poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 4 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.mask.nxv4i64.i64.p0(<vscale x 4 x i64>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64ff_v_i64m8_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x i64>, i64 } @llvm.riscv.vleff.mask.nxv8i64.i64.p0(<vscale x 8 x i64> poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   %5
# | ...
# `---data was truncated (10240/15508) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560170ddceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560170dd9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560170ddd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe194733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe19478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe194733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe19471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560170d72bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560170d72a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560170d578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560170a06e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560170a06b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe19471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe19471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe19471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560170a06a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c (1178 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16mf4x6(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16mf2x6(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16m1x6(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005585fbd88eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005585fbd85e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005585fbd8962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa7b8649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa7b86a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa7b8649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa7b8631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005585fbd1ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005585fbd1ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005585fbd038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005585fb9b2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005585fb9b2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa7b8632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa7b86330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa7b86330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005585fb9b2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c (1179 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005588dace3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005588dace0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005588dace462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa9ebd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa9ebd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa9ebd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa9ebd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005588dac79bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005588dac79a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005588dac5e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005588da90de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005588da90db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa9ebd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa9ebd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa9ebd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005588da90da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c (1180 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsac_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsac_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsac_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsac_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsac_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsac_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsac_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsac_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 
# | ...
# `---data was truncated (10240/64244) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba2f5abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ba2f5a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ba2f5ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f61c8e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f61c8ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f61c8e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f61c8e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba2f541bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ba2f541a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ba2f5268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ba2f1d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ba2f1d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f61c8e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61c8e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61c8e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba2f1d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c (1181 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_f32m2x4_tu(target("riscv.vector.tuple", <vscale x 1
# | ...
# `---data was truncated (10240/227763) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560295f49eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560295f46e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560295f4a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa927733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa92778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa927733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa92771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560295edfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560295edfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560295ec48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560295b73e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560295b73b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa92771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa92771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa92771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560295b73a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c (1182 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f16m1x6(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f32m1x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f64m1x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef
# | ...
# `---data was truncated (10240/69988) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559905241eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055990523ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055990524262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9e81d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9e81d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9e81d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9e81d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005599051d7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005599051d7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005599051bc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559904e6be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559904e6bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9e81d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9e81d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9e81d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559904e6ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c (1183 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsge_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsge_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsge_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsge_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsge_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsge_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsge_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i
# | ...
# `---data was truncated (10240/63579) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005574b4e84eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005574b4e81e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005574b4e8562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f02dd133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f02dd18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f02dd133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f02dd11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005574b4e1abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005574b4e1aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005574b4dff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005574b4aaee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005574b4aaeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f02dd11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f02dd11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f02dd11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005574b4aaea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/neon/subtraction.c (1184 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/subtraction.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c --check-prefixes=LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vsub_s8(<8 x i8> noundef %v1, <8 x i8> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %v1.addr = alloca <8 x i8>, align 8
# |   %v2.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %v1, ptr %v1.addr, align 8
# |   store <8 x i8> %v2, ptr %v2.addr, align 8
# |   %0 = load <8 x i8>, ptr %v1.addr, align 8
# |   %1 = load <8 x i8>, ptr %v2.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %sub.i = sub <8 x i8> %2, %3
# |   store <8 x i8> %sub.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vsubq_s8(<16 x i8> noundef %v1, <16 x i8> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %v1.addr = alloca <16 x i8>, align 16
# |   %v2.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v1, ptr %v1.addr, align 16
# |   store <16 x i8> %v2, ptr %v2.addr, align 16
# |   %0 = load <16 x i8>, ptr %v1.addr, align 16
# |   %1 = load <16 x i8>, ptr %v2.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %sub.i = sub <16 x i8> %2, %3
# |   store <16 x i8> %sub.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vsub_s16(<4 x i16> noundef %v1, <4 x i16> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %v1.addr = alloca <4 x i16>, align 8
# |   %v2.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %v1, ptr %v1.addr, align 8
# |   store <4 x i16> %v2, ptr %v2.addr, align 8
# |   %0 = load <4 x i16>, ptr %v1.addr, align 8
# |   %1 = load <4 x i16>, ptr %v2.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %sub.i = sub <4 x i16> %2, %3
# |   store <4 x i16> %sub.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vsubq_s16(<8 x i16> noundef %v1, <8 x i16> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %v1.addr = alloca <8 x i16>, align 16
# |   %v2.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %v1, ptr %v1.addr, align 16
# |   store <8 x i16> %v2, ptr %v2.addr, align 16
# |   %0 = load <8 x i16>, ptr %v1.addr, align 16
# |   %1 = load <8 x i16>, ptr %v2.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %3 = load <8 x i16>, ptr %__p1.addr.i, align 16
# |   %sub.i = sub <8 x i16> %2, %3
# |   store <8 x i16> %sub.i, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vsub_s32(<2 x i32> noundef %v1, <2 x i32> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %v1.addr = alloca <2 x i32>, align 8
# |   %v2.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %v1, ptr %v1.addr, align 8
# |   store <2 x i32> %v2, ptr %v2.addr, align 8
# |   %0 = load <2 x i32>, ptr %v1.addr, align 8
# |   %1 = load <2 x i32>, ptr %v2.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %sub.i = sub <2 x i32> %2, %3
# |   store <2 x i32> %sub.i, ptr %__ret.i, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vsubq_s32(<4 x i32> noundef %v1, <4 x i32> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %v1.addr = alloca <4 x i32>, align 16
# |   %v2.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %v1, ptr %v1.addr, align 16
# |   store <4 x i32> %v2, ptr %v2.addr, align 16
# |   %0 = load <4 x i32>, ptr %v1.addr, align 16
# |   %1 = load <4 x i32>, ptr %v2.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <4 x i32> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %3 = load <4 x i32>, ptr %__p1.addr.i, align 16
# |   %sub.i = sub <4 x i32> %2, %3
# |   store <4 x i32> %sub.i, ptr %__ret.i, align 16
# |   %4 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vsub_s64(<1 x i64> noundef %v1, <1 x i64> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %v1.addr = alloca <1 x i64>, align 8
# |   %v2.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %v1, ptr %v1.addr, align 8
# |   store <1 x i64> %v2, ptr %v2.addr, align 8
# |   %0 = load <1 x i64>, ptr %v1.addr, align 8
# |   %1 = load <1 x i64>, ptr %v2.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   %3 = load <1 x i64>, ptr %__p1.addr.i, align 8
# |   %sub.i = sub <1 x i64> %2, %3
# |   store <1 x i64> %sub.i, ptr %__ret.i, align 8
# |   %4 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vsubq_s64(<2 x i64> noundef %v1, <2 x i64> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__p1.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %v1.addr = alloca <2 x i64>, align 16
# |   %v2.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %v1, ptr %v1.addr, align 16
# |   store <2 x i64> %v2, ptr %v2.addr, align 16
# |   %0 = load <2 x i64>, ptr %v1.addr, align 16
# |   %1 = load <2 x i64>, ptr %v2.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %3 = load <2 x i64>, ptr %__p1.addr.i, align 16
# |   %sub.i = sub <2 x i64> %2, %3
# |   store <2 x i64> %sub.i, ptr %__ret.i, align 16
# |   %4 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vsub_u8(<8 x i8> noundef %v1, <8 x i8> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %v1.addr = alloca <8 x i8>, align 8
# |   %v2.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %v1, ptr %v1.addr, align 8
# |   store <8 x i8> %v2, ptr %v2.addr, align 8
# |   %0 = load <8 x i8>, ptr %v1.addr, align 8
# |   %1 = load <8 x i8>, ptr %v2.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %sub.i = sub <8 x i8> %2, %3
# |   store <8 x i8> %sub.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vsub_u16(<4 x i16> noundef %v1, <4 x i16> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %v1.addr = alloca <4 x i16>, align 8
# |   %v2.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %v1, ptr %v1.addr, align 8
# |   store <4 x i16> %v2, ptr %v2.addr, align 8
# |   %0 = load <4 x i16>, ptr %v1.addr, align 8
# |   %1 = load <4 x i16>, ptr %v2.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %sub.i = sub <4 x i16> %2, %3
# |   store <4 x i16> %sub.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vsub_u32(<2 x i32> noundef %v1, <2 x i32> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %v1.addr = alloca <2 x i32>, align 8
# |   %v2.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %v1, ptr %v1.addr, align 8
# |   store <2 x i32> %v2, ptr %v2.addr, align 8
# |   %0 = load <2 x i32>, ptr %v1.addr, align 8
# |   %1 = load <2 x i32>, ptr %v2.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %sub.i = sub <2 x i32> %2, %3
# |   store <2 x i32> %sub.i, ptr %__ret.i, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vsub_u64(<1 x i64> noundef %v1, <1 x i64> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %v1.addr = alloca <1 x i64>, align 8
# |   %v2.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %v1, ptr %v1.addr, align 8
# |   
# | ...
# `---data was truncated (10240/170019) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# |  #0 0x0000555d764c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555d764bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555d764c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff14a81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff14a8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff14a81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff14a803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555d76457bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555d76457a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555d7643c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555d760ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555d760ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff14a804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff14a8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff14a8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555d760eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c --check-prefixes=LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c --check-prefixes=LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c (1185 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vunzipe_v_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 2 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(<vscale x 1 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(<vscale x 1 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vunzipe_v_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 4 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(<vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(<vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vunzipe_v_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 8 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vunzipe_v_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 16 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(<vscale x 8 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(<vscale x 8 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vunzipe_v_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 32 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(<vscale x 16 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(<vscale x 16 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vunzipe_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 2 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(<vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(<vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vunzipe_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 4 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(<vscale x 2 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vunzipe_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 8 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(<vscale x 4 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(<vscale x 4 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vunzipe_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 16 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(<vscale x 8 x float> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(<vscale x 8 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vunzipe_v_f64m1_tu(<vscale x 1 x double> %vd, <vscale x 2 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x double>, ptr %vs.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscal
# | ...
# `---data was truncated (10240/44426) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056484f1f7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056484f1f4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056484f1f862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab72649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab726a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab72649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab72631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056484f18dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056484f18da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056484f1728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056484ee21e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056484ee21b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fab72632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab726330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab726330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056484ee21a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c (1186 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vandn_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vandn_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vandn_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vandn_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vandn_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vandn_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vandn_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vandn_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vandn_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   
# | ...
# `---data was truncated (10240/223129) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c4c80d4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c4c80d1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c4c80d562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f86c8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f86c878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f86c8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f86c871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c4c806abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c4c806aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c4c804f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c4c7cfee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c4c7cfeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f86c871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f86c871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f86c871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c4c7cfea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c (1187 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4aus_vx_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4aus_vx_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Fu
# | ...
# `---data was truncated (10240/25086) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055984eb8deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055984eb8ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055984eb8e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1994a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1994aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1994a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1994a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055984eb23bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055984eb23a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055984eb088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055984e7b7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055984e7b7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1994a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1994a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1994a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055984e7b7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/neon-dot-product.c (1188 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-dot-product.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +dotprod  -disable-O0-optnone  -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +dotprod -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vdot_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <8 x i8> %3 to <2 x i32>
# |   %vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %4, <8 x i8> %5)
# |   store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vdotq_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   %c.addr = alloca <16 x i8>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   store <16 x i8> %c, ptr %c.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   %2 = load <16 x i8>, ptr %c.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vdot.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vdot1.i = call <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32> %vdot.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vdot1.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vdot_s32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <8 x i8> %3 to <2 x i32>
# |   %vdot1.i = call <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %4, <8 x i8> %5)
# |   store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vdotq_s32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   %c.addr = alloca <16 x i8>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   store <16 x i8> %c, ptr %c.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   %2 = load <16 x i8>, ptr %c.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vdot.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vdot1.i = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> %vdot.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vdot1.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vdot_lane_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   %__ret_831 = alloca <2 x i32>, align 8
# |   %__s0_831 = alloca <2 x i32>, align 8
# |   %__s1_831 = alloca <8 x i8>, align 8
# |   %__s2_831 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <2 x i32>, align 8
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp1 = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   %tmp2 = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0_831, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1_831, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <8 x i8> %2, ptr %__s2_831, align 8
# |   %3 = load <2 x i32>, ptr %__s0_831, align 8
# |   %4 = load <8 x i8>, ptr %__s1_831, align 8
# |   %5 = load <2 x i32>, ptr %__s2_831, align 8
# |   store <2 x i32> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x i32>
# |   %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> <i32 1, i32 1>
# |   store <2 x i32> %lane, ptr %ref.tmp1, align 8
# |   %8 = load <2 x i32>, ptr %ref.tmp1, align 8
# |   store <2 x i32> %8, ptr %__ret, align 8
# |   %9 = load <2 x i32>, ptr %__ret, align 8
# |   store <2 x i32> %9, ptr %tmp, align 8
# |   %10 = load <2 x i32>, ptr %tmp, align 8
# |   store <2 x i32> %10, ptr %ref.tmp, align 8
# |   %11 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <2 x i32> %3, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %4, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %11, ptr %__p2.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %14 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <8 x i8> %12 to <2 x i32>
# |   %vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %13, <8 x i8> %14)
# |   store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8
# |   %15 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %15, ptr %__ret.i, align 8
# |   %16 = load <2 x i32>, ptr %__ret.i, align 8
# |   store <2 x i32> %16, ptr %__ret_831, align 8
# |   %17 = load <2 x i32>, ptr %__ret_831, align 8
# |   store <2 x i32> %17, ptr %tmp2, align 8
# |   %18 = load <2 x i32>, ptr %tmp2, align 8
# |   ret <2 x i32> %18
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vdotq_lane_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   %c.addr = alloca <8 x i8>, align 8
# |   %__ret_827 = alloca <4 x i32>, align 16
# |   %__s0_827 = alloca <4 x i32>, align 16
# |   %__s1_827 = alloca <16 x i8>, align 16
# |   %__s2_827 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <4 x i32>, align 16
# |   %__ret = alloca <4 x i32>, align 16
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp1 = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x i32>, align 16
# |   %tmp2 = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__s0_827, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   store <16 x i8> %1, ptr %__s1_827, align 16
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <8 x i8> %2, ptr %__s2_827, align 8
# |   %3 = load <4 x i32>, ptr %__s0_827, align 16
# |   %4 = load <16 x i8>, ptr %__s1_827, align 16
# |   %5 = load <2 x i32>, ptr %__s2_827, align 8
# |   store <2 x i32> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__
# | ...
# `---data was truncated (10240/29862) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine
# |  #0 0x000055eaa9658eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eaa9655e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eaa965962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f21ea81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f21ea8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f21ea81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f21ea803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eaa95eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eaa95eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eaa95d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eaa9282e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eaa9282b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f21ea804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f21ea8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f21ea8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eaa9282a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c (1189 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdm_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdm.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdm.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdm_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdm_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdm_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesdm_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdm_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdm_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare
# | ...
# `---data was truncated (10240/20141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b6211feeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b6211fbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b6211ff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc72049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc720a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc72049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc72031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b621194bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b621194a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b6211798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b620e28e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b620e28b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcc72032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc720330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc720330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b620e28a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c (1190 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4au_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4au_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.add
# | ...
# `---data was truncated (10240/14453) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056122a71eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056122a71be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056122a71f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3044c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3044ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3044c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3044c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056122a6b4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056122a6b4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056122a6998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056122a348e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056122a348b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3044c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3044c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3044c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056122a348a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c (1191 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8(<vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4(<vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2(<vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1(<vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_x_f_qf_i8m2(<vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs
# | ...
# `---data was truncated (10240/12433) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cc0e993eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cc0e990e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cc0e99462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feda8d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feda8d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feda8d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feda8d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc0e929bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cc0e929a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cc0e90e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cc0e5bde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cc0e5bdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feda8d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feda8d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feda8d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc0e5bda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c (1192 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vv_f32mf2(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vf_f32mf2(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wv_f32mf2(<vscale x 1 x float> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wf_f32mf2(<vscale x 1 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vv_f32m1(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vf_f32m1(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wv_f32m1(<vscale x 2 x float> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wf_f32m1(<vscale x 2 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwsub_vv_f32m2(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwsub_vf_f32m2(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2
# | ...
# `---data was truncated (10240/151911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564a8b8f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564a8b8f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564a8b8f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f69bea1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f69bea725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f69bea1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f69bea03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564a8b88ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564a8b88ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564a8b8738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564a8b522e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564a8b522b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f69bea04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f69bea050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f69bea050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564a8b522a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c (1193 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfdiv_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfdiv_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfdiv_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfdiv_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfdiv_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfdiv_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfdiv_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfdiv_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfdiv_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfdiv.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfdiv.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfdiv_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfdiv.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i
# | ...
# `---data was truncated (10240/125641) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561ae9469eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561ae9466e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561ae946a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd32133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd3218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd32133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd3211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561ae93ffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561ae93ffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561ae93e48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561ae9093e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561ae9093b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcd3211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd3211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd3211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561ae9093a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/distributed-thin-lto/objc-contract-pass.ll (1194 of 27911)
******************** TEST 'Clang :: CodeGen/distributed-thin-lto/objc-contract-pass.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/objc-contract-pass.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/objc-contract-pass.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/objc-contract-pass.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/objc-contract-pass.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/objc-contract-pass.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/objc-contract-pass.ll
# |  #0 0x000055c224df9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c224df6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c224dfa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8feee1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8feee725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8feee1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8feee03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c224d8fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c224d8fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c224d748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c224a23e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c224a23b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8feee04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8feee050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8feee050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c224a23a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c (1195 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaeskf2_vi_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaeskf2.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaeskf2.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaeskf2_vi_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaeskf2.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaeskf2.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaeskf2_vi_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaeskf2_vi_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaeskf2.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaeskf2.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaeskf2_vi_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaeskf2.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaeskf2.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a57e0a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a57e09fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a57e0a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f338101bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f33810725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f338101ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3381003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a57e038bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a57e038a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a57e01d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a57dccce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a57dcccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3381004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f33810050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f33810050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a57dccca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c (1196 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrol_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrol_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrol_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrol_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrol_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrol_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrol_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrol_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrol_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %v
# | ...
# `---data was truncated (10240/222307) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bcdbb2eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bcdbb2be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bcdbb2f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff608533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff60858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff608533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff60851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bcdbac4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bcdbac4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bcdbaa98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bcdb758e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bcdb758b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff60851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff60851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff60851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bcdb758a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c (1197 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei32_v_i8mf8x5
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056356cd1deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056356cd1ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056356cd1e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f19ec849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f19ec8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f19ec849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f19ec831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056356ccb3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056356ccb3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056356cc988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056356c947e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056356c947b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f19ec832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f19ec8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f19ec8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056356c947a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c (1198 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_f32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_f32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_i32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_i32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_u32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_u32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vsca
# | ...
# `---data was truncated (10240/15944) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c6d28cfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c6d28cce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c6d28d062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2912249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f29122a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2912249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2912231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c6d2865bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c6d2865a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c6d284a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c6d24f9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c6d24f9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2912232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f29122330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f29122330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c6d24f9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c (1199 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vbrev_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vbrev_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vbrev.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vbrev.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vbrev_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vbrev.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vbrev.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vbrev_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vbrev.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vbrev.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vbrev_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vbrev.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vbrev.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vbrev_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vbrev.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vbrev.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vbrev_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vbrev.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vbrev.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vbrev_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vbrev.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vbrev.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vbrev_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vbrev.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vbrev.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vbrev_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vbrev.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vbrev.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define ds
# | ...
# `---data was truncated (10240/95215) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eba4971eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eba496ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eba497262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5904733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f590478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5904733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f590471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eba4907bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eba4907a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eba48ec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eba459be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eba459bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f590471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f590471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f590471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eba459ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/neon/bf16-getset.c (1200 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/bf16-getset.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local bfloat @test_vduph_lane_bf16(<4 x bfloat> noundef %v) #0 {
# | entry:
# |   %v.addr = alloca <4 x bfloat>, align 8
# |   %__ret = alloca bfloat, align 2
# |   %__s0 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca bfloat, align 2
# |   %tmp = alloca bfloat, align 2
# |   store <4 x bfloat> %v, ptr %v.addr, align 8
# |   %0 = load <4 x bfloat>, ptr %v.addr, align 8
# |   store <4 x bfloat> %0, ptr %__s0, align 8
# |   %1 = load <4 x bfloat>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x bfloat> %1, i32 1
# |   store bfloat %vget_lane, ptr %ref.tmp, align 2
# |   %2 = load bfloat, ptr %ref.tmp, align 2
# |   store bfloat %2, ptr %__ret, align 2
# |   %3 = load bfloat, ptr %__ret, align 2
# |   store bfloat %3, ptr %tmp, align 2
# |   %4 = load bfloat, ptr %tmp, align 2
# |   ret bfloat %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local bfloat @test_vduph_laneq_bf16(<8 x bfloat> noundef %v) #0 {
# | entry:
# |   %v.addr = alloca <8 x bfloat>, align 16
# |   %__ret = alloca bfloat, align 2
# |   %__s0 = alloca <8 x bfloat>, align 16
# |   %ref.tmp = alloca bfloat, align 2
# |   %tmp = alloca bfloat, align 2
# |   store <8 x bfloat> %v, ptr %v.addr, align 16
# |   %0 = load <8 x bfloat>, ptr %v.addr, align 16
# |   store <8 x bfloat> %0, ptr %__s0, align 16
# |   %1 = load <8 x bfloat>, ptr %__s0, align 16
# |   %vgetq_lane = extractelement <8 x bfloat> %1, i32 7
# |   store bfloat %vgetq_lane, ptr %ref.tmp, align 2
# |   %2 = load bfloat, ptr %ref.tmp, align 2
# |   store bfloat %2, ptr %__ret, align 2
# |   %3 = load bfloat, ptr %__ret, align 2
# |   store bfloat %3, ptr %tmp, align 2
# |   %4 = load bfloat, ptr %tmp, align 2
# |   ret bfloat %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vdup_lane_bf16(<4 x bfloat> noundef %v) #0 {
# | entry:
# |   %v.addr = alloca <4 x bfloat>, align 8
# |   %__ret_48 = alloca <4 x bfloat>, align 8
# |   %__s0_48 = alloca <4 x bfloat>, align 8
# |   %__ret = alloca <4 x bfloat>, align 8
# |   %__s0 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x bfloat>, align 8
# |   %tmp1 = alloca <4 x bfloat>, align 8
# |   store <4 x bfloat> %v, ptr %v.addr, align 8
# |   %0 = load <4 x bfloat>, ptr %v.addr, align 8
# |   store <4 x bfloat> %0, ptr %__s0_48, align 8
# |   %1 = load <4 x bfloat>, ptr %__s0_48, align 8
# |   store <4 x bfloat> %1, ptr %__s0, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = bitcast <8 x i8> %2 to <4 x bfloat>
# |   %lane = shufflevector <4 x bfloat> %3, <4 x bfloat> %3, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
# |   store <4 x bfloat> %lane, ptr %ref.tmp, align 8
# |   %4 = load <4 x bfloat>, ptr %ref.tmp, align 8
# |   store <4 x bfloat> %4, ptr %__ret, align 8
# |   %5 = load <4 x bfloat>, ptr %__ret, align 8
# |   store <4 x bfloat> %5, ptr %tmp, align 8
# |   %6 = load <4 x bfloat>, ptr %tmp, align 8
# |   store <4 x bfloat> %6, ptr %__ret_48, align 8
# |   %7 = load <4 x bfloat>, ptr %__ret_48, align 8
# |   store <4 x bfloat> %7, ptr %tmp1, align 8
# |   %8 = load <4 x bfloat>, ptr %tmp1, align 8
# |   ret <4 x bfloat> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vdupq_lane_bf16(<4 x bfloat> noundef %v) #0 {
# | entry:
# |   %v.addr = alloca <4 x bfloat>, align 8
# |   %__ret_46 = alloca <8 x bfloat>, align 16
# |   %__s0_46 = alloca <4 x bfloat>, align 8
# |   %__ret = alloca <8 x bfloat>, align 16
# |   %__s0 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x bfloat>, align 16
# |   %tmp1 = alloca <8 x bfloat>, align 16
# |   store <4 x bfloat> %v, ptr %v.addr, align 8
# |   %0 = load <4 x bfloat>, ptr %v.addr, align 8
# |   store <4 x bfloat> %0, ptr %__s0_46, align 8
# |   %1 = load <4 x bfloat>, ptr %__s0_46, align 8
# |   store <4 x bfloat> %1, ptr %__s0, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = bitcast <8 x i8> %2 to <4 x bfloat>
# |   %lane = shufflevector <4 x bfloat> %3, <4 x bfloat> %3, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
# |   store <8 x bfloat> %lane, ptr %ref.tmp, align 16
# |   %4 = load <8 x bfloat>, ptr %ref.tmp, align 16
# |   store <8 x bfloat> %4, ptr %__ret, align 16
# |   %5 = load <8 x bfloat>, ptr %__ret, align 16
# |   store <8 x bfloat> %5, ptr %tmp, align 16
# |   %6 = load <8 x bfloat>, ptr %tmp, align 16
# |   store <8 x bfloat> %6, ptr %__ret_46, align 16
# |   %7 = load <8 x bfloat>, ptr %__ret_46, align 16
# |   store <8 x bfloat> %7, ptr %tmp1, align 16
# |   %8 = load <8 x bfloat>, ptr %tmp1, align 16
# |   ret <8 x bfloat> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vdup_laneq_bf16(<8 x bfloat> noundef %v) #0 {
# | entry:
# |   %v.addr = alloca <8 x bfloat>, align 16
# |   %__ret_52 = alloca <4 x bfloat>, align 8
# |   %__s0_52 = alloca <8 x bfloat>, align 16
# |   %__ret = alloca <4 x bfloat>, align 8
# |   %__s0 = alloca <8 x bfloat>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x bfloat>, align 8
# |   %tmp1 = alloca <4 x bfloat>, align 8
# |   store <8 x bfloat> %v, ptr %v.addr, align 16
# |   %0 = load <8 x bfloat>, ptr %v.addr, align 16
# |   store <8 x bfloat> %0, ptr %__s0_52, align 16
# |   %1 = load <8 x bfloat>, ptr %__s0_52, align 16
# |   store <8 x bfloat> %1, ptr %__s0, align 16
# |   %2 = load <16 x i8>, ptr %__s0, align 16
# |   %3 = bitcast <16 x i8> %2 to <8 x bfloat>
# |   %lane = shufflevector <8 x bfloat> %3, <8 x bfloat> %3, <4 x i32> <i32 7, i32 7, i32 7, i32 7>
# |   store <4 x bfloat> %lane, ptr %ref.tmp, align 8
# |   %4 = load <4 x bfloat>, ptr %ref.tmp, align 8
# |   store <4 x bfloat> %4, ptr %__ret, align 8
# |   %5 = load <4 x bfloat>, ptr %__ret, align 8
# |   store <4 x bfloat> %5, ptr %tmp, align 8
# |   %6 = load <4 x bfloat>, ptr %tmp, align 8
# |   store <4 x bfloat> %6, ptr %__ret_52, align 8
# |   %7 = load <4 x bfloat>, ptr %__ret_52, align 8
# |   store <4 x bfloat> %7, ptr %tmp1, align 8
# |   %8 = load <4 x bfloat>, ptr %tmp1, align 8
# |   ret <4 x bfloat> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vdupq_laneq_bf16(<8 x bfloat> noundef %v) #0 {
# | entry:
# |   %v.addr = alloca <8 x bfloat>, align 16
# |   %__ret_50 = alloca <8 x bfloat>, align 16
# |   %__s0_50 = alloca <8 x bfloat>, align 16
# |   %__ret = alloca <8 x bfloat>, align 16
# |   %__s0 = alloca <8 x bfloat>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x bfloat>, align 16
# |   %tmp1 = alloca <8 x bfloat>, align 16
# |   store <8 x bfloat> %v, ptr %v.addr, align 16
# |   %0 = load <8 x bfloat>, ptr %v.addr, align 16
# |   store <8 x bfloat> %0, ptr %__s0_50, align 16
# |   %1 = load <8 x bfloat>, ptr %__s0_50, align 16
# |   store <8 x bfloat> %1, ptr %__s0, align 16
# |   %2 = load <16 x i8>, ptr %__s0, align 16
# |   %3 = bitcast <16 x i8> %2 to <8 x bfloat>
# |   %lane = shufflevector <8 x bfloat> %3, <8 x bfloat> %3, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
# |   store <8 x bfloat> %lane, ptr %ref.tmp, align 16
# |   %4 = load <8 x bfloat>, ptr %ref.tmp, align 16
# |   store <8 x bfloat> %4, ptr %__ret, align 16
# |   %5 = load <8 x bfloat>, ptr %__ret, align 16
# |   store <8 x bfloat> %5, ptr %tmp, align 16
# |   %6 = load <8 x bfloat>, ptr %tmp, align 16
# |   store <8 x bfloat> %6, ptr %__ret_50, align 16
# |   %7 = load <8 x bfloat>, ptr %__ret_50, align 16
# |   store <8 x bfloat> %7, ptr %tmp1, align 16
# |   %8 = load <8 x bfloat>, ptr %tmp1, align 16
# |   ret <8 x bfloat> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vdup_n_bf16(bfloat noundef %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca bfloat, align 2
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %.compoundliteral.i = alloca <4 x bfloat>, align 8
# |   %v.addr = alloca bfloat, align 2
# |   store bfloat %v, ptr %v.addr, align 2
# |   %0 = load bfloat, ptr %v.addr, align 2
# |   store bfloat %0, ptr %__p0.addr.i, align 2
# |   %1 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit.i = insertelement <4 x bfloat> poison, bfloat %1, i32 0
# |   %2 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit1.i = insertelement <4 x bfloat> %vecinit.i, bfloat %2, i32 1
# |   %3 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit2.i = insertelement <4 x bfloat> %vecinit1.i, bfloat %3, i32 2
# |   %4 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit3.i = insertelement <4 x bfloat> %vecinit2.i, bfloat %4, i32 3
# |   store <4 x bfloat> %vecinit3.i, ptr %.compoundliteral.i, align 8
# |   %5 = load <4 x bfloat>, ptr %.compoundliteral.i, align 8
# |   store <4 x bfloat> %5, ptr %__ret.i, align 8
# |   %6 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vdupq_n_bf16(bfloat noundef %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca bfloat, align 2
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %.compoundliteral.i = alloca <8 x bfloat>, align 16
# |   %v.addr = alloca bfloat, align 2
# |   store bfloat %v, ptr %v.addr, align 2
# |   %0 = load bfloat, ptr %v.addr, align 2
# |   store bfloat %0, ptr %__p0.addr.i, align 2
# |   %1 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit.i = insertelement <8 x bfloat> poison, bfloat %1, i32 0
# |   %2 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit1.i = insertelement <8 x bfloat> %vecinit.i, bfloat %2, i32 1
# |   %3 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit2.i = insertelement <8 x bfloat> %vecinit1.i, bfloat %3, i32 2
# |   %4 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit3.i = insertelement <8 x bfloat> %vecinit2.i, bfloat %4, i32 3
# |   %5 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit4.i = insertelement <8 x bfloat> %vecinit3.i, bfloat %5, i32 4
# |   %6 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit5.i = insertelement <8 x bfloat> %vecinit4.i, bfloat %6, i32 5
# |   %7 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit6.i = insertelement <8 x bfloat> %vecinit5.i, bfloat %7, i32 6
# |   %8 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit7.i = insertelement <8 x bfloat> %vecinit6.i, bfloat %8, i32 7
# |   store <8 x bfloat> %vecinit7.i, ptr %.compoundliteral.i, align 16
# |   %9 = load <8 x bfloat>, ptr %.compoundliteral.i, align 16
# |   store <8 x bfloat> %9, ptr %__ret.i, align 16
# |   %10 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %10
# | }
# | 
# | ; Function Attrs: noinline noun
# | ...
# `---data was truncated (10240/13833) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055b295b6beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b295b68e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b295b6c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe8bb333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe8bb38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe8bb333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe8bb31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b295b01bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b295b01a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b295ae68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b295795e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b295795b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe8bb31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe8bb31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe8bb31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b295795a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGenCXX/ctor-globalopt.cpp (1201 of 27911)
******************** TEST 'Clang :: CodeGenCXX/ctor-globalopt.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp -O2 | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp --check-prefix=O1
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp -O2
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | %struct.B = type <{ ptr, i32, [4 x i8], %struct.A.base, [4 x i8] }>
# | %struct.A.base = type <{ ptr, i32 }>
# | 
# | @b = local_unnamed_addr global %struct.B <{ ptr getelementptr inbounds inrange(-24, 8) (i8, ptr @_ZTV1B, i64 24), i32 0, [4 x i8] zeroinitializer, %struct.A.base <{ ptr getelementptr inbounds inrange(-24, 8) (i8, ptr @_ZTV1B, i64 56), i32 0 }>, [4 x i8] zeroinitializer }>, align 8
# | @_ZTV1B = external constant { [4 x ptr], [4 x ptr] }, align 8
# | @llvm.global_ctors = appending global [0 x { i32, ptr, ptr }] zeroinitializer
# | 
# | !llvm.ident = !{!0}
# | !llvm.errno.tbaa = !{!1}
# | 
# | !0 = !{!"clang version 24.0.0"}
# | !1 = !{!2, !3, i64 0}
# | !2 = !{!"__libc_errno", !3, i64 0}
# | !3 = !{!"int", !4, i64 0}
# | !4 = !{!"omnipotent char", !5, i64 0}
# | !5 = !{!"Simple C++ TBAA"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o -
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o -
# |  #0 0x00005585a08f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005585a08efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005585a08f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f12d361bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f12d36725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f12d361ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f12d3603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005585a0888bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005585a0888a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005585a086d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005585a051ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005585a051cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f12d3604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f12d36050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f12d36050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005585a051ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp --check-prefix=O1
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp --check-prefix=O1
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c (1202 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f16mf4(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f16mf2(ptr noundef %base, <vscale x 2 x i64> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f16m1(ptr noundef %base, <vscale x 4 x i64> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f16m2(ptr noundef %base, <vscale x 8 x i64> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f32mf2(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f32m1(ptr noundef %base, <vscale x 2 x i64> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f32m2(ptr noundef %base, <vscale x 4 x i64> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f32m4(ptr noundef %base, <vscale x 8 x i64> %bindex, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f64m1(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret voi
# | ...
# `---data was truncated (10240/102304) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e46bb8deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e46bb8ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e46bb8e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fae02a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fae02aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fae02a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fae02a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e46bb23bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e46bb23a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e46bb088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e46b7b7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e46b7b7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fae02a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fae02a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fae02a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e46b7b7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/neon/conversion-fullfp16.c (1203 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/conversion-fullfp16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16           -emit-llvm  /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c --check-prefixes=LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcvt_s16_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %vcvtz.i = call <4 x i16> @llvm.fptosi.sat.v4i16.v4f16(<4 x half> %2)
# |   store <4 x i16> %vcvtz.i, ptr %ref.tmp.i, align 8
# |   %3 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %3, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcvtq_s16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %vcvtz.i = call <8 x i16> @llvm.fptosi.sat.v8i16.v8f16(<8 x half> %2)
# |   store <8 x i16> %vcvtz.i, ptr %ref.tmp.i, align 16
# |   %3 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %3, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcvt_u16_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %vcvtz.i = call <4 x i16> @llvm.fptoui.sat.v4i16.v4f16(<4 x half> %2)
# |   store <4 x i16> %vcvtz.i, ptr %ref.tmp.i, align 8
# |   %3 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %3, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcvtq_u16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %vcvtz.i = call <8 x i16> @llvm.fptoui.sat.v8i16.v8f16(<8 x half> %2)
# |   store <8 x i16> %vcvtz.i, ptr %ref.tmp.i, align 16
# |   %3 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %3, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i16> @llvm.fptosi.sat.v4i16.v4f16(<4 x half>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i16> @llvm.fptosi.sat.v8i16.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i16> @llvm.fptoui.sat.v4i16.v4f16(<4 x half>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i16> @llvm.fptoui.sat.v8i16.v8f16(<8 x half>) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000560f6859ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560f68599e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560f6859d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe515e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe515ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe515e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe515e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f68532bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560f68532a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560f685178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560f681c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560f681c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe515e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe515e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe515e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f681c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c --check-prefixes=LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c --check-prefixes=LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c (1204 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vcreate_v_bf16m1_bf16m2(<vscale x 4 x bfloat> %v0, <vscale x 4 x bfloat> %v1) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %v0, ptr %v0.addr, align 2
# |   store <vscale x 4 x bfloat> %v1, ptr %v1.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %v1.addr, align 2
# |   %2 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   %3 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> %2, <vscale x 4 x bfloat> %1, i64 4)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vcreate_v_bf16m1_bf16m4(<vscale x 4 x bfloat> %v0, <vscale x 4 x bfloat> %v1, <vscale x 4 x bfloat> %v2, <vscale x 4 x bfloat> %v3) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %v0, ptr %v0.addr, align 2
# |   store <vscale x 4 x bfloat> %v1, ptr %v1.addr, align 2
# |   store <vscale x 4 x bfloat> %v2, ptr %v2.addr, align 2
# |   store <vscale x 4 x bfloat> %v3, ptr %v3.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %v1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %v2.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %v3.addr, align 2
# |   %4 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   %5 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> %4, <vscale x 4 x bfloat> %1, i64 4)
# |   %6 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> %5, <vscale x 4 x bfloat> %2, i64 8)
# |   %7 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> %6, <vscale x 4 x bfloat> %3, i64 12)
# |   ret <vscale x 16 x bfloat> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vcreate_v_bf16m1_bf16m8(<vscale x 4 x bfloat> %v0, <vscale x 4 x bfloat> %v1, <vscale x 4 x bfloat> %v2, <vscale x 4 x bfloat> %v3, <vscale x 4 x bfloat> %v4, <vscale x 4 x bfloat> %v5, <vscale x 4 x bfloat> %v6, <vscale x 4 x bfloat> %v7) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v4.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v5.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v6.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v7.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %v0, ptr %v0.addr, align 2
# |   store <vscale x 4 x bfloat> %v1, ptr %v1.addr, align 2
# |   store <vscale x 4 x bfloat> %v2, ptr %v2.addr, align 2
# |   store <vscale x 4 x bfloat> %v3, ptr %v3.addr, align 2
# |   store <vscale x 4 x bfloat> %v4, ptr %v4.addr, align 2
# |   store <vscale x 4 x bfloat> %v5, ptr %v5.addr, align 2
# |   store <vscale x 4 x bfloat> %v6, ptr %v6.addr, align 2
# |   store <vscale x 4 x bfloat> %v7, ptr %v7.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %v1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %v2.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %v3.addr, align 2
# |   %4 = load <vscale x 4 x bfloat>, ptr %v4.addr, align 2
# |   %5 = load <vscale x 4 x bfloat>, ptr %v5.addr, align 2
# |   %6 = load <vscale x 4 x bfloat>, ptr %v6.addr, align 2
# |   %7 = load <vscale x 4 x bfloat>, ptr %v7.addr, align 2
# |   %8 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   %9 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %8, <vscale x 4 x bfloat> %1, i64 4)
# |   %10 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %9, <vscale x 4 x bfloat> %2, i64 8)
# |   %11 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %10, <vscale x 4 x bfloat> %3, i64 12)
# |   %12 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %11, <vscale x 4 x bfloat> %4, i64 16)
# |   %13 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %12, <vscale x 4 x bfloat> %5, i64 20)
# |   %14 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %13, <vscale x 4 x bfloat> %6, i64 24)
# |   %15 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %14, <vscale x 4 x bfloat> %7, i64 28)
# |   ret <vscale x 32 x bfloat> %15
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vcreate_v_bf16m2_bf16m4(<vscale x 8 x bfloat> %v0, <vscale x 8 x bfloat> %v1) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %v1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %v0, ptr %v0.addr, align 2
# |   store <vscale x 8 x bfloat> %v1, ptr %v1.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %v1.addr, align 2
# |   %2 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 0)
# |   %3 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat> %2, <vscale x 8 x bfloat> %1, i64 8)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vcreate_v_bf16m2_bf16m8(<vscale x 8 x bfloat> %v0, <vscale x 8 x bfloat> %v1, <vscale x 8 x bfloat> %v2, <vscale x 8 x bfloat> %v3) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %v1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %v2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %v3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %v0, ptr %v0.addr, align 2
# |   store <vscale x 8 x bfloat> %v1, ptr %v1.addr, align 2
# |   store <vscale x 8 x bfloat> %v2, ptr %v2.addr, align 2
# |   store <vscale x 8 x bfloat> %v3, ptr %v3.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %v1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %v2.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %v3.addr, align 2
# |   %4 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 0)
# |   %5 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat> %4, <vscale x 8 x bfloat> %1, i64 8)
# |   %6 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat> %5, <vscale x 8 x bfloat> %2, i64 16)
# |   %7 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat> %6, <vscale x 8 x bfloat> %3, i64 24)
# |   ret <vscale x 32 x bfloat> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat>, <vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vcreate_v_bf16m4_bf16m8(<vscale x 16 x bfloat> %v0, <vscale x 16 x bfloat> %v1) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %v1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %v0, ptr %v0.addr, align 2
# |   store <vscale x 16 x bfloat> %v1, ptr %v1.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %v1.addr, align 2
# |   %2 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv16bf16(<vscale x 32 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 0)
# |   %3 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv16bf16(<vscale x 32 x bfloat> %2, <vscale x 16 x bfloat> %1, i64 16)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv16bf16(<vscale x 32 x bfloat>, <vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vcreate_v_bf16mf4x2(<vscale x 1 x bfloat> %v0, <vscale x 1 x bfloat> %v1) #0 {
# | entry:
# |   %v0.add
# | ...
# `---data was truncated (10240/71275) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005597a86cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005597a86cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005597a86ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c07a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c07aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c07a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c07a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005597a8663bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005597a8663a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005597a86488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005597a82f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005597a82f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7c07a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c07a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c07a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005597a82f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c (1205 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgtu_vv_u8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgtu_vx_u8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgtu_vv_u8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgtu_vx_u8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgtu_vv_u8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgtu_vx_u8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgtu_vv_u8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgtu_vx_u8m1_b8(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgtu_vv_u8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgtu_vx_u8m2_b4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsgtu_vv_u8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.n
# | ...
# `---data was truncated (10240/95355) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558ff84e1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558ff84dee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558ff84e262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb5e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb5e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb5e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb5e11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558ff8477bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558ff8477a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558ff845c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558ff810be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558ff810bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feb5e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb5e11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb5e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558ff810ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c (1206 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_i16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_i16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8
# | ...
# `---data was truncated (10240/80508) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a0ecb41eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a0ecb3ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a0ecb4262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec3481bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec348725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec3481ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec34803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a0ecad7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a0ecad7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a0ecabc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a0ec76be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a0ec76bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fec34804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec348050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec348050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a0ec76ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c (1207 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_i16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_i16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_i16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_u16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_u16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x 
# | ...
# `---data was truncated (10240/53338) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ab716efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ab716ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ab716f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f089d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f089d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f089d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f089d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ab71685bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ab71685a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ab7166a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ab71319e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ab71319b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f089d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f089d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f089d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ab71319a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c (1208 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_f32m2x3_tu(target("riscv.vector.tuple", <vscale x 1
# | ...
# `---data was truncated (10240/227763) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba9df8deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ba9df8ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ba9df8e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0497a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0497aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0497a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0497a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba9df23bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ba9df23a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ba9df088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ba9dbb7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ba9dbb7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0497a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0497a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0497a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba9dbb7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c (1209 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_bf16mf4x2(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_bf16mf2x2(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_bf16m1x2(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_bf16m2x2(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_bf16m4x2(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x
# | ...
# `---data was truncated (10240/12177) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056201cbaeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056201cbabe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056201cbaf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f65d5b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f65d5b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f65d5b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f65d5b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056201cb44bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056201cb44a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056201cb298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056201c7d8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056201c7d8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f65d5b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f65d5b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f65d5b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056201c7d8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c (1210 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vclz_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vclz_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vclz.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vclz.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vclz_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vclz.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vclz.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vclz_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vclz.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vclz.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vclz_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vclz.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vclz.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vclz_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vclz.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vclz.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vclz_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vclz.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vclz.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vclz_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vclz.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vclz.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vclz_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vclz.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vclz.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vclz_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vclz.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vclz.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i1
# | ...
# `---data was truncated (10240/95001) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f25bb6beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f25bb68e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f25bb6c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f58f5849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f58f58a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f58f5849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f58f5831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f25bb01bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f25bb01a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f25bae68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f25b795e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f25b795b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f58f5832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f58f58330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f58f58330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f25b795a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c (1211 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8(<vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4(<vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2(<vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1(<vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_x_f_qf_i8m2(<vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocall
# | ...
# `---data was truncated (10240/12425) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e0bf3fdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e0bf3fae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e0bf3fe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f643a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f643a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f643a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f643a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e0bf393bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e0bf393a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e0bf3788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e0bf027e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e0bf027b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f643a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f643a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f643a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e0bf027a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c (1212 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei64_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005621c9f28eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005621c9f25e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005621c9f2962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f549a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f549a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f549a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f549a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005621c9ebebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005621c9ebea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005621c9ea38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005621c9b52e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005621c9b52b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f549a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f549a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f549a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005621c9b52a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/arm-neon-fma.c (1213 of 27911)
******************** TEST 'Clang :: CodeGen/arm-neon-fma.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-none-linux-gnueabihf    -target-abi aapcs    -target-cpu cortex-a7    -mfloat-abi hard    -ffreestanding    -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-none-linux-gnueabihf -target-abi aapcs -target-cpu cortex-a7 -mfloat-abi hard -ffreestanding -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv7-none-linux-gnueabihf"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_fma_order(<2 x float> noundef %accum, <2 x float> noundef %lhs, <2 x float> noundef %rhs) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__p2.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %accum.addr = alloca <2 x float>, align 8
# |   %lhs.addr = alloca <2 x float>, align 8
# |   %rhs.addr = alloca <2 x float>, align 8
# |   store <2 x float> %accum, ptr %accum.addr, align 8
# |   store <2 x float> %lhs, ptr %lhs.addr, align 8
# |   store <2 x float> %rhs, ptr %rhs.addr, align 8
# |   %0 = load <2 x float>, ptr %accum.addr, align 8
# |   %1 = load <2 x float>, ptr %lhs.addr, align 8
# |   %2 = load <2 x float>, ptr %rhs.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   store <2 x float> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %6 = bitcast <8 x i8> %3 to <2 x float>
# |   %7 = bitcast <8 x i8> %4 to <2 x float>
# |   %8 = bitcast <8 x i8> %5 to <2 x float>
# |   %9 = call <2 x float> @llvm.fma.v2f32(<2 x float> %7, <2 x float> %8, <2 x float> %6)
# |   store <2 x float> %9, ptr %ref.tmp.i, align 8
# |   %10 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %10, ptr %__ret.i, align 8
# |   %11 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_fmaq_order(<4 x float> noundef %accum, <4 x float> noundef %lhs, <4 x float> noundef %rhs) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__p1.addr.i = alloca <4 x float>, align 8
# |   %__p2.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %accum.addr = alloca <4 x float>, align 8
# |   %lhs.addr = alloca <4 x float>, align 8
# |   %rhs.addr = alloca <4 x float>, align 8
# |   store <4 x float> %accum, ptr %accum.addr, align 8
# |   store <4 x float> %lhs, ptr %lhs.addr, align 8
# |   store <4 x float> %rhs, ptr %rhs.addr, align 8
# |   %0 = load <4 x float>, ptr %accum.addr, align 8
# |   %1 = load <4 x float>, ptr %lhs.addr, align 8
# |   %2 = load <4 x float>, ptr %rhs.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x float> %1, ptr %__p1.addr.i, align 8
# |   store <4 x float> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 8
# |   %6 = bitcast <16 x i8> %3 to <4 x float>
# |   %7 = bitcast <16 x i8> %4 to <4 x float>
# |   %8 = bitcast <16 x i8> %5 to <4 x float>
# |   %9 = call <4 x float> @llvm.fma.v4f32(<4 x float> %7, <4 x float> %8, <4 x float> %6)
# |   store <4 x float> %9, ptr %ref.tmp.i, align 8
# |   %10 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %10, ptr %__ret.i, align 8
# |   %11 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vfma_n_f32(<2 x float> noundef %a, <2 x float> noundef %b, float noundef %n) #0 {
# | entry:
# |   %__p0.addr.i.i = alloca <2 x float>, align 8
# |   %__p1.addr.i.i = alloca <2 x float>, align 8
# |   %__p2.addr.i.i = alloca <2 x float>, align 8
# |   %__ret.i.i = alloca <2 x float>, align 8
# |   %ref.tmp.i.i = alloca <8 x i8>, align 8
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__p2.addr.i = alloca float, align 4
# |   %__ret.i = alloca <2 x float>, align 8
# |   %.compoundliteral.i = alloca <2 x float>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %n.addr = alloca float, align 4
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   store float %n, ptr %n.addr, align 4
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   %2 = load float, ptr %n.addr, align 4
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   store float %2, ptr %__p2.addr.i, align 4
# |   %3 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %4 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %5 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit.i = insertelement <2 x float> poison, float %5, i32 0
# |   %6 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit1.i = insertelement <2 x float> %vecinit.i, float %6, i32 1
# |   store <2 x float> %vecinit1.i, ptr %.compoundliteral.i, align 8
# |   %7 = load <2 x float>, ptr %.compoundliteral.i, align 8
# |   store <2 x float> %3, ptr %__p0.addr.i.i, align 8
# |   store <2 x float> %4, ptr %__p1.addr.i.i, align 8
# |   store <2 x float> %7, ptr %__p2.addr.i.i, align 8
# |   %8 = load <8 x i8>, ptr %__p0.addr.i.i, align 8
# |   %9 = load <8 x i8>, ptr %__p1.addr.i.i, align 8
# |   %10 = load <8 x i8>, ptr %__p2.addr.i.i, align 8
# |   %11 = bitcast <8 x i8> %8 to <2 x float>
# |   %12 = bitcast <8 x i8> %9 to <2 x float>
# |   %13 = bitcast <8 x i8> %10 to <2 x float>
# |   %14 = call <2 x float> @llvm.fma.v2f32(<2 x float> %12, <2 x float> %13, <2 x float> %11)
# |   store <2 x float> %14, ptr %ref.tmp.i.i, align 8
# |   %15 = load <2 x float>, ptr %ref.tmp.i.i, align 8
# |   store <2 x float> %15, ptr %__ret.i.i, align 8
# |   %16 = load <2 x float>, ptr %__ret.i.i, align 8
# |   store <2 x float> %16, ptr %__ret.i, align 8
# |   %17 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %17
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vfmaq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %n) #0 {
# | entry:
# |   %__p0.addr.i.i = alloca <4 x float>, align 8
# |   %__p1.addr.i.i = alloca <4 x float>, align 8
# |   %__p2.addr.i.i = alloca <4 x float>, align 8
# |   %__ret.i.i = alloca <4 x float>, align 8
# |   %ref.tmp.i.i = alloca <16 x i8>, align 8
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__p1.addr.i = alloca <4 x float>, align 8
# |   %__p2.addr.i = alloca float, align 4
# |   %__ret.i = alloca <4 x float>, align 8
# |   %.compoundliteral.i = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %n.addr = alloca float, align 4
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store float %n, ptr %n.addr, align 4
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load float, ptr %n.addr, align 4
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x float> %1, ptr %__p1.addr.i, align 8
# |   store float %2, ptr %__p2.addr.i, align 4
# |   %3 = load <4 x float>, ptr %__p0.addr.i, align 8
# |   %4 = load <4 x float>, ptr %__p1.addr.i, align 8
# |   %5 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit.i = insertelement <4 x float> poison, float %5, i32 0
# |   %6 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit1.i = insertelement <4 x float> %vecinit.i, float %6, i32 1
# |   %7 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %7, i32 2
# |   %8 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %8, i32 3
# |   store <4 x float> %vecinit3.i, ptr %.compoundliteral.i, align 8
# |   %9 = load <4 x float>, ptr %.compoundliteral.i, align 8
# |   store <4 x float> %3, ptr %__p0.addr.i.i, align 8
# |   store <4 x float> %4, ptr %__p1.addr.i.i, align 8
# |   store <4 x float> %9, ptr %__p2.addr.i.i, align 8
# |   %10 = load <16 x i8>, ptr %__p0.addr.i.i, align 8
# |   %11 = load <16 x i8>, ptr %__p1.addr.i.i, align 8
# |   %12 = load <16 x i8>, ptr %__p2.addr.i.i, align 8
# |   %13 = bitcast <16 x i8> %10 to <4 x float>
# |   %14 = bitcast <16 x i8> %11 to <4 x float>
# |   %15 = bitcast <16 x i8> %12 to <4 x float>
# |   %16 = call <4 x float> @llvm.fma.v4f32(<4 x float> %14, <4 x float> %15, <4 x float> %13)
# |   store <4 x float> %16, ptr %ref.tmp.i.i, align 8
# |   %17 = load <4 x float>, ptr %ref.tmp.i.i, align 8
# |   store <4 x float> %17, ptr %__ret.i.i, align 8
# |   %18 = load <4 x float>, ptr %__ret.i.i, align 8
# |   store <4 x float> %18, ptr %__ret.i, align 8
# |   %19 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %19
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) #1
# | 
# | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a7" "target-features"="+armv7-a,+d32,+dsp,+fp16,+fp64,+hwdiv,+hwdiv-arm,+neon,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1}
# | !llvm.ident = !{!2}
# | 
# | !0 = !{i32 1, !"target-abi", !"aapcs"}
# | !1 = !{i32 1, !"min_enum_size", i32 4}
# | !2 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000557e63eafeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557e63eace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557e63eb062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ed0333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ed038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ed0333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ed031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e63e45bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557e63e45a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557e63e2a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557e63ad9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557e63ad9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5ed031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ed031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ed031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e63ad9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c (1214 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_tu(<vscale x 16 x half> %vd, <vsc
# | ...
# `---data was truncated (10240/295319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563eb81e6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563eb81e3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563eb81e762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd237649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd2376a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd237649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd237631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563eb817cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563eb817ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563eb81618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563eb7e10e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563eb7e10b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd237632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd2376330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd2376330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563eb7e10a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-builtin-reduce-ops.c (1215 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-builtin-reduce-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v  -disable-O0-optnone   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_add_i32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.add = call i32 @llvm.vector.reduce.add.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.add
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.add.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_and_i32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.and = call i32 @llvm.vector.reduce.and.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.and
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.and.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_or_i32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.or = call i32 @llvm.vector.reduce.or.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.or
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.or.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_xor_i32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.xor = call i32 @llvm.vector.reduce.xor.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.xor
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.xor.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_smax_i32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.min = call i32 @llvm.vector.reduce.smax.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.min
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.smax.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_smin_i32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.min = call i32 @llvm.vector.reduce.smin.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.min
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.smin.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_umax_u32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.min = call i32 @llvm.vector.reduce.umax.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.min
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.umax.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_umin_u32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.min = call i32 @llvm.vector.reduce.umin.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.min
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.umin.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @reduce_fmax_f32(<vscale x 2 x float> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 2 x float> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x float>, ptr %a.addr, align 4
# |   %rdx.min = call float @llvm.vector.reduce.fmax.nxv2f32(<vscale x 2 x float> %0)
# |   ret float %rdx.min
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare float @llvm.vector.reduce.fmax.nxv2f32(<vscale x 2 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @reduce_fmin_f32(<vscale x 2 x float> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 2 x float> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x float>, ptr %a.addr, align 4
# |   %rdx.min = call float @llvm.vector.reduce.fmin.nxv2f32(<vscale x 2 x float> %0)
# |   ret float %rdx.min
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare float @llvm.vector.reduce.fmin.nxv2f32(<vscale x 2 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @reduce_fmaximum_f32(<vscale x 2 x float> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 2 x float> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x float>, ptr %a.addr, align 4
# |   %rdx.maximum = call float @llvm.vector.reduce.fmaximum.nxv2f32(<vscale x 2 x float> %0)
# |   ret float %rdx.maximum
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare float @llvm.vector.reduce.fmaximum.nxv2f32(<vscale x 2 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @reduce_fminimum_f32(<vscale x 2 x float> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 2 x float> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x float>, ptr %a.addr, align 4
# |   %rdx.minimum = call float @llvm.vector.reduce.fminimum.nxv2f32(<vscale x 2 x float> %0)
# |   ret float %rdx.minimum
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare float @llvm.vector.reduce.fminimum.nxv2f32(<vscale x 2 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_add_i32_m8(<vscale x 16 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i32>, align 4
# |   store <vscale x 16 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 16 x i32>, ptr %a.addr, align 4
# |   %rdx.add = call i32 @llvm.vector.reduce.add.nxv16i32(<vscale x 16 x i32> %0)
# |   ret i32 %rdx.add
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.add.nxv16i32(<vscale x 16 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @reduce_add_i64(<vscale x 1 x i64> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 1 x i64>, align 8
# |   store <vscale x 1 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %a.addr, align 8
# |   %rdx.add = call i64 @llvm.vector.reduce.add.nxv1i64(<vscale x 1 x i64> %0)
# |   ret i64 %rdx.add
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.vector.reduce.add.nxv1i64(<vscale x 1 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_mul_i32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.mul = call i32 @llvm.vector.reduce.mul.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.mul
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.mul.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055a90fdf9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a90fdf6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a90fdfa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd5bc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd5bca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd5bc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd5bc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a90fd8fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a90fd8fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a90fd748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a90fa23e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a90fa23b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbd5bc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd5bc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd5bc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a90fa23a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c (1216 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +xandesvbfhcvt -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4_rm(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2_rm(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1_rm(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2_rm(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4_rm(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055be14fbceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055be14fb9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055be14fbd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3286733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f328678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3286733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f328671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055be14f52bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055be14f52a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055be14f378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055be14be6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055be14be6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f328671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f328671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f328671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055be14be6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c (1217 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 8 x i64>, ptr %
# | ...
# `---data was truncated (10240/20631) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c4d1805eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c4d1802e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c4d180662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f08b6449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f08b64a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f08b6449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f08b6431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c4d179bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c4d179ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c4d17808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c4d142fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c4d142fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f08b6432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f08b64330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f08b64330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c4d142fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c (1218 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvpackfph -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadt_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadt_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadt_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadt_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(<vscale x 8 x half>, <vscale x 8 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_nds_vfpmadt_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(<vscale x 16 x half>, <vscale x 16 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_nds_vfpmadt_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(<vscale x 32 x half>, <vscale x 32 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadt_vf_f16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load float, ptr %op2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(<vscale x 1 x half> %1, <vscale x 1 x half> %2, float %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadt_vf_f16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load float, ptr %op2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64(<vscale x 2 x half> %1, <vscale x 2 x half> %2, float %3, <vscale x 2 
# | ...
# `---data was truncated (10240/59595) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dec2504eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dec2501e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dec250562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb1d6a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb1d6a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb1d6a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb1d6a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dec249abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dec249aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dec247f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dec212ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dec212eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb1d6a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb1d6a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb1d6a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dec212ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c (1219 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8ff_v_i8mf8x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv1i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv1i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8ff_v_i8mf4x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8ff_v_i8mf2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8ff_v_i8m1x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8ff_v_i8m2x2_m(<vscale x 16 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8ff_v_i8m4x2_m(<vscale x 32 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv32i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 32 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv32i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8ff_v
# | ...
# `---data was truncated (10240/18520) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c963615eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c963612e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c96361662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6d42733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6d4278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6d42733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6d4271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9635abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c9635aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c9635908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c96323fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c96323fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6d4271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6d4271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6d4271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c96323fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c (1220 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zve64x    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e8w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 0, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.sf.vsettk.i64(i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e8w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 0, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e8w4(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 0, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e16w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 1, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e16w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 1, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e16w4(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 1, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e32w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 2, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e32w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 2, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e64w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 3, i64 1)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005556a676feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005556a676ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005556a677062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f660ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f660ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f660ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f660ab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005556a6705bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005556a6705a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005556a66ea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005556a6399e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005556a6399b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f660ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f660ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f660ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005556a6399a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c (1221 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmad_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %4 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.mad.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %4, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.mad.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmad_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %6 = call <vscale x 8 x i16> @llvm.aarch64.sve.mad.nxv8i16(<vscale x 8 x i1> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.mad.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmad_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %6 = call <vscale x 4 x i32> @llvm.aarch64.sve.mad.nxv4i32(<vscale x 4 x i1> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3)
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.mad.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmad_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   %op3.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x i64> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %6 = call <vscale x 2 x i64> @llvm.aarch64.sve.mad.nxv2i64(<vscale x 2 x i1> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3)
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.mad.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmad_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %4 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.mad.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %4, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmad_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %6 = call <vscale x 8 x i16> @llvm.aarch64.sve.mad.nxv8i16(<vscale x 8 x i1> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmad_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %6 = call <vscale x 4 x i32> @llvm.aarch64.sve.mad.nxv4i32(<vscale x 4 x i1> %4, <vs
# | ...
# `---data was truncated (10240/86847) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055fe96909eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fe96906e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fe9690a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6038105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f603815c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6038105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f60380ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fe9689fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fe9689fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fe968848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fe96533e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fe96533b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f60380eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f60380ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f60380ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fe96533a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c (1222 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei64_v_i8mf8x5
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c92d913eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c92d910e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c92d91462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd02481bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd0248725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd02481ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd024803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c92d8a9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c92d8a9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c92d88e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c92d53de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c92d53db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd024804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd0248050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd0248050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c92d53da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c (1223 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", 
# | ...
# `---data was truncated (10240/16800) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f3999e6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f3999e3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f3999e762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8aee849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8aee8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8aee849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8aee831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f39997cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f39997ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f3999618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f399610e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f399610b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8aee832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8aee8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8aee8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f399610a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/distributed-thin-lto/newpm.ll (1224 of 27911)
******************** TEST 'Clang :: CodeGen/distributed-thin-lto/newpm.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 11
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/newpm.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/newpm.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/newpm.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/newpm.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/newpm.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/newpm.ll
# |  #0 0x0000559aaf7ffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559aaf7fce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559aaf80062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1a49133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1a4918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1a49133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1a4911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559aaf795bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559aaf795a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559aaf77a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559aaf429e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559aaf429b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1a4911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1a4911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1a4911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559aaf429a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c (1225 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei16_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei16_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei16_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei16_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei16_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vluxei16_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, <vscale x 32 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei16_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei16_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none)
# | ...
# `---data was truncated (10240/30609) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558c3391feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558c3391ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558c3392062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6109049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f61090a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6109049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6109031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c338b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558c338b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558c3389a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558c33549e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558c33549b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6109032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61090330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61090330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c33549a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c (1226 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vf_f32mf2(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vf_f32m1(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vf_f32m2(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vf_f32m4(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float>, ha
# | ...
# `---data was truncated (10240/90685) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b4b7576eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b4b7573e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b4b757762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe29401bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe2940725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe29401ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe294003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b4b750cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b4b750ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b4b74f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b4b71a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b4b71a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe294004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe2940050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe2940050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b4b71a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c (1227 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2ms_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2ms_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2ms_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2ms_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2ms_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2ms_vv_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2ms_vv_u64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2ms_vv_u64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | 
# | ...
# `---data was truncated (10240/12216) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005564e750ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005564e7509e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005564e750d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd12e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd12e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd12e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd12e431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005564e74a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005564e74a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005564e74878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005564e7136e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005564e7136b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd12e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd12e4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd12e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005564e7136a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/fp8-extract.c (1228 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-extract.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +neon -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_var(<16 x i8> %v, i32 noundef %i) #0 {
# | entry:
# |   %v.addr = alloca <16 x i8>, align 16
# |   %i.addr = alloca i32, align 4
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   store i32 %i, ptr %i.addr, align 4
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   %1 = load i32, ptr %i.addr, align 4
# |   %vecext = extractelement <16 x i8> %0, i32 %1
# |   %mfp8ext = insertelement <1 x i8> poison, i8 %vecext, i64 0
# |   call void @g(<1 x i8> %mfp8ext)
# |   ret void
# | }
# | 
# | declare void @g(<1 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_cst(<16 x i8> %v) #0 {
# | entry:
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   %vecext = extractelement <16 x i8> %0, i32 3
# |   %mfp8ext = insertelement <1 x i8> poison, i8 %vecext, i64 0
# |   call void @g(<1 x i8> %mfp8ext)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine
# |  #0 0x000055d0c646deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d0c646ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d0c646e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fea5d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fea5d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fea5d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fea5d031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0c6403bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d0c6403a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d0c63e88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d0c6097e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d0c6097b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fea5d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fea5d0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fea5d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d0c6097a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c (1229 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8ff_v_i8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8ff_v_i8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8ff_v_i8mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8ff_v_i8m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8ff_v_i8m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8ff_v_u8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { targe
# | ...
# `---data was truncated (10240/68233) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557b9e0d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557b9e0d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557b9e0d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa3d0c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa3d0ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa3d0c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa3d0c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b9e06cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557b9e06ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557b9e0518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557b9dd00e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557b9dd00b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa3d0c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa3d0c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa3d0c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b9dd00a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/neon-vsqadd-float-conversion.c (1230 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-vsqadd-float-conversion.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon   -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,dce  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i8 @test_vsqaddb_u8() #0 {
# | entry:
# |   %__p0.addr.i = alloca i8, align 1
# |   %__p1.addr.i = alloca i8, align 1
# |   %__ret.i = alloca i8, align 1
# |   %ref.tmp.i = alloca i8, align 1
# |   store i8 1, ptr %__p0.addr.i, align 1
# |   store i8 -1, ptr %__p1.addr.i, align 1
# |   %0 = load i8, ptr %__p0.addr.i, align 1
# |   %1 = load i8, ptr %__p1.addr.i, align 1
# |   %2 = insertelement <8 x i8> poison, i8 %0, i64 0
# |   %3 = insertelement <8 x i8> poison, i8 %1, i64 0
# |   %vsqaddb_u8.i = call <8 x i8> @llvm.aarch64.neon.usqadd.v8i8(<8 x i8> %2, <8 x i8> %3)
# |   %4 = extractelement <8 x i8> %vsqaddb_u8.i, i64 0
# |   store i8 %4, ptr %ref.tmp.i, align 1
# |   %5 = load i8, ptr %ref.tmp.i, align 1
# |   store i8 %5, ptr %__ret.i, align 1
# |   %6 = load i8, ptr %__ret.i, align 1
# |   ret i8 %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vsqaddh_u16() #0 {
# | entry:
# |   %__p0.addr.i = alloca i16, align 2
# |   %__p1.addr.i = alloca i16, align 2
# |   %__ret.i = alloca i16, align 2
# |   %ref.tmp.i = alloca i16, align 2
# |   store i16 1, ptr %__p0.addr.i, align 2
# |   store i16 -1, ptr %__p1.addr.i, align 2
# |   %0 = load i16, ptr %__p0.addr.i, align 2
# |   %1 = load i16, ptr %__p1.addr.i, align 2
# |   %2 = insertelement <4 x i16> poison, i16 %0, i64 0
# |   %3 = insertelement <4 x i16> poison, i16 %1, i64 0
# |   %vsqaddh_u16.i = call <4 x i16> @llvm.aarch64.neon.usqadd.v4i16(<4 x i16> %2, <4 x i16> %3)
# |   %4 = extractelement <4 x i16> %vsqaddh_u16.i, i64 0
# |   store i16 %4, ptr %ref.tmp.i, align 2
# |   %5 = load i16, ptr %ref.tmp.i, align 2
# |   store i16 %5, ptr %__ret.i, align 2
# |   %6 = load i16, ptr %__ret.i, align 2
# |   ret i16 %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_vsqadds_u32() #0 {
# | entry:
# |   %__p0.addr.i = alloca i32, align 4
# |   %__p1.addr.i = alloca i32, align 4
# |   %__ret.i = alloca i32, align 4
# |   %ref.tmp.i = alloca i32, align 4
# |   store i32 1, ptr %__p0.addr.i, align 4
# |   store i32 -1, ptr %__p1.addr.i, align 4
# |   %0 = load i32, ptr %__p0.addr.i, align 4
# |   %1 = load i32, ptr %__p1.addr.i, align 4
# |   %vsqadds_u32.i = call i32 @llvm.aarch64.neon.usqadd.i32(i32 %0, i32 %1)
# |   store i32 %vsqadds_u32.i, ptr %ref.tmp.i, align 4
# |   %2 = load i32, ptr %ref.tmp.i, align 4
# |   store i32 %2, ptr %__ret.i, align 4
# |   %3 = load i32, ptr %__ret.i, align 4
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_vsqaddd_u64() #0 {
# | entry:
# |   %__p0.addr.i = alloca i64, align 8
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca i64, align 8
# |   %ref.tmp.i = alloca i64, align 8
# |   store i64 1, ptr %__p0.addr.i, align 8
# |   store i64 -1, ptr %__p1.addr.i, align 8
# |   %0 = load i64, ptr %__p0.addr.i, align 8
# |   %1 = load i64, ptr %__p1.addr.i, align 8
# |   %vsqaddd_u64.i = call i64 @llvm.aarch64.neon.usqadd.i64(i64 %0, i64 %1)
# |   store i64 %vsqaddd_u64.i, ptr %ref.tmp.i, align 8
# |   %2 = load i64, ptr %ref.tmp.i, align 8
# |   store i64 %2, ptr %__ret.i, align 8
# |   %3 = load i64, ptr %__ret.i, align 8
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i8> @llvm.aarch64.neon.usqadd.v8i8(<8 x i8>, <8 x i8>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i16> @llvm.aarch64.neon.usqadd.v4i16(<4 x i16>, <4 x i16>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.neon.usqadd.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.aarch64.neon.usqadd.i64(i64, i64) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,dce
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,dce
# |  #0 0x000055cc3ed9beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cc3ed98e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cc3ed9c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8543f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8543f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8543f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8543f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc3ed31bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cc3ed31a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cc3ed168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cc3e9c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cc3e9c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8543f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8543f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8543f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc3e9c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c (1231 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmacc_vv_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmacc_vx_i8mf8_tu(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmacc_vv_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmacc_vx_i8mf4_tu(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmacc_vv_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmacc_vx_i8mf2_tu(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmacc_vv_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmacc_vx_i8m1_tu(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmacc_vv_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %
# | ...
# `---data was truncated (10240/414517) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557aeba1deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557aeba1ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557aeba1e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c4a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c4a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c4a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c4a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557aeb9b3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557aeb9b3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557aeb9988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557aeb647e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557aeb647b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8c4a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c4a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c4a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557aeb647a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c (1232 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16
# | ...
# `---data was truncated (10240/295311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005638fca7beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005638fca78e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005638fca7c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3239733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f323978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3239733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f323971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005638fca11bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005638fca11a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005638fc9f68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005638fc6a5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005638fc6a5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f323971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f323971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f323971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005638fc6a5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c (1233 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei32_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei32_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei32_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei32_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei32_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei32_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei32_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei32_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei32_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, <vscale x 8 
# | ...
# `---data was truncated (10240/255538) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed08ad4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ed08ad1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ed08ad562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff351449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff3514a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff351449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff351431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed08a6abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ed08a6aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ed08a4f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ed086fee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ed086feb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff351432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff3514330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff3514330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed086fea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c (1234 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei8_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple
# | ...
# `---data was truncated (10240/31938) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005641a866beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005641a8668e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005641a866c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f07c8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f07c878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f07c8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f07c871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005641a8601bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005641a8601a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005641a85e68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005641a8295e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005641a8295b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f07c871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f07c871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f07c871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005641a8295a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c (1235 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgather_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %index.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %index.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgather_vx_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %index.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgather_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %index.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %index.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgather_vx_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %index.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgather_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %index.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %index.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgather_vx_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %index.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgather_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %index.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgather_vx_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %index.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgather_vv_f16m4_tu(<vscale x 16 x h
# | ...
# `---data was truncated (10240/619135) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555a2992beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555a29928e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555a2992c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8611705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f861175c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8611705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f86116ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555a298c1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555a298c1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555a298a68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555a29555e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555a29555b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f86116eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f86116ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f86116ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555a29555a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c (1236 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmadd_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmadd_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmadd_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmadd_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmadd_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmadd_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmadd_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmadd_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bflo
# | ...
# `---data was truncated (10240/34364) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055afc83b9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055afc83b6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055afc83ba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f4801bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f480725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f4801ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f48003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055afc834fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055afc834fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055afc83348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055afc7fe3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055afc7fe3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2f48004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f480050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f480050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055afc7fe3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c (1237 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vundefined_f16mf4() #0 {
# | entry:
# |   ret <vscale x 1 x half> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vundefined_f16mf2() #0 {
# | entry:
# |   ret <vscale x 2 x half> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vundefined_f16m1() #0 {
# | entry:
# |   ret <vscale x 4 x half> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vundefined_f16m2() #0 {
# | entry:
# |   ret <vscale x 8 x half> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vundefined_f16m4() #0 {
# | entry:
# |   ret <vscale x 16 x half> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vundefined_f16m8() #0 {
# | entry:
# |   ret <vscale x 32 x half> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vundefined_f32mf2() #0 {
# | entry:
# |   ret <vscale x 1 x float> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vundefined_f32m1() #0 {
# | entry:
# |   ret <vscale x 2 x float> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vundefined_f32m2() #0 {
# | entry:
# |   ret <vscale x 4 x float> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vundefined_f32m4() #0 {
# | entry:
# |   ret <vscale x 8 x float> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vundefined_f32m8() #0 {
# | entry:
# |   ret <vscale x 16 x float> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vundefined_f64m1() #0 {
# | entry:
# |   ret <vscale x 1 x double> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vundefined_f64m2() #0 {
# | entry:
# |   ret <vscale x 2 x double> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vundefined_f64m4() #0 {
# | entry:
# |   ret <vscale x 4 x double> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vundefined_f64m8() #0 {
# | entry:
# |   ret <vscale x 8 x double> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vundefined_i8mf8() #0 {
# | entry:
# |   ret <vscale x 1 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vundefined_i8mf4() #0 {
# | entry:
# |   ret <vscale x 2 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vundefined_i8mf2() #0 {
# | entry:
# |   ret <vscale x 4 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vundefined_i8m1() #0 {
# | entry:
# |   ret <vscale x 8 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vundefined_i8m2() #0 {
# | entry:
# |   ret <vscale x 16 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vundefined_i8m4() #0 {
# | entry:
# |   ret <vscale x 32 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vundefined_i8m8() #0 {
# | entry:
# |   ret <vscale x 64 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vundefined_i16mf4() #0 {
# | entry:
# |   ret <vscale x 1 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vundefined_i16mf2() #0 {
# | entry:
# |   ret <vscale x 2 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vundefined_i16m1() #0 {
# | entry:
# |   ret <vscale x 4 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vundefined_i16m2() #0 {
# | entry:
# |   ret <vscale x 8 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vundefined_i16m4() #0 {
# | entry:
# |   ret <vscale x 16 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vundefined_i16m8() #0 {
# | entry:
# |   ret <vscale x 32 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vundefined_i32mf2() #0 {
# | entry:
# |   ret <vscale x 1 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vundefined_i32m1() #0 {
# | entry:
# |   ret <vscale x 2 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vundefined_i32m2() #0 {
# | entry:
# |   ret <vscale x 4 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vundefined_i32m4() #0 {
# | entry:
# |   ret <vscale x 8 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vundefined_i32m8() #0 {
# | entry:
# |   ret <vscale x 16 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vundefined_i64m1() #0 {
# | entry:
# |   ret <vscale x 1 x i64> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vundefined_i64m2() #0 {
# | entry:
# |   ret <vscale x 2 x i64> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vundefined_i64m4() #0 {
# | entry:
# |   ret <vscale x 4 x i64> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vundefined_i64m8() #0 {
# | entry:
# |   ret <vscale x 8 x i64> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vundefined_u8mf8() #0 {
# | entry:
# |   ret <vscale x 1 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vundefined_u8mf4() #0 {
# | entry:
# |   ret <vscale x 2 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vundefined_u8mf2() #0 {
# | entry:
# |   ret <vscale x 4 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vundefined_u8m1() #0 {
# | entry:
# |   ret <vscale x 8 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vundefined_u8m2() #0 {
# | entry:
# |   ret <vscale x 16 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vundefined_u8m4() #0 {
# | entry:
# |   ret <vscale x 32 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vundefined_u8m8() #0 {
# | entry:
# |   ret <vscale x 64 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vundefined_u16mf4() #0 {
# | entry:
# |   ret <vscale x 1 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vundefined_u16mf2() #0 {
# | entry:
# |   ret <vscale x 2 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vundefined_u16m1() #0 {
# | entry:
# |   ret <vscale x 4 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vundefined_u16m2() #0 {
# | entry:
# |   ret <vscale x 8 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vundefined_u16m4() #0 {
# | entry:
# |   ret <vscale x 16 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vundefined_u16m8() #0 {
# | entry:
# |   ret <vscale x 32 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vundefined_u32mf2() #0 {
# | entry:
# |   ret <vscale x 1 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vundefined_u32m1() #0 {
# | entry:
# |   ret <vscale x 2 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vundefined_u32m2() #0 {
# | entry:
# |   ret <vscale x 4 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vundefined_u32m4() #0 {
# | entry:
# |   ret <vscale x 8 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vundefined_u32m8() #0 {
# | entry:
# |   ret <vscale x 16 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vundefined_u64m1() #0 {
# | entry:
# |   ret <vscale x 1 x i64> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vundefined_u64m2() #0 {
# | entry:
# |   ret <vscale x 2 x i64> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vundefined_u64m4() #0 {
# | entry:
# |   ret <vscale x 4 x i64> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vundefined_u64m8() #0 {
# | entry:
# |   ret <vscale x 8 x i64> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vsca
# | ...
# `---data was truncated (10240/63140) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555cd9b40eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555cd9b3de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555cd9b4162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9c64733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9c6478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9c64733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9c6471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555cd9ad6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555cd9ad6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555cd9abb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555cd976ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555cd976ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9c6471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9c6471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9c6471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555cd976aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c (1238 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563f94606eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563f94603e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563f9460762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3f07d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3f07d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3f07d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3f07d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563f9459cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563f9459ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563f945818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563f94230e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563f94230b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3f07d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3f07d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3f07d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563f94230a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/arm-crc32.c (1239 of 27911)
******************** TEST 'Clang :: CodeGen/arm-crc32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-gnueabi -target-feature +crc   -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-gnueabi -target-feature +crc -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8-none-linux-gnueabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32b(i32 noundef %a, i8 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i8, align 1
# |   store i32 %a, ptr %a.addr, align 4
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i8, ptr %b.addr, align 1
# |   %2 = zext i8 %1 to i32
# |   %3 = call i32 @llvm.arm.crc32b(i32 %0, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.crc32b(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32cb(i32 noundef %a, i8 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i8, align 1
# |   store i32 %a, ptr %a.addr, align 4
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i8, ptr %b.addr, align 1
# |   %2 = zext i8 %1 to i32
# |   %3 = call i32 @llvm.arm.crc32cb(i32 %0, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.crc32cb(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32h(i32 noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i16, ptr %b.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call i32 @llvm.arm.crc32h(i32 %0, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.crc32h(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32ch(i32 noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i16, ptr %b.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call i32 @llvm.arm.crc32ch(i32 %0, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.crc32ch(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32w(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.arm.crc32w(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.crc32w(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32cw(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.arm.crc32cw(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.crc32cw(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32d(i32 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i64, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i64, ptr %b.addr, align 8
# |   %2 = trunc i64 %1 to i32
# |   %3 = lshr i64 %1, 32
# |   %4 = trunc i64 %3 to i32
# |   %5 = call i32 @llvm.arm.crc32w(i32 %0, i32 %2)
# |   %6 = call i32 @llvm.arm.crc32w(i32 %5, i32 %4)
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32cd(i32 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i64, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i64, ptr %b.addr, align 8
# |   %2 = trunc i64 %1 to i32
# |   %3 = lshr i64 %1, 32
# |   %4 = trunc i64 %3 to i32
# |   %5 = call i32 @llvm.arm.crc32cw(i32 %0, i32 %2)
# |   %6 = call i32 @llvm.arm.crc32cw(i32 %5, i32 %4)
# |   ret i32 %6
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8-a,+crc,-thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1}
# | !llvm.ident = !{!2}
# | 
# | !0 = !{i32 1, !"target-abi", !"aapcs-linux"}
# | !1 = !{i32 1, !"min_enum_size", i32 4}
# | !2 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b7610b1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b7610aee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b7610b262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffae2849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffae28a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffae2849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffae2831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b761047bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b761047a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b76102c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b760cdbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b760cdbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffae2832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffae28330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffae28330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b760cdba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c (1240 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_f32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_i32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_i32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_i32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_u32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_u32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vsc
# | ...
# `---data was truncated (10240/53446) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ceaa159eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ceaa156e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ceaa15a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f57fe049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57fe0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f57fe049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f57fe031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ceaa0efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ceaa0efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ceaa0d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cea9d83e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cea9d83b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f57fe032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57fe0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57fe0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cea9d83a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c (1241 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmin_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmin_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmin_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmin_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmin_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmin_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmin_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmin_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmin_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmin_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16
# | ...
# `---data was truncated (10240/69305) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005641150cceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005641150c9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005641150cd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f899a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f899a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f899a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f899a231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564115062bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564115062a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005641150478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564114cf6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564114cf6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f899a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f899a2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f899a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564114cf6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c (1242 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsac_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsac_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsac_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsac_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsac_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsac_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsac_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsac_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <v
# | ...
# `---data was truncated (10240/64252) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b5b8e2beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b5b8e28e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b5b8e2c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1db0305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1db035c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1db0305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1db02ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b5b8dc1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b5b8dc1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b5b8da68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b5b8a55e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b5b8a55b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1db02eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1db02ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1db02ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b5b8a55a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c (1243 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_f64m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_f64m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_f64m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_i64m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_i64m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_i64m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_u64m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_u64m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_u64m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_f64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(arg
# | ...
# `---data was truncated (10240/20531) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555fffc71eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555fffc6ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555fffc7262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe9c3849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe9c38a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe9c3849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe9c3831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555fffc07bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555fffc07a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555fffbec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555fff89be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555fff89bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe9c3832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe9c38330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe9c38330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555fff89ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c (1244 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmerge_vvm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmerge_vxm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmerge_vvm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmerge_vxm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmerge_vvm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmerge_vxm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmerge_vvm_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso
# | ...
# `---data was truncated (10240/148012) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055923e3fbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055923e3f8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055923e3fc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1ba9333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1ba938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1ba9333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1ba931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055923e391bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055923e391a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055923e3768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055923e025e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055923e025b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1ba931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1ba931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1ba931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055923e025a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c (1245 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f    -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_sf_vfexp_v_bf16mf4(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_sf_vfexp_v_bf16mf2(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_sf_vfexp_v_bf16m1(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_sf_vfexp_v_bf16m2(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_sf_vfexp_v_bf16m4(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_sf_vfexp_v_bf16m8(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_sf_vfexp_v_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_sf_vfexp_v_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_sf_vfexp_v_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_sf_vfexp_v_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_sf_vfexp_v_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   
# | ...
# `---data was truncated (10240/12381) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005612f7cdceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005612f7cd9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005612f7cdd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0d0bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0d0bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0d0bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0d0bf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005612f7c72bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005612f7c72a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005612f7c578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005612f7906e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005612f7906b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0d0bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0d0bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0d0bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005612f7906a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c (1246 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmset_m_b1(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 64 x i1> @llvm.riscv.vmset.nxv64i1.i64(i64 %0)
# |   ret <vscale x 64 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmset.nxv64i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmset_m_b2(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 32 x i1> @llvm.riscv.vmset.nxv32i1.i64(i64 %0)
# |   ret <vscale x 32 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmset.nxv32i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmset_m_b4(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 16 x i1> @llvm.riscv.vmset.nxv16i1.i64(i64 %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmset.nxv16i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmset_m_b8(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 8 x i1> @llvm.riscv.vmset.nxv8i1.i64(i64 %0)
# |   ret <vscale x 8 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmset.nxv8i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmset_m_b16(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 4 x i1> @llvm.riscv.vmset.nxv4i1.i64(i64 %0)
# |   ret <vscale x 4 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmset.nxv4i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmset_m_b32(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 2 x i1> @llvm.riscv.vmset.nxv2i1.i64(i64 %0)
# |   ret <vscale x 2 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmset.nxv2i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmset_m_b64(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 1 x i1> @llvm.riscv.vmset.nxv1i1.i64(i64 %0)
# |   ret <vscale x 1 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmset.nxv1i1.i64(i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563239cfbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563239cf8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563239cfc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f475c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f475c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f475c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f475c31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563239c91bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563239c91a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563239c768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563239925e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563239925b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f475c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f475c31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f475c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563239925a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c (1247 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558a5d3d7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558a5d3d4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558a5d3d862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe7a8449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe7a84a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe7a8449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe7a8431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a5d36dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558a5d36da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558a5d3528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558a5d001e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558a5d001b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe7a8432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe7a84330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe7a84330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a5d001a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c (1248 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558859ab6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558859ab3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558859ab762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa44bb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa44bb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa44bb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa44baed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558859a4cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558859a4ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558859a318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005588596e0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005588596e0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa44baeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa44baef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa44baef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005588596e0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c (1249 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmul_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmul_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmul_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmul_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmul_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmul_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmul_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmul_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmul_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/424843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005607668a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005607668a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005607668a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa6e0c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa6e0ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa6e0c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa6e0c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056076683bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056076683ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005607668208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005607664cfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005607664cfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa6e0c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa6e0c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa6e0c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607664cfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vadc.c (1250 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vadc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vadciq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry_out.addr = alloca ptr, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry_out, ptr %carry_out.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 0)
# |   %3 = extractvalue { <4 x i32>, i32 } %2, 1
# |   %4 = lshr i32 %3, 29
# |   %5 = and i32 1, %4
# |   %6 = load ptr, ptr %carry_out.addr, align 4
# |   store i32 %5, ptr %6, align 4
# |   %7 = extractvalue { <4 x i32>, i32 } %2, 0
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vadcq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry.addr = alloca ptr, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry, ptr %carry.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load ptr, ptr %carry.addr, align 4
# |   %3 = load i32, ptr %2, align 4
# |   %4 = shl i32 %3, 29
# |   %5 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 %4)
# |   %6 = extractvalue { <4 x i32>, i32 } %5, 1
# |   %7 = lshr i32 %6, 29
# |   %8 = and i32 1, %7
# |   store i32 %8, ptr %2, align 4
# |   %9 = extractvalue { <4 x i32>, i32 } %5, 0
# |   ret <4 x i32> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vadciq_m_u32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry_out.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry_out, ptr %carry_out.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x i32>, ptr %a.addr, align 8
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 0, <4 x i1> %5)
# |   %7 = extractvalue { <4 x i32>, i32 } %6, 1
# |   %8 = lshr i32 %7, 29
# |   %9 = and i32 1, %8
# |   %10 = load ptr, ptr %carry_out.addr, align 4
# |   store i32 %9, ptr %10, align 4
# |   %11 = extractvalue { <4 x i32>, i32 } %6, 0
# |   ret <4 x i32> %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i32>, i32, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vadcq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry, ptr %carry.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x i32>, ptr %a.addr, align 8
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = load ptr, ptr %carry.addr, align 4
# |   %4 = load i32, ptr %3, align 4
# |   %5 = shl i32 %4, 29
# |   %6 = load i16, ptr %p.addr, align 2
# |   %7 = zext i16 %6 to i32
# |   %8 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %7)
# |   %9 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 %5, <4 x i1> %8)
# |   %10 = extractvalue { <4 x i32>, i32 } %9, 1
# |   %11 = lshr i32 %10, 29
# |   %12 = and i32 1, %11
# |   store i32 %12, ptr %3, align 4
# |   %13 = extractvalue { <4 x i32>, i32 } %9, 0
# |   ret <4 x i32> %13
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbciq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry_out.addr = alloca ptr, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry_out, ptr %carry_out.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 536870912)
# |   %3 = extractvalue { <4 x i32>, i32 } %2, 1
# |   %4 = lshr i32 %3, 29
# |   %5 = and i32 1, %4
# |   %6 = load ptr, ptr %carry_out.addr, align 4
# |   store i32 %5, ptr %6, align 4
# |   %7 = extractvalue { <4 x i32>, i32 } %2, 0
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbciq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry_out.addr = alloca ptr, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry_out, ptr %carry_out.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 536870912)
# |   %3 = extractvalue { <4 x i32>, i32 } %2, 1
# |   %4 = lshr i32 %3, 29
# |   %5 = and i32 1, %4
# |   %6 = load ptr, ptr %carry_out.addr, align 4
# |   store i32 %5, ptr %6, align 4
# |   %7 = extractvalue { <4 x i32>, i32 } %2, 0
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbcq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry.addr = alloca ptr, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry, ptr %carry.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load ptr, ptr %carry.addr, align 4
# |   %3 = load i32, ptr %2, align 4
# |   %4 = shl i32 %3, 29
# |   %5 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 %4)
# |   %6 = extractvalue { <4 x i32>, i32 } %5, 1
# |   %7 = lshr i32 %6, 29
# |   %8 = and i32 1, %7
# |   store i32 %8, ptr %2, align 4
# |   %9 = extractvalue { <4 x i32>, i32 } %5, 0
# |   ret <4 x i32> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbcq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry.addr = alloca ptr, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry, ptr %carry.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load ptr, ptr %carry.addr, align 4
# |   %3 = load i32, ptr %2, align 4
# |   %4 = shl i32 %3, 29
# |   %5 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 %4)
# |   %6 = extractvalue { <4 x i32>, i32 } %5, 1
# |   %7 = lshr i32 %6, 29
# |   %8 = and i32 1, %7
# |   store i32 %8, ptr %2, align 4
# |   %9 = extractvalue { <4 x i32>, i32 } %5, 0
# |   ret <4 x i32> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbciq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry_out.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry_out, ptr %carry_out.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x i32>, ptr %a.addr, align 8
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 536870912, <4 x i1> %5)
# |   %7 = extractvalue { <4 x i32>, i32 } %6, 1
# |   %8 = lshr i32 %7, 29
# |   %9 = and i32 1, %8
# |   %10 = load ptr, ptr %carry_out.addr, align 4
# |   store i32 %9, ptr %10, align 4
# |   %11 = extractvalue { <4 x i32>, i32 } %6, 0
# |   ret <4 x i32> %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <4 x i32>, i32 } @llvm.arm.mve.vsbc.predicated.v4i32.v4i1(<4 x i32>,
# | ...
# `---data was truncated (10240/14775) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d7e754eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558d7e751e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558d7e75562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc6e5649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc6e56a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc6e5649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc6e5631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d7e6eabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558d7e6eaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558d7e6cf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558d7e37ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558d7e37eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc6e5632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc6e56330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc6e56330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d7e37ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c (1251 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556989586eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556989583e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055698958762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9e6c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9e6c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9e6c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9e6c831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055698951cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055698951ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005569895018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005569891b0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005569891b0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9e6c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9e6c8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9e6c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005569891b0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c (1252 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmflt_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmflt_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmflt_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 3
# | ...
# `---data was truncated (10240/27794) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c12bd2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563c12bcfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563c12bd362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd3fc733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd3fc78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd3fc733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd3fc71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c12b68bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563c12b68a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563c12b4d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563c127fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563c127fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd3fc71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd3fc71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd3fc71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c127fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c (1253 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16mf4(ptr noundef %base, <vscale x 1 x i8> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16mf2(ptr noundef %base, <vscale x 2 x i8> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16m1(ptr noundef %base, <vscale x 4 x i8> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16m2(ptr noundef %base, <vscale x 8 x i8> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16m4(ptr noundef %base, <vscale x 16 x i8> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16m8(ptr noundef %base, <vscale x 32 x i8> %bindex, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> %2, ptr %0, <vscale x 32 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f32mf2(ptr noundef %base, <vscale x 1 x i8> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f32m1(ptr noundef %base, <vscale x 2 x i8> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f32m2(ptr noundef %base, <vscale x 4 x i8> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory
# | ...
# `---data was truncated (10240/135997) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ef25121eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ef2511ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ef2512262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9691133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f969118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9691133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f969111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ef250b7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ef250b7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ef2509c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ef24d4be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ef24d4bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f969111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f969111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f969111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ef24d4ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c (1254 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_i32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_i32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_u32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_u32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005574db5c9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005574db5c6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005574db5ca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f83cc81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83cc8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f83cc81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f83cc803507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005574db55fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005574db55fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005574db5448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005574db1f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005574db1f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f83cc804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83cc8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83cc8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005574db1f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c (1255 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfneg_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfneg_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfneg_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfneg_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfneg_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfneg_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfneg_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfneg_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfneg_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfneg_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfsgnjn.nxv8f32.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfsgnjn.nxv8f32.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfneg_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfsgnjn.nxv16f32.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfsgnjn.nxv16f32.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfneg_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.
# | ...
# `---data was truncated (10240/30869) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005636307b8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005636307b5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005636307b962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8234849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f82348a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8234849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8234831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056363074ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056363074ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005636307338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005636303e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005636303e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8234832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f82348330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f82348330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005636303e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c (1256 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vreinterpret_p8_mf8(<8 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %v.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %v, ptr %v.addr, align 8
# |   %0 = load <8 x i8>, ptr %v.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__ret.i, align 8
# |   %2 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vreinterpret_p64_mf8(<8 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %v.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %v, ptr %v.addr, align 8
# |   %0 = load <8 x i8>, ptr %v.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__ret.i, align 8
# |   %2 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vreinterpret_p16_mf8(<8 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %v.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %v, ptr %v.addr, align 8
# |   %0 = load <8 x i8>, ptr %v.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vreinterpretq_p8_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__ret.i, align 16
# |   %2 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vreinterpretq_p64_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__ret.i, align 16
# |   %2 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vreinterpretq_p16_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vreinterpretq_u8_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__ret.i, align 16
# |   %2 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vreinterpretq_u32_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   store <4 x i32> %1, ptr %__ret.i, align 16
# |   %2 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vreinterpretq_u64_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__ret.i, align 16
# |   %2 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vreinterpretq_u16_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vreinterpretq_s8_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__ret.i, align 16
# |   %2 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vreinterpretq_f64_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x double>, ptr %__p0.addr.i, align 16
# |   store <2 x double> %1, ptr %__ret.i, align 16
# |   %2 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vreinterpretq_f32_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__ret.i, align 16
# |   %2 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vreinterpretq_f16_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x half>, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vreinterpretq_s32_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   store <4 x i32> %1, ptr %__ret.i, align 16
# |   %2 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vreinterpretq_s64_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__ret.i, align 16
# |   %2 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vreinterpretq_mf8_p8(<16 x i8> noundef %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__ret.i, align 16
# |   %2 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vreinterpretq_mf8_p128(i128 noundef %v) #0 {
# | entry:
# |   
# | ...
# `---data was truncated (10240/32178) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# |  #0 0x0000557d30ce1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557d30cdee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557d30ce262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f0e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f0e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f0e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f0e91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557d30c77bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557d30c77a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557d30c5c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557d3090be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557d3090bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4f0e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f0e91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f0e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557d3090ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c (1257 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei16_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale
# | ...
# `---data was truncated (10240/32108) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564128a58eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564128a55e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564128a5962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5017849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f50178a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5017849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5017831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005641289eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005641289eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005641289d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564128682e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564128682b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5017832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f50178330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f50178330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564128682a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c (1258 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f16m1x5(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f32m1x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f64m1x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei64_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eb43d75eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eb43d72e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eb43d7662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa9d5333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa9d538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa9d5333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa9d531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb43d0bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eb43d0ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eb43cf08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eb4399fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eb4399fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa9d531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa9d531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa9d531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb4399fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c (1259 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, ali
# | ...
# `---data was truncated (10240/223367) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005636e2ec5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005636e2ec2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005636e2ec662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbed6f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbed6f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbed6f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbed6eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005636e2e5bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005636e2e5ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005636e2e408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005636e2aefe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005636e2aefb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbed6eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbed6eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbed6eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005636e2aefa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c (1260 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d794a8eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d794a8be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d794a8f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f363e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f363e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f363e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f363e831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d794a24bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d794a24a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d794a098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d7946b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d7946b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f363e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f363e8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f363e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d7946b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c (1261 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesz_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesz_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesz_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesz_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesz_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesz_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesz_vs_u32m1_u32m8(<vscale x 16 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32m2_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind
# | ...
# `---data was truncated (10240/15211) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005557f16c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005557f16c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005557f16c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8fc2d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8fc2d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8fc2d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8fc2d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005557f165abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005557f165aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005557f163f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005557f12eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005557f12eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8fc2d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8fc2d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8fc2d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005557f12eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c (1262 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f16m1x8(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f32m1x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f64m1x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d174041eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d17403ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d17404262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f64bd449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f64bd4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f64bd449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f64bd431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d173fd7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d173fd7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d173fbc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d173c6be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d173c6bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f64bd432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f64bd4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f64bd4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d173c6ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c (1263 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjn_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjn_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjn_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjn_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjn_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjn_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjn_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjn_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjn_vv_f16m4_tu(<vscale x 16 x half> %maske
# | ...
# `---data was truncated (10240/157777) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d7c16f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d7c16f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d7c16f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa87b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa87b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa87b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa87b631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d7c1689bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d7c1689a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d7c166e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d7c131de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d7c131db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa87b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa87b6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa87b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d7c131da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c (1264 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmv_v_v_i8mf8(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmv_v_x_i8mf8(i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i8, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i64(<vscale x 1 x i8> poison, i8 %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmv_v_v_i8mf4(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmv_v_x_i8mf4(i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i8, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i64(<vscale x 2 x i8> poison, i8 %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmv_v_v_i8mf2(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmv_v_x_i8mf2(i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i8, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i64(<vscale x 4 x i8> poison, i8 %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmv_v_v_i8m1(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmv_v_x_i8m1(i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i8, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8> poison, i8 %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmv_v_v_i8m2(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmv_v_x_i8m2(i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i8, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i64(<vscale x 16 x i8> poison, i8 %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmv_v_v_i8m4(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmv_v_x_i8m4(i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i8, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vmv.v.x.nxv32i8.i64(<vscale x 32 x i8> poison, i8 %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmv.v.x.nxv32i8.i64(<vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vmv_v_v_i8m8(<vscale x 64 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vmv_v_x_i8m8(i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i8, ptr %src.addr, align 1
# |   %1 = load
# | ...
# `---data was truncated (10240/121927) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560cf78f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560cf78f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560cf78f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8186249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f81862a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8186249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8186231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560cf788abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560cf788aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560cf786f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560cf751ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560cf751eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8186232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f81862330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f81862330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560cf751ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c (1265 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_e4m3_e5m2_w4_f8e4m3m8_f8e5m2m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056121063deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056121063ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056121063e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fad3bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fad3bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fad3bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fad3bd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005612105d3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005612105d3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005612105b88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561210267e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561210267b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fad3bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fad3bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fad3bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561210267a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/neon-extract.c (1266 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-extract.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon   -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vext_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %vext = shufflevector <8 x i8> %2, <8 x i8> %3, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
# |   store <8 x i8> %vext, ptr %ref.tmp, align 8
# |   %4 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %4, ptr %__ret, align 8
# |   %5 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %5, ptr %tmp, align 8
# |   %6 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vext_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   %__ret = alloca <4 x i16>, align 8
# |   %__s0 = alloca <4 x i16>, align 8
# |   %__s1 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__s0, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %4 = bitcast <8 x i8> %2 to <4 x i16>
# |   %5 = bitcast <8 x i8> %3 to <4 x i16>
# |   %vext = shufflevector <4 x i16> %4, <4 x i16> %5, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
# |   store <4 x i16> %vext, ptr %ref.tmp, align 8
# |   %6 = load <4 x i16>, ptr %ref.tmp, align 8
# |   store <4 x i16> %6, ptr %__ret, align 8
# |   %7 = load <4 x i16>, ptr %__ret, align 8
# |   store <4 x i16> %7, ptr %tmp, align 8
# |   %8 = load <4 x i16>, ptr %tmp, align 8
# |   ret <4 x i16> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vext_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %__s1 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   store <2 x i32> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %4 = bitcast <8 x i8> %2 to <2 x i32>
# |   %5 = bitcast <8 x i8> %3 to <2 x i32>
# |   %vext = shufflevector <2 x i32> %4, <2 x i32> %5, <2 x i32> <i32 1, i32 2>
# |   store <2 x i32> %vext, ptr %ref.tmp, align 8
# |   %6 = load <2 x i32>, ptr %ref.tmp, align 8
# |   store <2 x i32> %6, ptr %__ret, align 8
# |   %7 = load <2 x i32>, ptr %__ret, align 8
# |   store <2 x i32> %7, ptr %tmp, align 8
# |   %8 = load <2 x i32>, ptr %tmp, align 8
# |   ret <2 x i32> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vext_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <1 x i64>, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   %__ret = alloca <1 x i64>, align 8
# |   %__s0 = alloca <1 x i64>, align 8
# |   %__s1 = alloca <1 x i64>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   store <1 x i64> %0, ptr %__s0, align 8
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %4 = bitcast <8 x i8> %2 to <1 x i64>
# |   %5 = bitcast <8 x i8> %3 to <1 x i64>
# |   %vext = shufflevector <1 x i64> %4, <1 x i64> %5, <1 x i32> zeroinitializer
# |   store <1 x i64> %vext, ptr %ref.tmp, align 8
# |   %6 = load <1 x i64>, ptr %ref.tmp, align 8
# |   store <1 x i64> %6, ptr %__ret, align 8
# |   %7 = load <1 x i64>, ptr %__ret, align 8
# |   store <1 x i64> %7, ptr %tmp, align 8
# |   %8 = load <1 x i64>, ptr %tmp, align 8
# |   ret <1 x i64> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vextq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   %__ret = alloca <16 x i8>, align 16
# |   %__s0 = alloca <16 x i8>, align 16
# |   %__s1 = alloca <16 x i8>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__s0, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   store <16 x i8> %1, ptr %__s1, align 16
# |   %2 = load <16 x i8>, ptr %__s0, align 16
# |   %3 = load <16 x i8>, ptr %__s1, align 16
# |   %vext = shufflevector <16 x i8> %2, <16 x i8> %3, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17>
# |   store <16 x i8> %vext, ptr %ref.tmp, align 16
# |   %4 = load <16 x i8>, ptr %ref.tmp, align 16
# |   store <16 x i8> %4, ptr %__ret, align 16
# |   %5 = load <16 x i8>, ptr %__ret, align 16
# |   store <16 x i8> %5, ptr %tmp, align 16
# |   %6 = load <16 x i8>, ptr %tmp, align 16
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vextq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   %__ret = alloca <8 x i16>, align 16
# |   %__s0 = alloca <8 x i16>, align 16
# |   %__s1 = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__s0, align 16
# |   %1 = load <8 x i16>, ptr %b.addr, align 16
# |   store <8 x i16> %1, ptr %__s1, align 16
# |   %2 = load <16 x i8>, ptr %__s0, align 16
# |   %3 = load <16 x i8>, ptr %__s1, align 16
# |   %4 = bitcast <16 x i8> %2 to <8 x i16>
# |   %5 = bitcast <16 x i8> %3 to <8 x i16>
# |   %vext = shufflevector <8 x i16> %4, <8 x i16> %5, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
# |   store <8 x i16> %vext, ptr %ref.tmp, align 16
# |   %6 = load <8 x i16>, ptr %ref.tmp, align 16
# |   store <8 x i16> %6, ptr %__ret, align 16
# |   %7 = load <8 x i16>, ptr %__ret, align 16
# |   store <8 x i16> %7, ptr %tmp, align 16
# |   %8 = load <8 x i16>, ptr %tmp, align 16
# |   ret <8 x i16> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vextq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <4 x i32>, align 16
# |   %__ret = alloca <4 x i32>, align 16
# |   %__s0 = alloca <4 x i32>, align 16
# |   %__s1 = alloca <4 x i32>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__s0, align 16
# |   %1 = load <4 x i32>, ptr %b.addr, align 16
# |   store <4 x i32> %1, ptr %__s1, align 16
# |   %2 = load <16 x i8>, ptr %__s0, align 16
# |   %3 = load <16 x i8>, ptr %__s1, align 16
# |   %4 = bitcast <16 x i8> %2 to <4 x i32>
# |   %5 = bitcast <16 x i8> %3 to <4 x i32>
# |   %vext = shufflevector <4 x i32> %4, <4 x i32> %5, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
# |   store <4 x i32> %vext, ptr %ref.tmp, align 16
# |   %6 = load <4 x i32>, ptr %ref.tmp, align 16
# |   store <4 x i32> %6, ptr %__ret, align 16
# |   %7 = load <4 x i32>, ptr %__ret, align 16
# |   store <4 x i32> %7, ptr %tmp, align 16
# |   %8 = load <4 x i32>, ptr %tmp, align 16
# |   ret <4 x i32> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vextq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   %b.addr = alloca <2 x i64>, align 16
# |   %__ret = alloca <2 x i64>, align 16
# |   %__s0 = alloca <2 x i64>, align 16
# |   %__s1 = alloca <2 x i64>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__s0, align 16
# |   %1 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %1, ptr %__s1, align 16
# |   %2 = load <16 x i8>, ptr %__s0, align 16
# |   %3 = load <16 x i8>, ptr %__s1, align 16
# |   %4 = bitcast <16 x i8> %2 to <2 x i64>
# |   %5 = bitcast <16 x i8> %3 to <2 x i64>
# |   %vext = shufflevector <2 x i64> %4, <2 x i64> %5, <2 x i32> <i32 1, i32 2>
# |   store <2 x i64> %vext, ptr %ref.tmp, align 16
# |   %6 = load <2 x i64>, ptr %ref.tmp, align 16
# |   store <2 x i64> %6, ptr %__ret, align 16
# |   %7 = load <2 x i64>, ptr %__ret, align 16
# |   store <2 x i64> %7, ptr %tmp, align 16
# |   %8 = load <2 x i64>, ptr %tmp, align 16
# |   ret <2 x i64> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vext_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8>
# | ...
# `---data was truncated (10240/29598) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005643a8cb8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005643a8cb5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005643a8cb962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7866f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7866f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7866f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7866f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005643a8c4ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005643a8c4ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005643a8c338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005643a88e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005643a88e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7866f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7866f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7866f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005643a88e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/bf16-getset-intrinsics.c (1267 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/bf16-getset-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vcreate_bf16(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %__ret = alloca <4 x bfloat>, align 8
# |   %__promote = alloca i64, align 8
# |   %tmp = alloca <4 x bfloat>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   store i64 %0, ptr %__promote, align 8
# |   %1 = load <4 x bfloat>, ptr %__promote, align 8
# |   store <4 x bfloat> %1, ptr %__ret, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret, align 8
# |   store <4 x bfloat> %2, ptr %tmp, align 8
# |   %3 = load <4 x bfloat>, ptr %tmp, align 8
# |   ret <4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcombine_bf16(<4 x bfloat> noundef %low, <4 x bfloat> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x bfloat>, align 8
# |   %__p1.addr.i = alloca <4 x bfloat>, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %low.addr = alloca <4 x bfloat>, align 8
# |   %high.addr = alloca <4 x bfloat>, align 8
# |   store <4 x bfloat> %low, ptr %low.addr, align 8
# |   store <4 x bfloat> %high, ptr %high.addr, align 8
# |   %0 = load <4 x bfloat>, ptr %low.addr, align 8
# |   %1 = load <4 x bfloat>, ptr %high.addr, align 8
# |   store <4 x bfloat> %0, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x bfloat>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <4 x bfloat> %2, <4 x bfloat> %3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x bfloat> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vset_lane_bf16(bfloat noundef %a, <4 x bfloat> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca bfloat, align 2
# |   %v.addr = alloca <4 x bfloat>, align 8
# |   %__ret = alloca <4 x bfloat>, align 8
# |   %__s0 = alloca bfloat, align 2
# |   %__s1 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca <4 x bfloat>, align 8
# |   %tmp = alloca <4 x bfloat>, align 8
# |   store bfloat %a, ptr %a.addr, align 2
# |   store <4 x bfloat> %v, ptr %v.addr, align 8
# |   %0 = load bfloat, ptr %a.addr, align 2
# |   store bfloat %0, ptr %__s0, align 2
# |   %1 = load <4 x bfloat>, ptr %v.addr, align 8
# |   store <4 x bfloat> %1, ptr %__s1, align 8
# |   %2 = load bfloat, ptr %__s0, align 2
# |   %3 = load <4 x bfloat>, ptr %__s1, align 8
# |   %vset_lane = insertelement <4 x bfloat> %3, bfloat %2, i32 1
# |   store <4 x bfloat> %vset_lane, ptr %ref.tmp, align 8
# |   %4 = load <4 x bfloat>, ptr %ref.tmp, align 8
# |   store <4 x bfloat> %4, ptr %__ret, align 8
# |   %5 = load <4 x bfloat>, ptr %__ret, align 8
# |   store <4 x bfloat> %5, ptr %tmp, align 8
# |   %6 = load <4 x bfloat>, ptr %tmp, align 8
# |   ret <4 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vsetq_lane_bf16(bfloat noundef %a, <8 x bfloat> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca bfloat, align 2
# |   %v.addr = alloca <8 x bfloat>, align 16
# |   %__ret = alloca <8 x bfloat>, align 16
# |   %__s0 = alloca bfloat, align 2
# |   %__s1 = alloca <8 x bfloat>, align 16
# |   %ref.tmp = alloca <8 x bfloat>, align 16
# |   %tmp = alloca <8 x bfloat>, align 16
# |   store bfloat %a, ptr %a.addr, align 2
# |   store <8 x bfloat> %v, ptr %v.addr, align 16
# |   %0 = load bfloat, ptr %a.addr, align 2
# |   store bfloat %0, ptr %__s0, align 2
# |   %1 = load <8 x bfloat>, ptr %v.addr, align 16
# |   store <8 x bfloat> %1, ptr %__s1, align 16
# |   %2 = load bfloat, ptr %__s0, align 2
# |   %3 = load <8 x bfloat>, ptr %__s1, align 16
# |   %vset_lane = insertelement <8 x bfloat> %3, bfloat %2, i32 7
# |   store <8 x bfloat> %vset_lane, ptr %ref.tmp, align 16
# |   %4 = load <8 x bfloat>, ptr %ref.tmp, align 16
# |   store <8 x bfloat> %4, ptr %__ret, align 16
# |   %5 = load <8 x bfloat>, ptr %__ret, align 16
# |   store <8 x bfloat> %5, ptr %tmp, align 16
# |   %6 = load <8 x bfloat>, ptr %tmp, align 16
# |   ret <8 x bfloat> %6
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055caeddd3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055caeddd0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055caeddd462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff845a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff845aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff845a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff845a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055caedd69bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055caedd69a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055caedd4e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055caed9fde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055caed9fdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff845a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff845a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff845a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055caed9fda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c (1268 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558403530eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055840352de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055840353162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9217c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9217ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9217c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9217c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005584034c6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005584034c6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005584034ab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055840315ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055840315ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9217c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9217c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9217c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055840315aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c (1269 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_f64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_f64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_i64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_i64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_u64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_u64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_f64m1x4_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple",
# | ...
# `---data was truncated (10240/40860) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564147c95eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564147c92e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564147c9662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2733705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f273375c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2733705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f27336ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564147c2bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564147c2ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564147c108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005641478bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005641478bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f27336eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f27336ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f27336ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005641478bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c (1270 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpairo_vv_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vpairo.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpairo.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpairo_vv_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vpairo.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpairo.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpairo_vv_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vpairo.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vpairo.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vpairo_vv_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vpairo.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vpairo.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vpairo_vv_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vpairo.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vpairo.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vpairo_vv_bf16m8(<vscale x 32 x bfloat> %vs2, <vscale x 32 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vpairo.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vpairo.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpairo_vv_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vpairo.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpairo.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpairo_vv_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vpairo.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpairo.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpairo_vv_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr
# | ...
# `---data was truncated (10240/15320) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560be43d2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560be43cfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560be43d362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4375849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f43758a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4375849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4375831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560be4368bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560be4368a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560be434d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560be3ffce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560be3ffcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4375832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f43758330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f43758330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560be3ffca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c (1271 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=maytrap -DEXCEPT=1 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not=fpexcept.maytrap --implicit-check-not=' @llvm.fma.'
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=maytrap -DEXCEPT=1 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <4 x half> @test_vfma_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %6 = bitcast <8 x i8> %3 to <4 x half>
# |   %7 = bitcast <8 x i8> %4 to <4 x half>
# |   %8 = bitcast <8 x i8> %5 to <4 x half>
# |   %9 = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> %7, <4 x half> %8, <4 x half> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <4 x half> %9, ptr %ref.tmp.i, align 8
# |   %10 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %10, ptr %__ret.i, align 8
# |   %11 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <8 x half> @test_vfmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %6 = bitcast <16 x i8> %3 to <8 x half>
# |   %7 = bitcast <16 x i8> %4 to <8 x half>
# |   %8 = bitcast <16 x i8> %5 to <8 x half>
# |   %9 = call <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half> %7, <8 x half> %8, <8 x half> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <8 x half> %9, ptr %ref.tmp.i, align 16
# |   %10 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %10, ptr %__ret.i, align 16
# |   %11 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <4 x half> @test_vfma_lane_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca <4 x half>, align 8
# |   %__s1 = alloca <4 x half>, align 8
# |   %__s2 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__s0, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %1, ptr %__s1, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x half> %2, ptr %__s2, align 8
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <8 x i8>, ptr %__s2, align 8
# |   %6 = bitcast <8 x i8> %5 to <4 x half>
# |   %lane = shufflevector <4 x half> %6, <4 x half> %6, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
# |   %fmla = bitcast <8 x i8> %4 to <4 x half>
# |   %fmla1 = bitcast <8 x i8> %3 to <4 x half>
# |   %fmla2 = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> %fmla, <4 x half> %lane, <4 x half> %fmla1, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <4 x half> %fmla2, ptr %ref.tmp, align 8
# |   %7 = load <4 x half>, ptr %ref.tmp, align 8
# |   store <4 x half> %7, ptr %__ret, align 8
# |   %8 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %8, ptr %tmp, align 8
# |   %9 = load <4 x half>, ptr %tmp, align 8
# |   ret <4 x half> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half>, <4 x half>, <4 x half>, metadata, metadata) #1
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <8 x half> @test_vfmaq_lane_f16(<8 x half> noundef %a, <8 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <4 x half>, align 8
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca <8 x half>, align 16
# |   %__s1 = alloca <8 x half>, align 16
# |   %__s2 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__s0, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %1, ptr %__s1, align 16
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x half> %2, ptr %__s2, align 8
# |   %3 = load <16 x i8>, ptr %__s0, align 16
# |   %4 = load <16 x i8>, ptr %__s1, align 16
# |   %5 = load <8 x i8>, ptr %__s2, align 8
# |   %6 = bitcast <8 x i8> %5 to <4 x half>
# |   %lane = shufflevector <4 x half> %6, <4 x half> %6, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
# |   %fmla = bitcast <16 x i8> %4 to <8 x half>
# |   %fmla1 = bitcast <16 x i8> %3 to <8 x half>
# |   %fmla2 = call <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half> %fmla, <8 x half> %lane, <8 x half> %fmla1, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <8 x half> %fmla2, ptr %ref.tmp, align 16
# |   %7 = load <8 x half>, ptr %ref.tmp, align 16
# |   store <8 x half> %7, ptr %__ret, align 16
# |   %8 = load <8 x half>, ptr %__ret, align 16
# |   store <8 x half> %8, ptr %tmp, align 16
# |   %9 = load <8 x half>, ptr %tmp, align 16
# |   ret <8 x half> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half>, <8 x half>, <8 x half>, metadata, metadata) #1
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <4 x half> @test_vfma_laneq_f16(<4 x half> noundef %a, <4 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 16
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca <4 x half>, align 8
# |   %__s1 = alloca <4 x half>, align 8
# |   %__s2 = alloca <8 x half>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__s0, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %1, ptr %__s1, align 8
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <8 x half> %2, ptr %__s2, align 16
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <16 x i8>, ptr %__s2, align 16
# |   %6 = bitcast <8 x i8> %3 to <4 x half>
# |   %7 = bitcast <8 x i8> %4 to <4 x half>
# |   %8 = bitcast <16 x i8> %5 to <8 x half>
# |   %lane = shufflevector <8 x half> %8, <8 x half> %8, <4 x i32> <i32 7, i32 7, i32 7, i32 7>
# |   %9 = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> %lane, <4 x half> %7, <4 x half> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <4 x half> %9, ptr %ref.tmp, align 8
# |   %10 = load <4 x half>, ptr %ref.tmp, align 8
# |   store <4 x half> %10, ptr %__ret, align 8
# |   %11 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %11, ptr %tmp, align 8
# |   %12 = load <4 x half>, ptr %tmp, align 8
# |   ret <4 x half> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <8 x half> @test_vfmaq_laneq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca <8 x half>, align 16
# |   %__s1 = alloca <8 x half>, align 16
# |   %__s2 = alloca <8 x half>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__s0, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %1, ptr %__s1, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <8 x half> %2, ptr %__s2, align 16
# |   %3 = load <16 x i8>, ptr %__s0, align 16
# |   %4 = load <16
# | ...
# `---data was truncated (10240/13273) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055aaeb657eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aaeb654e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aaeb65862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3d27133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3d2718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3d27133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3d2711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aaeb5edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aaeb5eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aaeb5d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aaeb281e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aaeb281b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3d2711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3d2711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3d2711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aaeb281a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not=fpexcept.maytrap '--implicit-check-not= @llvm.fma.'
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not=fpexcept.maytrap --implicit-check-not= @llvm.fma.
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c (1272 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssra_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssra_vx_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssra_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssra_vx_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssra_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssra_vx_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssra_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssra_vx_i8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssra_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssra_vx_i8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; 
# | ...
# `---data was truncated (10240/100289) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005651771b2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005651771afe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005651771b362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b87449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b874a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b87449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b87431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565177148bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565177148a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056517712d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565176ddce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565176ddcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3b87432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b874330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b874330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565176ddca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c (1273 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vloxei16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> poison, ptr %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca 
# | ...
# `---data was truncated (10240/14311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562a8f2a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562a8f2a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562a8f2a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f73e3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f73e3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f73e3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f73e3f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562a8f23bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562a8f23ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562a8f2208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562a8eecfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562a8eecfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f73e3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73e3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73e3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562a8eecfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c (1274 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei32_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei32_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei32_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei32_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei32_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei32_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei32_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei32_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei32_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, <vsc
# | ...
# `---data was truncated (10240/255546) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cf00c3aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cf00c37e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cf00c3b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1fcc849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1fcc8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1fcc849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1fcc831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf00bd0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cf00bd0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cf00bb58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cf00864e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cf00864b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1fcc832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1fcc8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1fcc8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf00864a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/neon-vcombine.c (1275 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-vcombine.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vcombine_s8(<8 x i8> noundef %low, <8 x i8> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %low.addr = alloca <8 x i8>, align 8
# |   %high.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %low, ptr %low.addr, align 8
# |   store <8 x i8> %high, ptr %high.addr, align 8
# |   %0 = load <8 x i8>, ptr %low.addr, align 8
# |   %1 = load <8 x i8>, ptr %high.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <8 x i8> %2, <8 x i8> %3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   store <16 x i8> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcombine_s16(<4 x i16> noundef %low, <4 x i16> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %low.addr = alloca <4 x i16>, align 8
# |   %high.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %low, ptr %low.addr, align 8
# |   store <4 x i16> %high, ptr %high.addr, align 8
# |   %0 = load <4 x i16>, ptr %low.addr, align 8
# |   %1 = load <4 x i16>, ptr %high.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <4 x i16> %2, <4 x i16> %3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x i16> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcombine_s32(<2 x i32> noundef %low, <2 x i32> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %low.addr = alloca <2 x i32>, align 8
# |   %high.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %low, ptr %low.addr, align 8
# |   store <2 x i32> %high, ptr %high.addr, align 8
# |   %0 = load <2 x i32>, ptr %low.addr, align 8
# |   %1 = load <2 x i32>, ptr %high.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <2 x i32> %2, <2 x i32> %3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
# |   store <4 x i32> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vcombine_s64(<1 x i64> noundef %low, <1 x i64> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %low.addr = alloca <1 x i64>, align 8
# |   %high.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %low, ptr %low.addr, align 8
# |   store <1 x i64> %high, ptr %high.addr, align 8
# |   %0 = load <1 x i64>, ptr %low.addr, align 8
# |   %1 = load <1 x i64>, ptr %high.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   %3 = load <1 x i64>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <1 x i64> %2, <1 x i64> %3, <2 x i32> <i32 0, i32 1>
# |   store <2 x i64> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vcombine_u8(<8 x i8> noundef %low, <8 x i8> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %low.addr = alloca <8 x i8>, align 8
# |   %high.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %low, ptr %low.addr, align 8
# |   store <8 x i8> %high, ptr %high.addr, align 8
# |   %0 = load <8 x i8>, ptr %low.addr, align 8
# |   %1 = load <8 x i8>, ptr %high.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <8 x i8> %2, <8 x i8> %3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   store <16 x i8> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcombine_u16(<4 x i16> noundef %low, <4 x i16> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %low.addr = alloca <4 x i16>, align 8
# |   %high.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %low, ptr %low.addr, align 8
# |   store <4 x i16> %high, ptr %high.addr, align 8
# |   %0 = load <4 x i16>, ptr %low.addr, align 8
# |   %1 = load <4 x i16>, ptr %high.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <4 x i16> %2, <4 x i16> %3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x i16> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcombine_u32(<2 x i32> noundef %low, <2 x i32> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %low.addr = alloca <2 x i32>, align 8
# |   %high.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %low, ptr %low.addr, align 8
# |   store <2 x i32> %high, ptr %high.addr, align 8
# |   %0 = load <2 x i32>, ptr %low.addr, align 8
# |   %1 = load <2 x i32>, ptr %high.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <2 x i32> %2, <2 x i32> %3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
# |   store <4 x i32> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vcombine_u64(<1 x i64> noundef %low, <1 x i64> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %low.addr = alloca <1 x i64>, align 8
# |   %high.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %low, ptr %low.addr, align 8
# |   store <1 x i64> %high, ptr %high.addr, align 8
# |   %0 = load <1 x i64>, ptr %low.addr, align 8
# |   %1 = load <1 x i64>, ptr %high.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   %3 = load <1 x i64>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <1 x i64> %2, <1 x i64> %3, <2 x i32> <i32 0, i32 1>
# |   store <2 x i64> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vcombine_p64(<1 x i64> noundef %low, <1 x i64> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %low.addr = alloca <1 x i64>, align 8
# |   %high.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %low, ptr %low.addr, align 8
# |   store <1 x i64> %high, ptr %high.addr, align 8
# |   %0 = load <1 x i64>, ptr %low.addr, align 8
# |   %1 = load <1 x i64>, ptr %high.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   %3 = load <1 x i64>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <1 x i64> %2, <1 x i64> %3, <2 x i32> <i32 0, i32 1>
# |   store <2 x i64> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vcombine_f16(<4 x half> noundef %low, <4 x half> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <8 x half>, align 16
# |   %low.addr = alloca <4 x half>, align 8
# |   %high.addr = alloca <4 x half>, align 8
# |   store <4 x half> %low, ptr %low.addr, align 8
# |   store <4 x half> %high, ptr %high.addr, align 8
# |   %0 = load <4 x half>, ptr %low.addr, align 8
# |   %1 = load <4 x half>, ptr %high.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x half>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x half>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <4 x half> %2, <4 x half> %3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x half> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vcombine_f32(<2 x float> noundef %low, <2 x float> noundef %high) #0 {
# | entry:
# |   %__p0.addr.
# | ...
# `---data was truncated (10240/14613) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561b7367eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561b7367be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561b7367f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f22f9049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f22f90a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f22f9049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f22f9031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561b73614bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561b73614a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561b735f98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561b732a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561b732a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f22f9032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f22f90330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f22f90330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561b732a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c (1276 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmandn_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmandn.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmandn.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmandn_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmandn.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmandn.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmandn_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmandn.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmandn.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmandn_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmandn.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmandn.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmandn_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmandn.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmandn.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmandn_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmandn.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmandn.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmandn_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmandn.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmandn.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005601593e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005601593e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005601593e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5709133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f570918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5709133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f570911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056015937bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056015937ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005601593608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056015900fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056015900fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f570911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f570911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f570911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056015900fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c (1277 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsra_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsra_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsra_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsra_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsra_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsra_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsra_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsra_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsra_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 
# | ...
# `---data was truncated (10240/223863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005633bc68beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005633bc688e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005633bc68c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2304b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2304b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2304b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2304b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005633bc621bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005633bc621a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005633bc6068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005633bc2b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005633bc2b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2304b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2304b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2304b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005633bc2b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c (1278 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf8_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> %0, <vscale x 1 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16>, <vscale x 1 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> %0, <vscale x 2 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16>, <vscale x 2 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf2_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m1_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> %0, <vscale x 8 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16>, <vscale x 8 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m2_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> %0, <vscale x 16 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16>, <vscale x 16 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> %0, <vscale x 32 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16>, <vscale x 32 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m8_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> %0, <vscale x 64 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16>, <vscale x 64 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16mf4_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(<vscale x 
# | ...
# `---data was truncated (10240/51193) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005573f47bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005573f47b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005573f47bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0fc6c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0fc6ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0fc6c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0fc6c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005573f4752bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005573f4752a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005573f47378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005573f43e6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005573f43e6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0fc6c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0fc6c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0fc6c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005573f43e6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c (1279 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_f32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_f32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_i32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_i32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_u32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_u32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounw
# | ...
# `---data was truncated (10240/15952) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559e15318eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559e15315e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559e1531962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c17249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c172a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c17249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c17231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e152aebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559e152aea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559e152938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559e14f42e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559e14f42b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7c17232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c172330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c172330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e14f42a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c (1280 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_viota_m_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_viota_m_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_viota_m_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_viota_m_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_viota_m_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_viota_m_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_viota_m_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_viota_m_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_viota_m_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_viota_m_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_viota_m_u16m2
# | ...
# `---data was truncated (10240/94673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c9d37d0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c9d37cde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c9d37d162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8548249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f85482a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8548249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8548231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9d3766bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c9d3766a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c9d374b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c9d33fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c9d33fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8548232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f85482330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f85482330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c9d33faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c (1281 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8ff_v_i8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8ff_v_i8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8ff_v_i8m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_u8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8ff_v_u8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8ff
# | ...
# `---data was truncated (10240/54702) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005630a9b18eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005630a9b15e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005630a9b1962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f34b2333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f34b238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f34b2333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f34b231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005630a9aaebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005630a9aaea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005630a9a938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005630a9742e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005630a9742b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f34b231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f34b231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f34b231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005630a9742a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c (1282 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf4_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> %0, <vscale x 1 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float>, <vscale x 1 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 4 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> %0, <vscale x 4 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float>, <vscale x 4 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 8 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> %0, <vscale x 8 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float>, <vscale x 8 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m4_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 16 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> %0, <vscale x 16 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float>, <vscale x 16 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m8_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 32 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float>, <vscale x 32 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32mf2_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 1 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x double> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m1_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 2 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca 
# | ...
# `---data was truncated (10240/60342) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055875915aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558759157e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055875915b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffa2c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffa2c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffa2c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffa2c231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005587590f0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005587590f0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005587590d58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558758d84e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558758d84b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffa2c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffa2c2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffa2c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558758d84a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c (1283 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmulhu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vsca
# | ...
# `---data was truncated (10240/98171) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055980b121eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055980b11ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055980b12262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6976a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6976a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6976a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6976a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055980b0b7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055980b0b7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055980b09c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055980ad4be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055980ad4bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6976a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6976a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6976a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055980ad4ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c (1284 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, ali
# | ...
# `---data was truncated (10240/14621) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562b94daeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562b94dabe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562b94daf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7d1d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7d1d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7d1d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7d1d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b94d44bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562b94d44a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562b94d298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562b949d8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562b949d8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7d1d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7d1d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7d1d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b949d8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c (1285 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei16_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aa03f56eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aa03f53e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aa03f5762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d22c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d22ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d22c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d22c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa03eecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aa03eeca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aa03ed18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aa03b80e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aa03b80b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8d22c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d22c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d22c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa03b80a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c (1286 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_f64m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_f64m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_i64m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_i64m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_u64m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_u64m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_i64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_i64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tu
# | ...
# `---data was truncated (10240/14044) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e55d45beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e55d458e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e55d45c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffbada1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffbada725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffbada1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffbada03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e55d3f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e55d3f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e55d3d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e55d085e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e55d085b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffbada04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffbada050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffbada050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e55d085a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c (1287 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vandn_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vandn_vx_u8mf8(<vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vandn_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vandn_vx_u8mf4(<vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vandn_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vandn_vx_u8mf2(<vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vandn_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vandn_vx_u8m1(<vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vandn_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vandn.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vandn.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vandn_vx_u8m2(<vscale x 16 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vandn.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vandn.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vandn_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <v
# | ...
# `---data was truncated (10240/98125) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005628a8707eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005628a8704e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005628a870862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f16a3533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f16a358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f16a3533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f16a351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005628a869dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005628a869da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005628a86828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005628a8331e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005628a8331b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f16a351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f16a351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f16a351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005628a8331a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c (1288 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_bf16m1x2_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl
# | ...
# `---data was truncated (10240/27434) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558ecdc1eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558ecdc1be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558ecdc1f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc7ffb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc7ffb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc7ffb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc7ffaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558ecdbb4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558ecdbb4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558ecdb998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558ecd848e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558ecd848b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc7ffaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc7ffaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc7ffaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558ecd848a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c (1289 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_f32mf2_tu(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_f32m1_tu(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_f32m2_tu(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_f32m4_tu(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmac
# | ...
# `---data was truncated (10240/179511) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005649648eaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005649648e7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005649648eb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3db981bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3db98725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3db981ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3db9803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564964880bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564964880a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005649648658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564964514e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564964514b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3db9804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3db98050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3db98050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564964514a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c (1290 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i16> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i16> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i16> %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> %2, ptr %0, <vscale x 32 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x
# | ...
# `---data was truncated (10240/15614) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005588d656feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005588d656ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005588d657062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efdf7f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efdf7f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efdf7f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efdf7f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005588d6505bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005588d6505a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005588d64ea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005588d6199e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005588d6199b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efdf7f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efdf7f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efdf7f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005588d6199a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c (1291 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005599f9cd0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005599f9ccde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005599f9cd162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f15e5449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f15e54a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f15e5449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f15e5431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005599f9c66bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005599f9c66a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005599f9c4b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005599f98fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005599f98fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f15e5432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15e54330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15e54330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005599f98faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c (1292 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsub_vv_i8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsub_vx_i8mf8(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsub_vv_i8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsub_vx_i8mf4(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsub_vv_i8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsub_vx_i8mf2(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsub_vv_i8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsub_vx_i8m1(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnmsub_vv_i8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8
# | ...
# `---data was truncated (10240/208191) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fffe421eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fffe41ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fffe42262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f90b5b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f90b5b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f90b5b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f90b5aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fffe3b7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fffe3b7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fffe39c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fffe04be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fffe04bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f90b5aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f90b5aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f90b5aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fffe04ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c (1293 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vf_f32mf2_tu(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vf_f32m1_tu(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vf_f32m2_tu(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vf_f32m4_tu(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f3
# | ...
# `---data was truncated (10240/179503) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f5490feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559f5490ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559f5491062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f886ae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f886aea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f886ae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f886ae31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f548a5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559f548a5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559f5488a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559f54539e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559f54539b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f886ae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f886ae330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f886ae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f54539a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c (1294 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f16m1x8(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f32m1x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f64m1x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i32> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557b8059ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557b80599e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557b8059d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9471049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f94710a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9471049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9471031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b80532bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557b80532a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557b805178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557b801c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557b801c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9471032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f94710330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f94710330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b801c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c (1295 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_tu(<vscale x 16 x half> %vd, <vsc
# | ...
# `---data was truncated (10240/295319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005587938f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005587938f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005587938f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f296f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f296f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f296f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f296f91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055879388abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055879388aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055879386f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055879351ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055879351eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f296f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f296f91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f296f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055879351ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c (1296 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzp1_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uzp1.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzp1_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uzp1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzp1_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uzp1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzp1_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzp1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uzp1.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzp1_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzp1_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzp1_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzp1_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzp1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svuzp1_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.uzp1.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.uzp1.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svuzp1_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.uzp1.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.uzp1.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svuzp1_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.uzp1.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.uzp1.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svuzp1_b8(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.uzp1.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.uzp1.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svuzp1_b16(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.uzp1.b16(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | ...
# `---data was truncated (10240/13404) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055cc6817beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cc68178e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cc6817c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f20e2905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f20e295c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f20e2905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f20e28ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc68111bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cc68111a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cc680f68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cc67da5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cc67da5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f20e28eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f20e28ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f20e28ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc67da5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c (1297 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrec7_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrec7_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrec7_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrec7_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrec7_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrec7_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrec7_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrec7_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrec7_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrec7_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.
# | ...
# `---data was truncated (10240/128424) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005565d8befeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005565d8bece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005565d8bf062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f40bc333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f40bc38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f40bc333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f40bc31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005565d8b85bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005565d8b85a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005565d8b6a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005565d8819e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005565d8819b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f40bc31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f40bc31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f40bc31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005565d8819a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c (1298 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsbf_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsbf_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsbf_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsbf_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbf_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbf_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbf_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsbf_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1> poison, <vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsbf_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1> poison, <vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsbf_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1> poison, <vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsbf_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1> poison, <vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbf_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1.i64(<vscale x 4 x i1> poison, <vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree no
# | ...
# `---data was truncated (10240/13023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ba1153eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557ba1150e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557ba115462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbbe9305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbbe935c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbbe9305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbbe92ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ba10e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557ba10e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557ba10ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557ba0d7de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557ba0d7db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbbe92eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbbe92ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbbe92ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ba0d7da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c (1299 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmadd_vv_i8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmadd_vx_i8mf8(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmadd_vv_i8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmadd_vx_i8mf4(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmadd_vv_i8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmadd_vx_i8mf2(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmadd_vv_i8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmadd_vx_i8m1(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmadd_vv_i8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, a
# | ...
# `---data was truncated (10240/207757) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564d91591eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564d9158ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564d9159262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0f4c01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0f4c0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0f4c01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0f4c003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d91527bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564d91527a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564d9150c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564d911bbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564d911bbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0f4c004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0f4c0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0f4c0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d911bba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c (1300 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei8_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, p
# | ...
# `---data was truncated (10240/14521) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eeae9e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eeae9e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eeae9e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c05f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c05f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c05f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c05f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eeae97bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eeae97ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eeae9608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eeae60fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eeae60fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7c05f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c05f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c05f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eeae60fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-neon-vst.c (1301 of 27911)
******************** TEST 'Clang :: CodeGen/arm-neon-vst.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-gnueabi -target-feature +neon      -target-feature +fp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c |      /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-gnueabi -target-feature +neon -target-feature +fp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8-none-linux-gnueabi"
# | 
# | %struct.float16x4x2_t = type { [2 x <4 x half>] }
# | %struct.float16x4x3_t = type { [3 x <4 x half>] }
# | %struct.float16x4x4_t = type { [4 x <4 x half>] }
# | %struct.float32x2x2_t = type { [2 x <2 x float>] }
# | %struct.float32x2x3_t = type { [3 x <2 x float>] }
# | %struct.float32x2x4_t = type { [4 x <2 x float>] }
# | %struct.poly16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.poly16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.poly16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.poly8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.poly8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.poly8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.int16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.int16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.int16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.int32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.int32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.int32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.int64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.int64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.int64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.int8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.int8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.int8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.uint16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.uint16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.uint16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.uint32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.uint32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.uint32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.uint64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.uint64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.uint64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.uint8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.uint8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.uint8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.float16x8x2_t = type { [2 x <8 x half>] }
# | %struct.float16x8x3_t = type { [3 x <8 x half>] }
# | %struct.float16x8x4_t = type { [4 x <8 x half>] }
# | %struct.float32x4x2_t = type { [2 x <4 x float>] }
# | %struct.float32x4x3_t = type { [3 x <4 x float>] }
# | %struct.float32x4x4_t = type { [4 x <4 x float>] }
# | %struct.poly16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.poly16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.poly16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.poly8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.poly8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.poly8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.int16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.int16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.int16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.int32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.int32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.int32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.int64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.int64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.int64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.int8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.int8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.int8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.uint16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.uint16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.uint16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.uint32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.uint32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.uint32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.uint64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.uint64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.uint64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.uint8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.uint8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.uint8x16x4_t = type { [4 x <16 x i8>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_f16_x2(ptr noundef %a, [2 x i64] %b.coerce) #0 {
# | entry:
# |   %b = alloca %struct.float16x4x2_t, align 8
# |   %a.addr = alloca ptr, align 4
# |   %__s1 = alloca %struct.float16x4x2_t, align 8
# |   %coerce.dive = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %b, i32 0, i32 0
# |   store [2 x i64] %b.coerce, ptr %coerce.dive, align 8
# |   store ptr %a, ptr %a.addr, align 4
# |   call void @llvm.memcpy.p0.p0.i32(ptr align 8 %__s1, ptr align 8 %b, i32 16, i1 false)
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %val = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx = getelementptr inbounds [2 x <4 x half>], ptr %val, i32 0, i32 0
# |   %1 = load <8 x i8>, ptr %arrayidx, align 8
# |   %val1 = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx2 = getelementptr inbounds [2 x <4 x half>], ptr %val1, i32 0, i32 1
# |   %2 = load <8 x i8>, ptr %arrayidx2, align 8
# |   %3 = bitcast <8 x i8> %1 to <4 x i16>
# |   %4 = bitcast <8 x i8> %2 to <4 x i16>
# |   call void @llvm.arm.neon.vst1x2.p0.v4i16(ptr %0, <4 x i16> %3, <4 x i16> %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.memcpy.p0.p0.i32(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i32, i1 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.arm.neon.vst1x2.p0.v4i16(ptr captures(none), <4 x i16>, <4 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_f16_x3(ptr noundef %a, [3 x i64] %b.coerce) #0 {
# | entry:
# |   %b = alloca %struct.float16x4x3_t, align 8
# |   %a.addr = alloca ptr, align 4
# |   %__s1 = alloca %struct.float16x4x3_t, align 8
# |   %coerce.dive = getelementptr inbounds nuw %struct.float16x4x3_t, ptr %b, i32 0, i32 0
# |   store [3 x i64] %b.coerce, ptr %coerce.dive, align 8
# |   store ptr %a, ptr %a.addr, align 4
# |   call void @llvm.memcpy.p0.p0.i32(ptr align 8 %__s1, ptr align 8 %b, i32 24, i1 false)
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %val = getelementptr inbounds nuw %struct.float16x4x3_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx = getelementptr inbounds [3 x <4 x half>], ptr %val, i32 0, i32 0
# |   %1 = load <8 x i8>, ptr %arrayidx, align 8
# |   %val1 = getelementptr inbounds nuw %struct.float16x4x3_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx2 = getelementptr inbounds [3 x <4 x half>], ptr %val1, i32 0, i32 1
# |   %2 = load <8 x i8>, ptr %arrayidx2, align 8
# |   %val3 = getelementptr inbounds nuw %struct.float16x4x3_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx4 = getelementptr inbounds [3 x <4 x half>], ptr %val3, i32 0, i32 2
# |   %3 = load <8 x i8>, ptr %arrayidx4, align 8
# |   %4 = bitcast <8 x i8> %1 to <4 x i16>
# |   %5 = bitcast <8 x i8> %2 to <4 x i16>
# |   %6 = bitcast <8 x i8> %3 to <4 x i16>
# |   call void @llvm.arm.neon.vst1x3.p0.v4i16(ptr %0, <4 x i16> %4, <4 x i16> %5, <4 x i16> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.arm.neon.vst1x3.p0.v4i16(ptr captures(none), <4 x i16>, <4 x i16>, <4 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_f16_x4(ptr noundef %a, [4 x i64] %b.coerce) #0 {
# | entry:
# |   %b = alloca %struct.float16x4x4_t, align 8
# |   %a.addr = alloca ptr, align 4
# |   %__s1 = alloca %struct.float16x4x4_t, align 8
# |   %coerce.dive = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %b, i32 0, i32 0
# |   store [4 x i64] %b.coerce, ptr %coerce.dive, align 8
# |   store ptr %a, ptr %a.addr, align 4
# |   call void @llvm.memcpy.p0.p0.i32(ptr align 8 %__s1, ptr align 8 %b, i32 32, i1 false)
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %val = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx = getelementptr inbounds [4 x <4 x half>], ptr %val, i32 0, i32 0
# |   %1 = load <8 x i8>, ptr %arrayidx, align 8
# |   %val1 = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx2 = getelementptr inbounds [4 x <4 x half>], ptr %val1, i32 0, i32 1
# |   %2 = load <8 x i8>, ptr %arrayidx2, align 8
# |   %val3 = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx4 = getelementptr inbounds [4 x <4 x half>], ptr %val3, i32 0, i32 2
# |   %3 = load <8 x i8>, ptr %arrayidx4, align 8
# |   %val5 = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx6 = getelementptr inbounds [4 x <4 x half>], ptr %val5, i32 0, i32 3
# |   %4 = load <8 x i8>, ptr %arrayidx6, align 8
# |   %5 = bitcast <8 x i8> %1 to <4 x i16>
# |   %6 = bitcast <8 x i8> %2 to <4 x i16>
# |   %7 = bitcast <8 x i8> %3 to <4 x i16>
# |   %8 = bitcast <8 x i8> %4 to <4 x i16>
# |   call void @llvm.arm.neon.vst1x4.p0.v4i16(ptr %0, <4 x i16> %5, <4 x i16> %6, <4 x i16> %7, <4 x i16> %8)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.arm.neon.vst1x4.p0.v4i16(ptr captures(none), <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_f32_x2(ptr noundef %a, [2 x i64] %b.coerce) #0 {
# | entry:
# |   %b = alloca %struct.float32x2x2_t, align 8
# |   %a.addr = alloca ptr, align 4
# |   %__s1 = alloca %struct.float32x2x2_t, align 8
# |   %coerce.dive = getelementptr inbounds nuw %struct.float32x2x2_t, ptr %b, i32 0, i32 0
# |   store [2 x i64] %b.coerce, ptr %coerce.dive, align 8
# |   store ptr %a, ptr %a.addr, align 4
# |   call void @llvm.memcpy.p0.p0.i32(ptr align 8 %__s1, ptr align 8 %b, i32 16, i1 false)
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %val = getelementptr inbounds nuw %struct.float32x2x2_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx = getelementptr inbounds [2 x <2 x float>], ptr %val, i32 0, i32 0
# |   %1 = load <8 x i8>, ptr %arrayidx, align 8
# |   %val1 = getelementptr inbounds nuw %struct.float32x2x2_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx2 = getelementptr inbounds [2 x <2 x float>], ptr %val1, i32 0, i32 1
# |   %2 = load <8 x i8>, ptr %arrayidx2, align 8
# |   %3 = bitcast <8 x i8> %1 to <2 x float>
# |   %4 = bitcast <8 x i8> %2 to <2 x float>
# |   call void @llvm.arm.neon.vst1x2.p0.v2f32(ptr %0, <2 x float> %3, <2 x float> %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.arm.neon.vst1x2.p0.v2f32(ptr captures(none), <2 x float>, <2 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_f32_x3(ptr noundef %a, [3 x i64] %b.coerce) #0 {
# | entry:
# |   %b = alloca %s
# | ...
# `---data was truncated (10240/108866) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000560f50f95eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560f50f92e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560f50f9662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb4a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb4a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb4a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb4a231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f50f2bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560f50f2ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560f50f108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560f50bbfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560f50bbfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feb4a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb4a2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb4a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f50bbfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c (1302 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrol_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrol_vx_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrol_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrol_vx_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrol_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrol_vx_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrol_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrol_vx_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrol_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrol.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrol.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrol_vx_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrol.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrol.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vrol_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = al
# | ...
# `---data was truncated (10240/97675) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555960433eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555960430e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055596043462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd7f8a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd7f8aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd7f8a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd7f8a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005559603c9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005559603c9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005559603ae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055596005de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055596005db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd7f8a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd7f8a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd7f8a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055596005da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/neon/fullfp16-constrained.c (1303 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/fullfp16-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=strict -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,simplifycfg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not=' @llvm.fma.' --implicit-check-not=' @llvm.sqrt.'
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=strict -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local half @test_vsqrth_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vsqrt = call half @llvm.experimental.constrained.sqrt.f16(half %1, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store half %vsqrt, ptr %ref.tmp, align 2
# |   %2 = load half, ptr %ref.tmp, align 2
# |   store half %2, ptr %__ret, align 2
# |   %3 = load half, ptr %__ret, align 2
# |   store half %3, ptr %tmp, align 2
# |   %4 = load half, ptr %tmp, align 2
# |   ret half %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare half @llvm.experimental.constrained.sqrt.f16(half, metadata, metadata) #1
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local half @test_vfmah_f16(half noundef %a, half noundef %b, half noundef %c) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %c.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %__s2 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   store half %c, ptr %c.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %c.addr, align 2
# |   store half %2, ptr %__s2, align 2
# |   %3 = load half, ptr %__s0, align 2
# |   %4 = load half, ptr %__s1, align 2
# |   %5 = load half, ptr %__s2, align 2
# |   %6 = call half @llvm.experimental.constrained.fma.f16(half %4, half %5, half %3, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store half %6, ptr %ref.tmp, align 2
# |   %7 = load half, ptr %ref.tmp, align 2
# |   store half %7, ptr %__ret, align 2
# |   %8 = load half, ptr %__ret, align 2
# |   store half %8, ptr %tmp, align 2
# |   %9 = load half, ptr %tmp, align 2
# |   ret half %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare half @llvm.experimental.constrained.fma.f16(half, half, half, metadata, metadata) #1
# | 
# | attributes #0 = { noinline nounwind strictfp "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon" }
# | attributes #1 = { nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) }
# | attributes #2 = { strictfp }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,simplifycfg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,simplifycfg
# |  #0 0x000055ff08a77eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ff08a74e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ff08a7862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f33fbc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f33fbca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f33fbc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f33fbc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ff08a0dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ff08a0da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ff089f28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ff086a1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ff086a1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f33fbc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f33fbc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f33fbc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ff086a1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c --check-prefixes=ALL,LLVM '--implicit-check-not= @llvm.fma.' '--implicit-check-not= @llvm.sqrt.'
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not= @llvm.fma. --implicit-check-not= @llvm.sqrt.
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl (1304 of 27911)
******************** TEST 'Clang :: CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O0 -cl-std=CL2.0 -triple amdgpu-amd-amdhsa -fno-ident -DKERNEL_NAME=test_kernel_first -DTYPE=float -DCONST=256.0f -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O0 -cl-std=CL2.0 -triple amdgpu-amd-amdhsa -fno-ident -DKERNEL_NAME=test_kernel_first -DTYPE=float -DCONST=256.0f -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O0 -cl-std=CL2.0 -triple amdgpu-amd-amdhsa -fno-ident -DKERNEL_NAME=test_kernel_second -DTYPE=int -DCONST=128.0f -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.1.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O0 -cl-std=CL2.0 -triple amdgpu-amd-amdhsa -fno-ident -DKERNEL_NAME=test_kernel_second -DTYPE=int -DCONST=128.0f -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.1.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl
# RUN: at line 8
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=globalopt -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.opt.0.bc /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=globalopt -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.opt.0.bc /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=globalopt -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.opt.0.bc /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc
# |  #0 0x000055d4d8cf1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d4d8ceee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d4d8cf262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7b8c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7b8c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7b8c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7b8c231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d4d8c87bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d4d8c87a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d4d8c6c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d4d891be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d4d891bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7b8c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7b8c2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7b8c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d4d891ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c (1305 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zkne -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c  -check-prefix=RV32ZKNE
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zkne -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @aes32esi(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   %2 = call i32 @llvm.riscv.aes32esi(i32 %0, i32 %1, i32 3)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.aes32esi(i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @aes32esmi(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   %2 = call i32 @llvm.riscv.aes32esmi(i32 %0, i32 %1, i32 3)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.aes32esmi(i32, i32, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zkne" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zkne1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de93048eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055de93045e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055de9304962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f159ea1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f159ea725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f159ea1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f159ea03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de92fdebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055de92fdea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055de92fc38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055de92c72e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055de92c72b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f159ea04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f159ea050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f159ea050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de92c72a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c -check-prefix=RV32ZKNE
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c -check-prefix=RV32ZKNE
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c (1306 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_i32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_i32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_u32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_u32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_f32mf2x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_f32m1x5_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("ri
# | ...
# `---data was truncated (10240/32023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de99b1aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055de99b17e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055de99b1b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7cdf533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7cdf58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7cdf533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7cdf51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de99ab0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055de99ab0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055de99a958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055de99744e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055de99744b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7cdf51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7cdf51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7cdf51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de99744a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/neon/f16-getset.c (1307 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/f16-getset.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -disable-O0-optnone           -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vdup_n_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca half, align 2
# |   %.compoundliteral = alloca <4 x half>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vecinit = insertelement <4 x half> poison, half %1, i32 0
# |   %2 = load half, ptr %__s0, align 2
# |   %vecinit1 = insertelement <4 x half> %vecinit, half %2, i32 1
# |   %3 = load half, ptr %__s0, align 2
# |   %vecinit2 = insertelement <4 x half> %vecinit1, half %3, i32 2
# |   %4 = load half, ptr %__s0, align 2
# |   %vecinit3 = insertelement <4 x half> %vecinit2, half %4, i32 3
# |   store <4 x half> %vecinit3, ptr %.compoundliteral, align 8
# |   %5 = load <4 x half>, ptr %.compoundliteral, align 8
# |   store <4 x half> %5, ptr %__ret, align 8
# |   %6 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %6, ptr %tmp, align 8
# |   %7 = load <4 x half>, ptr %tmp, align 8
# |   ret <4 x half> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vdupq_n_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca half, align 2
# |   %.compoundliteral = alloca <8 x half>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vecinit = insertelement <8 x half> poison, half %1, i32 0
# |   %2 = load half, ptr %__s0, align 2
# |   %vecinit1 = insertelement <8 x half> %vecinit, half %2, i32 1
# |   %3 = load half, ptr %__s0, align 2
# |   %vecinit2 = insertelement <8 x half> %vecinit1, half %3, i32 2
# |   %4 = load half, ptr %__s0, align 2
# |   %vecinit3 = insertelement <8 x half> %vecinit2, half %4, i32 3
# |   %5 = load half, ptr %__s0, align 2
# |   %vecinit4 = insertelement <8 x half> %vecinit3, half %5, i32 4
# |   %6 = load half, ptr %__s0, align 2
# |   %vecinit5 = insertelement <8 x half> %vecinit4, half %6, i32 5
# |   %7 = load half, ptr %__s0, align 2
# |   %vecinit6 = insertelement <8 x half> %vecinit5, half %7, i32 6
# |   %8 = load half, ptr %__s0, align 2
# |   %vecinit7 = insertelement <8 x half> %vecinit6, half %8, i32 7
# |   store <8 x half> %vecinit7, ptr %.compoundliteral, align 16
# |   %9 = load <8 x half>, ptr %.compoundliteral, align 16
# |   store <8 x half> %9, ptr %__ret, align 16
# |   %10 = load <8 x half>, ptr %__ret, align 16
# |   store <8 x half> %10, ptr %tmp, align 16
# |   %11 = load <8 x half>, ptr %tmp, align 16
# |   ret <8 x half> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vdup_lane_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x half>, align 8
# |   %__ret_39 = alloca <4 x half>, align 8
# |   %__s0_39 = alloca <4 x half>, align 8
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   %tmp1 = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__s0_39, align 8
# |   %1 = load <4 x half>, ptr %__s0_39, align 8
# |   store <4 x half> %1, ptr %__s0, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = bitcast <8 x i8> %2 to <4 x half>
# |   %lane = shufflevector <4 x half> %3, <4 x half> %3, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
# |   store <4 x half> %lane, ptr %ref.tmp, align 8
# |   %4 = load <4 x half>, ptr %ref.tmp, align 8
# |   store <4 x half> %4, ptr %__ret, align 8
# |   %5 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %5, ptr %tmp, align 8
# |   %6 = load <4 x half>, ptr %tmp, align 8
# |   store <4 x half> %6, ptr %__ret_39, align 8
# |   %7 = load <4 x half>, ptr %__ret_39, align 8
# |   store <4 x half> %7, ptr %tmp1, align 8
# |   %8 = load <4 x half>, ptr %tmp1, align 8
# |   ret <4 x half> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vdupq_lane_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x half>, align 8
# |   %__ret_20 = alloca <8 x half>, align 16
# |   %__s0_20 = alloca <4 x half>, align 8
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   %tmp1 = alloca <8 x half>, align 16
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__s0_20, align 8
# |   %1 = load <4 x half>, ptr %__s0_20, align 8
# |   store <4 x half> %1, ptr %__s0, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = bitcast <8 x i8> %2 to <4 x half>
# |   %lane = shufflevector <4 x half> %3, <4 x half> %3, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
# |   store <8 x half> %lane, ptr %ref.tmp, align 16
# |   %4 = load <8 x half>, ptr %ref.tmp, align 16
# |   store <8 x half> %4, ptr %__ret, align 16
# |   %5 = load <8 x half>, ptr %__ret, align 16
# |   store <8 x half> %5, ptr %tmp, align 16
# |   %6 = load <8 x half>, ptr %tmp, align 16
# |   store <8 x half> %6, ptr %__ret_20, align 16
# |   %7 = load <8 x half>, ptr %__ret_20, align 16
# |   store <8 x half> %7, ptr %tmp1, align 16
# |   %8 = load <8 x half>, ptr %tmp1, align 16
# |   ret <8 x half> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vdup_laneq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 16
# |   %__ret_432 = alloca <4 x half>, align 8
# |   %__s0_432 = alloca <8 x half>, align 16
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca <8 x half>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   %tmp1 = alloca <4 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__s0_432, align 16
# |   %1 = load <8 x half>, ptr %__s0_432, align 16
# |   store <8 x half> %1, ptr %__s0, align 16
# |   %2 = load <16 x i8>, ptr %__s0, align 16
# |   %3 = bitcast <16 x i8> %2 to <8 x half>
# |   %lane = shufflevector <8 x half> %3, <8 x half> %3, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
# |   store <4 x half> %lane, ptr %ref.tmp, align 8
# |   %4 = load <4 x half>, ptr %ref.tmp, align 8
# |   store <4 x half> %4, ptr %__ret, align 8
# |   %5 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %5, ptr %tmp, align 8
# |   %6 = load <4 x half>, ptr %tmp, align 8
# |   store <4 x half> %6, ptr %__ret_432, align 8
# |   %7 = load <4 x half>, ptr %__ret_432, align 8
# |   store <4 x half> %7, ptr %tmp1, align 8
# |   %8 = load <4 x half>, ptr %tmp1, align 8
# |   ret <4 x half> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vdupq_laneq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 16
# |   %__ret_408 = alloca <8 x half>, align 16
# |   %__s0_408 = alloca <8 x half>, align 16
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca <8 x half>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   %tmp1 = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__s0_408, align 16
# |   %1 = load <8 x half>, ptr %__s0_408, align 16
# |   store <8 x half> %1, ptr %__s0, align 16
# |   %2 = load <16 x i8>, ptr %__s0, align 16
# |   %3 = bitcast <16 x i8> %2 to <8 x half>
# |   %lane = shufflevector <8 x half> %3, <8 x half> %3, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
# |   store <8 x half> %lane, ptr %ref.tmp, align 16
# |   %4 = load <8 x half>, ptr %ref.tmp, align 16
# |   store <8 x half> %4, ptr %__ret, align 16
# |   %5 = load <8 x half>, ptr %__ret, align 16
# |   store <8 x half> %5, ptr %tmp, align 16
# |   %6 = load <8 x half>, ptr %tmp, align 16
# |   store <8 x half> %6, ptr %__ret_408, align 16
# |   %7 = load <8 x half>, ptr %__ret_408, align 16
# |   store <8 x half> %7, ptr %tmp1, align 16
# |   %8 = load <8 x half>, ptr %tmp1, align 16
# |   ret <8 x half> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vduph_lane_f16(<4 x half> noundef %vec) #0 {
# | entry:
# |   %vec.addr = alloca <4 x half>, align 8
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store <4 x half> %vec, ptr %vec.addr, align 8
# |   %0 = load <4 x half>, ptr %vec.addr, align 8
# |   store <4 x half> %0, ptr %__s0, align 8
# |   %1 = load <4 x half>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x half> %1, i32 3
# |   store half %vget_lane, ptr %ref.tmp, align 2
# |   %2 = load half, ptr %ref.tmp, align 2
# |   store half %2, ptr %__ret, align 2
# |   %3 = load half, ptr %__ret, align 2
# |   store half %3, ptr %tmp, align 2
# |   %4 = load half, ptr %tmp, align 2
# |   ret half %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vduph_laneq_f16(<8 x half> noundef %vec) #0 {
# | entry:
# |   %vec.addr = alloca <8 x half>, align 16
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca <8 x half>, align 16
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store <8 x half> %vec, ptr %vec.addr, align 16
# |   %0 = load <8 x half>, ptr %vec.addr, align 16
# |   store <8 x half> %0, ptr %__s0, align 16
# |   %1 = load <8 x half>, ptr %__s0, align 16
# |   %vgetq_lane = extractelement <8 x half> %1, i32 7
# |   store half %vgetq_lane, ptr %ref.tmp, align 2
# |   %2 = load half, ptr %ref.tmp, align 2
# |   store half %2, ptr %__ret, align 2
# |   %3 = load half, ptr %__ret, align 2
# |   store half %3, ptr %tmp, align 2
# |   %4 = load half, ptr %tmp, align 2
# |   ret half %4
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-s
# | ...
# `---data was truncated (10240/10414) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055972e330eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055972e32de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055972e33162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbf8fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbf8fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbf8fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbf8fc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055972e2c6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055972e2c6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055972e2ab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055972df5ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055972df5ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbf8fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbf8fc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbf8fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055972df5aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vornq.c (1308 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vornq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vornq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = xor <16 x i8> %1, splat (i8 -1)
# |   %3 = or <16 x i8> %0, %2
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vornq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = xor <8 x i16> %1, splat (i16 -1)
# |   %3 = or <8 x i16> %0, %2
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vornq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = xor <4 x i32> %1, splat (i32 -1)
# |   %3 = or <4 x i32> %0, %2
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vornq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = xor <4 x i32> %3, splat (i32 -1)
# |   %5 = or <4 x i32> %1, %4
# |   %6 = bitcast <4 x i32> %5 to <4 x float>
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vornq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.orn.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.orn.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vornq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vornq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.orn.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.orn.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vornq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <8 x i16>
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = bitcast <8 x half> %2 to <8 x i16>
# |   %4 = load i16, ptr %p.addr, align 2
# |   %5 = zext i16 %4 to i32
# |   %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5)
# |   %7 = load <8 x half>, ptr %inactive.addr, align 8
# |   %8 = bitcast <8 x half> %7 to <8 x i16>
# |   %9 = call <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8)
# |   %10 = bitcast <8 x i16> %9 to <8 x half>
# |   ret <8 x half> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vornq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.orn.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vornq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vornq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.orn.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vornq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = load i16, ptr %p.addr, al
# | ...
# `---data was truncated (10240/11056) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005614f5012eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005614f500fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005614f501362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faf94449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faf944a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faf94449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faf94431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005614f4fa8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005614f4fa8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005614f4f8d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005614f4c3ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005614f4c3cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faf94432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faf944330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faf944330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005614f4c3ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c (1309 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a8ac21feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a8ac21ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a8ac22062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f48e9049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f48e90a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f48e9049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f48e9031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a8ac1b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a8ac1b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a8ac19a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a8abe49e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a8abe49b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f48e9032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f48e90330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f48e90330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a8abe49a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c (1310 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vv_f32mf2(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vf_f32mf2(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vv_f32m1(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vf_f32m1(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vv_f32m2(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vf_f32m2(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vv_f32m4(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vf_f32m4(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64(<vscale x 8 x float> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwmul_vv_f32m8(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwmul.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwmul.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwmul_vf_f32m8(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %o
# | ...
# `---data was truncated (10240/76627) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ba9f8eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564ba9f8be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564ba9f8f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9b93449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9b934a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9b93449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9b93431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ba9f24bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564ba9f24a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564ba9f098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564ba9bb8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564ba9bb8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9b93432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9b934330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9b934330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ba9bb8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c (1311 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfdiv_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfdiv_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfdiv_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfdiv_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfdiv_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfdiv_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfdiv_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfdiv_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | ...
# `---data was truncated (10240/302389) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ccd9e75eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ccd9e72e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ccd9e7662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec1ae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec1aea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec1ae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec1ae31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ccd9e0bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ccd9e0ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ccd9df08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ccd9a9fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ccd9a9fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fec1ae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec1ae330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec1ae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ccd9a9fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c (1312 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f16m1x7(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f32m1x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f64m1x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ec3cd6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564ec3cd3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564ec3cd762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f15de533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f15de58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f15de533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f15de51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ec3c6cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564ec3c6ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564ec3c518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564ec3900e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564ec3900b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f15de51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15de51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15de51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ec3900a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c (1313 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfslide1up_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfslide1up_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfslide1up_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfslide1up_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfslide1up_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfslide1up_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfslide1up_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load float, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfslide1up_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load float, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfslide1up_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x
# | ...
# `---data was truncated (10240/78032) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562812b44eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562812b41e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562812b4562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f89f5e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f89f5ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f89f5e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f89f5e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562812adabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562812adaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562812abf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056281276ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056281276eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f89f5e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f89f5e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f89f5e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056281276ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c (1314 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willr
# | ...
# `---data was truncated (10240/44361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ad7c085eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ad7c082e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ad7c08662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f93adc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f93adca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f93adc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f93adc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad7c01bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ad7c01ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ad7c0008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ad7bcafe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ad7bcafb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f93adc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f93adc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f93adc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad7bcafa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c (1315 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlsseg2e8_v_i8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e8_v_i8mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e8_v_i8mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e8_v_i8m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e8_v_i8m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e8_v_i8m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlsseg2e8_v_u8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.
# | ...
# `---data was truncated (10240/72143) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e70ceaaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e70cea7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e70ceab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3e5e905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3e5e95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3e5e905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3e5e8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e70ce40bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e70ce40a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e70ce258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e70cad4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e70cad4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3e5e8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3e5e8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3e5e8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e70cad4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c (1316 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_x_f_w_bf16mf4_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_x_f_w_bf16mf2_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_x_f_w_bf16m1_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_x_f_w_bf16m2_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_x_f_w_bf16m4_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_x_f_w_bf16m8_i8m4_tu(<vscale x 32 x i8> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_xu_f_w_bf16mf4_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_xu_f_w_bf16mf2_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_xu_f_w_bf16m1_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_xu_f_w_bf16m2_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.v
# | ...
# `---data was truncated (10240/53192) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560f6851feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560f6851ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560f6852062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcb90b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcb90b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcb90b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcb90aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f684b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560f684b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560f6849a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560f68149e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560f68149b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcb90aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcb90aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcb90aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f68149a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c (1317 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556656d0beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556656d08e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556656d0c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e16f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e16f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e16f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e16f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556656ca1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556656ca1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556656c868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556656935e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556656935b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8e16f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e16f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e16f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556656935a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c (1318 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabdau_vv_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabdau_vx_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabdau_vv_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabdau_vx_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabdau_vv_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabdau_vx_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabdau_vv_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabdau_vx_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwabdau_vv_u16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   st
# | ...
# `---data was truncated (10240/110292) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f7b130eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f7b130be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f7b130f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f19b6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f19b6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f19b6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f19b6b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f7b12a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f7b12a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f7b12898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f7b0f38e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f7b0f38b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f19b6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f19b6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f19b6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f7b0f38a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c (1319 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_lane_bf16_idx1(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 1)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.lane.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_lane_bf16_idx3(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_lane_bf16_idx7(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 7)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16b16,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055957e87deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055957e87ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055957e87e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd081933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd08198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd081933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd08191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055957e813bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055957e813a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055957e7f88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055957e4a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055957e4a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd08191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd08191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd08191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055957e4a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c (1320 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1sb_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sb_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sb_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1sb_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sb_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sb_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1sb_vnum_s16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sb_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i8> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sb_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i8> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1sb_vnum_u16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sb_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x
# | ...
# `---data was truncated (10240/28299) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000555724e0deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555724e0ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555724e0e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f15a3449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f15a34a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f15a3449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f15a3431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555724da3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555724da3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555724d888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555724a37e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555724a37b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f15a3432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15a34330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15a34330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555724a37a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c (1321 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f16m1x6(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f32m1x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f64m1x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei32_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055944a461eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055944a45ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055944a46262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8f19f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8f19f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8f19f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8f19f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055944a3f7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055944a3f7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055944a3dc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055944a08be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055944a08bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8f19f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8f19f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8f19f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055944a08ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c (1322 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_i8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_i8mf2x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8_v_i8m1x8_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_u8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_u8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_u8mf2x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8_v_u8m1x8_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aef8f3aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aef8f37e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aef8f3b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1004333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f100438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1004333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f100431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aef8ed0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aef8ed0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aef8eb58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aef8b64e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aef8b64b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f100431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f100431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f100431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aef8b64a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c (1323 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vcompress_vm_f16mf4(<vscale x 1 x half> %src, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vcompress_vm_f16mf2(<vscale x 2 x half> %src, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vcompress_vm_f16m1(<vscale x 4 x half> %src, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vcompress_vm_f16m2(<vscale x 8 x half> %src, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vcompress_vm_f16m4(<vscale x 16 x half> %src, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vcompress_vm_f16m8(<vscale x 32 x half> %src, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vcompress_vm_f32mf2(<vscale x 1 x float> %src, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vcompress_vm_f32m1(<vscale x 2 x float> %src, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vcompress.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vcompress.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vcompress_vm_f32m2(<vscale x 4 x float> %src, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vcompress.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vcompress.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vcompress_vm_f32m4(<vscale x 8 x float> %src, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load <v
# | ...
# `---data was truncated (10240/62964) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f861e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559f861e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559f861e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ef9c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ef9ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ef9c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ef9c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f8617bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559f8617ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559f861608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559f85e0fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559f85e0fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4ef9c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ef9c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ef9c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f85e0fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c (1324 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_f16m1x2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_f16m2x2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_f32m1x2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_f32m2x2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei64_v_f32m4x2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8
# | ...
# `---data was truncated (10240/96911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563eebe07eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563eebe04e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563eebe0862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa5c4049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa5c40a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa5c4049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa5c4031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563eebd9dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563eebd9da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563eebd828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563eeba31e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563eeba31b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa5c4032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa5c40330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa5c40330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563eeba31a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/scatter-gather.c (1325 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/scatter-gather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_s16(ptr noundef %base, <8 x i16> noundef %offset) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <8 x i16>, align 8
# |   store ptr %base, ptr %base.addr, align 4
# |   store <8 x i16> %offset, ptr %offset.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x i16>, ptr %offset.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.v8i16.p0.v8i16(ptr %0, <8 x i16> %1, i32 8, i32 0, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <8 x i16> @llvm.arm.mve.vldr.gather.offset.v8i16.p0.v8i16(ptr, <8 x i16>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_s32(ptr noundef %base, <4 x i32> noundef %offset) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <4 x i32>, align 8
# |   store ptr %base, ptr %base.addr, align 4
# |   store <4 x i32> %offset, ptr %offset.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <4 x i32>, ptr %offset.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr %0, <4 x i32> %1, i32 8, i32 0, i32 0)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr, <4 x i32>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_gather_offset_s8(ptr noundef %base, <16 x i8> noundef %offset) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <16 x i8>, align 8
# |   store ptr %base, ptr %base.addr, align 4
# |   store <16 x i8> %offset, ptr %offset.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <16 x i8>, ptr %offset.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vldr.gather.offset.v16i8.p0.v16i8(ptr %0, <16 x i8> %1, i32 8, i32 0, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <16 x i8> @llvm.arm.mve.vldr.gather.offset.v16i8.p0.v16i8(ptr, <16 x i8>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_u16(ptr noundef %base, <8 x i16> noundef %offset) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <8 x i16>, align 8
# |   store ptr %base, ptr %base.addr, align 4
# |   store <8 x i16> %offset, ptr %offset.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x i16>, ptr %offset.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.v8i16.p0.v8i16(ptr %0, <8 x i16> %1, i32 8, i32 0, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_u32(ptr noundef %base, <4 x i32> noundef %offset) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <4 x i32>, align 8
# |   store ptr %base, ptr %base.addr, align 4
# |   store <4 x i32> %offset, ptr %offset.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <4 x i32>, ptr %offset.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr %0, <4 x i32> %1, i32 8, i32 0, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_gather_offset_u8(ptr noundef %base, <16 x i8> noundef %offset) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <16 x i8>, align 8
# |   store ptr %base, ptr %base.addr, align 4
# |   store <16 x i8> %offset, ptr %offset.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <16 x i8>, ptr %offset.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vldr.gather.offset.v16i8.p0.v16i8(ptr %0, <16 x i8> %1, i32 8, i32 0, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_z_s16(ptr noundef %base, <8 x i16> noundef %offset, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store <8 x i16> %offset, ptr %offset.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x i16>, ptr %offset.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.predicated.v8i16.p0.v8i16.v8i1(ptr %0, <8 x i16> %1, i32 8, i32 0, i32 0, <8 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <8 x i16> @llvm.arm.mve.vldr.gather.offset.predicated.v8i16.p0.v8i16.v8i1(ptr, <8 x i16>, i32, i32, i32, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_z_s32(ptr noundef %base, <4 x i32> noundef %offset, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store <4 x i32> %offset, ptr %offset.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <4 x i32>, ptr %offset.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0.v4i32.v4i1(ptr %0, <4 x i32> %1, i32 8, i32 0, i32 0, <4 x i1> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0.v4i32.v4i1(ptr, <4 x i32>, i32, i32, i32, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_gather_offset_z_s8(ptr noundef %base, <16 x i8> noundef %offset, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store <16 x i8> %offset, ptr %offset.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <16 x i8>, ptr %offset.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vldr.gather.offset.predicated.v16i8.p0.v16i8.v16i1(ptr %0, <16 x i8> %1, i32 8, i32 0, i32 0, <16 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <16 x i8> @llvm.arm.mve.vldr.gather.offset.predicated.v16i8.p0.v16i8.v16i1(ptr, <16 x i8>, i32, i32, i32, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_z_u16(ptr noundef %base, <8 x i16> noundef %offset, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store <8 x i16> %offset, ptr %offset.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x i16>, ptr %offset.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.predicated.v8i16.p0.v8i16.v8i1(ptr %0, <8 x i16> %1, i32 8, i32 0, i32 1, <8 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_z_u32(ptr noundef %base, <4 x i32> noundef %offset, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store <4 x i32> %offset, ptr %offset.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <4 x i32>, ptr %offset.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0.v4i32.v4i1(ptr %0, <4 x i32> %1, i32 8, i32 0, i32 1, <4 x i1> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_gather_offset_z_u8(ptr noundef %base, <16 x i8> noundef %offset, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store <16 x i8> %offset, ptr %offset.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <16 x i8>, ptr %offset.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vldr.gather.offset.predicated.v16i8.p0.v16i8.v16i1(ptr %0, <16 x i8> %1, i32 8, i32 0, i32 1, <16 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vf
# | ...
# `---data was truncated (10240/117019) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555f62a33eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555f62a30e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555f62a3462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3324933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f332498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3324933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f332491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f629c9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555f629c9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555f629ae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555f6265de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555f6265db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f332491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f332491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f332491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f6265da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/builtin-cpu-is.c (1326 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/builtin-cpu-is.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-unknown-linux-gnu -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c -o -    | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c --check-prefix=CHECK-RV64
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-unknown-linux-gnu -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64-unknown-linux-gnu"
# | 
# | @__riscv_cpu_model = external dso_local global { i32, i64, i64 }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @test_cpu_is_spacemit_x60() #0 {
# | entry:
# |   %0 = load i32, ptr @__riscv_cpu_model, align 4
# |   %1 = icmp eq i32 %0, 1808
# |   %2 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 8), align 8
# |   %3 = icmp eq i64 %2, -9223372035378380799
# |   %4 = and i1 %1, %3
# |   %5 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 16), align 8
# |   %6 = icmp eq i64 %5, 1152921505839391232
# |   %7 = and i1 %4, %6
# |   %conv = zext i1 %7 to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @test_cpu_is_sifive_p550() #0 {
# | entry:
# |   %0 = load i32, ptr @__riscv_cpu_model, align 4
# |   %1 = icmp eq i32 %0, 1161
# |   %2 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 8), align 8
# |   %3 = icmp eq i64 %2, -9223372036854775800
# |   %4 = and i1 %1, %3
# |   %5 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 16), align 8
# |   %6 = icmp eq i64 %5, 102892581
# |   %7 = and i1 %4, %6
# |   %conv = zext i1 %7 to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @test_cpu_is_sifive_p870_d() #0 {
# | entry:
# |   %0 = load i32, ptr @__riscv_cpu_model, align 4
# |   %1 = icmp eq i32 %0, 1161
# |   %2 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 8), align 8
# |   %3 = icmp eq i64 %2, -9223372036854775543
# |   %4 = and i1 %1, %3
# |   %5 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 16), align 8
# |   %6 = icmp eq i64 %5, 337970694
# |   %7 = and i1 %4, %6
# |   %conv = zext i1 %7 to i32
# |   ret i32 %conv
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i" }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005613ba93deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005613ba93ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005613ba93e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7364449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f73644a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7364449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7364431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005613ba8d3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005613ba8d3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005613ba8b88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005613ba567e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005613ba567b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7364432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73644330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73644330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005613ba567a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c --check-prefix=CHECK-RV64
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c --check-prefix=CHECK-RV64
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c (1327 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei8_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8
# | ...
# `---data was truncated (10240/160141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005604bbeeeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005604bbeebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005604bbeef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1436449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f14364a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1436449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1436431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005604bbe84bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005604bbe84a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005604bbe698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005604bbb18e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005604bbb18b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1436432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f14364330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f14364330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005604bbb18a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c (1328 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1ub_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1ub_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1ub_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1ub_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1ub_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1ub_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1ub_vnum_s16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1ub_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i8> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1ub_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i8> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1ub_vnum_u16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1ub_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x
# | ...
# `---data was truncated (10240/11944) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c7c04efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c7c04ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c7c04f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f84e5649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f84e56a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f84e5649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f84e5631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c7c0485bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c7c0485a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c7c046a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c7c0119e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c7c0119b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f84e5632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f84e56330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f84e56330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c7c0119a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c (1329 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_i32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_i32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_u32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_u32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_f32mf2x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple,
# | ...
# `---data was truncated (10240/40726) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562bb4ef8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562bb4ef5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562bb4ef962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdb99133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdb9918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdb99133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdb9911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562bb4e8ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562bb4e8ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562bb4e738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562bb4b22e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562bb4b22b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdb9911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdb9911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdb9911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562bb4b22a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c (1330 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf8x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_u8mf8x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_u8mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_u8mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_u8m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, pt
# | ...
# `---data was truncated (10240/18980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563f3560ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563f35609e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563f3560d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe591333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe59138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe591333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe59131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563f355a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563f355a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563f355878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563f35236e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563f35236b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe59131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe59131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe59131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563f35236a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c (1331 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhsu_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhsu_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmulhsu_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, a
# | ...
# `---data was truncated (10240/98437) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056546c080eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056546c07de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056546c08162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb8ed533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb8ed58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb8ed533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb8ed51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056546c016bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056546c016a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056546bffb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056546bcaae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056546bcaab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb8ed51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb8ed51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb8ed51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056546bcaaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c (1332 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_x_f_w_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_x_f_w_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_x_f_w_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_x_f_w_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_x_f_w_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_x_f_w_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_xu_f_w_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_xu_f_w_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_xu_f_w_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_xu_f_w_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   
# | ...
# `---data was truncated (10240/135119) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056156ba56eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056156ba53e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056156ba5762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1aaf449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1aaf4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1aaf449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1aaf431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056156b9ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056156b9eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056156b9d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056156b680e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056156b680b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1aaf432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1aaf4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1aaf4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056156b680a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c (1333 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaeskf2_vi_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaeskf2.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaeskf2.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaeskf2_vi_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaeskf2.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaeskf2.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaeskf2_vi_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaeskf2_vi_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaeskf2.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaeskf2.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaeskf2_vi_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaeskf2.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaeskf2.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d6c2ed7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d6c2ed4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d6c2ed862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faa3921bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faa392725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faa3921ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faa39203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d6c2e6dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d6c2e6da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d6c2e528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d6c2b01e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d6c2b01b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faa39204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faa392050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faa392050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d6c2b01a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c (1334 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bb2027beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bb20278e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bb2027c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe56a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe56a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe56a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe56a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bb20211bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bb20211a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bb201f68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bb1fea5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bb1fea5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe56a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe56a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe56a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bb1fea5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c (1335 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f16m1x7(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f32m1x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f64m1x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d37ba46eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d37ba43e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d37ba4762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff1b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff1b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff1b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff1b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d37b9dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d37b9dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d37b9c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d37b670e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d37b670b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007eff1b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff1b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff1b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d37b670a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c (1336 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560dad15feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560dad15ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560dad16062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd00333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd0038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd00333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd0031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560dad0f5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560dad0f5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560dad0da8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560dacd89e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560dacd89b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbd0031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd0031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd0031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560dacd89a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c (1337 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_i16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_i16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_i16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_lo
# | ...
# `---data was truncated (10240/70863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055879f5aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055879f5a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055879f5ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc248649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc2486a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc248649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc248631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055879f540bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055879f540a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055879f5258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055879f1d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055879f1d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc248632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc2486330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc2486330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055879f1d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c (1338 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte8_i8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte8.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vlte8.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte8_u8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte8.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005561de685eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005561de682e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005561de68662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe204b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe204b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe204b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe204b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005561de61bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005561de61ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005561de6008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005561de2afe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005561de2afb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe204b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe204b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe204b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005561de2afa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c (1339 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_f64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_f64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_i64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_i64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_u64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_u64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_f64m1x3_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local t
# | ...
# `---data was truncated (10240/36031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560727a77eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560727a74e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560727a7862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f256ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f256ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f256ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f256ad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560727a0dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560727a0da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005607279f28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005607276a1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005607276a1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f256ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f256ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f256ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607276a1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c (1340 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsmul_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsmul_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsmul_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsmul_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsmul_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsmul_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsmul_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsmul_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsmul_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsmul_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsmul_vv_i8
# | ...
# `---data was truncated (10240/99577) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ae6a97eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ae6a97be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ae6a97f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe781849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe7818a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe781849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe781831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ae6a914bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ae6a914a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ae6a8f98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ae6a5a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ae6a5a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe781832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe7818330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe7818330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ae6a5a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c (1341 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_i16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_i16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_i16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_u16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, ali
# | ...
# `---data was truncated (10240/60543) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d734543eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d734540e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d73454462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc6a641bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc6a64725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc6a641ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc6a6403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d7344d9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d7344d9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d7344be8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d73416de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d73416db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc6a6404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc6a64050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc6a64050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d73416da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c (1342 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i16> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i
# | ...
# `---data was truncated (10240/15699) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562bb6a3eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562bb6a3be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562bb6a3f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7456649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f74566a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7456649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7456631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562bb69d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562bb69d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562bb69b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562bb6668e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562bb6668b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7456632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f74566330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f74566330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562bb6668a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c (1343 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vle.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vle.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vle.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vle.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vle.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vle.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vle.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vle.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vle.nxv16bf16.p0.i64(<vscale x 16 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vle.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vle.nxv32bf16.p0.i64(<vscale x 32 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vle.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16_v_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.
# | ...
# `---data was truncated (10240/24951) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055614db6eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055614db6be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055614db6f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1133933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f113398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1133933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f113391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055614db04bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055614db04a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055614dae98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055614d798e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055614d798b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f113391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f113391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f113391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055614d798a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c (1344 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte32_f32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vlte32.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte32_i32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte32_u32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d21f090eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d21f08de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d21f09162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c0af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c0af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c0af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c0af1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d21f026bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d21f026a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d21f00b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d21ecbae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d21ecbab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1c0af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c0af1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c0af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d21ecbaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c (1345 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f16m1x2(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f16m2x2(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f32m1x2(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f32m2x2(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f32m4x2(ptr noundef %base, <vscale x 8 x i64
# | ...
# `---data was truncated (10240/110129) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055802b74deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055802b74ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055802b74e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd216705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd21675c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd216705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd2166ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055802b6e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055802b6e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055802b6c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055802b377e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055802b377b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd2166eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd2166ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd2166ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055802b377a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c (1346 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei32_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei32_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei32_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei32_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei32_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei32_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei32_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei32_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei32_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, <vscale x 8 
# | ...
# `---data was truncated (10240/255538) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ea984beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557ea9848e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557ea984c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5188249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f51882a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5188249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5188231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ea97e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557ea97e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557ea97c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557ea9475e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557ea9475b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5188232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51882330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51882330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ea9475a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c (1347 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei32_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, ali
# | ...
# `---data was truncated (10240/14621) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565310f1ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565310f19e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000565310f1d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e3cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e3cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e3cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e3cf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565310eb2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565310eb2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000565310e978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565310b46e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565310b46b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7e3cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e3cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e3cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565310b46a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c (1348 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_f32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_f32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_i32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_i32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_u32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_u32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vsca
# | ...
# `---data was truncated (10240/15944) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005577e9aaaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005577e9aa7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005577e9aab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f09e3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f09e3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f09e3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f09e3f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005577e9a40bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005577e9a40a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005577e9a258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005577e96d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005577e96d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f09e3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f09e3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f09e3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005577e96d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c (1349 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561698864eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561698861e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056169886562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f66d2533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f66d258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f66d2533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f66d251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005616987fabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005616987faa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005616987df8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056169848ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056169848eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f66d251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f66d251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f66d251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056169848ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c (1350 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsaddu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsaddu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsaddu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsaddu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsaddu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsaddu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsaddu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsaddu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsaddu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   s
# | ...
# `---data was truncated (10240/223359) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cbe0b1ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cbe0b19e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cbe0b1d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f848de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f848dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f848de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f848de31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cbe0ab2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cbe0ab2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cbe0a978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cbe0746e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cbe0746b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f848de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f848de330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f848de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cbe0746a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c (1351 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vsc
# | ...
# `---data was truncated (10240/11789) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c43b754eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c43b751e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c43b75562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff61449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff614a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff61449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff61431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c43b6eabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c43b6eaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c43b6cf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c43b37ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c43b37eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007eff61432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff614330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff614330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c43b37ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c (1352 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e053062eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e05305fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e05306362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f11da333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f11da38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f11da333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f11da31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e052ff8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e052ff8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e052fdd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e052c8ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e052c8cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f11da31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f11da31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f11da31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e052c8ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c (1353 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjx_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjx_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjx_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjx_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjx_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjx_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjx_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjx_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2,
# | ...
# `---data was truncated (10240/65194) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564a78a01eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564a789fee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564a78a0262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2824b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2824b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2824b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2824aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564a78997bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564a78997a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564a7897c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564a7862be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564a7862bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2824aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2824aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2824aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564a7862ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c (1354 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabs_v_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabs_v_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabs_v_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabs_v_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabs_v_u8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vabs_v_u8m4_tu(<vscale x 32 x i8> %vd, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vabs_v_u8m8_tu(<vscale x 64 x i8> %vd, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vabs_v_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vabs_v_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vabs_v_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vabs_v_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, al
# | ...
# `---data was truncated (10240/92370) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a932d60eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a932d5de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a932d6162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa6a3b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa6a3b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa6a3b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa6a3b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a932cf6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a932cf6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a932cdb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a93298ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a93298ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa6a3b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa6a3b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa6a3b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a93298aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c (1355 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste8_i8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste8.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.sf.vste8.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste8_u8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste8.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb126b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fb126b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fb126b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe23d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe23d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe23d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe23d71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb1264dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fb1264da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fb126328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fb122e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fb122e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe23d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe23d71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe23d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb122e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c (1356 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmseq_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmseq_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmseq_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmseq_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmseq_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmseq_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmseq_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmseq_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmseq_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmseq_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmseq_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8.nxv32i8.i64(<vscale x 32 x 
# | ...
# `---data was truncated (10240/171389) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559bb57dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559bb57dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559bb57e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f638da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f638daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f638da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f638da31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559bb5775bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559bb5775a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559bb575a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559bb5409e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559bb5409b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f638da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f638da330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f638da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559bb5409a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c (1357 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslidedown_vx_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslidedown_vx_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vslidedown_vx_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vslidedown_vx_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.
# | ...
# `---data was truncated (10240/30759) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c87ca6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562c87ca3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562c87ca762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f42e7a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42e7aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f42e7a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f42e7a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c87c3cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562c87c3ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562c87c218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562c878d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562c878d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f42e7a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42e7a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42e7a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c878d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c (1358 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f16m1x8(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f32m1x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f64m1x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i64> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557883016eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557883013e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055788301762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3a4b41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3a4b4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3a4b41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3a4b403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557882facbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557882faca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557882f918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557882c40e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557882c40b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3a4b404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3a4b4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3a4b4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557882c40a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c (1359 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   st
# | ...
# `---data was truncated (10240/11797) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005643de1fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005643de1f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005643de1fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa2d5733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa2d578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa2d5733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa2d571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005643de192bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005643de192a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005643de1778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005643dde26e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005643dde26b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa2d571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa2d571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa2d571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005643dde26a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c (1360 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dotsu_vv_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dotsu_vv_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dotsu_vv_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dotsu_vv_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dotsu_vv_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dotsu_vv_i64m1_tu(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dotsu_vv_i64m2_tu(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dotsu_vv_i64m4_tu(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotsu.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv
# | ...
# `---data was truncated (10240/47720) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bc32daeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bc32dabe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bc32daf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1df8049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1df80a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1df8049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1df8031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bc32d44bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bc32d44a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bc32d298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bc329d8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bc329d8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1df8032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1df80330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1df80330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bc329d8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c (1361 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055df3fffbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055df3fff8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055df3fffc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f48849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f488a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f48849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f48831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055df3ff91bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055df3ff91a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055df3ff768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055df3fc25e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055df3fc25b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1f48832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f488330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f488330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055df3fc25a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c (1362 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_u_u_w4_u8m8_u8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.u.u.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.u.u.i64.nxv64i8.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f35d061eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f35d05ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f35d06262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f13e3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13e3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f13e3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f13e3f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f35cff7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f35cff7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f35cfdc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f35cc8be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f35cc8bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f13e3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13e3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13e3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f35cc8ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c (1363 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16mf4x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16mf2x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16m1x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16m2x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("risc
# | ...
# `---data was truncated (10240/11912) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ede0495eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ede0492e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ede049662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb57ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb57ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb57ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb57ad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ede042bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ede042ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ede04108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ede00bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ede00bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb57ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb57ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb57ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ede00bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c (1364 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056109d5c7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056109d5c4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056109d5c862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5140305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f514035c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5140305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f51402ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056109d55dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056109d55da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056109d5428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056109d1f1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056109d1f1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f51402eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51402ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51402ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056109d1f1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c (1365 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8ff_v_i8mf8x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8ff_v_i8mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8ff_v_i8mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8ff_v_i8m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8ff_v_i8m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8ff_v_u8mf8x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8ff_v_u8mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8ff_v_u8mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vec
# | ...
# `---data was truncated (10240/27595) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562d1cf23eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562d1cf20e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562d1cf2462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc591449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5914a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc591449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc591431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d1ceb9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562d1ceb9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562d1ce9e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562d1cb4de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562d1cb4db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc591432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5914330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5914330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d1cb4da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c (1366 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m4_bf16m8(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x i8> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x i8> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 
# | ...
# `---data was truncated (10240/24206) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bb1aa74eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bb1aa71e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bb1aa7562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2015a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2015aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2015a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2015a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bb1aa0abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bb1aa0aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bb1a9ef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bb1a69ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bb1a69eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2015a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2015a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2015a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bb1a69ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c (1367 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclipu_wv_u8mf8(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclipu_wx_u8mf8(<vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclipu_wv_u8mf4(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclipu_wx_u8mf4(<vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclipu_wv_u8mf2(<vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclipu_wx_u8mf2(<vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclipu_wv_u8m1(<vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclipu_wx_u8m1(<vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclipu_wv_u8m2(<vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclipu_wx_u8m2(<vscale x 16 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale
# | ...
# `---data was truncated (10240/70021) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005564bc4a9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005564bc4a6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005564bc4aa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1de8b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1de8b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1de8b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1de8b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005564bc43fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005564bc43fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005564bc4248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005564bc0d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005564bc0d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1de8b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1de8b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1de8b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005564bc0d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c (1368 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsne_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsne_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsne_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsne_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsne_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsne_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsne_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i
# | ...
# `---data was truncated (10240/116267) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056428d0eceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056428d0e9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056428d0ed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb23e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb23ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb23e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb23e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056428d082bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056428d082a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056428d0678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056428cd16e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056428cd16b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feb23e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb23e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb23e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056428cd16a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c (1369 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_2x8x2_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_2x8x2_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_2x8x2_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_2x8x2_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005652fd4b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005652fd4b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005652fd4b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb2acb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb2acb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb2acb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb2acb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005652fd449bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005652fd449a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005652fd42e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005652fd0dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005652fd0ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb2acb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb2acb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb2acb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005652fd0dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c (1370 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2ch_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2ch_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2ch_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2ch_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2ch_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2ch_vv_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2ch_vv_u64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2ch_vv_u64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define d
# | ...
# `---data was truncated (10240/12208) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559a42f42eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559a42f3fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559a42f4362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f19af249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f19af2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f19af249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f19af231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a42ed8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559a42ed8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559a42ebd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559a42b6ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559a42b6cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f19af232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f19af2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f19af2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a42b6ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c (1371 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f16m1x4(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f16m2x4(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f32m1x4(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f32m2x4(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f64m1x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tu
# | ...
# `---data was truncated (10240/99186) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055910bd9ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055910bd99e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055910bd9d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f808b41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f808b4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f808b41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f808b403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055910bd32bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055910bd32a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055910bd178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055910b9c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055910b9c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f808b404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f808b4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f808b4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055910b9c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmulhq.c (1372 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmulhq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulhq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vmulh.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vmulh.v16i8(<16 x i8>, <16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulhq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vmulh.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vmulh.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulhq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vmulh.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vmulh.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulhq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.mulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.mulh.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulhq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.mulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.mulh.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulhq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.mulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.mulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulhq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.mulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulhq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.mulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulhq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.mulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555f0493eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555f0493be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555f0493f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f177f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f177f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f177f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f177f91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f048d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555f048d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555f048b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555f04568e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555f04568b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f177f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f177f91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f177f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f04568a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c (1373 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_i16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_i16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_i16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local targ
# | ...
# `---data was truncated (10240/70855) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005619030b0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005619030ade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005619030b162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c4a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c4a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c4a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c4a91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561903046bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561903046a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056190302b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561902cdae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561902cdab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1c4a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c4a91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c4a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561902cdaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c (1374 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055af81d38eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055af81d35e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055af81d3962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc6cec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc6ceca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc6cec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc6cec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055af81ccebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055af81ccea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055af81cb38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055af81962e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055af81962b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc6cec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc6cec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc6cec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055af81962a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c (1375 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmul_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmul_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmul_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmul_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmul_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmul_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmul_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmul_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmul_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmul_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmul_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/175155) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005569dd587eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005569dd584e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005569dd58862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9436e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9436ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9436e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9436e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005569dd51dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005569dd51da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005569dd5028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005569dd1b1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005569dd1b1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9436e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9436e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9436e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005569dd1b1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c (1376 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vxor_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vxor_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vxor_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vxor_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vxor_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vxor_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vxor_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vxor_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vxor_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vxor_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vxor_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/175163) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005627c029beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005627c0298e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005627c029c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc85dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc85dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc85dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc85dd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005627c0231bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005627c0231a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005627c02168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005627bfec5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005627bfec5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc85dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc85dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc85dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005627bfec5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c (1377 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vzip_vv_bf16m4(<vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vzip_vv_bf16m8(<vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vzip_vv_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale 
# | ...
# `---data was truncated (10240/13048) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ff83571eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ff8356ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ff8357262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4a0ba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4a0baa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4a0ba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4a0ba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ff83507bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ff83507a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ff834ec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ff8319be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ff8319bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4a0ba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4a0ba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4a0ba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ff8319ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c (1378 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_f64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_f64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_f64m4x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_i64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_i64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_i64m4x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_u64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_u64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_u64m4x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_
# | ...
# `---data was truncated (10240/10440) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562030922eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056203091fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056203092362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f95b2c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f95b2ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f95b2c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f95b2c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005620308b8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005620308b8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056203089d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056203054ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056203054cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f95b2c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f95b2c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f95b2c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056203054ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c (1379 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmv_v_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmv_v_x_i8mf8_tu(<vscale x 1 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmv_v_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmv_v_x_i8mf4_tu(<vscale x 2 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmv_v_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmv_v_x_i8mf2_tu(<vscale x 4 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmv_v_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmv_v_x_i8m1_tu(<vscale x 8 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmv_v_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmv_v_x_i8m2_tu(<vscale x 16 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmv_v_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = l
# | ...
# `---data was truncated (10240/134736) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c3b34afeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c3b34ace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c3b34b062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff2a4a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff2a4aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff2a4a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff2a4a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c3b3445bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c3b3445a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c3b342a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c3b30d9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c3b30d9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff2a4a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff2a4a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff2a4a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c3b30d9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c (1380 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f16m1x4(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f16m2x4(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f32m1x4(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f32m2x4(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f64m1x4(ptr noundef %base, <vscale x 1 x i32
# | ...
# `---data was truncated (10240/99762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c180bdeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c180bdbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c180bdf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbf6d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbf6d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbf6d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbf6d031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c180b74bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c180b74a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c180b598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c180808e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c180808b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbf6d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbf6d0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbf6d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c180808a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c (1381 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_f64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_i64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_u64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559092fc4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559092fc1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559092fc562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1adb61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1adb6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1adb61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1adb603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559092f5abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559092f5aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559092f3f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559092beee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559092beeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1adb604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1adb6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1adb6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559092beea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c (1382 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmul_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmul_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmul_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmul_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmul_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmul_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmul_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmul_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfm
# | ...
# `---data was truncated (10240/65574) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056543ec76eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056543ec73e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056543ec7762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f55a9733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f55a978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f55a9733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f55a971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056543ec0cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056543ec0ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056543ebf18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056543e8a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056543e8a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f55a971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f55a971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f55a971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056543e8a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c (1383 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16mf4x7(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16mf2x7(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16m1x7(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005650c3224eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005650c3221e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005650c322562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fed78b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fed78b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fed78b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fed78b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005650c31babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005650c31baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005650c319f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005650c2e4ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005650c2e4eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fed78b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fed78b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fed78b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005650c2e4ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c (1384 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svlsl_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svlsl_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svlsl_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svlsl_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svlsl_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svlsl_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svlsl_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svlsl_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svlsl_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, pt
# | ...
# `---data was truncated (10240/53158) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000564f85f05eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564f85f02e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564f85f0662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb633249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb6332a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb633249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb633231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f85e9bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564f85e9ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564f85e808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564f85b2fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564f85b2fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb633232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb6332330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb6332330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f85b2fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c (1385 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf8_i64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf8_i64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf8_i64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf8_i64m2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i64> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf8_i64m4_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i64> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf8_i64m8_tum(<vscale x 8 x i1> %mask, <vscale x 8 x i64> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1_tumu(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64>
# | ...
# `---data was truncated (10240/18217) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556b2f495eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556b2f492e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556b2f49662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5f5f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5f5f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5f5f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5f5f51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b2f42bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556b2f42ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556b2f4108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556b2f0bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556b2f0bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5f5f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5f5f51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5f5f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b2f0bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c (1386 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f16m1x7(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f32m1x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f64m1x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i32> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005582919a1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055829199ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005582919a262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa84f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa84f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa84f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa84f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558291937bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558291937a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055829191c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005582915cbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005582915cbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa84f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa84f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa84f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005582915cba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/poly64.c (1387 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/poly64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -flax-vector-conversions=none  -ffp-contract=fast -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa   | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -flax-vector-conversions=none -ffp-contract=fast -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vceq_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %ref.tmp.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   %3 = load <1 x i64>, ptr %__p1.addr.i, align 8
# |   %cmp.i = icmp eq <1 x i64> %2, %3
# |   %sext.i = sext <1 x i1> %cmp.i to <1 x i64>
# |   store <1 x i64> %sext.i, ptr %ref.tmp.i, align 8
# |   %4 = load <1 x i64>, ptr %ref.tmp.i, align 8
# |   store <1 x i64> %4, ptr %__ret.i, align 8
# |   %5 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vceqq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__p1.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %ref.tmp.i = alloca <2 x i64>, align 16
# |   %a.addr = alloca <2 x i64>, align 16
# |   %b.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %3 = load <2 x i64>, ptr %__p1.addr.i, align 16
# |   %cmp.i = icmp eq <2 x i64> %2, %3
# |   %sext.i = sext <2 x i1> %cmp.i to <2 x i64>
# |   store <2 x i64> %sext.i, ptr %ref.tmp.i, align 16
# |   %4 = load <2 x i64>, ptr %ref.tmp.i, align 16
# |   store <2 x i64> %4, ptr %__ret.i, align 16
# |   %5 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vtst_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = bitcast <8 x i8> %2 to <1 x i64>
# |   %5 = bitcast <8 x i8> %3 to <1 x i64>
# |   %6 = and <1 x i64> %4, %5
# |   %7 = icmp ne <1 x i64> %6, zeroinitializer
# |   %vtst.i = sext <1 x i1> %7 to <1 x i64>
# |   store <1 x i64> %vtst.i, ptr %ref.tmp.i, align 8
# |   %8 = load <1 x i64>, ptr %ref.tmp.i, align 8
# |   store <1 x i64> %8, ptr %__ret.i, align 8
# |   %9 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vtstq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__p1.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x i64>, align 16
# |   %b.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %4 = bitcast <16 x i8> %2 to <2 x i64>
# |   %5 = bitcast <16 x i8> %3 to <2 x i64>
# |   %6 = and <2 x i64> %4, %5
# |   %7 = icmp ne <2 x i64> %6, zeroinitializer
# |   %vtst.i = sext <2 x i1> %7 to <2 x i64>
# |   store <2 x i64> %vtst.i, ptr %ref.tmp.i, align 16
# |   %8 = load <2 x i64>, ptr %ref.tmp.i, align 16
# |   store <2 x i64> %8, ptr %__ret.i, align 16
# |   %9 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vcopy_lane_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <1 x i64>, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   %__ret_913 = alloca <1 x i64>, align 8
# |   %__s0_913 = alloca <1 x i64>, align 8
# |   %__s2_913 = alloca <1 x i64>, align 8
# |   %__ret = alloca <1 x i64>, align 8
# |   %__s0 = alloca i64, align 8
# |   %__ret1 = alloca i64, align 8
# |   %__s02 = alloca <1 x i64>, align 8
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   %__s1 = alloca <1 x i64>, align 8
# |   %ref.tmp3 = alloca <1 x i64>, align 8
# |   %tmp4 = alloca <1 x i64>, align 8
# |   %tmp5 = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   store <1 x i64> %0, ptr %__s0_913, align 8
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %1, ptr %__s2_913, align 8
# |   %2 = load <1 x i64>, ptr %__s2_913, align 8
# |   store <1 x i64> %2, ptr %__s02, align 8
# |   %3 = load <1 x i64>, ptr %__s02, align 8
# |   %vget_lane = extractelement <1 x i64> %3, i32 0
# |   store i64 %vget_lane, ptr %ref.tmp, align 8
# |   %4 = load i64, ptr %ref.tmp, align 8
# |   store i64 %4, ptr %__ret1, align 8
# |   %5 = load i64, ptr %__ret1, align 8
# |   store i64 %5, ptr %tmp, align 8
# |   %6 = load i64, ptr %tmp, align 8
# |   store i64 %6, ptr %__s0, align 8
# |   %7 = load <1 x i64>, ptr %__s0_913, align 8
# |   store <1 x i64> %7, ptr %__s1, align 8
# |   %8 = load i64, ptr %__s0, align 8
# |   %9 = load <1 x i64>, ptr %__s1, align 8
# |   %vset_lane = insertelement <1 x i64> %9, i64 %8, i32 0
# |   store <1 x i64> %vset_lane, ptr %ref.tmp3, align 8
# |   %10 = load <1 x i64>, ptr %ref.tmp3, align 8
# |   store <1 x i64> %10, ptr %__ret, align 8
# |   %11 = load <1 x i64>, ptr %__ret, align 8
# |   store <1 x i64> %11, ptr %tmp4, align 8
# |   %12 = load <1 x i64>, ptr %tmp4, align 8
# |   store <1 x i64> %12, ptr %__ret_913, align 8
# |   %13 = load <1 x i64>, ptr %__ret_913, align 8
# |   store <1 x i64> %13, ptr %tmp5, align 8
# |   %14 = load <1 x i64>, ptr %tmp5, align 8
# |   ret <1 x i64> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vcopyq_lane_p64(<2 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   %b.addr = alloca <1 x i64>, align 8
# |   %__ret_909 = alloca <2 x i64>, align 16
# |   %__s0_909 = alloca <2 x i64>, align 16
# |   %__s2_909 = alloca <1 x i64>, align 8
# |   %__ret = alloca <2 x i64>, align 16
# |   %__s0 = alloca i64, align 8
# |   %__ret1 = alloca i64, align 8
# |   %__s02 = alloca <1 x i64>, align 8
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   %__s1 = alloca <2 x i64>, align 16
# |   %ref.tmp3 = alloca <2 x i64>, align 16
# |   %tmp4 = alloca <2 x i64>, align 16
# |   %tmp5 = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__s0_909, align 16
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %1, ptr %__s2_909, align 8
# |   %2 = load <1 x i64>, ptr %__s2_909, align 8
# |   store <1 x i64> %2, ptr %__s02, align 8
# |   %3 = load <1 x i64>, ptr %__s02, align 8
# |   %vget_lane = extractelement <1 x i64> %3, i32 0
# |   store i64 %vget_lane, ptr %ref.tmp, align 8
# |   %4 = load i64, ptr %ref.tmp, align 8
# |   store i64 %4, ptr %__ret1, align 8
# |   %5 = load i64, ptr %__ret1, align 8
# |   store i64 %5, ptr %tmp, align 8
# |   %6 = load i64, ptr %tmp, align 8
# |   store i64 %6, ptr %__s0, align 8
# |   %7 = load <2 x i64>, ptr %__s0_909, align 16
# |   store <2 x i64> %7, ptr %__s1, align 16
# |   %8 = load i64, ptr %__s0, align 8
# |   %9 = load <2 x i64>, ptr %__s1, align 16
# |   %vset_lane = insertelement <2 x i64> %9, i64 %8, i32 1
# |   store <2 x i64> %vset_lane, ptr %ref.tmp3, align 16
# |   %10 = load <2 x i64>, ptr %ref.tmp3, align 16
# |   store <2 x i64> %10, ptr %__ret, align 16
# |   %11 = load <2 x i64>, ptr %__ret, align 16
# |   store <2 x i64> %11, ptr %tmp4, align 16
# |   %12 = load <2 x i64>, ptr %tmp4, align 16
# |   store <2 x i64> %12, ptr %__ret_909, align 16
# |   %13 = load <2 x i64>, ptr %__ret_909, align 16
# |   store <2 x i64> %13, ptr %tmp5, align 16
# |   %14 = load <2 x i64>, ptr %tmp5, align 16
# |   ret <2 x i64> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vcopyq_laneq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   %b.addr = alloca <2 x i64>, align 16
# |   %__ret_915 = alloca <2 x i64>, align 16
# |   %__s0_915 = alloca <2 x i64>, align 16
# |   %__s2_915 = alloca <2 x i64>, align 16
# |   %__ret = alloca <2 x i64>, align 16
# |   %__s0 = alloca i64, align 8
# |   %__ret1 = alloca i64, align 8
# |   %__s02 = alloca <2 x i64>, align 16
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   %__s1 = alloca <2 x i64>, align 16
# |   %ref.tmp3 = alloca <2 x i64>, align 16
# |   %tmp4 = alloca <2 x i64>, align 16
# |   %tmp5 = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__s0_915, align 16
# |   %1 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %1, ptr %__s2_915, align 16
# |   %2 = load <2 x i64>, ptr %__s2_915, align 16
# |   store <2 x i64> %2, ptr %__s02, align 16
# |   %3 = load <2 x i64>, ptr %__s02, align 16
# |   %vgetq_lane = extractelement <2 x i64> %3, i32 1
# |   store i64 %vgetq_lane, ptr %ref.tmp, align 8
# |   %4 = load i64, ptr %ref.tmp, align 8
# |   store i64 %4, ptr %__ret1, align 8
# |   %5 = 
# | ...
# `---data was truncated (10240/22456) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055bf303bfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bf303bce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bf303c062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3eb4b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3eb4b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3eb4b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3eb4b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bf30355bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bf30355a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bf3033a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bf2ffe9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bf2ffe9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3eb4b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3eb4b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3eb4b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bf2ffe9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c (1388 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_vv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_wv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_wx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_vv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_wv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_wx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwadd_vv_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i
# | ...
# `---data was truncated (10240/306017) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560683a08eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560683a05e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560683a0962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f54add33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54add8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f54add33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f54add1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056068399ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056068399ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005606839838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560683632e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560683632b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f54add1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54add1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54add1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560683632a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c (1389 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_v
# | ...
# `---data was truncated (10240/216258) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d154969eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d154966e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d15496a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8184933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f818498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8184933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f818491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d1548ffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d1548ffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d1548e48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d154593e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d154593b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f818491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f818491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f818491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d154593a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c (1390 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmax_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmax_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmax_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmax_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmax_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmax_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmax_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmax_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmax_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmax_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmax_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/97647) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055781638feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055781638ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055781639062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa2e0e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa2e0ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa2e0e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa2e0e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557816325bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557816325a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055781630a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557815fb9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557815fb9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa2e0e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa2e0e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa2e0e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557815fb9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c (1391 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f16m1x7(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f32m1x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f64m1x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c0d645deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c0d645ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c0d645e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0113449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f01134a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0113449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0113431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c0d63f3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c0d63f3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c0d63d88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c0d6087e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c0d6087b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0113432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f01134330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f01134330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c0d6087a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c (1392 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrsub_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrsub_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrsub_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrsub_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrsub_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vrsub_vx_i8m4(<vscale x 32 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vrsub_vx_i8m8(<vscale x 64 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vrsub_vx_i16mf4(<vscale x 1 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vrsub_vx_i16mf2(<vscale x 2 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vrsub_vx_i16m1(<vscale x 4 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vrsub_vx_i16m2(<vscale x 8 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vrsub
# | ...
# `---data was truncated (10240/84979) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559077212eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055907720fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055907721362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f930e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f930e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f930e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f930e031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005590771a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005590771a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055907718d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559076e3ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559076e3cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f930e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f930e0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f930e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559076e3ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c (1393 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsbf_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsbf_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsbf_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsbf_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbf_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbf_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbf_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsbf_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1> poison, <vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsbf_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1> poison, <vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsbf_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1> poison, <vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsbf_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1> poison, <vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbf_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1.i64(<vscale x 4 x i1> poison, <vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback n
# | ...
# `---data was truncated (10240/13031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558473ed6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558473ed3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558473ed762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f7b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f7b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f7b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f7b831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558473e6cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558473e6ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558473e518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558473b00e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558473b00b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4f7b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f7b8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f7b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558473b00a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c (1394 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055917ee9deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055917ee9ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055917ee9e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7086049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f70860a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7086049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7086031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055917ee33bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055917ee33a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055917ee188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055917eac7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055917eac7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7086032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f70860330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f70860330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055917eac7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-vls-arith-ops.c (1395 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-arith-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d  -target-feature +f -target-feature +d -disable-O0-optnone  -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c |  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @add_i8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %add = add <32 x i8> %0, %1
# |   store <32 x i8> %add, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8>, <32 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @add_i16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %add = add <16 x i16> %0, %1
# |   store <16 x i16> %add, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16>, <16 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @add_i32(<vscale x 2 x i32> noundef %a.coerce, <vscale x 2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i32>, align 8
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca <8 x i32>, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %b.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i32>, ptr %b.addr, align 8
# |   %add = add <8 x i32> %0, %1
# |   store <8 x i32> %add, ptr %retval, align 8
# |   %2 = load <8 x i32>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> %2, i64 0)
# |   ret <vscale x 2 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32>, <8 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 1 x i64> @add_i64(<vscale x 1 x i64> noundef %a.coerce, <vscale x 1 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <4 x i64>, align 8
# |   %a.addr = alloca <4 x i64>, align 8
# |   %b.addr = alloca <4 x i64>, align 8
# |   %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %a.coerce, i64 0)
# |   %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %b.coerce, i64 0)
# |   store <4 x i64> %a, ptr %a.addr, align 8
# |   store <4 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i64>, ptr %a.addr, align 8
# |   %1 = load <4 x i64>, ptr %b.addr, align 8
# |   %add = add <4 x i64> %0, %1
# |   store <4 x i64> %add, ptr %retval, align 8
# |   %2 = load <4 x i64>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64> poison, <4 x i64> %2, i64 0)
# |   ret <vscale x 1 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64>, <4 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @add_u8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %add = add <32 x i8> %0, %1
# |   store <32 x i8> %add, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @add_u16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %add = add <16 x i16> %0, %1
# |   store <16 x i16> %add, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @add_u32(<vscale x 2 x i32> noundef %a.coerce, <vscale x 2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i32>, align 8
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca <8 x i32>, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %b.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i32>, ptr %b.addr, align 8
# |   %add = add <8 x i32> %0, %1
# |   store <8 x i32> %add, ptr %retval, align 8
# |   %2 = load <8 x i32>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> %2, i64 0)
# |   ret <vscale x 2 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 1 x i64> @add_u64(<vscale x 1 x i64> noundef %a.coerce, <vscale x 1 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <4 x i64>, align 8
# |   %a.addr = alloca <4 x i64>, align 8
# |   %b.addr = alloca <4 x i64>, align 8
# |   %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %a.coerce, i64 0)
# |   %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %b.coerce, i64 0)
# |   store <4 x i64> %a, ptr %a.addr, align 8
# |   store <4 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i64>, ptr %a.addr, align 8
# |   %1 = load <4 x i64>, ptr %b.addr, align 8
# |   %add = add <4 x i64> %0, %1
# |   store <4 x i64> %add, ptr %retval, align 8
# |   %2 = load <4 x i64>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64> poison, <4 x i64> %2, i64 0)
# |   ret <vscale x 1 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x float> @add_f32(<vscale x 2 x float> noundef %a.coerce, <vscale x 2 x float> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x float>, align 8
# |   %a.addr = alloca <8 x float>, align 8
# |   %b.addr = alloca <8 x float>, align 8
# |   %a = call <8 x float> @llvm.vector.extract.v8f32.nxv2f32(<vscale x 2 x float> %a.coerce, i64 0)
# |   %b = call <8 x float> @llvm.vector.extract.v8f32.nxv2f32(<vscale x 2 x float> %b.coerce, i64 0)
# |   store <8 x float> %a, ptr %a.addr, align 8
# |   store <8 x float> %b, ptr %b.addr, align 8
# |   %0 = load <8 x float>, ptr %a.addr, align 8
# |   %1 = load <8 x float>, ptr %b.addr, align 8
# |   %add = fadd <8 x float> %0, %1
# |   store <8 x float> %add, ptr %retval, align 8
# |   %2 = load <8 x float>, ptr %retval,
# | ...
# `---data was truncated (10240/145303) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x00005636aa0ddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005636aa0dae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005636aa0de62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f346a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f346a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f346a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f346a31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005636aa073bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005636aa073a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005636aa0588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005636a9d07e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005636a9d07b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f346a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f346a31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f346a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005636a9d07a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c (1396 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f16m1x3(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_f16m2x3(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f32m1x3(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_f32m2x3(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f64m1x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/87892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562f3d783eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562f3d780e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562f3d78462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb54841bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb5484725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb54841ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb548403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562f3d719bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562f3d719a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562f3d6fe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562f3d3ade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562f3d3adb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb548404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb5484050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb5484050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562f3d3ada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c (1397 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmaxu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmaxu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmaxu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmaxu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmaxu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmaxu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmaxu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmaxu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmaxu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmaxu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmaxu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr
# | ...
# `---data was truncated (10240/97905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559372e0beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559372e08e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559372e0c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f17ee61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f17ee6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f17ee61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f17ee603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559372da1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559372da1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559372d868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559372a35e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559372a35b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f17ee604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f17ee6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f17ee6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559372a35a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c (1398 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabs_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabs_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabs_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabs_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabs_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vabs_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vabs_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vabs_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vabs_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vabs_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vabs_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vabd.nxv8i16.i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vabd.nxv8i16.i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vabs_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vabd.nxv16i16.i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vabd.nxv16i16.i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vabs_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i
# | ...
# `---data was truncated (10240/41094) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005639080bfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005639080bce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005639080c062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcab6e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcab6ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcab6e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcab6e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563908055bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563908055a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056390803a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563907ce9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563907ce9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcab6e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcab6e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcab6e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563907ce9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c (1399 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsra_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsra_vx_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsra_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsra_vx_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsra_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsra_vx_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsra_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsra_vx_i8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsra_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsra_vx_i8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsra_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>
# | ...
# `---data was truncated (10240/98343) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561773848eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561773845e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056177384962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f243ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f243ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f243ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f243ab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005617737debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005617737dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005617737c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561773472e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561773472b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f243ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f243ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f243ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561773472a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c (1400 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vzip_vv_bf16m4(<vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vzip_vv_bf16m8(<vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vzip_vv_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bf
# | ...
# `---data was truncated (10240/13040) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005566c3e66eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005566c3e63e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005566c3e6762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5a06449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5a064a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5a06449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5a06431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005566c3dfcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005566c3dfca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005566c3de18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005566c3a90e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005566c3a90b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5a06432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5a064330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5a064330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005566c3a90a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c (1401 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei8_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8
# | ...
# `---data was truncated (10240/160141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e21a36aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e21a367e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e21a36b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb37f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb37f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb37f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb37f51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e21a300bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e21a300a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e21a2e58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e219f94e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e219f94b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb37f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb37f51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb37f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e219f94a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm64_vcreate.c (1402 of 27911)
******************** TEST 'Clang :: CodeGen/arm64_vcreate.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c"
# | target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-apple-ios7"
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define <2 x float> @test_vcreate_f32(i64 noundef %a1) #0 {
# | entry:
# |   %a1.addr = alloca i64, align 8
# |   %__ret = alloca <2 x float>, align 8
# |   %__promote = alloca i64, align 8
# |   %tmp = alloca <2 x float>, align 8
# |   store i64 %a1, ptr %a1.addr, align 8
# |   %0 = load i64, ptr %a1.addr, align 8
# |   store i64 %0, ptr %__promote, align 8
# |   %1 = load <2 x float>, ptr %__promote, align 8
# |   store <2 x float> %1, ptr %__ret, align 8
# |   %2 = load <2 x float>, ptr %__ret, align 8
# |   store <2 x float> %2, ptr %tmp, align 8
# |   %3 = load <2 x float>, ptr %tmp, align 8
# |   ret <2 x float> %3
# | }
# | 
# | attributes #0 = { noinline nounwind optnone "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b5c2555eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b5c2552e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b5c255662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3380533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f338058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3380533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f338051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b5c24ebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b5c24eba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b5c24d08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b5c217fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b5c217fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f338051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f338051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f338051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b5c217fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c (1403 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.
# | ...
# `---data was truncated (10240/101402) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557860a41eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557860a3ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557860a4262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c0a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c0a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c0a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c0a31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005578609d7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005578609d7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005578609bc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055786066be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055786066bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1c0a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c0a31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c0a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055786066ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c (1404 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrem_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrem_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrem_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrem_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrem_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrem_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrem_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrem_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrem_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrem.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrem.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrem_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrem.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrem.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vrem_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/97647) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056496ea0eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056496ea0be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056496ea0f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f861001bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f86100725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f861001ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8610003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056496e9a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056496e9a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056496e9898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056496e638e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056496e638b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8610004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f86100050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f86100050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056496e638a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c (1405 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vneg_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vneg_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vneg_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vneg_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vneg_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vneg_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vneg_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vneg_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vneg_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vneg_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4
# | ...
# `---data was truncated (10240/96257) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d8a121deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d8a121ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d8a121e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9908d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9908d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9908d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9908d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d8a11b3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d8a11b3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d8a11988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d8a0e47e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d8a0e47b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9908d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9908d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9908d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d8a0e47a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c (1406 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f16m1x7(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f32m1x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f64m1x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei32_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005579a4cc1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005579a4cbee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005579a4cc262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f99d1e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f99d1ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f99d1e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f99d1e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005579a4c57bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005579a4c57a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005579a4c3c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005579a48ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005579a48ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f99d1e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f99d1e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f99d1e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005579a48eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c (1407 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_i16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_i16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_i16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.
# | ...
# `---data was truncated (10240/78690) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b3026c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b3026c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b3026c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7218b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7218b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7218b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7218b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b30265ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b30265ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b3026438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b3022f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b3022f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7218b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7218b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7218b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b3022f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c (1408 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_s_u_w4_i8m8_u8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.s.u.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.s.u.i64.nxv64i8.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557341f86eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557341f83e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557341f8762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4da5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4da52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4da5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4da5231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557341f1cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557341f1ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557341f018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557341bb0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557341bb0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4da5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4da52330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4da52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557341bb0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c (1409 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_f64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_f64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_f64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_i64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_i64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_i64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_u64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_u64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_u64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = loa
# | ...
# `---data was truncated (10240/23447) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556cbb14eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556cbb14be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556cbb14f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb717449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb7174a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb717449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb717431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556cbb0e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556cbb0e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556cbb0c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556cbad78e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556cbad78b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb717432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb7174330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb7174330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556cbad78a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c (1410 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_i64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_i64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_u64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_u64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055db6c72feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055db6c72ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055db6c73062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fda22b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fda22b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fda22b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fda22b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055db6c6c5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055db6c6c5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055db6c6aa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055db6c359e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055db6c359b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fda22b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fda22b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fda22b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055db6c359a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c (1411 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4e
# | ...
# `---data was truncated (10240/216250) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561302862eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056130285fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056130286362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f8a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f8a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f8a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f8a831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005613027f8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005613027f8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005613027dd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056130248ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056130248cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2f8a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f8a8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f8a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056130248ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c (1412 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_f16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_f16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_f16m1x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_i16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_i16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_i16m1x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_u16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("ri
# | ...
# `---data was truncated (10240/13634) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005650b95d7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005650b95d4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005650b95d862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f34c0249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f34c02a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f34c0249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f34c0231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005650b956dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005650b956da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005650b95528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005650b9201e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005650b9201b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f34c0232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f34c02330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f34c02330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005650b9201a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c (1413 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f16m1x7(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f32m1x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f64m1x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i32> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a9cf2a4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a9cf2a1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a9cf2a562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe604133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe60418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe604133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe60411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a9cf23abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a9cf23aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a9cf21f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a9ceecee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a9ceeceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe60411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe60411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe60411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a9ceecea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c (1414 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabdu_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabdu_vx_u8mf8(<vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabdu_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabdu_vx_u8mf4(<vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabdu_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabdu_vx_u8mf2(<vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabdu_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabdu_vx_u8m1(<vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabdu_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabdu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabdu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabdu_vx_u8m2(<vscale x 16 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabdu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabdu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vabdu_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 
# | ...
# `---data was truncated (10240/97506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005595c75d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005595c75d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005595c75d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f83a9333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83a938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f83a9333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f83a931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005595c756ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005595c756ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005595c75538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005595c7202e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005595c7202b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f83a931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83a931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83a931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005595c7202a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c (1415 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadc_vvm_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadc_vxm_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadc_vvm_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadc_vxm_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadc_vvm_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadc_vxm_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadc_vvm_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadc_vxm_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, <vscale x 8 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vadc_vvm_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |  
# | ...
# `---data was truncated (10240/98141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562099b15eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562099b12e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562099b1662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9ba2733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9ba278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9ba2733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9ba271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562099aabbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562099aaba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562099a908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056209973fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056209973fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9ba271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9ba271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9ba271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056209973fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c (1416 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsne_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsne_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsne_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsne_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsne_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsne_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsne_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | 
# | ...
# `---data was truncated (10240/116259) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555e45f96eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555e45f93e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555e45f9762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9fdbb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9fdbb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9fdbb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9fdbb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555e45f2cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555e45f2ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555e45f118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555e45bc0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555e45bc0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9fdbb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9fdbb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9fdbb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555e45bc0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c (1417 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_bf16mf4_u16mf4(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1bf16.i64(<vscale x 1 x i16> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1bf16.i64(<vscale x 1 x i16>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_bf16mf2_u16mf2(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2bf16.i64(<vscale x 2 x i16> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2bf16.i64(<vscale x 2 x i16>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_bf16m1_u16m1(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4bf16.i64(<vscale x 4 x i16> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4bf16.i64(<vscale x 4 x i16>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_bf16m2_u16m2(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8bf16.i64(<vscale x 8 x i16> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8bf16.i64(<vscale x 8 x i16>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_bf16m4_u16m4(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16bf16.i64(<vscale x 16 x i16> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16bf16.i64(<vscale x 16 x i16>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfclass_v_bf16m8_u16m8(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32bf16.i64(<vscale x 32 x i16> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32bf16.i64(<vscale x 32 x i16>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_bf16mf4_u16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1bf16.i64(<vscale x 1 x i16> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1bf16.i64(<vscale x 1 x i16>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_bf16mf2_u16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2bf16.i64(<vscale x 2 x i16> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2bf16.i64(<vscale x 2 x i16>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_bf16m1_u16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4bf16.i64(<vscale x 4 x i16> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4bf16.i64(<vscale x 4 x i16>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_bf16m2_u16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfclass.mask.nxv8bf16.i64(<vscale x 8 x i16> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.mask.nxv8bf16.i64(<vscale x 8 x i16>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_bf16m4_u16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfclass.mask.nxv16bf16.i64(<vscale x 16 x i16> poison, <vscale x 16 x bfloat> 
# | ...
# `---data was truncated (10240/12298) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562a0b86aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562a0b867e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562a0b86b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5874b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5874b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5874b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5874b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562a0b800bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562a0b800a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562a0b7e58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562a0b494e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562a0b494b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5874b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5874b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5874b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562a0b494a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c (1418 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsif_m_b1_mu(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %maskedoff, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %2, <vscale x 64 x i1> %0, i64 %3)
# |   ret <vscale x 64 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsif_m_b2_mu(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %maskedoff, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %2, <vscale x 32 x i1> %0, i64 %3)
# |   ret <vscale x 32 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsif_m_b4_mu(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %maskedoff, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %2, <vscale x 16 x i1> %0, i64 %3)
# |   ret <vscale x 16 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsif_m_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %2, <vscale x 8 x i1> %0, i64 %3)
# |   ret <vscale x 8 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsif_m_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %2, <vscale x 4 x i1> %0, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsif_m_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %2, <vscale x 2 x i1> %0, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsif_m_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1.i64(<vscale x 1 x i1> %1, <vscale x 1 x i1> %2, <vscale x 1 x i1> %0, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b305bd6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b305bd3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b305bd762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd492849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd4928a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd492849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd492831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b305b6cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b305b6ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b305b518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b305800e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b305800b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd492832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd4928330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd4928330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b305800a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c (1419 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_i8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_i8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8_v_i8mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8_v_i8m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8_v_i8m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_u8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_u8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8_v_u8mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv
# | ...
# `---data was truncated (10240/53726) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561ff4f61eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561ff4f5ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561ff4f6262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5228e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5228ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5228e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5228e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561ff4ef7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561ff4ef7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561ff4edc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561ff4b8be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561ff4b8bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5228e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5228e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5228e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561ff4b8ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-bf16-params-returns.c (1420 of 27911)
******************** TEST 'Clang :: CodeGen/arm-bf16-params-returns.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.6a-arm-none-eabi -target-abi aapcs -mfloat-abi hard -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c --check-prefix=CHECK32-HARD
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.6a-arm-none-eabi -target-abi aapcs -mfloat-abi hard -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8.6a-arm-none-eabi"
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
# | define dso_local arm_aapcs_vfpcc noundef bfloat @test_ret_bf16(bfloat noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret bfloat %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
# | define dso_local arm_aapcs_vfpcc noundef <4 x bfloat> @test_ret_bf16x4_t(<4 x bfloat> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <4 x bfloat> %v
# | }
# | 
# | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.6-a,+bf16,+neon,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,-thumb-mode" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | !llvm.errno.tbaa = !{!6}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# | !6 = !{!7, !8, i64 0}
# | !7 = !{!"__libc_errno", !8, i64 0}
# | !8 = !{!"int", !9, i64 0}
# | !9 = !{!"omnipotent char", !10, i64 0}
# | !10 = !{!"Simple C/C++ TBAA"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000056157ad2beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056157ad28e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056157ad2c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b11133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b1118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b11133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b1111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056157acc1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056157acc1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056157aca68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056157a955e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056157a955b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5b1111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b1111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b1111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056157a955a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c --check-prefix=CHECK32-HARD
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c --check-prefix=CHECK32-HARD
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c (1421 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmul_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmul_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmul_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmul_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmul_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmul_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmul_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmul_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmul_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmul.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmul.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmul_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmul.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i
# | ...
# `---data was truncated (10240/125641) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561f3eda6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561f3eda3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561f3eda762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f33c2649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f33c26a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f33c2649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f33c2631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f3ed3cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561f3ed3ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561f3ed218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561f3e9d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561f3e9d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f33c2632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f33c26330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f33c26330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f3e9d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c (1422 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vv_f32mf2(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vf_f32mf2(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vv_f32m1(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vf_f32m1(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vv_f32m2(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vf_f32m2(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vv_f32m4(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vf_f32m4(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64(<vscale x 8 x float> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwmul_vv_f32m8(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwmul.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwmul.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwmul_vf_f32m8(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>
# | ...
# `---data was truncated (10240/76635) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c78b61eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562c78b5ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562c78b6262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa75b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa75b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa75b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa75b71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c78af7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562c78af7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562c78adc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562c7878be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562c7878bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa75b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa75b71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa75b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c7878ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c (1423 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_f32mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_f32m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e32_v_f32m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e32_v_f32m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_i32mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_i32m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e32_v_i32m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e32_v_i32m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_u32mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_u32m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("ris
# | ...
# `---data was truncated (10240/26965) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559acbe35eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559acbe32e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559acbe3662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd675b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd675b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd675b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd675b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559acbdcbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559acbdcba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559acbdb08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559acba5fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559acba5fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd675b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd675b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd675b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559acba5fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c (1424 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsub_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsub_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsub_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsub_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsub_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsub_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsub_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsub_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfs
# | ...
# `---data was truncated (10240/65574) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dc7dd5deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dc7dd5ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dc7dd5e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5837049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f58370a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5837049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5837031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc7dcf3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dc7dcf3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dc7dcd88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dc7d987e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dc7d987b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5837032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f58370330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f58370330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc7d987a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c (1425 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   st
# | ...
# `---data was truncated (10240/11797) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555ff723eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555ff723be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555ff723f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0ad8d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0ad8d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0ad8d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0ad8d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555ff71d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555ff71d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555ff71b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555ff6e68e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555ff6e68b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0ad8d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0ad8d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0ad8d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555ff6e68a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c (1426 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfneg_v_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfneg_v_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfneg_v_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1_tum(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# | ...
# `---data was truncated (10240/29304) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ddad292eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ddad28fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ddad29362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f70cd333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f70cd38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f70cd333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f70cd31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ddad228bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ddad228a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ddad20d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ddacebce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ddacebcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f70cd31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f70cd31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f70cd31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ddacebca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c (1427 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_f64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_f64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_i64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_i64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_u64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_u64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_f64m1x4_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_f64m2x4_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %2, <vscale x 2 x i1> 
# | ...
# `---data was truncated (10240/32133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055588970eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055588970be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055588970f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff141a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff141aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff141a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff141a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005558896a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005558896a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005558896898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555889338e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555889338b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff141a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff141a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff141a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555889338a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c (1428 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8ff_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8ff_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(<vscale x 2 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8ff_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(<vscale x 4 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8ff_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(<vscale x 8 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8ff_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(<vscale x 16 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 16 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8ff_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(<vscale x 32 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 32 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 32 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8ff_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(<vscale x 64 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 64 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 64 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 64 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8ff_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8ff_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloc
# | ...
# `---data was truncated (10240/71123) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bd0d5ddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bd0d5dae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bd0d5de62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc11ee1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc11ee725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc11ee1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc11ee03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bd0d573bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bd0d573a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bd0d5588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bd0d207e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bd0d207b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc11ee04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc11ee050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc11ee050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bd0d207a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c (1429 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste64_f64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.sf.vste64.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste64_i64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste64_u64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ebe3086eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ebe3083e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ebe308762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f898d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f898d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f898d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f898d231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ebe301cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ebe301ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ebe30018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ebe2cb0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ebe2cb0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f898d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f898d2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f898d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ebe2cb0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c (1430 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_f16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_f16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_f16m1x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_i16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_i16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_i16m1x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_u16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_u16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_u16m1x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_
# | ...
# `---data was truncated (10240/10396) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562fa807beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562fa8078e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562fa807c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcb74e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcb74ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcb74e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcb74e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562fa8011bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562fa8011a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562fa7ff68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562fa7ca5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562fa7ca5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcb74e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcb74e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcb74e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562fa7ca5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c (1431 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf8_i16m1(<vscale x 1 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> poison, <vscale x 1 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16>, <vscale x 1 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf4_i16m1(<vscale x 2 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> poison, <vscale x 2 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16>, <vscale x 2 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf2_i16m1(<vscale x 4 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m1_i16m1(<vscale x 8 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> poison, <vscale x 8 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16>, <vscale x 8 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m2_i16m1(<vscale x 16 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> poison, <vscale x 16 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16>, <vscale x 16 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m4_i16m1(<vscale x 32 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> poison, <vscale x 32 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16>, <vscale x 32 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m8_i16m1(<vscale x 64 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> poison, <vscale x 64 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16>, <vscale x 64 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16mf4_i32m1(<vscale x 1 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(<vscale x 2 x i32> poison, <vscale x 1 x i16> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(<vscale x 2 x i32>, <vscale x 1 x i16>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16mf2_i32m1(<vscale x 2 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16m1_i32m1(<vscale x 4 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, ali
# | ...
# `---data was truncated (10240/43507) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005624d42b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005624d42b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005624d42b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4035c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4035c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4035c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4035c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005624d4249bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005624d4249a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005624d422e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005624d3edde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005624d3eddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4035c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4035c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4035c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005624d3edda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c (1432 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsub_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsub_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsub_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsub_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsub_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsub_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsub_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsub_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsub_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/424835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560c5cdd6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560c5cdd3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560c5cdd762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3db861bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3db86725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3db861ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3db8603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c5cd6cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560c5cd6ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560c5cd518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560c5ca00e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560c5ca00b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3db8604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3db86050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3db86050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c5ca00a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c (1433 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback n
# | ...
# `---data was truncated (10240/100952) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555d3c6d4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555d3c6d1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555d3c6d562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcea5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcea52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcea5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcea5231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555d3c66abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555d3c66aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555d3c64f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555d3c2fee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555d3c2feb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcea5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcea52330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcea52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555d3c2fea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c (1434 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8dot2 -target-feature +fp8dot4 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8dot2 -target-feature +fp8dot4 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vdot_f16(<4 x half> noundef %vd, <8 x i8> %vn, <8 x i8> %vm, i64 noundef %fpmr) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <4 x half>, align 8
# |   %vd.addr = alloca <4 x half>, align 8
# |   %vn.addr = alloca <8 x i8>, align 8
# |   %vm.addr = alloca <8 x i8>, align 8
# |   %fpmr.addr = alloca i64, align 8
# |   store <4 x half> %vd, ptr %vd.addr, align 8
# |   store <8 x i8> %vn, ptr %vn.addr, align 8
# |   store <8 x i8> %vm, ptr %vm.addr, align 8
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <4 x half>, ptr %vd.addr, align 8
# |   %1 = load <8 x i8>, ptr %vn.addr, align 8
# |   %2 = load <8 x i8>, ptr %vm.addr, align 8
# |   %3 = load i64, ptr %fpmr.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %6 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %fdot2.i = bitcast <8 x i8> %4 to <4 x half>
# |   %fdot21.i = call <4 x half> @llvm.aarch64.neon.fp8.fdot2.v4f16.v8i8(<4 x half> %fdot2.i, <8 x i8> %5, <8 x i8> %6)
# |   store <4 x half> %fdot21.i, ptr %ref.tmp.i, align 8
# |   %8 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %8, ptr %__ret.i, align 8
# |   %9 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vdotq_f16(<8 x half> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpmr) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <8 x half>, align 16
# |   %vd.addr = alloca <8 x half>, align 16
# |   %vn.addr = alloca <16 x i8>, align 16
# |   %vm.addr = alloca <16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <8 x half> %vd, ptr %vd.addr, align 16
# |   store <16 x i8> %vn, ptr %vn.addr, align 16
# |   store <16 x i8> %vm, ptr %vm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <8 x half>, ptr %vd.addr, align 16
# |   %1 = load <16 x i8>, ptr %vn.addr, align 16
# |   %2 = load <16 x i8>, ptr %vm.addr, align 16
# |   %3 = load i64, ptr %fpmr.addr, align 8
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %fdot2.i = bitcast <16 x i8> %4 to <8 x half>
# |   %fdot21.i = call <8 x half> @llvm.aarch64.neon.fp8.fdot2.v8f16.v16i8(<8 x half> %fdot2.i, <16 x i8> %5, <16 x i8> %6)
# |   store <8 x half> %fdot21.i, ptr %ref.tmp.i, align 16
# |   %8 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %8, ptr %__ret.i, align 16
# |   %9 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vdot_lane_f16(<4 x half> noundef %vd, <8 x i8> %vn, <8 x i8> %vm, i64 noundef %fpmr) #0 {
# | entry:
# |   %vd.addr = alloca <4 x half>, align 8
# |   %vn.addr = alloca <8 x i8>, align 8
# |   %vm.addr = alloca <8 x i8>, align 8
# |   %fpmr.addr = alloca i64, align 8
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca <4 x half>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %__s2 = alloca <8 x i8>, align 8
# |   %__s4 = alloca i64, align 8
# |   %ref.tmp = alloca <4 x half>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   store <4 x half> %vd, ptr %vd.addr, align 8
# |   store <8 x i8> %vn, ptr %vn.addr, align 8
# |   store <8 x i8> %vm, ptr %vm.addr, align 8
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <4 x half>, ptr %vd.addr, align 8
# |   store <4 x half> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %vn.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %vm.addr, align 8
# |   store <8 x i8> %2, ptr %__s2, align 8
# |   %3 = load i64, ptr %fpmr.addr, align 8
# |   store i64 %3, ptr %__s4, align 8
# |   %4 = load <8 x i8>, ptr %__s0, align 8
# |   %5 = load <8 x i8>, ptr %__s1, align 8
# |   %6 = load <8 x i8>, ptr %__s2, align 8
# |   %7 = load i64, ptr %__s4, align 8
# |   %8 = call <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8> poison, <8 x i8> %6, i64 0)
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %fdot2_lane = bitcast <8 x i8> %4 to <4 x half>
# |   %fdot2_lane1 = call <4 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v4f16.v8i8(<4 x half> %fdot2_lane, <8 x i8> %5, <16 x i8> %8, i32 3)
# |   store <4 x half> %fdot2_lane1, ptr %ref.tmp, align 8
# |   %9 = load <4 x half>, ptr %ref.tmp, align 8
# |   store <4 x half> %9, ptr %__ret, align 8
# |   %10 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %10, ptr %tmp, align 8
# |   %11 = load <4 x half>, ptr %tmp, align 8
# |   ret <4 x half> %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8>, <8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <4 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v4f16.v8i8(<4 x half>, <8 x i8>, <16 x i8>, i32 immarg) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vdot_laneq_f16(<4 x half> noundef %vd, <8 x i8> %vn, <16 x i8> %vm, i64 noundef %fpmr) #0 {
# | entry:
# |   %vd.addr = alloca <4 x half>, align 8
# |   %vn.addr = alloca <8 x i8>, align 8
# |   %vm.addr = alloca <16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca <4 x half>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %__s2 = alloca <16 x i8>, align 16
# |   %__s4 = alloca i64, align 8
# |   %ref.tmp = alloca <4 x half>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   store <4 x half> %vd, ptr %vd.addr, align 8
# |   store <8 x i8> %vn, ptr %vn.addr, align 8
# |   store <16 x i8> %vm, ptr %vm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <4 x half>, ptr %vd.addr, align 8
# |   store <4 x half> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %vn.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <16 x i8>, ptr %vm.addr, align 16
# |   store <16 x i8> %2, ptr %__s2, align 16
# |   %3 = load i64, ptr %fpmr.addr, align 8
# |   store i64 %3, ptr %__s4, align 8
# |   %4 = load <8 x i8>, ptr %__s0, align 8
# |   %5 = load <8 x i8>, ptr %__s1, align 8
# |   %6 = load <16 x i8>, ptr %__s2, align 16
# |   %7 = load i64, ptr %__s4, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %fdot2_lane = bitcast <8 x i8> %4 to <4 x half>
# |   %fdot2_lane1 = call <4 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v4f16.v8i8(<4 x half> %fdot2_lane, <8 x i8> %5, <16 x i8> %6, i32 7)
# |   store <4 x half> %fdot2_lane1, ptr %ref.tmp, align 8
# |   %8 = load <4 x half>, ptr %ref.tmp, align 8
# |   store <4 x half> %8, ptr %__ret, align 8
# |   %9 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %9, ptr %tmp, align 8
# |   %10 = load <4 x half>, ptr %tmp, align 8
# |   ret <4 x half> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vdotq_lane_f16(<8 x half> noundef %vd, <16 x i8> %vn, <8 x i8> %vm, i64 noundef %fpmr) #0 {
# | entry:
# |   %vd.addr = alloca <8 x half>, align 16
# |   %vn.addr = alloca <16 x i8>, align 16
# |   %vm.addr = alloca <8 x i8>, align 8
# |   %fpmr.addr = alloca i64, align 8
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca <8 x half>, align 16
# |   %__s1 = alloca <16 x i8>, align 16
# |   %__s2 = alloca <8 x i8>, align 8
# |   %__s4 = alloca i64, align 8
# |   %ref.tmp = alloca <8 x half>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   store <8 x half> %vd, ptr %vd.addr, align 16
# |   store <16 x i8> %vn, ptr %vn.addr, align 16
# |   store <8 x i8> %vm, ptr %vm.addr, align 8
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <8 x half>, ptr %vd.addr, align 16
# |   store <8 x half> %0, ptr %__s0, align 16
# |   %1 = load <16 x i8>, ptr %vn.addr, align 16
# |   store <16 x i8> %1, ptr %__s1, align 16
# |   %2 = load <8 x i8>, ptr %vm.addr, align 8
# |   store <8 x i8> %2, ptr %__s2, align 8
# |   %3 = load i64, ptr %fpmr.addr, align 8
# |   store i64 %3, ptr %__s4, align 8
# |   %4 = load <16 x i8>, ptr %__s0, align 16
# |   %5 = load <16 x i8>, ptr %__s1, align 16
# |   %6 = load <8 x i8>, ptr %__s2, align 8
# |   %7 = load i64, ptr %__s4, align 8
# |   %8 = call <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8> poison, <8 x i8> %6, i64 0)
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %fdot2_lane = bitcast <16 x i8> %4 to <8 x half>
# |   %fdot2_lane1 = call <8 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v8f16.v16i8(<8 x half> %fdot2_lane, <16 x i8> %5, <16 x i8> %8, i32 3)
# |   store <8 x half> %fdot2_lane1, ptr %ref.tmp, align 16
# |   %9 = load <8 x half>, ptr %ref.tmp, align 16
# |   store <8 x half> %9, ptr %__ret, align 16
# |   %10 = load <8 x half>, ptr %__ret, align 16
# |   store <8 x half> %10, ptr %tmp, align 16
# |   %11 = load <8 x half>, ptr %tmp, align 16
# |   ret <8 x half> %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <8 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v8f16.v16i8(<8 x half>, <16 x i8>, <16 x i8>, i32 immarg) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vdotq_laneq_f16(<8 x half> noundef %vd, <16 x i8> %vn, <
# | ...
# `---data was truncated (10240/24508) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# |  #0 0x000055aa15787eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aa15784e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aa1578862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcf0321bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcf032725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcf0321ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcf03203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa1571dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aa1571da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aa157028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aa153b1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aa153b1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcf03204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcf032050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcf032050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa153b1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c (1435 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei16_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei16_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei16_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei16_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei16_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vluxei16_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, <vscale x 32 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei16_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei16_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei16_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %
# | ...
# `---data was truncated (10240/280171) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562143f88eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562143f85e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562143f8962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff2cfc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff2cfca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff2cfc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff2cfc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562143f1ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562143f1ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562143f038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562143bb2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562143bb2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff2cfc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff2cfc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff2cfc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562143bb2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c (1436 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_f32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_f32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_f32m2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_i32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_i32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_i32m2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_u32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_u32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_u3
# | ...
# `---data was truncated (10240/11880) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055701b6f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055701b6efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055701b6f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f067c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f067c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f067c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f067c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055701b688bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055701b688a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055701b66d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055701b31ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055701b31cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f067c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f067c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f067c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055701b31ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c (1437 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_f16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_f16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_f16m1x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_i16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_i16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_i16m1x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_u16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_u16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_u16m1x5_m(<vs
# | ...
# `---data was truncated (10240/11851) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005653e610deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005653e610ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005653e610e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f95b7c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f95b7c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f95b7c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f95b7c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005653e60a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005653e60a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005653e60888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005653e5d37e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005653e5d37b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f95b7c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f95b7c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f95b7c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005653e5d37a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c (1438 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8mf8x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_u8mf8x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_u8mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_u8mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_u8m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   
# | ...
# `---data was truncated (10240/21558) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558484571eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055848456ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055848457262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2745333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f274538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2745333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f274531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558484507bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558484507a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005584844ec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055848419be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055848419bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f274531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f274531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f274531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055848419ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c (1439 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfwmacc_4x4x4_f32mf2(<vscale x 1 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 4 x bfloat>, <vscale x 1 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfwmacc_4x4x4_f32m1(<vscale x 2 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 4 x bfloat>, <vscale x 2 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfwmacc_4x4x4_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfwmacc_4x4x4_f32m4(<vscale x 8 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfwmacc_4x4x4_f32m8(<vscale x 16 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(<vscale x 16 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 4 x bfloat>, <vscale x 16 x bfloat>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvfwmaccqqq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvfwmaccqqq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a71d7eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a71d7ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a71d7ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ee2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ee2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ee2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ee2f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a71d784bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a71d784a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a71d7698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a71d418e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a71d418b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3ee2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ee2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ee2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a71d418a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c (1440 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vmlalb(<8 x half> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <8 x half>, align 16
# |   %vd.addr = alloca <8 x half>, align 16
# |   %vn.addr = alloca <16 x i8>, align 16
# |   %vm.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <8 x half> %vd, ptr %vd.addr, align 16
# |   store <16 x i8> %vn, ptr %vn.addr, align 16
# |   store <16 x i8> %vm, ptr %vm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <8 x half>, ptr %vd.addr, align 16
# |   %1 = load <16 x i8>, ptr %vn.addr, align 16
# |   %2 = load <16 x i8>, ptr %vm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %vmlal.i = bitcast <16 x i8> %4 to <8 x half>
# |   %vmlal1.i = call <8 x half> @llvm.aarch64.neon.fp8.fmlalb.v8f16(<8 x half> %vmlal.i, <16 x i8> %5, <16 x i8> %6)
# |   store <8 x half> %vmlal1.i, ptr %ref.tmp.i, align 16
# |   %8 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %8, ptr %__ret.i, align 16
# |   %9 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vmlalt(<8 x half> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <8 x half>, align 16
# |   %vd.addr = alloca <8 x half>, align 16
# |   %vn.addr = alloca <16 x i8>, align 16
# |   %vm.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <8 x half> %vd, ptr %vd.addr, align 16
# |   store <16 x i8> %vn, ptr %vn.addr, align 16
# |   store <16 x i8> %vm, ptr %vm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <8 x half>, ptr %vd.addr, align 16
# |   %1 = load <16 x i8>, ptr %vn.addr, align 16
# |   %2 = load <16 x i8>, ptr %vm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %vmlal.i = bitcast <16 x i8> %4 to <8 x half>
# |   %vmlal1.i = call <8 x half> @llvm.aarch64.neon.fp8.fmlalt.v8f16(<8 x half> %vmlal.i, <16 x i8> %5, <16 x i8> %6)
# |   store <8 x half> %vmlal1.i, ptr %ref.tmp.i, align 16
# |   %8 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %8, ptr %__ret.i, align 16
# |   %9 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmlallbb(<4 x float> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <4 x float>, align 16
# |   %vd.addr = alloca <4 x float>, align 16
# |   %vn.addr = alloca <16 x i8>, align 16
# |   %vm.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <4 x float> %vd, ptr %vd.addr, align 16
# |   store <16 x i8> %vn, ptr %vn.addr, align 16
# |   store <16 x i8> %vm, ptr %vm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <4 x float>, ptr %vd.addr, align 16
# |   %1 = load <16 x i8>, ptr %vn.addr, align 16
# |   %2 = load <16 x i8>, ptr %vm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %vmlall.i = call <4 x float> @llvm.aarch64.neon.fp8.fmlallbb.v4f32(<4 x float> %4, <16 x i8> %5, <16 x i8> %6)
# |   store <4 x float> %vmlall.i, ptr %ref.tmp.i, align 16
# |   %8 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %8, ptr %__ret.i, align 16
# |   %9 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmlallbt(<4 x float> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <4 x float>, align 16
# |   %vd.addr = alloca <4 x float>, align 16
# |   %vn.addr = alloca <16 x i8>, align 16
# |   %vm.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <4 x float> %vd, ptr %vd.addr, align 16
# |   store <16 x i8> %vn, ptr %vn.addr, align 16
# |   store <16 x i8> %vm, ptr %vm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <4 x float>, ptr %vd.addr, align 16
# |   %1 = load <16 x i8>, ptr %vn.addr, align 16
# |   %2 = load <16 x i8>, ptr %vm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %vmlall.i = call <4 x float> @llvm.aarch64.neon.fp8.fmlallbt.v4f32(<4 x float> %4, <16 x i8> %5, <16 x i8> %6)
# |   store <4 x float> %vmlall.i, ptr %ref.tmp.i, align 16
# |   %8 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %8, ptr %__ret.i, align 16
# |   %9 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmlalltb(<4 x float> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <4 x float>, align 16
# |   %vd.addr = alloca <4 x float>, align 16
# |   %vn.addr = alloca <16 x i8>, align 16
# |   %vm.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <4 x float> %vd, ptr %vd.addr, align 16
# |   store <16 x i8> %vn, ptr %vn.addr, align 16
# |   store <16 x i8> %vm, ptr %vm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <4 x float>, ptr %vd.addr, align 16
# |   %1 = load <16 x i8>, ptr %vn.addr, align 16
# |   %2 = load <16 x i8>, ptr %vm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %vmlall.i = call <4 x float> @llvm.aarch64.neon.fp8.fmlalltb.v4f32(<4 x float> %4, <16 x i8> %5, <16 x i8> %6)
# |   store <4 x float> %vmlall.i, ptr %ref.tmp.i, align 16
# |   %8 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %8, ptr %__ret.i, align 16
# |   %9 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmlalltt(<4 x float> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <4 x float>, align 16
# |   %vd.addr = alloca <4 x float>, align 16
# |   %vn.addr = alloca <16 x i8>, align 16
# |   %vm.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <4 x float> %vd, ptr %vd.addr, align 16
# |   store <16 x i8> %vn, ptr %vn.addr, align 16
# |   store <16 x i8> %vm, ptr %vm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <4 x float>, ptr %vd.addr, align 16
# |   %1 = load <16 x i8>, ptr %vn.addr, align 16
# |   %2 = load <16 x i8>, ptr %vm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 
# | ...
# `---data was truncated (10240/35980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# |  #0 0x00005620b3d63eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005620b3d60e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005620b3d6462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1aa9c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1aa9ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1aa9c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1aa9c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005620b3cf9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005620b3cf9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005620b3cde8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005620b398de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005620b398db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1aa9c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1aa9c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1aa9c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005620b398da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c (1441 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv1i8.nxv1i8.i32(i32 3, i32 31, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv1i8.nxv1i8.i32(i32 immarg, i32 immarg, <vscale x 1 x i8>, <vscale x 1 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv2i8.nxv2i8.i32(i32 3, i32 31, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv2i8.nxv2i8.i32(i32 immarg, i32 immarg, <vscale x 2 x i8>, <vscale x 2 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv4i8.nxv4i8.i32(i32 3, i32 31, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv4i8.nxv4i8.i32(i32 immarg, i32 immarg, <vscale x 4 x i8>, <vscale x 4 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv8i8.nxv8i8.i32(i32 3, i32 31, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv8i8.nxv8i8.i32(i32 immarg, i32 immarg, <vscale x 8 x i8>, <vscale x 8 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv16i8.nxv16i8.i32(i32 3, i32 31, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv16i8.nxv16i8.i32(i32 immarg, i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv32i8.nxv32i8.i32(i32 3, i32 31, <vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv32i8.nxv32i8.i32(i32 immarg, i32 immarg, <vscale x 32 x i8>, <vscale x 32 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv64i8.nxv64i8.i32(i32 3, i32 31, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv64i8.nxv64i8.i32(i32 immarg, i32 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u16mf4(<vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv1i16.nxv1i16.i32(i32 3, i32 31, <vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv1i16.nxv1i16.i32(i32 immarg, i32 immarg, <vscale x 1 x i16>, <vscale x 1 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u16mf2(<vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv2i16.nxv2i16.i32(i32 3, i32 31, <vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv2i16.nxv2i16.i32(i32 immarg, i32 immarg, <vscale x 2 x i16>, <vscale x 2 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u16m1(<vscale x 4 x i16> %vs2, <vscale x 4 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv4i16.nxv4i16.i32(i32 3, i32 31, <vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv4i16.nxv4i16.i32(i32 immarg, i32 immarg, <vscale x 4 x i16>, <vscale x 4 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u16m2(<vscale x 8 x i16> %vs2, <vscale x 8 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv8i16.nxv8i16.i32(i32 3, i32 31, <vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function
# | ...
# `---data was truncated (10240/200802) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561a83ae3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561a83ae0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561a83ae462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f54ffd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54ffd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f54ffd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f54ffd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a83a79bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561a83a79a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561a83a5e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561a8370de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561a8370db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f54ffd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54ffd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54ffd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a8370da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c (1442 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredxor_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor
# | ...
# `---data was truncated (10240/113039) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cadc9d1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cadc9cee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cadc9d262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0281449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f02814a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0281449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0281431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cadc967bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cadc967a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cadc94c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cadc5fbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cadc5fbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0281432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f02814330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f02814330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cadc5fba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c (1443 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005560e2239eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005560e2236e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005560e223a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feecd533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feecd58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feecd533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feecd51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005560e21cfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005560e21cfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005560e21b48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005560e1e63e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005560e1e63b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feecd51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feecd51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feecd51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005560e1e63a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c (1444 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm3c_vi_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm3c_vi_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm3c_vi_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm3c_vi_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm3c_vi_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056285a27deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056285a27ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056285a27e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f92cdb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f92cdb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f92cdb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f92cdb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056285a213bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056285a213a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056285a1f88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562859ea7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562859ea7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f92cdb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f92cdb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f92cdb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562859ea7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c (1445 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaadd_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaadd_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaadd_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaadd_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaadd_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaadd_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaadd_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaadd_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaadd_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/225205) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d8f9d2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558d8f9cfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558d8f9d362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4cab933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4cab98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4cab933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4cab91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d8f968bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558d8f968a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558d8f94d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558d8f5fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558d8f5fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4cab91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4cab91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4cab91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d8f5fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c (1446 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgeu_vv_u8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgeu_vx_u8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgeu_vv_u8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgeu_vx_u8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgeu_vv_u8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgeu_vx_u8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgeu_vv_u8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgeu_vx_u8m1_b8(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgeu_vv_u8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgeu_vx_u8m2_b4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsgeu_vv_u8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.n
# | ...
# `---data was truncated (10240/95355) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056060286feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056060286ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056060287062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb839e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb839ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb839e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb839e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560602805bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560602805a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005606027ea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560602499e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560602499b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb839e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb839e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb839e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560602499a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c (1447 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf4_f16m1(<vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf2_f16m1(<vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m1_f16m1(<vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m2_f16m1(<vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m4_f16m1(<vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m8_f16m1(<vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32mf2_f32m1(<vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m1_f32m1(<vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m2_f32m1(<vscale x 4 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x
# | ...
# `---data was truncated (10240/68062) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005576ae2fdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005576ae2fae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005576ae2fe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5c1b505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5c1b55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5c1b505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5c1b4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005576ae293bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005576ae293a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005576ae2788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005576adf27e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005576adf27b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5c1b4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5c1b4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5c1b4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005576adf27a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c (1448 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f16m1x8(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f32m1x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f64m1x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei16_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cdb3bc8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cdb3bc5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cdb3bc962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f41b2449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f41b24a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f41b2449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f41b2431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cdb3b5ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cdb3b5ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cdb3b438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cdb37f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cdb37f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f41b2432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f41b24330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f41b24330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cdb37f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c (1449 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsqrt_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsqrt_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsqrt_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsqrt_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsqrt_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfsqrt_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfsqrt_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfsqrt_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfsqrt_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfsqrt_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.
# | ...
# `---data was truncated (10240/128424) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb168c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fb168c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fb168c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff730533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff73058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff730533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff73051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb1685abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fb1685aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fb1683f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fb164eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fb164eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff73051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff73051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff73051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb164eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c (1450 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vremu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vremu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vremu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vremu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vremu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vremu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vremu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vremu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vremu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x
# | ...
# `---data was truncated (10240/222925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055691ca3eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055691ca3be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055691ca3f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fccab505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fccab55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fccab505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fccab4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055691c9d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055691c9d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055691c9b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055691c668e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055691c668b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fccab4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fccab4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fccab4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055691c668a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c (1451 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i16> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i16> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i16> %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> %2, ptr %0, <vscale x 32 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vsca
# | ...
# `---data was truncated (10240/15622) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005630bc106eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005630bc103e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005630bc10762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f29c4b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f29c4b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f29c4b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f29c4b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005630bc09cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005630bc09ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005630bc0818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005630bbd30e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005630bbd30b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f29c4b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f29c4b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f29c4b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005630bbd30a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c (1452 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmflt_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmflt_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmflt_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/66557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056351f024eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056351f021e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056351f02562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faf6ae1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faf6ae725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faf6ae1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faf6ae03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056351efbabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056351efbaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056351ef9f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056351ec4ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056351ec4eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faf6ae04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faf6ae050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faf6ae050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056351ec4ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c (1453 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16m1x2(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16m2x2(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16m4x2(ptr noundef %base, <vscale x 16 x i8> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f32m1x2(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f32m2x2(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_t
# | ...
# `---data was truncated (10240/128436) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e530b51eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e530b4ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e530b5262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3c5ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3c5caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3c5ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3c5ca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e530ae7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e530ae7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e530acc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e53077be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e53077bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3c5ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3c5ca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3c5ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e53077ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c (1454 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrol_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrol_vx_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrol_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrol_vx_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrol_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrol_vx_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrol_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrol_vx_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrol_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrol.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrol.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrol_vx_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrol.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrol.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vrol_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.a
# | ...
# `---data was truncated (10240/97683) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e4f20f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e4f20f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e4f20fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd77a41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd77a4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd77a41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd77a403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e4f208fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e4f208fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e4f20748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e4f1d23e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e4f1d23b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd77a404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd77a4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd77a4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e4f1d23a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/ternary.c (1455 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/ternary.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c --check-prefixes=CHECK,CHECK-NOSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vfmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 8
# |   %0 = load <8 x half>, ptr %b.addr, align 8
# |   %1 = load <8 x half>, ptr %c.addr, align 8
# |   %2 = load <8 x half>, ptr %a.addr, align 8
# |   %3 = call <8 x half> @llvm.fma.v8f16(<8 x half> %0, <8 x half> %1, <8 x half> %2)
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.fma.v8f16(<8 x half>, <8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vfmaq_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store <4 x float> %c, ptr %c.addr, align 8
# |   %0 = load <4 x float>, ptr %b.addr, align 8
# |   %1 = load <4 x float>, ptr %c.addr, align 8
# |   %2 = load <4 x float>, ptr %a.addr, align 8
# |   %3 = call <4 x float> @llvm.fma.v4f32(<4 x float> %0, <4 x float> %1, <4 x float> %2)
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vfmaq_n_f16(<8 x half> noundef %a, <8 x half> noundef %b, half noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca half, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store half %c, ptr %c.addr, align 2
# |   %0 = load half, ptr %c.addr, align 2
# |   %.splatinsert = insertelement <8 x half> poison, half %0, i64 0
# |   %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load <8 x half>, ptr %a.addr, align 8
# |   %3 = call <8 x half> @llvm.fma.v8f16(<8 x half> %1, <8 x half> %.splat, <8 x half> %2)
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vfmaq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca float, align 4
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store float %c, ptr %c.addr, align 4
# |   %0 = load float, ptr %c.addr, align 4
# |   %.splatinsert = insertelement <4 x float> poison, float %0, i64 0
# |   %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load <4 x float>, ptr %a.addr, align 8
# |   %3 = call <4 x float> @llvm.fma.v4f32(<4 x float> %1, <4 x float> %.splat, <4 x float> %2)
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vfmasq_n_f16(<8 x half> noundef %a, <8 x half> noundef %b, half noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca half, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store half %c, ptr %c.addr, align 2
# |   %0 = load half, ptr %c.addr, align 2
# |   %.splatinsert = insertelement <8 x half> poison, half %0, i64 0
# |   %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
# |   %1 = load <8 x half>, ptr %a.addr, align 8
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = call <8 x half> @llvm.fma.v8f16(<8 x half> %1, <8 x half> %2, <8 x half> %.splat)
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vfmasq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca float, align 4
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store float %c, ptr %c.addr, align 4
# |   %0 = load float, ptr %c.addr, align 4
# |   %.splatinsert = insertelement <4 x float> poison, float %0, i64 0
# |   %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer
# |   %1 = load <4 x float>, ptr %a.addr, align 8
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = call <4 x float> @llvm.fma.v4f32(<4 x float> %1, <4 x float> %2, <4 x float> %.splat)
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vfmsq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 8
# |   %0 = load <8 x half>, ptr %b.addr, align 8
# |   %1 = load <8 x half>, ptr %c.addr, align 8
# |   %2 = fneg <8 x half> %1
# |   %3 = load <8 x half>, ptr %a.addr, align 8
# |   %4 = call <8 x half> @llvm.fma.v8f16(<8 x half> %0, <8 x half> %2, <8 x half> %3)
# |   ret <8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vfmsq_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store <4 x float> %c, ptr %c.addr, align 8
# |   %0 = load <4 x float>, ptr %b.addr, align 8
# |   %1 = load <4 x float>, ptr %c.addr, align 8
# |   %2 = fneg <4 x float> %1
# |   %3 = load <4 x float>, ptr %a.addr, align 8
# |   %4 = call <4 x float> @llvm.fma.v4f32(<4 x float> %0, <4 x float> %2, <4 x float> %3)
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmlaq_n_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i8 noundef signext %c) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i8 %c, ptr %c.addr, align 1
# |   %0 = load <16 x i8>, ptr %b.addr, align 8
# |   %1 = load i8, ptr %c.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = mul <16 x i8> %0, %.splat
# |   %3 = load <16 x i8>, ptr %a.addr, align 8
# |   %4 = add <16 x i8> %2, %3
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmlaq_n_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef signext %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %c, ptr %c.addr, align 2
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = load i16, ptr %c.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = mul <8 x i16> %0, %.splat
# |   %3 = load <8 x i16>, ptr %a.addr, align 8
# |   %4 = add <8 x i16> %2, %3
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmlaq_n_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i32 noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i32 %c, ptr %c.addr, align 4
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = load i32, ptr %c.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = mul <4 x i32> %0, %.splat
# |   %3 = load <4 x i32>, ptr %a.addr, align 8
# |   %4 = add <4 x i32> %2, %3
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmlaq_n_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i8 noundef zeroext %c) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i8 %c, ptr %c.addr, align 1
# |   %0 = load <16 x i8>, ptr %b.addr, align 8
# |   %1 = load i8, ptr %c.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = mul <16 x i8> %0, %.splat
# |   %3 = load <16 x i8>, ptr %a.addr, align 8
# |   %4 = add <16 x i8> %2, %3
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmlaq_n_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, ali
# | ...
# `---data was truncated (10240/60411) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x0000561f7a6c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561f7a6bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561f7a6c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc6fd449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc6fd4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc6fd449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc6fd431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f7a657bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561f7a657a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561f7a63c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561f7a2ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561f7a2ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc6fd432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc6fd4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc6fd4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f7a2eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c --check-prefixes=CHECK,CHECK-NOSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c --check-prefixes=CHECK,CHECK-NOSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-cde-vfp.c (1456 of 27911)
******************** TEST 'Clang :: CodeGen/arm-cde-vfp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi    -target-feature +cdecp0 -target-feature +cdecp1    -mfloat-abi hard -O0 -disable-O0-optnone    -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +cdecp1 -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vcx1_u32() #0 {
# | entry:
# |   %0 = call float @llvm.arm.cde.vcx1.f32(i32 0, i32 11)
# |   %1 = bitcast float %0 to i32
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.cde.vcx1.f32(i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vcx1a_u32(i32 noundef %acc) #0 {
# | entry:
# |   %acc.addr = alloca i32, align 4
# |   store i32 %acc, ptr %acc.addr, align 4
# |   %0 = load i32, ptr %acc.addr, align 4
# |   %1 = bitcast i32 %0 to float
# |   %2 = call float @llvm.arm.cde.vcx1a.f32(i32 1, float %1, i32 12)
# |   %3 = bitcast float %2 to i32
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.cde.vcx1a.f32(i32 immarg, float, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vcx2_u32(i32 noundef %n) #0 {
# | entry:
# |   %n.addr = alloca i32, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   %0 = load i32, ptr %n.addr, align 4
# |   %1 = bitcast i32 %0 to float
# |   %2 = call float @llvm.arm.cde.vcx2.f32(i32 0, float %1, i32 21)
# |   %3 = bitcast float %2 to i32
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.cde.vcx2.f32(i32 immarg, float, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vcx2a_u32(i32 noundef %acc, i32 noundef %n) #0 {
# | entry:
# |   %acc.addr = alloca i32, align 4
# |   %n.addr = alloca i32, align 4
# |   store i32 %acc, ptr %acc.addr, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   %0 = load i32, ptr %acc.addr, align 4
# |   %1 = bitcast i32 %0 to float
# |   %2 = load i32, ptr %n.addr, align 4
# |   %3 = bitcast i32 %2 to float
# |   %4 = call float @llvm.arm.cde.vcx2a.f32(i32 0, float %1, float %3, i32 22)
# |   %5 = bitcast float %4 to i32
# |   ret i32 %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.cde.vcx2a.f32(i32 immarg, float, float, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vcx3_u32(i32 noundef %n, i32 noundef %m) #0 {
# | entry:
# |   %n.addr = alloca i32, align 4
# |   %m.addr = alloca i32, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   store i32 %m, ptr %m.addr, align 4
# |   %0 = load i32, ptr %n.addr, align 4
# |   %1 = bitcast i32 %0 to float
# |   %2 = load i32, ptr %m.addr, align 4
# |   %3 = bitcast i32 %2 to float
# |   %4 = call float @llvm.arm.cde.vcx3.f32(i32 1, float %1, float %3, i32 3)
# |   %5 = bitcast float %4 to i32
# |   ret i32 %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.cde.vcx3.f32(i32 immarg, float, float, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vcx3a_u32(i32 noundef %acc, i32 noundef %n, i32 noundef %m) #0 {
# | entry:
# |   %acc.addr = alloca i32, align 4
# |   %n.addr = alloca i32, align 4
# |   %m.addr = alloca i32, align 4
# |   store i32 %acc, ptr %acc.addr, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   store i32 %m, ptr %m.addr, align 4
# |   %0 = load i32, ptr %acc.addr, align 4
# |   %1 = bitcast i32 %0 to float
# |   %2 = load i32, ptr %n.addr, align 4
# |   %3 = bitcast i32 %2 to float
# |   %4 = load i32, ptr %m.addr, align 4
# |   %5 = bitcast i32 %4 to float
# |   %6 = call float @llvm.arm.cde.vcx3a.f32(i32 0, float %1, float %3, float %5, i32 5)
# |   %7 = bitcast float %6 to i32
# |   ret i32 %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.cde.vcx3a.f32(i32 immarg, float, float, float, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vcx1d_u64() #0 {
# | entry:
# |   %0 = call double @llvm.arm.cde.vcx1.f64(i32 0, i32 11)
# |   %1 = bitcast double %0 to i64
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.arm.cde.vcx1.f64(i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vcx1da_u64(i64 noundef %acc) #0 {
# | entry:
# |   %acc.addr = alloca i64, align 8
# |   store i64 %acc, ptr %acc.addr, align 8
# |   %0 = load i64, ptr %acc.addr, align 8
# |   %1 = bitcast i64 %0 to double
# |   %2 = call double @llvm.arm.cde.vcx1a.f64(i32 1, double %1, i32 12)
# |   %3 = bitcast double %2 to i64
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.arm.cde.vcx1a.f64(i32 immarg, double, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vcx2d_u64(i64 noundef %n) #0 {
# | entry:
# |   %n.addr = alloca i64, align 8
# |   store i64 %n, ptr %n.addr, align 8
# |   %0 = load i64, ptr %n.addr, align 8
# |   %1 = bitcast i64 %0 to double
# |   %2 = call double @llvm.arm.cde.vcx2.f64(i32 0, double %1, i32 21)
# |   %3 = bitcast double %2 to i64
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.arm.cde.vcx2.f64(i32 immarg, double, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vcx2da_u64(i64 noundef %acc, i64 noundef %n) #0 {
# | entry:
# |   %acc.addr = alloca i64, align 8
# |   %n.addr = alloca i64, align 8
# |   store i64 %acc, ptr %acc.addr, align 8
# |   store i64 %n, ptr %n.addr, align 8
# |   %0 = load i64, ptr %acc.addr, align 8
# |   %1 = bitcast i64 %0 to double
# |   %2 = load i64, ptr %n.addr, align 8
# |   %3 = bitcast i64 %2 to double
# |   %4 = call double @llvm.arm.cde.vcx2a.f64(i32 0, double %1, double %3, i32 22)
# |   %5 = bitcast double %4 to i64
# |   ret i64 %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.arm.cde.vcx2a.f64(i32 immarg, double, double, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vcx3d_u64(i64 noundef %n, i64 noundef %m) #0 {
# | entry:
# |   %n.addr = alloca i64, align 8
# |   %m.addr = alloca i64, align 8
# |   store i64 %n, ptr %n.addr, align 8
# |   store i64 %m, ptr %m.addr, align 8
# |   %0 = load i64, ptr %n.addr, align 8
# |   %1 = bitcast i64 %0 to double
# |   %2 = load i64, ptr %m.addr, align 8
# |   %3 = bitcast i64 %2 to double
# |   %4 = call double @llvm.arm.cde.vcx3.f64(i32 1, double %1, double %3, i32 3)
# |   %5 = bitcast double %4 to i64
# |   ret i64 %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.arm.cde.vcx3.f64(i32 immarg, double, double, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vcx3da_u64(i64 noundef %acc, i64 noundef %n, i64 noundef %m) #0 {
# | entry:
# |   %acc.addr = alloca i64, align 8
# |   %n.addr = alloca i64, align 8
# |   %m.addr = alloca i64, align 8
# |   store i64 %acc, ptr %acc.addr, align 8
# |   store i64 %n, ptr %n.addr, align 8
# |   store i64 %m, ptr %m.addr, align 8
# |   %0 = load i64, ptr %acc.addr, align 8
# |   %1 = bitcast i64 %0 to double
# |   %2 = load i64, ptr %n.addr, align 8
# |   %3 = bitcast i64 %2 to double
# |   %4 = load i64, ptr %m.addr, align 8
# |   %5 = bitcast i64 %4 to double
# |   %6 = call double @llvm.arm.cde.vcx3a.f64(i32 0, double %1, double %3, double %5, i32 5)
# |   %7 = bitcast double %6 to i64
# |   ret i64 %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.arm.cde.vcx3a.f64(i32 immarg, double, double, double, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+cdecp0,+cdecp1,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005653e0c3eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005653e0c3be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005653e0c3f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ecc249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ecc2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ecc249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ecc231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005653e0bd4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005653e0bd4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005653e0bb98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005653e0868e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005653e0868b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3ecc232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ecc2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ecc2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005653e0868a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c (1457 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_f16mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_f16mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_f16m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_i16mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_i16mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_i16m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_u16mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_u16mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_u16m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_f16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.ri
# | ...
# `---data was truncated (10240/20449) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056038a508eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056038a505e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056038a50962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1195b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1195b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1195b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1195aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056038a49ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056038a49ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056038a4838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056038a132e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056038a132b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1195aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1195aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1195aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056038a132a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c (1458 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_f64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_f64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_f64m4x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_i64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_i64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_i64m4x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_u64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_u64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_
# | ...
# `---data was truncated (10240/11895) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec22c6ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ec22c69e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ec22c6d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe3a0f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe3a0f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe3a0f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe3a0eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec22c02bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ec22c02a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ec22be78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ec22896e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ec22896b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe3a0eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe3a0eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe3a0eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec22896a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c (1459 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei64_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei64_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei64_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei64_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei64_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei64_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei64_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei64_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vloxei64_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, <vscale x 1 
# | ...
# `---data was truncated (10240/215949) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005650e98f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005650e98efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005650e98f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f58cb333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f58cb38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f58cb333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f58cb31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005650e9888bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005650e9888a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005650e986d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005650e951ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005650e951cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f58cb31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f58cb31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f58cb31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005650e951ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c (1460 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsbc_vvm_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsbc_vxm_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsbc_vvm_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsbc_vxm_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsbc_vvm_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsbc_vxm_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsbc_vvm_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsbc_vxm_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, <vscale x 8 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsbc_vvm_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.ad
# | ...
# `---data was truncated (10240/98581) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c2411f7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c2411f4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c2411f862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e5b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e5b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e5b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e5b831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c24118dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c24118da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c2411728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c240e21e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c240e21b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7e5b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e5b8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e5b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c240e21a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c (1461 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_4x8x4_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_4x8x4_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_4x8x4_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_4x8x4_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ecb6742eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ecb673fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ecb674362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7b9d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7b9d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7b9d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7b9d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ecb66d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ecb66d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ecb66bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ecb636ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ecb636cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7b9d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7b9d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7b9d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ecb636ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c (1462 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8mf8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 5)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8mf4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 6)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8mf2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 7)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8m1(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8m2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8m4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8m8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16mf4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 6)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16mf2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 7)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16m1(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16m2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16m4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16m8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32mf2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 7)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32m1(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32m2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32m4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32m8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e64m1(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e64m2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e64m4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e64m8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 3)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dfd1931eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dfd192ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dfd193262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc9e5b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc9e5b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc9e5b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc9e5b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dfd18c7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dfd18c7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dfd18ac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dfd155be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dfd155bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc9e5b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc9e5b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc9e5b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dfd155ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c (1463 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svcreate4_s8(<vscale x 16 x i8> %x0, <vscale x 16 x i8> %x1, <vscale x 16 x i8> %x2, <vscale x 16 x i8> %x4) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i8>, align 16
# |   %x1.addr = alloca <vscale x 16 x i8>, align 16
# |   %x2.addr = alloca <vscale x 16 x i8>, align 16
# |   %x4.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %x0, ptr %x0.addr, align 16
# |   store <vscale x 16 x i8> %x1, ptr %x1.addr, align 16
# |   store <vscale x 16 x i8> %x2, ptr %x2.addr, align 16
# |   store <vscale x 16 x i8> %x4, ptr %x4.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %x2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %x4.addr, align 16
# |   %4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %0, 0
# |   %5 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, <vscale x 16 x i8> %1, 1
# |   %6 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, <vscale x 16 x i8> %2, 2
# |   %7 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6, <vscale x 16 x i8> %3, 3
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %7
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svcreate4_s16(<vscale x 8 x i16> %x0, <vscale x 8 x i16> %x1, <vscale x 8 x i16> %x2, <vscale x 8 x i16> %x4) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x i16>, align 16
# |   %x1.addr = alloca <vscale x 8 x i16>, align 16
# |   %x2.addr = alloca <vscale x 8 x i16>, align 16
# |   %x4.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x i16> %x1, ptr %x1.addr, align 16
# |   store <vscale x 8 x i16> %x2, ptr %x2.addr, align 16
# |   store <vscale x 8 x i16> %x4, ptr %x4.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %x2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %x4.addr, align 16
# |   %4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %0, 0
# |   %5 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, <vscale x 8 x i16> %1, 1
# |   %6 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5, <vscale x 8 x i16> %2, 2
# |   %7 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6, <vscale x 8 x i16> %3, 3
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %7
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svcreate4_s32(<vscale x 4 x i32> %x0, <vscale x 4 x i32> %x1, <vscale x 4 x i32> %x2, <vscale x 4 x i32> %x4) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 4 x i32>, align 16
# |   %x1.addr = alloca <vscale x 4 x i32>, align 16
# |   %x2.addr = alloca <vscale x 4 x i32>, align 16
# |   %x4.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %x0, ptr %x0.addr, align 16
# |   store <vscale x 4 x i32> %x1, ptr %x1.addr, align 16
# |   store <vscale x 4 x i32> %x2, ptr %x2.addr, align 16
# |   store <vscale x 4 x i32> %x4, ptr %x4.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %x2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %x4.addr, align 16
# |   %4 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %0, 0
# |   %5 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, <vscale x 4 x i32> %1, 1
# |   %6 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, <vscale x 4 x i32> %2, 2
# |   %7 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %6, <vscale x 4 x i32> %3, 3
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %7
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svcreate4_s64(<vscale x 2 x i64> %x0, <vscale x 2 x i64> %x1, <vscale x 2 x i64> %x2, <vscale x 2 x i64> %x4) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 2 x i64>, align 16
# |   %x1.addr = alloca <vscale x 2 x i64>, align 16
# |   %x2.addr = alloca <vscale x 2 x i64>, align 16
# |   %x4.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %x0, ptr %x0.addr, align 16
# |   store <vscale x 2 x i64> %x1, ptr %x1.addr, align 16
# |   store <vscale x 2 x i64> %x2, ptr %x2.addr, align 16
# |   store <vscale x 2 x i64> %x4, ptr %x4.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %x2.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %x4.addr, align 16
# |   %4 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %0, 0
# |   %5 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, <vscale x 2 x i64> %1, 1
# |   %6 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5, <vscale x 2 x i64> %2, 2
# |   %7 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %6, <vscale x 2 x i64> %3, 3
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %7
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svcreate4_u8(<vscale x 16 x i8> %x0, <vscale x 16 x i8> %x1, <vscale x 16 x i8> %x2, <vscale x 16 x i8> %x4) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i8>, align 16
# |   %x1.addr = alloca <vscale x 16 x i8>, align 16
# |   %x2.addr = alloca <vscale x 16 x i8>, align 16
# |   %x4.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %x0, ptr %x0.addr, align 16
# |   store <vscale x 16 x i8> %x1, ptr %x1.addr, align 16
# |   store <vscale x 16 x i8> %x2, ptr %x2.addr, align 16
# |   store <vscale x 16 x i8> %x4, ptr %x4.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %x2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %x4.addr, align 16
# |   %4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %0, 0
# |   %5 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, <vscale x 16 x i8> %1, 1
# |   %6 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, <vscale x 16 x i8> %2, 2
# |   %7 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6, <vscale x 16 x i8> %3, 3
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %7
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svcreate4_u16(<vscale x 8 x i16> %x0, <vscale x 8 x i16> %x1, <vscale x 8 x i16> %x2, <vscale x 8 x i16> %x4) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x i16>, align 16
# |   %x1.addr = alloca <vscale x 8 x i16>, align 16
# |   %x2.addr = alloca <vscale x 8 x i16>, align 16
# |   %x4.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x i16> %x1, ptr %x1.addr, align 16
# |   store <vscale x 8 x i16> %x2, ptr %x2.addr, align 16
# |   store <vscale x 8 x i16> %x4, ptr %x4.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %x2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %x4.addr, align 16
# |   %4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %0, 0
# |   %5 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, <vscale x 8 x i16> %1, 1
# |   %6 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5, <vscale x 8 x i16> %2, 2
# |   %7 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6, <vscale x 8 x i16> %3, 3
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %7
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svcreate4_u32(<vscale x 4 x i32> %x0, <vscale x 4 x i32> %x1, <vscale x 4 x i32> %x2, <vscale x 4 x i32> %x4) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 4 x i32>, align 16
# |   %x1.addr = alloca <vscale x 4 x i32>, align 16
# |   %x2.addr = alloca <vscale x 4 x i32>, align 16
# |   %x4.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %x0, ptr %x0.addr, align 16
# |   store <vscale x 4 x i32> %x1, ptr %x1.addr, align 16
# |   store <vs
# | ...
# `---data was truncated (10240/21212) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005607f8cabeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005607f8ca8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005607f8cac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd273933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd27398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd273933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd27391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607f8c41bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005607f8c41a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005607f8c268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005607f88d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005607f88d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd27391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd27391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd27391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607f88d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c (1464 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005561ae484eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005561ae481e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005561ae48562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9403e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9403ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9403e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9403e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005561ae41abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005561ae41aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005561ae3ff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005561ae0aee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005561ae0aeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9403e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9403e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9403e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005561ae0aea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c (1465 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f16m1x5(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f32m1x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f64m1x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef
# | ...
# `---data was truncated (10240/69988) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056159f5c3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056159f5c0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056159f5c462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1a29a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1a29aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1a29a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1a29a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056159f559bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056159f559a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056159f53e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056159f1ede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056159f1edb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1a29a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1a29a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1a29a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056159f1eda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c (1466 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m1(ptr noundef %base, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x double>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1f64.p0.i64(<vscale x 1 x double> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m2(ptr noundef %base, <vscale x 2 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x double>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2f64.p0.i64(<vscale x 2 x double> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m4(ptr noundef %base, <vscale x 4 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x double>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4f64.p0.i64(<vscale x 4 x double> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m8(ptr noundef %base, <vscale x 8 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x double>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8f64.p0.i64(<vscale x 8 x double> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_i64m1(ptr noundef %base, <vscale x 1 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i64.p0.i64(<vscale x 1 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_i64m2(ptr noundef %base, <vscale x 2 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i64.p0.i64(<vscale x 2 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_i64m4(ptr noundef %base, <vscale x 4 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i64.p0.i64(<vscale x 4 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_i64m8(ptr noundef %base, <vscale x 8 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i64.p0.i64(<vscale x 8 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_u64m1(ptr noundef %base, <vscale x 1 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i64.p0.i64(<vscale x 1 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_u64m2(ptr noundef %base, <vscale x 2 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i64.p0.i64(<vscale x 2 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_u64m4(ptr noundef %base, <vscale x 4 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i64.p0.i64(<vscale x 4 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_u64m8(ptr noundef %base, <vscale x 8 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i64.p0.i64(<vscale x 8 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 
# | ...
# `---data was truncated (10240/22890) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f86e9deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564f86e9ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564f86e9e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2253733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f225378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2253733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f225371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f86e33bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564f86e33a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564f86e188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564f86ac7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564f86ac7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f225371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f225371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f225371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f86ac7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c (1467 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_i32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_i32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_u32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_u32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561761585eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561761582e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056176158662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f635ad05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f635ad5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f635ad05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f635aced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056176151bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056176151ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005617615008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005617611afe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005617611afb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f635aceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f635acef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f635acef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005617611afa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c (1468 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vbrev_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vbrev_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vbrev.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vbrev.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vbrev_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vbrev.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vbrev.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vbrev_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vbrev.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vbrev.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vbrev_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vbrev.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vbrev.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vbrev_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vbrev.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vbrev.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vbrev_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vbrev.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vbrev.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vbrev_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vbrev.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vbrev.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vbrev_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vbrev.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vbrev.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vbrev_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vbrev.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vbrev.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vbrev_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vbrev.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vbrev.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vbrev_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vbrev.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vbrev.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vbrev_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vbrev.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback n
# | ...
# `---data was truncated (10240/40795) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563f762e8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563f762e5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563f762e962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f66bf249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f66bf2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f66bf249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f66bf231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563f7627ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563f7627ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563f762638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563f75f12e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563f75f12b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f66bf232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f66bf2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f66bf2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563f75f12a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/X86/bfloat16-convert-half.c (1469 of 27911)
******************** TEST 'Clang :: CodeGen/X86/bfloat16-convert-half.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -disable-O0-optnone -emit-llvm    /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_convert_from_bf16_to_fp16(bfloat noundef %a) #0 {
# | entry:
# |   %a.addr = alloca bfloat, align 2
# |   store bfloat %a, ptr %a.addr, align 2
# |   %0 = load bfloat, ptr %a.addr, align 2
# |   %fpext = fpext bfloat %0 to float
# |   %fptrunc = fptrunc float %fpext to half
# |   ret half %fptrunc
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local bfloat @test_convert_from_fp16_to_bf16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   %fpext = fpext half %0 to float
# |   %fptrunc = fptrunc float %fpext to bfloat
# |   ret bfloat %fptrunc
# | }
# | 
# | attributes #0 = { noinline nounwind "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557d35527eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557d35524e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557d3552862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec78f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec78f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec78f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec78f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557d354bdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557d354bda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557d354a28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557d35151e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557d35151b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fec78f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec78f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec78f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557d35151a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c (1470 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesz_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesz_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesz_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesz_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesz_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesz_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesz_vs_u32m1_u32m8(<vscale x 16 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32m2_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willret
# | ...
# `---data was truncated (10240/15203) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557af5789eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557af5786e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557af578a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f42bd649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42bd6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f42bd649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f42bd631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557af571fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557af571fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557af57048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557af53b3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557af53b3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f42bd632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42bd6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42bd6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557af53b3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c (1471 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvpackfph -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadb_vf_f16mf4(<vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadb_vf_f16mf2(<vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadb_vf_f16m1(<vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadb_vf_f16m2(<vscale x 8 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half>, <vscale x 8 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_nds_vfpmadb_vf_f16m4(<vscale x 16 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half>, <vscale x 16 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_nds_vfpmadb_vf_f16m8(<vscale x 32 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half>, <vscale x 32 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadb_vf_f16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %1, float %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadb_vf_f16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %1, float %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadb_vf_f16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %1, float %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadb_vf_f16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x half> %op1, float noun
# | ...
# `---data was truncated (10240/25091) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c03305feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c03305ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c03306062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc0d4649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc0d46a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc0d4649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc0d4631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c032ff5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c032ff5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c032fda8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c032c89e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c032c89b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc0d4632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc0d46330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc0d46330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c032c89a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c (1472 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosy
# | ...
# `---data was truncated (10240/12666) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055769662ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557696629e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055769662d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcf9a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcf9a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcf9a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcf9a231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005576965c2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005576965c2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005576965a78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557696256e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557696256b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcf9a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcf9a2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcf9a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557696256a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c (1473 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei8_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = loa
# | ...
# `---data was truncated (10240/14529) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557b80a4feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557b80a4ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557b80a5062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9d98533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9d9858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9d98533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9d9851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b809e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557b809e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557b809ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557b80679e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557b80679b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9d9851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9d9851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9d9851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b80679a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c (1474 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsra_wv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsra_wx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsra_wv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsra_wx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsra_wv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsra_wx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsra_wv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsra_wx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsra_wv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vsca
# | ...
# `---data was truncated (10240/154601) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e6fcf06eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e6fcf03e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e6fcf0762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f03ef533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03ef58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f03ef533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f03ef51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e6fce9cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e6fce9ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e6fce818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e6fcb30e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e6fcb30b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f03ef51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03ef51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03ef51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e6fcb30a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c (1475 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_i32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_i32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_u32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_u32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_f32mf2x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple"
# | ...
# `---data was truncated (10240/35929) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005600697a8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005600697a5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005600697a962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f140a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f140a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f140a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f140a431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056006973ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056006973ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005600697238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005600693d2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005600693d2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f140a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f140a4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f140a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005600693d2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c (1476 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_i64m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_u64m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005562d3aa5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005562d3aa2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005562d3aa662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb5c0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb5c08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb5c0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb5c0831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005562d3a3bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005562d3a3ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005562d3a208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005562d36cfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005562d36cfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb5c0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb5c08330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb5c08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005562d36cfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c (1477 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasubu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasubu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasubu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasubu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasubu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasubu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasubu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasubu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasubu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasubu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vsc
# | ...
# `---data was truncated (10240/99843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556b8c7a0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556b8c79de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556b8c7a162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe28ad05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe28ad5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe28ad05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe28aced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b8c736bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556b8c736a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556b8c71b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556b8c3cae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556b8c3cab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe28aceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe28acef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe28acef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b8c3caa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c (1478 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f16m1x7(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f32m1x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f64m1x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005573c5d6beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005573c5d68e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005573c5d6c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f41b8649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f41b86a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f41b8649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f41b8631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005573c5d01bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005573c5d01a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005573c5ce68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005573c5995e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005573c5995b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f41b8632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f41b86330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f41b86330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005573c5995a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c (1479 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16mf2_f16mf4(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv2f16(<vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv2f16(<vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16m1_f16mf4(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv4f16(<vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv4f16(<vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_trunc_v_f16m1_f16mf2(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv4f16(<vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv4f16(<vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16m2_f16mf4(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv8f16(<vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_trunc_v_f16m2_f16mf2(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_trunc_v_f16m2_f16m1(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16m4_f16mf4(<vscale x 16 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_trunc_v_f16m4_f16mf2(<vscale x 16 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_trunc_v_f16m4_f16m1(<vscale x 16 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_trunc_v_f16m4_f16m2(<vscale x 16 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16m8_f16mf4(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_trunc_v_f16m8_f16mf2(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_trunc_v_f16m8_f16m1(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_trunc_v_f16m8_f16m2(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_trunc_v_f16m8_f16m4(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half>, i64 im
# | ...
# `---data was truncated (10240/78242) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dd04052eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dd0404fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dd0405362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e6c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e6c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e6c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e6c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd03fe8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dd03fe8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dd03fcd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dd03c7ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dd03c7cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8e6c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e6c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e6c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd03c7ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c (1480 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i64> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i64> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8_tum(<vscale x 8 x i1> %mask, <vscale x 8 x i64> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_tumu(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64>
# | ...
# `---data was truncated (10240/18217) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb7e075eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fb7e072e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fb7e07662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fabcc933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fabcc98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fabcc933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fabcc91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb7e00bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fb7e00ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fb7dff08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fb7dc9fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fb7dc9fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fabcc91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fabcc91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fabcc91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb7dc9fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c (1481 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhsu_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhsu_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i
# | ...
# `---data was truncated (10240/223809) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac95c7ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ac95c79e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ac95c7d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f81fad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f81fad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f81fad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f81fad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac95c12bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ac95c12a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ac95bf78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ac958a6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ac958a6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f81fad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f81fad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f81fad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac958a6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c (1482 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dots_vv_i32mf2(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dots_vv_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dots_vv_i32m2(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dots_vv_i32m4(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dots_vv_i32m8(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dots_vv_i64m1(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dots_vv_i64m2(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dots_vv_i64m4(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv
# | ...
# `---data was truncated (10240/25519) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a05e96ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a05e969e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a05e96d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac01933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac0198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac01933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac0191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a05e902bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a05e902a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a05e8e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a05e596e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a05e596b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fac0191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac0191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac0191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a05e596a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c (1483 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_i64m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_u64m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055671d9c9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055671d9c6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055671d9ca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee4b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee4b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee4b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee4b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055671d95fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055671d95fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055671d9448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055671d5f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055671d5f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fee4b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee4b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee4b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055671d5f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c (1484 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssra_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssra_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssra_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssra_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssra_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssra_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssra_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssra_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssra_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, al
# | ...
# `---data was truncated (10240/226593) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f2a9031eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f2a902ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f2a903262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5494249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54942a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5494249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5494231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f2a8fc7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f2a8fc7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f2a8fac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f2a8c5be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f2a8c5bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5494232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54942330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54942330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f2a8c5ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c (1485 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm3me_vv_u32mf2(<vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm3me_vv_u32m1(<vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm3me_vv_u32m2(<vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm3me_vv_u32m4(<vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm3me_vv_u32m8(<vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558bd1100eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558bd10fde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558bd110162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f200e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f200e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f200e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f200e71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558bd1096bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558bd1096a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558bd107b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558bd0d2ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558bd0d2ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f200e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f200e71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f200e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558bd0d2aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c (1486 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrsqrt7_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrsqrt7_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrsqrt7_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrsqrt7_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrsqrt7_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrsqrt7_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrsqrt7_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrsqrt7_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrsqrt7_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrsqrt7_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |  
# | ...
# `---data was truncated (10240/67482) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555b7e024eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555b7e021e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555b7e02562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f42f8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42f818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f42f8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f42f811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b7dfbabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555b7dfbaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555b7df9f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555b7dc4ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555b7dc4eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f42f811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42f811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42f811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b7dc4ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c (1487 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_i32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_i32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_u32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_u32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f9ce33beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f9ce338e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f9ce33c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2669133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f266918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2669133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f266911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f9ce2d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f9ce2d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f9ce2b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f9cdf65e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f9cdf65b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f266911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f266911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f266911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f9cdf65a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c (1488 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgt_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgt_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgt_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgt_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgt_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgt_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgt_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | 
# | ...
# `---data was truncated (10240/63571) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f02b7c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f02b7bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f02b7c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1821d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1821d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1821d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1821d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f02b757bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f02b757a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f02b73c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f02b3ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f02b3ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1821d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1821d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1821d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f02b3eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c (1489 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_f32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_f32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_f32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_i32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_i32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_i32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_u32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_u32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_u32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.v
# | ...
# `---data was truncated (10240/23413) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005618cfdb4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005618cfdb1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005618cfdb562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1906b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1906b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1906b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1906aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005618cfd4abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005618cfd4aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005618cfd2f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005618cf9dee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005618cf9deb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1906aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1906aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1906aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005618cf9dea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/f16f32dot-intrinsics.c (1490 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/f16f32dot-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +f16f32dot -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +f16f32dot -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vdot_f32_f16(<2 x float> noundef %r, <4 x half> noundef %a, <4 x half> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   store <2 x float> %r, ptr %r.addr, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %r.addr, align 8
# |   %1 = load <4 x half>, ptr %a.addr, align 8
# |   %2 = load <4 x half>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vdot1.i = bitcast <8 x i8> %4 to <4 x half>
# |   %vdot2.i = bitcast <8 x i8> %5 to <4 x half>
# |   %vdot3.i = call <2 x float> @llvm.aarch64.neon.fdot.v2f32.v4f16(<2 x float> %vdot.i, <4 x half> %vdot1.i, <4 x half> %vdot2.i)
# |   store <2 x float> %vdot3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vdotq_f32_f16(<4 x float> noundef %r, <8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %r.addr = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   store <4 x float> %r, ptr %r.addr, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %r.addr, align 16
# |   %1 = load <8 x half>, ptr %a.addr, align 16
# |   %2 = load <8 x half>, ptr %b.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vdot.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vdot1.i = bitcast <16 x i8> %4 to <8 x half>
# |   %vdot2.i = bitcast <16 x i8> %5 to <8 x half>
# |   %vdot3.i = call <4 x float> @llvm.aarch64.neon.fdot.v4f32.v8f16(<4 x float> %vdot.i, <8 x half> %vdot1.i, <8 x half> %vdot2.i)
# |   store <4 x float> %vdot3.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vdot_lane_f32_f16(<2 x float> noundef %r, <4 x half> noundef %a, <4 x half> noundef %b) #0 {
# | entry:
# |   %r.addr = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %__ret = alloca <2 x float>, align 8
# |   %__s0 = alloca <2 x float>, align 8
# |   %__s1 = alloca <4 x half>, align 8
# |   %__s2 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x float>, align 8
# |   store <2 x float> %r, ptr %r.addr, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %r.addr, align 8
# |   store <2 x float> %0, ptr %__s0, align 8
# |   %1 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %1, ptr %__s1, align 8
# |   %2 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %2, ptr %__s2, align 8
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <8 x i8>, ptr %__s2, align 8
# |   %6 = bitcast <8 x i8> %5 to <4 x half>
# |   %lane = shufflevector <4 x half> %6, <4 x half> %6, <4 x i32> zeroinitializer
# |   %vdot = bitcast <8 x i8> %3 to <2 x float>
# |   %vdot1 = bitcast <8 x i8> %4 to <4 x half>
# |   %vdot2 = call <2 x float> @llvm.aarch64.neon.fdot.v2f32.v4f16(<2 x float> %vdot, <4 x half> %vdot1, <4 x half> %lane)
# |   store <2 x float> %vdot2, ptr %ref.tmp, align 8
# |   %7 = load <2 x float>, ptr %ref.tmp, align 8
# |   store <2 x float> %7, ptr %__ret, align 8
# |   %8 = load <2 x float>, ptr %__ret, align 8
# |   store <2 x float> %8, ptr %tmp, align 8
# |   %9 = load <2 x float>, ptr %tmp, align 8
# |   ret <2 x float> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x float> @llvm.aarch64.neon.fdot.v2f32.v4f16(<2 x float>, <4 x half>, <4 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vdot_laneq_f32_f16(<2 x float> noundef %r, <4 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %r.addr = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 16
# |   %__ret = alloca <2 x float>, align 8
# |   %__s0 = alloca <2 x float>, align 8
# |   %__s1 = alloca <4 x half>, align 8
# |   %__s2 = alloca <8 x half>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x float>, align 8
# |   store <2 x float> %r, ptr %r.addr, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <2 x float>, ptr %r.addr, align 8
# |   store <2 x float> %0, ptr %__s0, align 8
# |   %1 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %1, ptr %__s1, align 8
# |   %2 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %2, ptr %__s2, align 16
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <16 x i8>, ptr %__s2, align 16
# |   %6 = bitcast <16 x i8> %5 to <8 x half>
# |   %lane = shufflevector <8 x half> %6, <8 x half> %6, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
# |   %vdot = bitcast <8 x i8> %3 to <2 x float>
# |   %vdot1 = bitcast <8 x i8> %4 to <4 x half>
# |   %vdot2 = call <2 x float> @llvm.aarch64.neon.fdot.v2f32.v4f16(<2 x float> %vdot, <4 x half> %vdot1, <4 x half> %lane)
# |   store <2 x float> %vdot2, ptr %ref.tmp, align 8
# |   %7 = load <2 x float>, ptr %ref.tmp, align 8
# |   store <2 x float> %7, ptr %__ret, align 8
# |   %8 = load <2 x float>, ptr %__ret, align 8
# |   store <2 x float> %8, ptr %tmp, align 8
# |   %9 = load <2 x float>, ptr %tmp, align 8
# |   ret <2 x float> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vdotq_lane_f32_f16(<4 x float> noundef %r, <8 x half> noundef %a, <4 x half> noundef %b) #0 {
# | entry:
# |   %r.addr = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <4 x half>, align 8
# |   %__ret = alloca <4 x float>, align 16
# |   %__s0 = alloca <4 x float>, align 16
# |   %__s1 = alloca <8 x half>, align 16
# |   %__s2 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x float>, align 16
# |   store <4 x float> %r, ptr %r.addr, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %r.addr, align 16
# |   store <4 x float> %0, ptr %__s0, align 16
# |   %1 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %1, ptr %__s1, align 16
# |   %2 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %2, ptr %__s2, align 8
# |   %3 = load <16 x i8>, ptr %__s0, align 16
# |   %4 = load <16 x i8>, ptr %__s1, align 16
# |   %5 = load <8 x i8>, ptr %__s2, align 8
# |   %6 = bitcast <8 x i8> %5 to <4 x half>
# |   %lane = shufflevector <4 x half> %6, <4 x half> %6, <8 x i32> zeroinitializer
# |   %vdot = bitcast <16 x i8> %3 to <4 x float>
# |   %vdot1 = bitcast <16 x i8> %4 to <8 x half>
# |   %vdot2 = call <4 x float> @llvm.aarch64.neon.fdot.v4f32.v8f16(<4 x float> %vdot, <8 x half> %vdot1, <8 x half> %lane)
# |   store <4 x float> %vdot2, ptr %ref.tmp, align 16
# |   %7 = load <4 x float>, ptr %ref.tmp, align 16
# |   store <4 x float> %7, ptr %__ret, align 16
# |   %8 = load <4 x float>, ptr %__ret, align 16
# |   store <4 x float> %8, ptr %tmp, align 16
# |   %9 = load <4 x float>, ptr %tmp, align 16
# |   ret <4 x float> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.aarch64.neon.fdot.v4f32.v8f16(<4 x float>, <8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vdotq_laneq_f32_f16(<4 x float> noundef %r, <8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %r.addr = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %__ret = alloca <4 x float>, align 16
# |   %__s0 = alloca <4 x float>, align 16
# |   %__s1 = alloca <8 x half>, align 16
# |   %__s2 = alloca <8 x half>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x float>, align 16
# |   store <4 x float> %r, ptr %r.addr, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %r.addr, align 16
# |   store <4 x float> %0, ptr %__s0, align 16
# |   %1 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %1, ptr %__s1, align 16
# |   %2 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %2, ptr %__s2, align 16
# |   %3 = load <16 x i8>, ptr %__s0, align 16
# |   %4 = load <16 x i8>, ptr %__s1, align 16
# |   %5 = load <16 x i8>, ptr %__s2, align 16
# |   %6 = bitcast <16 x i8> %5 to <8 x half>
# |   %lane = shufflevector <8 x half> %6, <8 x half> %6, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
# |   %vdot = bitcast <16 x i8> %3 to <4 x float>
# |   %vdot1 = bitcast <16 x i8> %4 to <8 x half>
# |   %vdot2 = call <4 x float> @llvm.aa
# | ...
# `---data was truncated (10240/11256) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# |  #0 0x00005562c0653eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005562c0650e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005562c065462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f653ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f653ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f653ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f653ff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005562c05e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005562c05e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005562c05ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005562c027de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005562c027db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f653ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f653ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f653ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005562c027da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c (1491 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfclass_v_u16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfclass_v_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfclass_v_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfclass_v_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfclass_v_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8f32.i64(<vscale x 8 x i32> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function 
# | ...
# `---data was truncated (10240/66322) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055705dc24eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055705dc21e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055705dc2562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcadf849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcadf8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcadf849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcadf831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055705dbbabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055705dbbaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055705db9f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055705d84ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055705d84eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcadf832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcadf8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcadf8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055705d84ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/v8.1a-neon-intrinsics.c (1492 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/v8.1a-neon-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-linux-gnu -target-feature +neon   -target-feature +v8.1a -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-linux-gnu -target-feature +neon -target-feature +v8.1a -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-unknown-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vqrdmlah_laneq_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <8 x i16> noundef %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__p2.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   %v.addr = alloca <8 x i16>, align 16
# |   %__ret_790 = alloca <4 x i16>, align 8
# |   %__s0_790 = alloca <4 x i16>, align 8
# |   %__s1_790 = alloca <4 x i16>, align 8
# |   %__s2_790 = alloca <8 x i16>, align 16
# |   %__ret = alloca <4 x i16>, align 8
# |   %__s0 = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x i16>, align 8
# |   %tmp1 = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %v, ptr %v.addr, align 16
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__s0_790, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %1, ptr %__s1_790, align 8
# |   %2 = load <8 x i16>, ptr %v.addr, align 16
# |   store <8 x i16> %2, ptr %__s2_790, align 16
# |   %3 = load <4 x i16>, ptr %__s0_790, align 8
# |   %4 = load <4 x i16>, ptr %__s1_790, align 8
# |   %5 = load <8 x i16>, ptr %__s2_790, align 16
# |   store <8 x i16> %5, ptr %__s0, align 16
# |   %6 = load <16 x i8>, ptr %__s0, align 16
# |   %7 = bitcast <16 x i8> %6 to <8 x i16>
# |   %lane = shufflevector <8 x i16> %7, <8 x i16> %7, <4 x i32> <i32 7, i32 7, i32 7, i32 7>
# |   store <4 x i16> %lane, ptr %ref.tmp, align 8
# |   %8 = load <4 x i16>, ptr %ref.tmp, align 8
# |   store <4 x i16> %8, ptr %__ret, align 8
# |   %9 = load <4 x i16>, ptr %__ret, align 8
# |   store <4 x i16> %9, ptr %tmp, align 8
# |   %10 = load <4 x i16>, ptr %tmp, align 8
# |   store <4 x i16> %3, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %4, ptr %__p1.addr.i, align 8
# |   store <4 x i16> %10, ptr %__p2.addr.i, align 8
# |   %11 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vqrdmlah_s16.i = bitcast <8 x i8> %11 to <4 x i16>
# |   %vqrdmlah_s161.i = bitcast <8 x i8> %12 to <4 x i16>
# |   %vqrdmlah_s162.i = bitcast <8 x i8> %13 to <4 x i16>
# |   %vqrdmlah_s163.i = call <4 x i16> @llvm.aarch64.neon.sqrdmlah.v4i16(<4 x i16> %vqrdmlah_s16.i, <4 x i16> %vqrdmlah_s161.i, <4 x i16> %vqrdmlah_s162.i)
# |   %vqrdmlah_s164.i = bitcast <4 x i16> %vqrdmlah_s163.i to <8 x i8>
# |   store <8 x i8> %vqrdmlah_s164.i, ptr %ref.tmp.i, align 8
# |   %14 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %14, ptr %__ret.i, align 8
# |   %15 = load <4 x i16>, ptr %__ret.i, align 8
# |   store <4 x i16> %15, ptr %__ret_790, align 8
# |   %16 = load <4 x i16>, ptr %__ret_790, align 8
# |   store <4 x i16> %16, ptr %tmp1, align 8
# |   %17 = load <4 x i16>, ptr %tmp1, align 8
# |   ret <4 x i16> %17
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vqrdmlah_laneq_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <4 x i32> noundef %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__p2.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   %v.addr = alloca <4 x i32>, align 16
# |   %__ret_788 = alloca <2 x i32>, align 8
# |   %__s0_788 = alloca <2 x i32>, align 8
# |   %__s1_788 = alloca <2 x i32>, align 8
# |   %__s2_788 = alloca <4 x i32>, align 16
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <4 x i32>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   %tmp1 = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %v, ptr %v.addr, align 16
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0_788, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   store <2 x i32> %1, ptr %__s1_788, align 8
# |   %2 = load <4 x i32>, ptr %v.addr, align 16
# |   store <4 x i32> %2, ptr %__s2_788, align 16
# |   %3 = load <2 x i32>, ptr %__s0_788, align 8
# |   %4 = load <2 x i32>, ptr %__s1_788, align 8
# |   %5 = load <4 x i32>, ptr %__s2_788, align 16
# |   store <4 x i32> %5, ptr %__s0, align 16
# |   %6 = load <16 x i8>, ptr %__s0, align 16
# |   %7 = bitcast <16 x i8> %6 to <4 x i32>
# |   %lane = shufflevector <4 x i32> %7, <4 x i32> %7, <2 x i32> <i32 3, i32 3>
# |   store <2 x i32> %lane, ptr %ref.tmp, align 8
# |   %8 = load <2 x i32>, ptr %ref.tmp, align 8
# |   store <2 x i32> %8, ptr %__ret, align 8
# |   %9 = load <2 x i32>, ptr %__ret, align 8
# |   store <2 x i32> %9, ptr %tmp, align 8
# |   %10 = load <2 x i32>, ptr %tmp, align 8
# |   store <2 x i32> %3, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %4, ptr %__p1.addr.i, align 8
# |   store <2 x i32> %10, ptr %__p2.addr.i, align 8
# |   %11 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vqrdmlah_s32.i = bitcast <8 x i8> %11 to <2 x i32>
# |   %vqrdmlah_s321.i = bitcast <8 x i8> %12 to <2 x i32>
# |   %vqrdmlah_s322.i = bitcast <8 x i8> %13 to <2 x i32>
# |   %vqrdmlah_s323.i = call <2 x i32> @llvm.aarch64.neon.sqrdmlah.v2i32(<2 x i32> %vqrdmlah_s32.i, <2 x i32> %vqrdmlah_s321.i, <2 x i32> %vqrdmlah_s322.i)
# |   %vqrdmlah_s324.i = bitcast <2 x i32> %vqrdmlah_s323.i to <8 x i8>
# |   store <8 x i8> %vqrdmlah_s324.i, ptr %ref.tmp.i, align 8
# |   %14 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %14, ptr %__ret.i, align 8
# |   %15 = load <2 x i32>, ptr %__ret.i, align 8
# |   store <2 x i32> %15, ptr %__ret_788, align 8
# |   %16 = load <2 x i32>, ptr %__ret_788, align 8
# |   store <2 x i32> %16, ptr %tmp1, align 8
# |   %17 = load <2 x i32>, ptr %tmp1, align 8
# |   ret <2 x i32> %17
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vqrdmlahq_laneq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__p2.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   %v.addr = alloca <8 x i16>, align 16
# |   %__ret_786 = alloca <8 x i16>, align 16
# |   %__s0_786 = alloca <8 x i16>, align 16
# |   %__s1_786 = alloca <8 x i16>, align 16
# |   %__s2_786 = alloca <8 x i16>, align 16
# |   %__ret = alloca <8 x i16>, align 16
# |   %__s0 = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x i16>, align 16
# |   %tmp1 = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x i16> %b, ptr %b.addr, align 16
# |   store <8 x i16> %v, ptr %v.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__s0_786, align 16
# |   %1 = load <8 x i16>, ptr %b.addr, align 16
# |   store <8 x i16> %1, ptr %__s1_786, align 16
# |   %2 = load <8 x i16>, ptr %v.addr, align 16
# |   store <8 x i16> %2, ptr %__s2_786, align 16
# |   %3 = load <8 x i16>, ptr %__s0_786, align 16
# |   %4 = load <8 x i16>, ptr %__s1_786, align 16
# |   %5 = load <8 x i16>, ptr %__s2_786, align 16
# |   store <8 x i16> %5, ptr %__s0, align 16
# |   %6 = load <16 x i8>, ptr %__s0, align 16
# |   %7 = bitcast <16 x i8> %6 to <8 x i16>
# |   %lane = shufflevector <8 x i16> %7, <8 x i16> %7, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
# |   store <8 x i16> %lane, ptr %ref.tmp, align 16
# |   %8 = load <8 x i16>, ptr %ref.tmp, align 16
# |   store <8 x i16> %8, ptr %__ret, align 16
# |   %9 = load <8 x i16>, ptr %__ret, align 16
# |   store <8 x i16> %9, ptr %tmp, align 16
# |   %10 = load <8 x i16>, ptr %tmp, align 16
# |   store <8 x i16> %3, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %4, ptr %__p1.addr.i, align 16
# |   store <8 x i16> %10, ptr %__p2.addr.i, align 16
# |   %11 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %12 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %13 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vqrdmlahq_s16.i = bitcast <16 x i8> %11 to <8 x i16>
# |   %vqrdmlahq_s161.i = bitcast <16 x i8> %12 to <8 x i16>
# |   %vqrdmlahq_s162.i = bitcast <16 x i8> %13 to <8 x i16>
# |   %vqrdmlahq_s163.i = call <8 x i16> @llvm.aarch64.neon.sqrdmlah.v8i16(<8 x i16> %vqrdmlahq_s16.i, <8 x i16> %vqrdmlahq_s161.i, <8 x i16> %vqrdmlahq_s162.i)
# |   %vqrdmlahq_s164.i = bitcast <8 x i16> %vqrdmlahq_s163.i to <16 x i8>
# |   store <16 x i8> %vqrdmlahq_s164.i, ptr %ref.tmp.i, align 16
# |   %14 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %14, ptr %__ret.i, align 16
# |   %15 = load <8 x i16>, ptr %__ret.i, align 16
# |   store <8 x i16> %15, ptr %__ret_786, align 16
# |   %16 = load <8 x i16>, ptr %__ret_786, align 16
# |   store <8 x i16> %16, ptr %tmp1, align 16
# |   %17 = load <8 x i16>, ptr %tmp1, align 16
# |   ret <8 x i16> %17
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vqrdmlahq_laneq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <4 x i32>, align 16
# |   %__p2.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <4 x i32>, align 16
# |   %v.addr = alloca <4 x i32>, align 16
# |   %__ret_784 = alloca <4 x i32>, align 16
# |   %__s0_784 = alloca <4 x i32>, align 16
# |   %__s1_784 = alloca <4 x i32>, align 16
# |   %__s2_784 = alloca <4 x i32>, align 16
# |   %__ret = alloca <4 x i32>, align 16
# |   %__s0 = alloca <4 x i32>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x i32>, align 16
# |   %tmp1 = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <4 x i32> %b, ptr %b.addr, align 16
# |   store <4 x i32> %v, ptr %v.addr, align 16
# |   %0 = load <4
# | ...
# `---data was truncated (10240/50621) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S
# |  #0 0x000055d2d2455eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d2d2452e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d2d245662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe286d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe286d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe286d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe286d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d2d23ebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d2d23eba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d2d23d08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d2d207fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d2d207fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe286d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe286d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe286d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d2d207fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c (1493 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei32_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a1273efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a1273ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a1273f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb83f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb83f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb83f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb83f831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a127385bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a127385a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a12736a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a127019e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a127019b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb83f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb83f8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb83f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a127019a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c (1494 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_v
# | ...
# `---data was truncated (10240/228865) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560bb8a59eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560bb8a56e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560bb8a5a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6d69933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6d6998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6d69933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6d6991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560bb89efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560bb89efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560bb89d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560bb8683e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560bb8683b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6d6991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6d6991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6d6991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560bb8683a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c (1495 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005599fd9eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005599fd9ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005599fd9ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1374449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13744a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1374449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1374431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005599fd984bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005599fd984a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005599fd9698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005599fd618e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005599fd618b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1374432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13744330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13744330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005599fd618a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c (1496 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4k_vi_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4k_vi_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4k_vi_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4k_vi_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm4k_vi_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b7cf696eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b7cf693e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b7cf69762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5f1d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5f1d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5f1d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5f1d31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b7cf62cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b7cf62ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b7cf6118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b7cf2c0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b7cf2c0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5f1d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5f1d31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5f1d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b7cf2c0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c (1497 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f16m1x4(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f16m2x4(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f32m1x4(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f32m2x4(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f64m1x4(ptr noundef %base, <vscale x 1 x i64
# | ...
# `---data was truncated (10240/94235) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056169da15eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056169da12e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056169da1662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5537449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f55374a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5537449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5537431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056169d9abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056169d9aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056169d9908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056169d63fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056169d63fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5537432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f55374330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f55374330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056169d63fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c (1498 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei16_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dfd2930eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dfd292de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dfd293162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f49d1a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f49d1aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f49d1a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f49d1a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dfd28c6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dfd28c6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dfd28ab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dfd255ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dfd255ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f49d1a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f49d1a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f49d1a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dfd255aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/neon/rounding.c (1499 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/rounding.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c --check-prefixes=LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrnd_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndz.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrndz1.i = call <2 x float> @llvm.trunc.v2f32(<2 x float> %vrndz.i)
# |   store <2 x float> %vrndz1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrndz.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndz1.i = call <4 x float> @llvm.trunc.v4f32(<4 x float> %vrndz.i)
# |   store <4 x float> %vrndz1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vrnd_f64(<1 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__ret.i = alloca <1 x double>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndz.i = bitcast <8 x i8> %1 to <1 x double>
# |   %vrndz1.i = call <1 x double> @llvm.trunc.v1f64(<1 x double> %vrndz.i)
# |   store <1 x double> %vrndz1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <1 x double>, ptr %ref.tmp.i, align 8
# |   store <1 x double> %2, ptr %__ret.i, align 8
# |   %3 = load <1 x double>, ptr %__ret.i, align 8
# |   ret <1 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vrndq_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrndz.i = bitcast <16 x i8> %1 to <2 x double>
# |   %vrndz1.i = call <2 x double> @llvm.trunc.v2f64(<2 x double> %vrndz.i)
# |   store <2 x double> %vrndz1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <2 x double>, ptr %ref.tmp.i, align 16
# |   store <2 x double> %2, ptr %__ret.i, align 16
# |   %3 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrndn_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndn.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrndn1.i = call <2 x float> @llvm.roundeven.v2f32(<2 x float> %vrndn.i)
# |   store <2 x float> %vrndn1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndnq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrndn.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndn1.i = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %vrndn.i)
# |   store <4 x float> %vrndn1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vrndn_f64(<1 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__ret.i = alloca <1 x double>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndn.i = bitcast <8 x i8> %1 to <1 x double>
# |   %vrndn1.i = call <1 x double> @llvm.roundeven.v1f64(<1 x double> %vrndn.i)
# |   store <1 x double> %vrndn1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <1 x double>, ptr %ref.tmp.i, align 8
# |   store <1 x double> %2, ptr %__ret.i, align 8
# |   %3 = load <1 x double>, ptr %__ret.i, align 8
# |   ret <1 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vrndnq_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrndn.i = bitcast <16 x i8> %1 to <2 x double>
# |   %vrndn1.i = call <2 x double> @llvm.roundeven.v2f64(<2 x double> %vrndn.i)
# |   store <2 x double> %vrndn1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <2 x double>, ptr %ref.tmp.i, align 16
# |   store <2 x double> %2, ptr %__ret.i, align 16
# |   %3 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vrndns_f32(float noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca float, align 4
# |   %__ret.i = alloca float, align 4
# |   %ref.tmp.i = alloca float, align 4
# |   %a.addr = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__p0.addr.i, align 4
# |   %1 = load float, ptr %__p0.addr.i, align 4
# |   %vrndn.i = call float @llvm.roundeven.f32(float %1)
# |   store float %vrndn.i, ptr %ref.tmp.i, align 4
# |   %2 = load float, ptr %ref.tmp.i, align 4
# |   store float %2, ptr %__ret.i, align 4
# |   %3 = load float, ptr %__ret.i, align 4
# |   ret float %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrndm_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndm.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrndm1.i = call <2 x float> @llvm.floor.v2f32(<2 x float> %vrndm.i)
# |   store <2 x float> %vrndm1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndmq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrndm.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndm1.i = call <4 x float> @llvm.floor.v4f32(<4 x float> %vrndm.i)
# |   store <4 x float> %vrndm1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vrndm_f64(<1 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__ret.i = alloca <1 x double>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndm.i = bitcast <8 x i8> %1 to <1 x double>
# |   %vrndm1.i = call <1 x double> @llvm.floor.v1f64(<1 x double> %vrndm.i)
# |   store <1 x double> %vrndm1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <1 x double>, ptr %ref.tmp.i, align 8
# |   store <1 x double> %2, ptr %__ret.i, align 8
# |   %3 = load <1 x double>, ptr %__ret.i, align 8
# |   ret <1 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vrndmq_f64(<2 x double> noundef %a
# | ...
# `---data was truncated (10240/29785) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000559b1ffdfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559b1ffdce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559b1ffe062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f292da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f292daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f292da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f292da31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559b1ff75bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559b1ff75a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559b1ff5a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559b1fc09e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559b1fc09b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f292da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f292da330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f292da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559b1fc09a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c --check-prefixes=LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c --check-prefixes=LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c (1500 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsll_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsll_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsll_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsll_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsll_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsll_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsll_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsll_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsll_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %o
# | ...
# `---data was truncated (10240/427567) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056282cd64eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056282cd61e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056282cd6562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9933249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f99332a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9933249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9933231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056282ccfabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056282ccfaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056282ccdf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056282c98ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056282c98eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9933232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f99332330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f99332330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056282c98ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c (1501 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056166966eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056166966be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056166966f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f37b0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f37b08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f37b0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f37b0831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561669604bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561669604a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005616695e98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561669298e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561669298b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f37b0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f37b08330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f37b08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561669298a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c (1502 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslidedown_vx_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslidedown_vx_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vslidedown_vx_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vslidedown_vx_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslidedo
# | ...
# `---data was truncated (10240/30751) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555c3e311eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555c3e30ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555c3e31262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff11f01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff11f0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff11f01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff11f003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555c3e2a7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555c3e2a7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555c3e28c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555c3df3be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555c3df3bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff11f004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff11f0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff11f0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555c3df3ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c (1503 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei16_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 
# | ...
# `---data was truncated (10240/296951) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005576ae176eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005576ae173e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005576ae17762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb2d201bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb2d20725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb2d201ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb2d2003507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005576ae10cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005576ae10ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005576ae0f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005576adda0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005576adda0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb2d2004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb2d20050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb2d20050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005576adda0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c (1504 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmv_v_v_i8mf8(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmv_v_v_i8mf4(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmv_v_v_i8mf2(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmv_v_v_i8m1(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmv_v_v_i8m2(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmv_v_v_i8m4(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vmv_v_v_i8m8(<vscale x 64 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vmv_v_v_i16mf4(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vmv.v.v.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vmv.v.v.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vmv_v_v_i16mf2(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vmv.v.v.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vmv.v.v.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vmv_v_v_i16m1(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vmv.v.v.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vmv.v.v.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vmv_v_v_i16m2(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vmv.v.v.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vmv.v.v.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vmv_v_v_i16m4(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vmv.v.v.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vmv.v.v.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vmv_v_v_i16m8(<vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vmv.v.v.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function A
# | ...
# `---data was truncated (10240/68067) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a2815ebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a2815e8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a2815ec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff8ee305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff8ee35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff8ee305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff8ee2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a281581bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a281581a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a2815668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a281215e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a281215b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff8ee2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff8ee2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff8ee2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a281215a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c (1505 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, a
# | ...
# `---data was truncated (10240/30276) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e216398eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e216395e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e21639962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8117505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f811755c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8117505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f81174ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e21632ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e21632ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e2163138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e215fc2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e215fc2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f81174eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f81174ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f81174ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e215fc2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c (1506 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_q_f8e4m3mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_q_f8e4m3mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_q_f8e4m3mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_f_f_q_f8e4m3m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_sat_f_f_q_f8e4m3m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_f_f_q_f8e4m3m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_sat_f_f_q_f8e4m3m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f
# | ...
# `---data was truncated (10240/165246) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005561f9efaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005561f9ef7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005561f9efb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc817a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc817aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc817a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc817a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005561f9e90bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005561f9e90a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005561f9e758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005561f9b24e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005561f9b24b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc817a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc817a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc817a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005561f9b24a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c (1507 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16m1x2(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16m2x2(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16m4x2(ptr noundef %base, <vscale x 16 x i16> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f32m1x2(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f32m2x2(ptr noundef %base, <vscale x
# | ...
# `---data was truncated (10240/129190) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005642d7df7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005642d7df4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005642d7df862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3dcc933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3dcc98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3dcc933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3dcc91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005642d7d8dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005642d7d8da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005642d7d728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005642d7a21e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005642d7a21b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3dcc91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3dcc91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3dcc91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005642d7a21a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c (1508 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabs_v_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabs_v_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabs_v_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabs_v_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabs_v_u8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vabs_v_u8m4_tu(<vscale x 32 x i8> %vd, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vabs_v_u8m8_tu(<vscale x 64 x i8> %vd, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vabs_v_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vabs_v_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vabs_v_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vabs_v_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   
# | ...
# `---data was truncated (10240/92362) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056420c547eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056420c544e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056420c54862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e75733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e7578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e75733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e7571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056420c4ddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056420c4dda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056420c4c28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056420c171e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056420c171b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4e7571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e7571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e7571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056420c171a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c (1509 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaaddu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaaddu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaaddu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaaddu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaaddu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaaddu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaaddu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaaddu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaaddu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.ad
# | ...
# `---data was truncated (10240/225647) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558988bb0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558988bade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558988bb162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f291cf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f291cf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f291cf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f291ceed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558988b46bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558988b46a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558988b2b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005589887dae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005589887dab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f291ceeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f291ceef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f291ceef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005589887daa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c (1510 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_i16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_i16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_i16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_u16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_u16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_u16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("ri
# | ...
# `---data was truncated (10240/47480) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561996f6ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561996f69e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561996f6d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0ad1849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0ad18a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0ad1849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0ad1831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561996f02bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561996f02a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561996ee78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561996b96e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561996b96b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0ad1832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0ad18330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0ad18330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561996b96a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c (1511 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_i8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_i8mf2x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8_v_i8m1x5_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_u8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_u8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_u8mf2x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8_v_u8m1x5_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005644a8653eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005644a8650e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005644a865462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2eb7533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2eb758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2eb7533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2eb751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005644a85e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005644a85e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005644a85ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005644a827de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005644a827db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2eb751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2eb751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2eb751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005644a827da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c (1512 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_i16mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_i16mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_i16m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_i16m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.a
# | ...
# `---data was truncated (10240/38299) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005567b1a3feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005567b1a3ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005567b1a4062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6069733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f606978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6069733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f606971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005567b19d5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005567b19d5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005567b19ba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005567b1669e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005567b1669b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f606971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f606971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f606971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005567b1669a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c (1513 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f16m1x7(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f32m1x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f64m1x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i16> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563a4e82deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563a4e82ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563a4e82e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f507bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f507bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f507bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f507bd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a4e7c3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563a4e7c3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563a4e7a88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563a4e457e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563a4e457b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f507bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f507bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f507bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a4e457a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c (1514 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560fc5d74eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560fc5d71e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560fc5d7562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe5a4b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe5a4b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe5a4b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe5a4b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560fc5d0abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560fc5d0aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560fc5cef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560fc599ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560fc599eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe5a4b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe5a4b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe5a4b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560fc599ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c (1515 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f16m1x2(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f16m2x2(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f32m1x2(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f32m2x2(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f32m4x2(ptr noundef %base, <vscale x 8 x i64> %binde
# | ...
# `---data was truncated (10240/110121) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a30045ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a300459e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a30045d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f79f7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f79f778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f79f7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f79f771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a3003f2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a3003f2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a3003d78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a300086e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a300086b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f79f771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f79f771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f79f771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a300086a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c (1516 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556476f47eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556476f44e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556476f4862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6401933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f640198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6401933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f640191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556476eddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556476edda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556476ec28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556476b71e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556476b71b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f640191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f640191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f640191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556476b71a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c (1517 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zve64x    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e8w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 0, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.sf.vsettm.i64(i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e8w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 0, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e8w4(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 0, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e16w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 1, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e16w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 1, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e16w4(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 1, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e32w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 2, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e32w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 2, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e64w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 3, i64 1)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e8e699beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e8e6998e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e8e699c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f96ad21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f96ad2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f96ad21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f96ad203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e8e6931bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e8e6931a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e8e69168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e8e65c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e8e65c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f96ad204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f96ad2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f96ad2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e8e65c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c (1518 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf8_i64m2(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf8_i64m4(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf8_i64m8(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf8_i64m2_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf8_i64m4_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf8_i64m8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005650aa705eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005650aa702e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005650aa70662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8808849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f88088a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8808849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8808831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005650aa69bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005650aa69ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005650aa6808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005650aa32fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005650aa32fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8808832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f88088330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f88088330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005650aa32fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c (1519 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf4_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> %0, <vscale x 1 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float>, <vscale x 1 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 4 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> %0, <vscale x 4 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float>, <vscale x 4 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 8 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> %0, <vscale x 8 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float>, <vscale x 8 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m4_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 16 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> %0, <vscale x 16 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float>, <vscale x 16 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m8_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 32 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float>, <vscale x 32 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32mf2_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 1 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x double> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m1_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 2 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, ali
# | ...
# `---data was truncated (10240/60334) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560d1ab23eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560d1ab20e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560d1ab2462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f19f8d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f19f8d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f19f8d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f19f8d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560d1aab9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560d1aab9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560d1aa9e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560d1a74de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560d1a74db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f19f8d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f19f8d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f19f8d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560d1a74da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c (1520 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16mf4(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1f16.p0.i64(<vscale x 1 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2f16.p0.i64(<vscale x 2 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16m1(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4f16.p0.i64(<vscale x 4 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16m2(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8f16.p0.i64(<vscale x 8 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16m4(ptr noundef %base, i64 noundef %bstride, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv16f16.p0.i64(<vscale x 16 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16m8(ptr noundef %base, i64 noundef %bstride, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv32f16.p0.i64(<vscale x 32 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_i16mf4(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i16.p0.i64(<vscale x 1 x i16> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_i16mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i16.p0.i64(<vscale x 2 x i16> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_i16m1(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i16.p0.i64(<vscale x 4 x i16> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_i16m2(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   cal
# | ...
# `---data was truncated (10240/39578) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564a283deeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564a283dbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564a283df62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff2f3849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff2f38a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff2f3849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff2f3831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564a28374bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564a28374a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564a283598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564a28008e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564a28008b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff2f3832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff2f38330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff2f38330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564a28008a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c (1521 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16
# | ...
# `---data was truncated (10240/295311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557c17d6deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557c17d6ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557c17d6e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdb6d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdb6d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdb6d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdb6d71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557c17d03bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557c17d03a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557c17ce88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557c17997e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557c17997b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdb6d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdb6d71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdb6d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557c17997a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c (1522 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vle16_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vle.nxv1f16.p0.i64(<vscale x 1 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x half> @llvm.riscv.vle.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vle16_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vle.nxv2f16.p0.i64(<vscale x 2 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x half> @llvm.riscv.vle.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vle16_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vle.nxv4f16.p0.i64(<vscale x 4 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x half> @llvm.riscv.vle.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vle16_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vle.nxv8f16.p0.i64(<vscale x 8 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x half> @llvm.riscv.vle.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vle16_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vle.nxv16f16.p0.i64(<vscale x 16 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x half> @llvm.riscv.vle.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vle16_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vle.nxv32f16.p0.i64(<vscale x 32 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x half> @llvm.riscv.vle.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16.p0.i64(<vscale x 1 x i16> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16.p0.i64(<vscale x 2 x i16> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vle16_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16.p0.i64(<vscale x 4 x i16> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vle16_v_i16m2_tu(<vscale x 8 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.p0.i64(<vscale x 8 x i16> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.p0.i64(<vscale x 8 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vle16_v_i16m4_tu(<vscale x 16 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/71947) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056344b855eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056344b852e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056344b85662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e9ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e9ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e9ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e9ff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056344b7ebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056344b7eba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056344b7d08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056344b47fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056344b47fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7e9ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e9ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e9ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056344b47fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c (1523 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f16m1x5(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f32m1x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f64m1x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/69980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005611cd3c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005611cd3c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005611cd3c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f41a8649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f41a86a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f41a8649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f41a8631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005611cd35abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005611cd35aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005611cd33f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005611ccfeee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005611ccfeeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f41a8632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f41a86330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f41a86330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005611ccfeea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c (1524 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_f64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_i64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_u64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560b8571eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560b8571be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560b8571f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f57cb01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57cb0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f57cb01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f57cb003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b856b4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560b856b4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560b856998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560b85348e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560b85348b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f57cb004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57cb0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57cb0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b85348a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c (1525 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei16_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a879537eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a879534e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a87953862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc246d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc246d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc246d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc246d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a8794cdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a8794cda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a8794b28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a879161e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a879161b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc246d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc246d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc246d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a879161a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c (1526 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8ff_v_i8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8ff_v_i8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8ff_v_i8mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8ff_v_i8m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8ff_v_i8m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8ff_v_u8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv
# | ...
# `---data was truncated (10240/68225) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056324d490eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056324d48de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056324d49162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efd47249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efd472a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efd47249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efd47231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056324d426bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056324d426a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056324d40b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056324d0bae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056324d0bab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efd47232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efd472330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efd472330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056324d0baa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c (1527 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32ff_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32ff_v_f32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32ff_v_f32m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_i32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32ff_v_i32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple",
# | ...
# `---data was truncated (10240/80648) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005579823f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005579823f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005579823f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff6141bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff614725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff6141ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff61403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055798238ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055798238ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005579823738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557982022e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557982022b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007eff61404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff614050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff614050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557982022a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c (1528 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f16m1x3(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f16m2x3(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f32m1x3(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f32m2x3(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f64m1x3(ptr noundef %base, <vscale x 1 x i64> %binde
# | ...
# `---data was truncated (10240/94227) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564959449eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564959446e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056495944a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efda6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efda618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efda6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efda611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005649593dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005649593dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005649593c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564959073e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564959073b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efda611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efda611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efda611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564959073a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c (1529 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmadd_vv_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmadd_vx_i8mf8_tu(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmadd_vv_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmadd_vx_i8mf4_tu(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmadd_vv_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmadd_vx_i8mf2_tu(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmadd_vv_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmadd_vx_i8m1_tu(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmadd_vv_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8
# | ...
# `---data was truncated (10240/414525) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556cad18aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556cad187e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556cad18b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5fc9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5fc9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5fc9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5fc9b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556cad120bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556cad120a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556cad1058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556cacdb4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556cacdb4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5fc9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5fc9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5fc9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556cacdb4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c (1530 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssubu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssubu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssubu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssubu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssubu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssubu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssubu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssubu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssubu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssubu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssubu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssubu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssubu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssubu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vssubu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vsca
# | ...
# `---data was truncated (10240/98171) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555a637eaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555a637e7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555a637eb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb073c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb073ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb073c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb073c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555a63780bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555a63780a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555a637658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555a63414e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555a63414b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb073c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb073c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb073c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555a63414a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c (1531 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_f32mf2(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_f32m1(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_f32m2(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_f32m4(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i6
# | ...
# `---data was truncated (10240/90867) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555c754a3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555c754a0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555c754a462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f476ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f476eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f476ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f476ea31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555c75439bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555c75439a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555c7541e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555c750cde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555c750cdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f476ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f476ea330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f476ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555c750cda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c (1532 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { targ
# | ...
# `---data was truncated (10240/21111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b1cb44eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563b1cb41e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563b1cb4562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdbcbd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdbcbd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdbcbd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdbcbd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b1cadabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563b1cadaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563b1cabf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563b1c76ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563b1c76eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdbcbd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdbcbd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdbcbd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b1c76ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c (1533 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svsub_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svsub_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svsub_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svsub_bf16_n_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svsub_bf16_n_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svsub_bf16_n_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005639b9c0aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005639b9c07e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005639b9c0b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4144f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4144f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4144f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4144f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005639b9ba0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005639b9ba0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005639b9b858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005639b9834e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005639b9834b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4144f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4144f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4144f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639b9834a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c (1534 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssubu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssubu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssubu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssubu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssubu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssubu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssubu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssubu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssubu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssubu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssubu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssubu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssubu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssubu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vssubu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = allo
# | ...
# `---data was truncated (10240/98179) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560bf9b4deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560bf9b4ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560bf9b4e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7cf1f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7cf1f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7cf1f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7cf1f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560bf9ae3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560bf9ae3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560bf9ac88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560bf9777e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560bf9777b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7cf1f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7cf1f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7cf1f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560bf9777a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c (1535 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei16_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557c1cfe6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557c1cfe3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557c1cfe762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0796c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0796c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0796c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0796c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557c1cf7cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557c1cf7ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557c1cf618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557c1cc10e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557c1cc10b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0796c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0796c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0796c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557c1cc10a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c (1536 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vxor_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vxor_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vxor_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vxor_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vxor_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vxor_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vxor_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vxor_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vxor_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/424835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055979b563eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055979b560e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055979b56462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff74cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff74cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff74cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff74cc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055979b4f9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055979b4f9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055979b4de8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055979b18de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055979b18db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff74cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff74cc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff74cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055979b18da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c (1537 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsra_wv_i8mf8(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsra_wx_i8mf8(<vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsra_wv_i8mf4(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsra_wx_i8mf4(<vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsra_wv_i8mf2(<vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsra_wx_i8mf2(<vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsra_wv_i8m1(<vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsra_wx_i8m1(<vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsra_wv_i8m2(<vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsra_wx_i8m2(<vscale x 16 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8>, <vs
# | ...
# `---data was truncated (10240/68517) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005571202f0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005571202ede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005571202f162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f20b5449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f20b54a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f20b5449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f20b5431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557120286bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557120286a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055712026b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055711ff1ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055711ff1ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f20b5432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f20b54330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f20b54330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055711ff1aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c (1538 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555f7553ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555f75539e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555f7553d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f044c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f044c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f044c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f044c831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f754d2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555f754d2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555f754b78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555f75166e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555f75166b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f044c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f044c8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f044c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f75166a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c (1539 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei32_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i
# | ...
# `---data was truncated (10240/32100) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a22073ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a220739e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a22073d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc84e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc84e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc84e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc84e71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a2206d2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a2206d2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a2206b78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a220366e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a220366b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc84e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc84e71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc84e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a220366a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c (1540 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_vv_i16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_vx_i16mf4(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_wv_i16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_wx_i16mf4(<vscale x 1 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_vv_i16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_vx_i16mf2(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_wv_i16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_wx_i16mf2(<vscale x 2 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwadd_vv_i16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwadd_vx_i16m1(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwadd_wv_i16m
# | ...
# `---data was truncated (10240/134565) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005621ae9e2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005621ae9dfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005621ae9e362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5a2b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5a2b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5a2b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5a2b71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005621ae978bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005621ae978a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005621ae95d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005621ae60ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005621ae60cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5a2b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5a2b71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5a2b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005621ae60ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c (1541 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u64m1(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 %0, i64 64, i64 0, i64 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 immarg, i64 immarg, i64 immarg, i64, i64 immarg, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u64m2(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 %0, i64 64, i64 1, i64 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u64m4(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 %0, i64 64, i64 2, i64 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u64m8(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 %0, i64 64, i64 3, i64 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_sf_vc_v_x_se_u64m1(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.x.se.nxv1i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 1 x i64> @llvm.riscv.sf.vc.v.x.se.nxv1i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_sf_vc_v_x_se_u64m2(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.x.se.nxv2i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 2 x i64> @llvm.riscv.sf.vc.v.x.se.nxv2i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_sf_vc_v_x_se_u64m4(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.x.se.nxv4i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 4 x i64> @llvm.riscv.sf.vc.v.x.se.nxv4i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_sf_vc_v_x_se_u64m8(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.x.se.nxv8i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 8 x i64> @llvm.riscv.sf.vc.v.x.se.nxv8i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_sf_vc_v_x_u64m1(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.x.nxv1i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.sf.vc.v.x.nxv1i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_sf_vc_v_x_u64m2(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.x.nxv2i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.sf.vc.v.x.nxv2i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_sf_vc_v_x_u64m4(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.x.nxv4i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.sf.vc.v.x.nxv4i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_sf_vc_v_x_u64m8(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.x.nxv8i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.sf.vc.v.x.nxv8i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvcp,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nounwind }
# | attributes #2 = { nounwind memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvcp1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556bddf97eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556bddf94e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556bddf9862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f419e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f419e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f419e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f419e71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556bddf2dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556bddf2da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556bddf128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556bddbc1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556bddbc1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f419e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f419e71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f419e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556bddbc1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c (1542 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4(<vscale x 16 x half> %vd, <vscale x 16 x half> %v
# | ...
# `---data was truncated (10240/148843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556d6e25ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556d6e259e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556d6e25d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8f95049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8f950a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8f95049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8f95031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556d6e1f2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556d6e1f2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556d6e1d78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556d6de86e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556d6de86b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8f95032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8f950330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8f950330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556d6de86a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c (1543 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i32> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i
# | ...
# `---data was truncated (10240/15699) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056435ea0feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056435ea0ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056435ea1062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f293a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f293a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f293a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f293a31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056435e9a5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056435e9a5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056435e98a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056435e639e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056435e639b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f293a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f293a31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f293a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056435e639a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c (1544 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vslideup_vx_f16mf4(<vscale x 1 x half> %dest, <vscale x 1 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vslideup_vx_f16mf2(<vscale x 2 x half> %dest, <vscale x 2 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vslideup_vx_f16m1(<vscale x 4 x half> %dest, <vscale x 4 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vslideup_vx_f16m2(<vscale x 8 x half> %dest, <vscale x 8 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vslideup_vx_f16m4(<vscale x 16 x half> %dest, <vscale x 16 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vslideup_vx_f16m8(<vscale x 32 x half> %dest, <vscale x 32 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vslideup_vx_f32mf2(<vscale x 1 x float> %dest, <vscale x 1 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vslideup_vx_f32m1(<vscale x 2 x float> %dest, <vscale x 2 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vslideup_vx_f32m2(<vscale x 4 x float> %dest, <vscale x 4 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %dest, ptr %dest.addr, align 4
# |   store <vscal
# | ...
# `---data was truncated (10240/142024) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558498431eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055849842ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055849843262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f992b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f992b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f992b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f992b431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005584983c7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005584983c7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005584983ac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055849805be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055849805bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f992b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f992b4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f992b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055849805ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c (1545 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm3c_vi_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm3c_vi_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm3c_vi_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm3c_vi_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm3c_vi_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aa95032eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aa9502fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aa9503362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f28a3849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f28a38a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f28a3849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f28a3831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa94fc8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aa94fc8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aa94fad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aa94c5ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aa94c5cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f28a3832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f28a38330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f28a38330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa94c5ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c (1546 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei8_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8
# | ...
# `---data was truncated (10240/160141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557c37e0feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557c37e0ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557c37e1062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f87c7d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87c7d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f87c7d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87c7d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557c37da5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557c37da5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557c37d8a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557c37a39e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557c37a39b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f87c7d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87c7d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87c7d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557c37a39a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/X86/sse.c (1547 of 27911)
******************** TEST 'Clang :: CodeGen/X86/sse.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple x86_64-- -target-feature +sse4.1 -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple x86_64-- -target-feature +sse4.1 -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-unknown"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_mm_slli_si128(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = bitcast <2 x i64> %0 to <16 x i8>
# |   %pslldq = shufflevector <16 x i8> zeroinitializer, <16 x i8> %1, <16 x i32> <i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26>
# |   %2 = bitcast <16 x i8> %pslldq to <2 x i64>
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_mm_slli_si128_0(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = bitcast <2 x i64> %0 to <16 x i8>
# |   %pslldq = shufflevector <16 x i8> zeroinitializer, <16 x i8> %1, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
# |   %2 = bitcast <16 x i8> %pslldq to <2 x i64>
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_mm_slli_si128_16(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = bitcast <2 x i64> %0 to <16 x i8>
# |   ret <2 x i64> zeroinitializer
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_mm_srli_si128(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = bitcast <2 x i64> %0 to <16 x i8>
# |   %psrldq = shufflevector <16 x i8> %1, <16 x i8> zeroinitializer, <16 x i32> <i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20>
# |   %2 = bitcast <16 x i8> %psrldq to <2 x i64>
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_mm_srli_si128_0(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = bitcast <2 x i64> %0 to <16 x i8>
# |   %psrldq = shufflevector <16 x i8> %1, <16 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   %2 = bitcast <16 x i8> %psrldq to <2 x i64>
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_mm_srli_si128_16(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = bitcast <2 x i64> %0 to <16 x i8>
# |   ret <2 x i64> zeroinitializer
# | }
# | 
# | attributes #0 = { noinline nounwind "min-legal-vector-width"="128" "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+sse3,+sse4.1,+ssse3,+x87" }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d8041d0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d8041cde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d8041d162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe273505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe27355c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe273505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe2734ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d804166bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d804166a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d80414b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d803dfae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d803dfab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe2734eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe2734ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe2734ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d803dfaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c (1548 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16mf4(ptr noundef %base, <vscale x 1 x i16> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16mf2(ptr noundef %base, <vscale x 2 x i16> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16m1(ptr noundef %base, <vscale x 4 x i16> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16m2(ptr noundef %base, <vscale x 8 x i16> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16m4(ptr noundef %base, <vscale x 16 x i16> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16m8(ptr noundef %base, <vscale x 32 x i16> %bindex, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> %2, ptr %0, <vscale x 32 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f32mf2(ptr noundef %base, <vscale x 1 x i16> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f32m1(ptr noundef %base, <vscale x 2 x i16> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f32m2(ptr noundef %base, <vscale x 4 x i16> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   
# | ...
# `---data was truncated (10240/132462) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005608e68fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005608e68f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005608e68fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f76e2649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f76e26a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f76e2649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f76e2631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005608e6892bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005608e6892a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005608e68778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005608e6526e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005608e6526b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f76e2632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f76e26330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f76e26330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005608e6526a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c (1549 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgatherei16_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgatherei16_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgatherei16_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vrgatherei16_vv_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, <vscale x 32 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64
# | ...
# `---data was truncated (10240/32709) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005642a864aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005642a8647e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005642a864b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d73333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d7338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d73333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d7331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005642a85e0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005642a85e0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005642a85c58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005642a8274e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005642a8274b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1d7331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d7331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d7331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005642a8274a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c (1550 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_f16mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_f16mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_f16m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_i16mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_i16mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_i16m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_u16mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_u16mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_u16m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_f16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.v
# | ...
# `---data was truncated (10240/20439) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f6bef07eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f6bef04e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f6bef0862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbc0d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbc0d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbc0d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbc0d11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f6bee9dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f6bee9da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f6bee828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f6beb31e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f6beb31b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbc0d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbc0d11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbc0d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f6beb31a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-neon-numeric-maxmin.c (1551 of 27911)
******************** TEST 'Clang :: CodeGen/arm-neon-numeric-maxmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8-unknown-linux-gnueabihf"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vmaxnm_f32(<2 x float> noundef %a, <2 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vmaxnm_v.i = bitcast <8 x i8> %2 to <2 x float>
# |   %vmaxnm_v1.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vmaxnm_v2.i = call <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float> %vmaxnm_v.i, <2 x float> %vmaxnm_v1.i)
# |   %vmaxnm_v3.i = bitcast <2 x float> %vmaxnm_v2.i to <8 x i8>
# |   store <8 x i8> %vmaxnm_v3.i, ptr %ref.tmp.i, align 8
# |   %4 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %4, ptr %__ret.i, align 8
# |   %5 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmaxnmq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__p1.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %vmaxnmq_v.i = bitcast <16 x i8> %2 to <4 x float>
# |   %vmaxnmq_v1.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vmaxnmq_v2.i = call <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float> %vmaxnmq_v.i, <4 x float> %vmaxnmq_v1.i)
# |   %vmaxnmq_v3.i = bitcast <4 x float> %vmaxnmq_v2.i to <16 x i8>
# |   store <16 x i8> %vmaxnmq_v3.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vminnm_f32(<2 x float> noundef %a, <2 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vminnm_v.i = bitcast <8 x i8> %2 to <2 x float>
# |   %vminnm_v1.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vminnm_v2.i = call <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float> %vminnm_v.i, <2 x float> %vminnm_v1.i)
# |   %vminnm_v3.i = bitcast <2 x float> %vminnm_v2.i to <8 x i8>
# |   store <8 x i8> %vminnm_v3.i, ptr %ref.tmp.i, align 8
# |   %4 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %4, ptr %__ret.i, align 8
# |   %5 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vminnmq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__p1.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %vminnmq_v.i = bitcast <16 x i8> %2 to <4 x float>
# |   %vminnmq_v1.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vminnmq_v2.i = call <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float> %vminnmq_v.i, <4 x float> %vminnmq_v1.i)
# |   %vminnmq_v3.i = bitcast <4 x float> %vminnmq_v2.i to <16 x i8>
# |   store <16 x i8> %vminnmq_v3.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float>, <2 x float>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float>, <2 x float>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float>, <4 x float>) #1
# | 
# | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a57" "target-features"="+aes,+armv8-a,+crc,+d32,+dsp,+fp-armv8,+fp-armv8d16,+fp-armv8d16sp,+fp-armv8sp,+fp16,+fp64,+hwdiv,+hwdiv-arm,+neon,+sha2,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1}
# | !llvm.ident = !{!2}
# | 
# | !0 = !{i32 1, !"target-abi", !"aapcs-linux"}
# | !1 = !{i32 1, !"min_enum_size", i32 4}
# | !2 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055bec529deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bec529ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bec529e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9411d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9411d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9411d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9411d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bec5233bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bec5233a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bec52188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bec4ec7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bec4ec7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9411d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9411d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9411d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bec4ec7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c (1552 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willr
# | ...
# `---data was truncated (10240/44361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055926bddeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055926bddbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055926bddf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feabe105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feabe15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feabe105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feabe0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055926bd74bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055926bd74a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055926bd598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055926ba08e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055926ba08b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feabe0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feabe0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feabe0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055926ba08a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c (1553 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_ext_v_f16mf4_f16mf2(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.insert.nxv2f16.nxv1f16(<vscale x 2 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.insert.nxv2f16.nxv1f16(<vscale x 2 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_ext_v_f16mf4_f16m1(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv1f16(<vscale x 4 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv1f16(<vscale x 4 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_ext_v_f16mf4_f16m2(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv1f16(<vscale x 8 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv1f16(<vscale x 8 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16mf4_f16m4(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv1f16(<vscale x 16 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv1f16(<vscale x 16 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16mf4_f16m8(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv1f16(<vscale x 32 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv1f16(<vscale x 32 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_ext_v_f16mf2_f16m1(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv2f16(<vscale x 4 x half> poison, <vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv2f16(<vscale x 4 x half>, <vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_ext_v_f16mf2_f16m2(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv2f16(<vscale x 8 x half> poison, <vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv2f16(<vscale x 8 x half>, <vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16mf2_f16m4(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv2f16(<vscale x 16 x half> poison, <vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv2f16(<vscale x 16 x half>, <vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16mf2_f16m8(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv2f16(<vscale x 32 x half> poison, <vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv2f16(<vscale x 32 x half>, <vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_ext_v_f16m1_f16m2(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16m1_f16m4(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16m1_f16m8(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16m2_f16m4(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half> poison, <vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16m2_f16m8(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> poison, <vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline n
# | ...
# `---data was truncated (10240/83088) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056291869eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056291869be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056291869f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f939981bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f93998725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f939981ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9399803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562918634bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562918634a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005629186198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005629182c8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005629182c8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9399804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f93998050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f93998050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005629182c8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c (1554 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslideup_vx_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vslideup.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslideup.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslideup_vx_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vslideup.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslideup.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslideup_vx_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vslideup.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslideup.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslideup_vx_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vslideup.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vslideup.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vslideup_vx_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vslideup.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vslideup.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vslideup_vx_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vslideup.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vslideup.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslideup_vx_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vslideup.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslideup.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslideup_vx_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vslideup.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslideup.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, 
# | ...
# `---data was truncated (10240/30635) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c72adceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563c72ad9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563c72add62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f84bbf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f84bbf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f84bbf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f84bbf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c72a72bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563c72a72a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563c72a578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563c72706e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563c72706b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f84bbf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f84bbf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f84bbf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c72706a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c (1555 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwcvt_x_x_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwcvt_x_x_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwcvt_x_x_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwcvt_x_x_v_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwcvt_x_x_v_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwcvt_x_x_v_i16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwcvt_x_x_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwcvt_x_x_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwcvt_x_x_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vwcvt_x_x_v_i32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 
# | ...
# `---data was truncated (10240/67006) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559098dd7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559098dd4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559098dd862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0ff2249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0ff22a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0ff2249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0ff2231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559098d6dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559098d6da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559098d528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559098a01e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559098a01b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0ff2232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0ff22330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0ff22330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559098a01a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c (1556 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_i8mf8x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8ff_v_i8mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8ff_v_i8mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8ff_v_i8m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_u8mf8x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8ff_v_u8mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8ff_v_u8mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8ff_v_u8m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %m
# | ...
# `---data was truncated (10240/22258) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559727b4eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559727b4be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559727b4f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc673a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc673aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc673a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc673a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559727ae4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559727ae4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559727ac98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559727778e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559727778b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc673a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc673a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc673a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559727778a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c (1557 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrsqrt7_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrsqrt7_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrsqrt7_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrsqrt7_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrsqrt7_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrsqrt7_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrsqrt7_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrsqrt7_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrsqrt7_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrsqrt7_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = ca
# | ...
# `---data was truncated (10240/67474) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a6af162eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a6af15fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a6af16362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c16449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c164a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c16449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c16431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a6af0f8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a6af0f8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a6af0dd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a6aed8ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a6aed8cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7c16432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c164330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c164330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a6aed8ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c (1558 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_bf16mf4x3(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_bf16mf2x3(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_bf16m1x3(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_bf16m2x3(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tup
# | ...
# `---data was truncated (10240/11051) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d914a62eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d914a5fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d914a6362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efebd049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efebd0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efebd049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efebd031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d9149f8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d9149f8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d9149dd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d91468ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d91468cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efebd032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efebd0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efebd0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d91468ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c (1559 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560f4a959eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560f4a956e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560f4a95a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffbeea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffbeeaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffbeea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffbeea31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f4a8efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560f4a8efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560f4a8d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560f4a583e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560f4a583b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffbeea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffbeea330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffbeea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f4a583a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c (1560 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_f32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_f32m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_i32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_i32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_i32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_i32m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>
# | ...
# `---data was truncated (10240/63169) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dd2f11aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dd2f117e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dd2f11b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f35a4b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f35a4b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f35a4b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f35a4b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd2f0b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dd2f0b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dd2f0958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dd2ed44e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dd2ed44b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f35a4b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f35a4b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f35a4b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd2ed44a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c (1561 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f16m1x6(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f32m1x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f64m1x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef
# | ...
# `---data was truncated (10240/69988) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005618b225beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005618b2258e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005618b225c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb737733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb73778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb737733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb73771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005618b21f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005618b21f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005618b21d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005618b1e85e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005618b1e85b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb73771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb73771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb73771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005618b1e85a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c (1562 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vlse8_v_i8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vlse.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i8> @llvm.riscv.vlse.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vlse8_v_i8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vlse.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i8> @llvm.riscv.vlse.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vlse8_v_i8mf2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vlse.mask.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i8> @llvm.riscv.vlse.mask.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vlse8_v_i8m1_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vlse.mask.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i8> @llvm.riscv.vlse.mask.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vlse8_v_i8m2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vlse.mask.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x i8> @llvm.riscv.vlse.mask.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vlse8_v_i8m4_m(<vscale x 32 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vlse.mask.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %1, i64 %2, <vscale x 32 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x i8> @llvm.riscv.vlse.mask.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64, <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vlse8_v_i8m8_m(<vscale x 64 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vlse.mask.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %1, i64 %2, <vscale x 64 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 64 x i8> @llvm.riscv.vlse.mask.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64, <vscale x 64 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vlse8_v_u8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vlse.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vlse8_v_u8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vlse.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vlse8_v_
# | ...
# `---data was truncated (10240/15323) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055889c237eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055889c234e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055889c23862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f602a105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f602a15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f602a105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f602a0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055889c1cdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055889c1cda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055889c1b28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055889be61e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055889be61b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f602a0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f602a0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f602a0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055889be61a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c (1563 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vv_bf16mf4_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vf_bf16mf4_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vv_bf16mf2_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vf_bf16mf2_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vv_bf16m1_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vf_bf16m1_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vv_bf16m2_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vf_bf16m2_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.bf16.nxv8bf16.i6
# | ...
# `---data was truncated (10240/51694) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d5fa5caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d5fa5c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d5fa5cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f03d6249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03d62a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f03d6249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f03d6231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d5fa560bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d5fa560a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d5fa5458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d5fa1f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d5fa1f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f03d6232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03d62330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03d62330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d5fa1f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c (1564 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabda_vv_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabda_vx_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabda_vv_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabda_vx_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabda_vv_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabda_vx_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabda_vv_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabda_vx_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwabda_vv_u16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd
# | ...
# `---data was truncated (10240/110070) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056310cd48eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056310cd45e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056310cd4962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efe62849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efe628a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efe62849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efe62831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056310ccdebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056310ccdea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056310ccc38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056310c972e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056310c972b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efe62832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efe628330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efe628330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056310c972a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c (1565 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_bf16mf2x8(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_bf16m1x8(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c49deaceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c49dea9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c49dead62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f634a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f634a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f634a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f634a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c49de42bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c49de42a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c49de278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c49dad6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c49dad6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f634a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f634a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f634a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c49dad6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c (1566 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdf_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdf.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdf.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdf_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdf_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdf_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesdf_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdf_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdf_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare
# | ...
# `---data was truncated (10240/20141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559ac9bb7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559ac9bb4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559ac9bb862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc202933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc20298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc202933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc20291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559ac9b4dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559ac9b4da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559ac9b328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559ac97e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559ac97e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc20291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc20291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc20291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559ac97e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/memcmp-inline-builtin-to-asm.c (1567 of 27911)
******************** TEST 'Clang :: CodeGen/memcmp-inline-builtin-to-asm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=verify | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64"
# | 
# | @con_unify_unimap_p1 = global ptr null, align 8
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @con_unify_unimap_q1() #0 {
# | entry:
# |   %p.addr.i = alloca ptr, align 8
# |   %q.addr.i = alloca ptr, align 8
# |   %size.addr.i = alloca i64, align 8
# |   %0 = load ptr, ptr @con_unify_unimap_p1, align 8
# |   store ptr %0, ptr %p.addr.i, align 8
# |   store ptr @con_unify_unimap_q1, ptr %q.addr.i, align 8
# |   store i64 4, ptr %size.addr.i, align 8
# |   %1 = load ptr, ptr %p.addr.i, align 8
# |   %2 = load ptr, ptr %q.addr.i, align 8
# |   %3 = load i64, ptr %size.addr.i, align 8
# |   %call.i = call i32 @memcmp(ptr noundef %1, ptr noundef %2, i64 noundef %3) #2
# |   ret i32 %call.i
# | }
# | 
# | ; Function Attrs: alwaysinline nobuiltin nounwind
# | declare i32 @memcmp(ptr noundef, ptr noundef, i64 noundef) #1
# | 
# | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #1 = { alwaysinline nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #2 = { nounwind }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=verify
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=verify
# |  #0 0x000056188238aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561882387e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056188238b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1103333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f110338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1103333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f110331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561882320bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561882320a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005618823058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561881fb4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561881fb4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f110331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f110331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f110331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561881fb4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c (1568 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssub_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssub_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssub_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssub_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssub_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssub_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssub_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssub_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssub_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op
# | ...
# `---data was truncated (10240/222917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562e46f0aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562e46f07e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562e46f0b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5dc9a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5dc9aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5dc9a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5dc9a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562e46ea0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562e46ea0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562e46e858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562e46b34e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562e46b34b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5dc9a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5dc9a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5dc9a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562e46b34a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c (1569 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005649f2ad9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005649f2ad6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005649f2ada62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff371533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff37158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff371533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff37151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005649f2a6fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005649f2a6fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005649f2a548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005649f2703e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005649f2703b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff37151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff37151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff37151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005649f2703a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c (1570 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vle.nxv1f64.p0.i64(<vscale x 1 x double> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x double> @llvm.riscv.vle.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64_v_f64m2_tu(<vscale x 2 x double> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vle.nxv2f64.p0.i64(<vscale x 2 x double> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.riscv.vle.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vle64_v_f64m4_tu(<vscale x 4 x double> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.vle.nxv4f64.p0.i64(<vscale x 4 x double> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x double> @llvm.riscv.vle.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vle64_v_f64m8_tu(<vscale x 8 x double> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.vle.nxv8f64.p0.i64(<vscale x 8 x double> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x double> @llvm.riscv.vle.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64_v_i64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64_v_i64m2_tu(<vscale x 2 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64_v_i64m4_tu(<vscale x 4 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64_v_i64m8_tu(<vscale x 8 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.p0.i64(<vscale x 8 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64_v_u64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64_v_u64m2_tu(<vscale x 2 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64_v_u64m4_tu(<vscale x 4 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | defi
# | ...
# `---data was truncated (10240/48385) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d27d6adeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d27d6aae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d27d6ae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f246cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f246cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f246cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f246cb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d27d643bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d27d643a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d27d6288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d27d2d7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d27d2d7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f246cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f246cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f246cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d27d2d7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c (1571 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005651604d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005651604d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005651604d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f54ad505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54ad55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f54ad505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f54ad4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056516046ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056516046ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005651604538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565160102e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565160102b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f54ad4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54ad4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54ad4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565160102a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c (1572 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind
# | ...
# `---data was truncated (10240/365431) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555baf355eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555baf352e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555baf35662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feee3733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feee378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feee3733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feee371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555baf2ebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555baf2eba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555baf2d08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555baef7fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555baef7fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feee371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feee371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feee371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555baef7fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c (1573 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvbfhcvt -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4_rm(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2_rm(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1_rm(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2_rm(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4_rm(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e37edd8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e37edd5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e37edd962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa04141bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa0414725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa04141ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa041403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e37ed6ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e37ed6ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e37ed538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e37ea02e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e37ea02b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa041404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa0414050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa0414050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e37ea02a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c (1574 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei16_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i
# | ...
# `---data was truncated (10240/32100) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560de5025eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560de5022e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560de502662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8926c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8926ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8926c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8926c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560de4fbbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560de4fbba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560de4fa08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560de4c4fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560de4c4fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8926c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8926c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8926c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560de4c4fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c (1575 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei32_v_i8mf8x8
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561e2fa4beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561e2fa48e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561e2fa4c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb609c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb609ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb609c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb609c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561e2f9e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561e2f9e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561e2f9c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561e2f675e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561e2f675b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb609c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb609c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb609c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561e2f675a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c (1576 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055684ad1ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055684ad19e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055684ad1d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdb7221bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdb722725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdb7221ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdb72203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055684acb2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055684acb2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055684ac978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055684a946e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055684a946b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdb72204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdb722050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdb722050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055684a946a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vector-shift-var.c (1577 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vector-shift-var.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %0, <16 x i8> %1, i32 0, i32 0, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8>, <16 x i8>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0, i32 0, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16>, <8 x i16>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %0, <4 x i32> %1, i32 0, i32 0, i32 0)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32>, <4 x i32>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %0, <16 x i8> %1, i32 0, i32 0, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0, i32 0, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %0, <4 x i32> %1, i32 0, i32 0, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_r_s8(<16 x i8> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> %0, i32 %1, i32 0, i32 0, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8>, i32, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_r_s16(<8 x i16> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> %0, i32 %1, i32 0, i32 0, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16>, i32, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_r_s32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> %0, i32 %1, i32 0, i32 0, i32 0)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32>, i32, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_r_u8(<16 x i8> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> %0, i32 %1, i32 0, i32 0, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_r_u16(<8 x i16> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> %0, i32 %1, i32 0, i32 0, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_r_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> %0, i32 %1, i32 0, i32 0, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqshlq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1, i32 0, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqshlq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %0, <8 x i16> %1, i32 1, i32 0, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqshlq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1, i32 0, i32 0)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqshlq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1, i32 0, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqshlq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %0, <8 x i16> %1, i32 1, i32 0, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounw
# | ...
# `---data was truncated (10240/79071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056124e18feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056124e18ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056124e19062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feac7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feac778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feac7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feac771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056124e125bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056124e125a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056124e10a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056124ddb9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056124ddb9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feac771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feac771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feac771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056124ddb9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c (1578 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmand_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmand_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmand_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmand_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmand_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmand_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmand_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c8a01aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562c8a017e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562c8a01b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4804f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4804f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4804f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4804eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c89fb0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562c89fb0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562c89f958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562c89c44e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562c89c44b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4804eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4804eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4804eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c89c44a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c (1579 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_f32mf2x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_f32m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_i32mf2x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_i32m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_u32mf2x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_u32m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_i32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_i32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_u32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8
# | ...
# `---data was truncated (10240/12059) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562781b07eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562781b04e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562781b0862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1caf133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1caf18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1caf133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1caf11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562781a9dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562781a9da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562781a828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562781731e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562781731b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1caf11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1caf11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1caf11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562781731a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c (1580 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_i8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e8_v_i8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e8_v_i8m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_u8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_u8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e8_v_u8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/48313) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556141504eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556141501e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055614150562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd5acf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd5acf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd5acf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd5acf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055614149abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055614149aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055614147f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055614112ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055614112eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd5acf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd5acf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd5acf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055614112ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c (1581 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a47416feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a47416ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a47417062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f23d2733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f23d278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f23d2733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f23d271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a474105bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a474105a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a4740ea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a473d99e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a473d99b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f23d271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f23d271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f23d271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a473d99a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c (1582 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f16m1x6(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f32m1x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f64m1x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei32_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d0ea287eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d0ea284e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d0ea28862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e81933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e8198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e81933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e8191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0ea21dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d0ea21da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d0ea2028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d0e9eb1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d0e9eb1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6e8191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e8191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e8191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d0e9eb1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c (1583 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16mf4x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16mf2x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16m1x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16m2x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("risc
# | ...
# `---data was truncated (10240/11912) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b98083eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b98083be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b98083f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb0fb849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb0fb8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb0fb849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb0fb831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b9807d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b9807d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b9807b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b980468e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b980468b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb0fb832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb0fb8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb0fb8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b980468a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c (1584 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssub_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssub_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssub_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssub_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssub_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssub_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssub_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssub_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssub_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssub_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vssub_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr
# | ...
# `---data was truncated (10240/97905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558a480ebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558a480e8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558a480ec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c25f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c25f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c25f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c25f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a48081bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558a48081a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558a480668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558a47d15e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558a47d15b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1c25f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c25f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c25f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a47d15a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c (1585 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8mf8x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_u8mf8x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_u8mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_u8mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_u8m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, al
# | ...
# `---data was truncated (10240/21566) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005622925a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056229259fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005622925a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f13fa133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13fa18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f13fa133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f13fa11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562292538bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562292538a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056229251d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005622921cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005622921ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f13fa11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13fa11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13fa11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005622921cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c (1586 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_i8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e8_v_i8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e8_v_i8m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_u8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_u8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e8_v_u8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/48305) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b6f6b6deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b6f6b6ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b6f6b6e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f60bdb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f60bdb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f60bdb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f60bdb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b6f6b03bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b6f6b03a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b6f6ae88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b6f6797e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b6f6797b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f60bdb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f60bdb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f60bdb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b6f6797a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c (1587 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_v
# | ...
# `---data was truncated (10240/216258) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560a63b60eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560a63b5de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560a63b6162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd782733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd78278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd782733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd78271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a63af6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560a63af6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560a63adb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560a6378ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560a6378ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd78271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd78271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd78271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a6378aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c (1588 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei64_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d81006eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558d81003e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558d8100762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcbd4533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcbd458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcbd4533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcbd451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d80f9cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558d80f9ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558d80f818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558d80c30e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558d80c30b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcbd451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcbd451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcbd451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d80c30a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c (1589 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16ff_v_bf16mf4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(<vscale x 1 x bfloat> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x bfloat>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x bfloat>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(<vscale x 1 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16ff_v_bf16mf2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(<vscale x 2 x bfloat> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x bfloat>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x bfloat>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(<vscale x 2 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16ff_v_bf16m1(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(<vscale x 4 x bfloat> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x bfloat>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x bfloat>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(<vscale x 4 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16ff_v_bf16m2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(<vscale x 8 x bfloat> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 8 x bfloat>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 8 x bfloat>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(<vscale x 8 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16ff_v_bf16m4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(<vscale x 16 x bfloat> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 16 x bfloat>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 16 x bfloat>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(<vscale x 16 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16ff_v_bf16m8(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(<vscale x 32 x bfloat> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 32 x bfloat>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 32 x bfloat>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(<vscale x 32 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16ff_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16ff_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 2 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16ff_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv4bf16.i64.p0(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 4 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ...
# `---data was truncated (10240/14904) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005607e9140eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005607e913de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005607e914162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f91d9449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f91d94a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f91d9449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f91d9431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607e90d6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005607e90d6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005607e90bb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005607e8d6ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005607e8d6ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f91d9432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f91d94330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f91d94330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607e8d6aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-bf16-convert-intrinsics.c (1590 of 27911)
******************** TEST 'Clang :: CodeGen/arm-bf16-convert-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc    -triple aarch64 -target-feature +neon -target-feature +bf16    -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c    | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa    | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +bf16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vcvt_f32_bf16(<4 x bfloat> noundef %a) #0 {
# | entry:
# |   %__p0_824.addr.i = alloca <4 x bfloat>, align 8
# |   %__ret_824.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %__s0.i = alloca <4 x i16>, align 8
# |   %ref.tmp1.i = alloca <16 x i8>, align 16
# |   %tmp.i = alloca <4 x i32>, align 16
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   store <4 x bfloat> %a, ptr %a.addr, align 8
# |   %0 = load <4 x bfloat>, ptr %a.addr, align 8
# |   store <4 x bfloat> %0, ptr %__p0_824.addr.i, align 8
# |   %1 = load <4 x i16>, ptr %__p0_824.addr.i, align 8
# |   store <4 x i16> %1, ptr %__s0.i, align 8
# |   %2 = load <8 x i8>, ptr %__s0.i, align 8
# |   %3 = bitcast <8 x i8> %2 to <4 x i16>
# |   %4 = zext <4 x i16> %3 to <4 x i32>
# |   %vshll_n.i = shl <4 x i32> %4, splat (i32 16)
# |   store <4 x i32> %vshll_n.i, ptr %ref.tmp1.i, align 16
# |   %5 = load <4 x i32>, ptr %ref.tmp1.i, align 16
# |   store <4 x i32> %5, ptr %__ret.i, align 16
# |   %6 = load <4 x i32>, ptr %__ret.i, align 16
# |   store <4 x i32> %6, ptr %tmp.i, align 16
# |   %7 = load <4 x i32>, ptr %tmp.i, align 16
# |   store <4 x i32> %7, ptr %ref.tmp.i, align 16
# |   %8 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %8, ptr %__ret_824.i, align 16
# |   %9 = load <4 x float>, ptr %__ret_824.i, align 16
# |   ret <4 x float> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vcvtq_low_f32_bf16(<8 x bfloat> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <8 x bfloat>, align 16
# |   %__ret.i2 = alloca <4 x bfloat>, align 8
# |   %__p0_824.addr.i.i = alloca <4 x bfloat>, align 8
# |   %__ret_824.i.i = alloca <4 x float>, align 16
# |   %ref.tmp.i.i = alloca <4 x i32>, align 16
# |   %__ret.i.i = alloca <4 x i32>, align 16
# |   %__s0.i.i = alloca <4 x i16>, align 8
# |   %ref.tmp1.i.i = alloca <16 x i8>, align 16
# |   %tmp.i.i = alloca <4 x i32>, align 16
# |   %__p0.addr.i = alloca <8 x bfloat>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x bfloat>, align 16
# |   store <8 x bfloat> %a, ptr %a.addr, align 16
# |   %0 = load <8 x bfloat>, ptr %a.addr, align 16
# |   store <8 x bfloat> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__p0.addr.i1, align 16
# |   %2 = load <8 x bfloat>, ptr %__p0.addr.i1, align 16
# |   %3 = load <8 x bfloat>, ptr %__p0.addr.i1, align 16
# |   %shuffle.i = shufflevector <8 x bfloat> %2, <8 x bfloat> %3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
# |   store <4 x bfloat> %shuffle.i, ptr %__ret.i2, align 8
# |   %4 = load <4 x bfloat>, ptr %__ret.i2, align 8
# |   store <4 x bfloat> %4, ptr %__p0_824.addr.i.i, align 8
# |   %5 = load <4 x i16>, ptr %__p0_824.addr.i.i, align 8
# |   store <4 x i16> %5, ptr %__s0.i.i, align 8
# |   %6 = load <8 x i8>, ptr %__s0.i.i, align 8
# |   %7 = bitcast <8 x i8> %6 to <4 x i16>
# |   %8 = zext <4 x i16> %7 to <4 x i32>
# |   %vshll_n.i.i = shl <4 x i32> %8, splat (i32 16)
# |   store <4 x i32> %vshll_n.i.i, ptr %ref.tmp1.i.i, align 16
# |   %9 = load <4 x i32>, ptr %ref.tmp1.i.i, align 16
# |   store <4 x i32> %9, ptr %__ret.i.i, align 16
# |   %10 = load <4 x i32>, ptr %__ret.i.i, align 16
# |   store <4 x i32> %10, ptr %tmp.i.i, align 16
# |   %11 = load <4 x i32>, ptr %tmp.i.i, align 16
# |   store <4 x i32> %11, ptr %ref.tmp.i.i, align 16
# |   %12 = load <4 x float>, ptr %ref.tmp.i.i, align 16
# |   store <4 x float> %12, ptr %__ret_824.i.i, align 16
# |   %13 = load <4 x float>, ptr %__ret_824.i.i, align 16
# |   store <4 x float> %13, ptr %__ret.i, align 16
# |   %14 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vcvtq_high_f32_bf16(<8 x bfloat> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <8 x bfloat>, align 16
# |   %__ret.i2 = alloca <4 x bfloat>, align 8
# |   %__p0_824.addr.i.i = alloca <4 x bfloat>, align 8
# |   %__ret_824.i.i = alloca <4 x float>, align 16
# |   %ref.tmp.i.i = alloca <4 x i32>, align 16
# |   %__ret.i.i = alloca <4 x i32>, align 16
# |   %__s0.i.i = alloca <4 x i16>, align 8
# |   %ref.tmp1.i.i = alloca <16 x i8>, align 16
# |   %tmp.i.i = alloca <4 x i32>, align 16
# |   %__p0.addr.i = alloca <8 x bfloat>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x bfloat>, align 16
# |   store <8 x bfloat> %a, ptr %a.addr, align 16
# |   %0 = load <8 x bfloat>, ptr %a.addr, align 16
# |   store <8 x bfloat> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__p0.addr.i1, align 16
# |   %2 = load <8 x bfloat>, ptr %__p0.addr.i1, align 16
# |   %3 = load <8 x bfloat>, ptr %__p0.addr.i1, align 16
# |   %shuffle.i = shufflevector <8 x bfloat> %2, <8 x bfloat> %3, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
# |   store <4 x bfloat> %shuffle.i, ptr %__ret.i2, align 8
# |   %4 = load <4 x bfloat>, ptr %__ret.i2, align 8
# |   store <4 x bfloat> %4, ptr %__p0_824.addr.i.i, align 8
# |   %5 = load <4 x i16>, ptr %__p0_824.addr.i.i, align 8
# |   store <4 x i16> %5, ptr %__s0.i.i, align 8
# |   %6 = load <8 x i8>, ptr %__s0.i.i, align 8
# |   %7 = bitcast <8 x i8> %6 to <4 x i16>
# |   %8 = zext <4 x i16> %7 to <4 x i32>
# |   %vshll_n.i.i = shl <4 x i32> %8, splat (i32 16)
# |   store <4 x i32> %vshll_n.i.i, ptr %ref.tmp1.i.i, align 16
# |   %9 = load <4 x i32>, ptr %ref.tmp1.i.i, align 16
# |   store <4 x i32> %9, ptr %__ret.i.i, align 16
# |   %10 = load <4 x i32>, ptr %__ret.i.i, align 16
# |   store <4 x i32> %10, ptr %tmp.i.i, align 16
# |   %11 = load <4 x i32>, ptr %tmp.i.i, align 16
# |   store <4 x i32> %11, ptr %ref.tmp.i.i, align 16
# |   %12 = load <4 x float>, ptr %ref.tmp.i.i, align 16
# |   store <4 x float> %12, ptr %__ret_824.i.i, align 16
# |   %13 = load <4 x float>, ptr %__ret_824.i.i, align 16
# |   store <4 x float> %13, ptr %__ret.i, align 16
# |   %14 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vcvt_bf16_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <4 x float>
# |   %3 = fptrunc <4 x float> %2 to <4 x bfloat>
# |   store <4 x bfloat> %3, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x bfloat>, ptr %ref.tmp.i, align 8
# |   store <4 x bfloat> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcvtq_low_bf16_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <4 x float>
# |   %3 = fptrunc <4 x float> %2 to <4 x bfloat>
# |   %4 = shufflevector <4 x bfloat> %3, <4 x bfloat> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x bfloat> %4, ptr %ref.tmp.i, align 16
# |   %5 = load <8 x bfloat>, ptr %ref.tmp.i, align 16
# |   store <8 x bfloat> %5, ptr %__ret.i, align 16
# |   %6 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcvtq_high_bf16_f32(<8 x bfloat> noundef %inactive, <4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x bfloat>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %inactive.addr = alloca <8 x bfloat>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <8 x bfloat> %inactive, ptr %inactive.addr, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <8 x bfloat>, ptr %inactive.addr, align 16
# |   %1 = load <4 x float>, ptr %a.addr, align 16
# |   store <8 x bfloat> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %4 = bitcast <16 x i8> %2 to <8 x bfloat>
# |   %5 = shufflevector <8 x bfloat> %4, <8 x bfloat> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
# |   %6 = bitcast <16 x i8> %3 to <4 x float>
# |   %7 = fptrunc <4 x float> %6 to <4 x bfloat>
# |   %8 = shufflevector <4 x bfloat> %5, <4 x bfloat> %7, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x bfloat> %8, ptr %ref.tmp.i, align 16
# |   %9 = load <8 x bfloat>, ptr %ref.tmp.i, align 16
# |   store <8 x bfloat> %9, ptr %__ret.i, align 16
# |   %10 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local bfloat @test_vcvth_bf16_f32(float noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca float, align 4
# |   %__ret.i = alloca bfloat, align 2
# |   %ref.tmp.i = alloca bfloat, align 2
# |   %a.addr = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__p0.addr.i, align 4
# |   %1 = load float, ptr %__p0.addr.i, align 4
# |   %2 = fptrunc float %1 to bfloat
# |   store bfloat %2, ptr %ref.tmp.i, align 2
# |   %3 = load bfloat, ptr %ref.tmp.i, align 2
# |   store bfloat %3, ptr %__ret.i, align 2
# |   %4 = load bfloat, ptr %__ret.i, align 2
# |   ret bfloat %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vcvtah_f32_bf16(bfloat noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca bfloat, align 2
# |   %__ret.i = alloca float, align 4
# |   %ref.tmp.i = alloca i32, align 4
# |   %a.addr = alloca bfloat, align 2
# |   store bfloat %a, ptr %a.addr, align 2
# |   %0 = load 
# | ...
# `---data was truncated (10240/10974) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005575f8813eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005575f8810e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005575f881462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4986b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4986b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4986b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4986b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005575f87a9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005575f87a9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005575f878e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005575f843de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005575f843db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4986b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4986b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4986b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005575f843da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c (1591 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vsc
# | ...
# `---data was truncated (10240/11789) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e137829eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e137826e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e13782a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3d08a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3d08aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3d08a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3d08a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e1377bfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e1377bfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e1377a48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e137453e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e137453b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3d08a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3d08a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3d08a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e137453a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c (1592 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_xvv_se_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.xvv.se.i64.nxv1i64.nxv1i64.i64.i64(i64 3, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.xvv.se.i64.nxv1i64.nxv1i64.i64.i64(i64 immarg, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_xvv_se_u64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.xvv.se.i64.nxv2i64.nxv2i64.i64.i64(i64 3, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.xvv.se.i64.nxv2i64.nxv2i64.i64.i64(i64 immarg, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_xvv_se_u64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.xvv.se.i64.nxv4i64.nxv4i64.i64.i64(i64 3, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.xvv.se.i64.nxv4i64.nxv4i64.i64.i64(i64 immarg, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_xvv_se_u64m8(<vscale x 8 x i64> %vd, <vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.xvv.se.i64.nxv8i64.nxv8i64.i64.i64(i64 3, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.xvv.se.i64.nxv8i64.nxv8i64.i64.i64(i64 immarg, <vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_sf_vc_v_xvv_se_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv1i64.i64.nxv1i64.nxv1i64.i64.i64(i64 3, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv1i64.i64.nxv1i64.nxv1i64.i64.i64(i64 immarg, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_sf_vc_v_xvv_se_u64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv2i64.i64.nxv2i64.nxv2i64.i64.i64(i64 3, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 2 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv2i64.i64.nxv2i64.nxv2i64.i64.i64(i64 immarg, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_sf_vc_v_xvv_se_u64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv4i64.i64.nxv4i64.nxv4i64.i64.i64(i64 3, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 4 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv4i64.i64.nxv4i64.nxv4i64.i64.i64(i64 immarg, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_sf_vc_v_xvv_se_u64m8(<vscale x 8 x i64> %vd, <vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv8i64.i64.nxv8i64.nxv8i64.i64.i64(i64 3, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 8 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv8i64.i64.nxv8i64.nxv8i64.i64.i64(i64 immarg, <vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_sf_vc_v_xvv_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xvv.nxv1i64.i64.nxv1i64.nxv1i64.i64.i64(i64 3, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xvv.nxv1i64.i64.nxv1i64.nxv1i64.i64.i64(i64 immarg, <vscale x 1 x i64>, <vsca
# | ...
# `---data was truncated (10240/14360) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e55c94beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e55c948e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e55c94c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f711ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f711caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f711ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f711ca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e55c8e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e55c8e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e55c8c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e55c575e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e55c575b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f711ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f711ca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f711ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e55c575a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c (1593 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561211704eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561211701e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056121170562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd172b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd172b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd172b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd172b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056121169abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056121169aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056121167f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056121132ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056121132eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd172b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd172b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd172b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056121132ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c (1594 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaeskf2_vi_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaeskf2.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaeskf2.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaeskf2_vi_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaeskf2.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaeskf2.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaeskf2_vi_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaeskf2_vi_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaeskf2.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaeskf2.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaeskf2_vi_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaeskf2.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaeskf2.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ead4a05eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ead4a02e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ead4a0662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f124e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f124e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f124e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f124e51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ead499bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ead499ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ead49808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ead462fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ead462fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f124e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f124e51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f124e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ead462fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c (1595 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vor_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vor_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vor_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vor_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vor_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vor_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vor_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vor_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vor_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vor_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vor_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, pt
# | ...
# `---data was truncated (10240/174721) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560d2776ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560d27769e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560d2776d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe22a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe22a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe22a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe22a631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560d27702bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560d27702a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560d276e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560d27396e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560d27396b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe22a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe22a6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe22a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560d27396a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c (1596 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vzext_vf2_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vzext_vf2_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vzext_vf2_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vzext_vf2_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vzext_vf2_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vzext_vf2_u16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf2_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf2_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf2_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vzext_vf2_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallbac
# | ...
# `---data was truncated (10240/66028) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055af3d673eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055af3d670e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055af3d67462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb0c5049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb0c50a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb0c5049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb0c5031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055af3d609bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055af3d609a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055af3d5ee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055af3d29de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055af3d29db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb0c5032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb0c50330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb0c50330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055af3d29da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c (1597 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16mf4(ptr noundef %base, <vscale x 1 x i32> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16mf2(ptr noundef %base, <vscale x 2 x i32> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16m1(ptr noundef %base, <vscale x 4 x i32> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16m2(ptr noundef %base, <vscale x 8 x i32> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16m4(ptr noundef %base, <vscale x 16 x i32> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f32mf2(ptr noundef %base, <vscale x 1 x i32> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f32m1(ptr noundef %base, <vscale x 2 x i32> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f32m2(ptr noundef %base, <vscale x 4 x i32> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f32m4(ptr noundef %base, <vscale x 8 x i32> %bindex, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | ...
# `---data was truncated (10240/120907) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c9b90cfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c9b90cce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c9b90d062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f309d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f309d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f309d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f309d431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9b9065bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c9b9065a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c9b904a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c9b8cf9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c9b8cf9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f309d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f309d4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f309d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c9b8cf9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c (1598 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei64_v_f16mf4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei64_v_f16mf2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei64_v_f16m1(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei64_v_f16m2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei64_v_f32mf2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei64_v_f32m1(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei64_v_f32m2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei64_v_f32m4(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vluxei64_v_f64m1(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vluxei64_v_f64m2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.p0.nxv2i64.i64(<vscale x 2 x double> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.p0.nxv2i64.i64(<vscale x 2 x double>, ptr 
# | ...
# `---data was truncated (10240/91267) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c93183eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c93183be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c93183f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc9aa449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc9aa4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc9aa449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc9aa431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9317d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c9317d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c9317b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c931468e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c931468b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc9aa432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc9aa4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc9aa4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c931468a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c (1599 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i64> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %3, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, <vscale x 8 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target
# | ...
# `---data was truncated (10240/10700) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564c4d528eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564c4d525e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564c4d52962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe86ee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe86eea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe86ee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe86ee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c4d4bebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564c4d4bea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564c4d4a38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564c4d152e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564c4d152b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe86ee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe86ee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe86ee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c4d152a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c (1600 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c47b78eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563c47b75e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563c47b7962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f75a8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f75a898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f75a8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f75a891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c47b0ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563c47b0ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563c47af38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563c477a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563c477a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f75a891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f75a891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f75a891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c477a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c (1601 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm3me_vv_u32mf2(<vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm3me_vv_u32m1(<vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm3me_vv_u32m2(<vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm3me_vv_u32m4(<vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm3me_vv_u32m8(<vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005642655a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005642655a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005642655a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe929d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe929d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe929d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe929d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056426553dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056426553da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005642655228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005642651d1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005642651d1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe929d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe929d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe929d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005642651d1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vrev.c (1602 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vrev.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev16q_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev16q_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev32q_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev32q_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrev32q_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrev32q_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrev32q_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x half> %0, <8 x half> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev64q_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev64q_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrev64q_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrev64q_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrev64q_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x half> %0, <8 x half> poison, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrev64q_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = shufflevector <4 x float> %0, <4 x float> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrev64q_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = shufflevector <4 x i32> %0, <4 x i32> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrev64q_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = shufflevector <4 x i32> %0, <4 x i32> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev16q_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = call <16 x i8> @llvm.arm.mve.vrev.predicated.v16i8.v16i1(<16 x i8> %0, i32 16, <16 x i1> %3, <16 x i8> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vrev.predicated.v16i8.v16i1(<16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev16q_m_u8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = call <16 x i8> @llvm.arm.mve.vrev.predicated.v16i8.v16i1(<16 x i8> %0, i32 16, <16 x i1> %3, <16 x i8> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrev32q_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x half>, ptr %inactive.addr, align 8
# |   %5 = call <8 x half> @llvm.arm.mve.vrev.predicated.v8f16.v8i1(<8 x half> %0, i32 32, <8 x i1> %3, <8 x half> %4)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vrev.predicated.v8f16.v8i1(<8 x half>, i32, <8 x i1>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev32q_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |  
# | ...
# `---data was truncated (10240/29535) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563ee89afeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563ee89ace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563ee89b062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f23ee733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f23ee78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f23ee733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f23ee71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ee8945bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563ee8945a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563ee892a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563ee85d9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563ee85d9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f23ee71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f23ee71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f23ee71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ee85d9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c (1603 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_f64m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_f64m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_f64m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_i64m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_i64m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_i64m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_u64m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_u64m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_u64m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_f64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llv
# | ...
# `---data was truncated (10240/20513) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a645869eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a645866e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a64586a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007facb7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007facb778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007facb7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007facb771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a6457ffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a6457ffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a6457e48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a645493e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a645493b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007facb771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007facb771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007facb771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a645493a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c (1604 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f16m1x3(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f16m2x3(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f32m1x3(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f32m2x3(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f64m1x3(ptr noundef %base, <vscale x 1 x i16> %binde
# | ...
# `---data was truncated (10240/99754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555928e35eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555928e32e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555928e3662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff366e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff366ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff366e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff366e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555928dcbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555928dcba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555928db08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555928a5fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555928a5fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff366e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff366e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff366e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555928a5fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c (1605 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_f64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_f64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_i64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_i64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_u64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_u64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_f64m1x4_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale
# | ...
# `---data was truncated (10240/40852) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f2dfba3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f2dfba0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f2dfba462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc384249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc3842a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc384249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc384231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f2dfb39bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f2dfb39a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f2dfb1e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f2df7cde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f2df7cdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc384232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc3842330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc3842330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f2df7cda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c (1606 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf4_u32m1(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf4_u32m2(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vzext_vf4_u32m4(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vzext_vf4_u32m8(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf4_u64m1(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf4_u64m2(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf4_u64m4(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf4_u64m8(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vzext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf4_u32m1_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vzext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf4_u32m2_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vzext.mask.nxv4i32.nxv4
# | ...
# `---data was truncated (10240/17503) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c6594f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c6594eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c6594f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f93af133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f93af18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f93af133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f93af11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c659487bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c659487a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c65946c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c65911be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c65911bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f93af11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f93af11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f93af11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c65911ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c (1607 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfgt_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfgt_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfgt_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64
# | ...
# `---data was truncated (10240/66565) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ca287deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564ca287ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564ca287e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f001d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f001d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f001d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f001d11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ca2813bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564ca2813a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564ca27f88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564ca24a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564ca24a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f001d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f001d11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f001d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ca24a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c (1608 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vsext_vf2_i16mf4(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vsext_vf2_i16mf2(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vsext_vf2_i16m1(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vsext_vf2_i16m2(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vsext_vf2_i16m4(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vsext_vf2_i16m8(<vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf2_i32mf2(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf2_i32m1(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf2_i32m2(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vsext_vf2_i32m4(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vsext_vf2_i32m8(<vscale x 16 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf2_i64m1(<vscale x 1 x i32> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf2_i64m2(<vscale x 2 x i32> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %op
# | ...
# `---data was truncated (10240/28563) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561513472eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056151346fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056151347362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f547601bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54760725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f547601ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5476003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561513408bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561513408a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005615133ed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056151309ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056151309cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5476004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54760050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54760050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056151309ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c (1609 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccus_vx_i16mf4(<vscale x 1 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccus_vx_i16mf2(<vscale x 2 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccus_vx_i16m1(<vscale x 4 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccus_vx_i16m2(<vscale x 8 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccus_vx_i16m4(<vscale x 16 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16>, i8, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwmaccus_vx_i16m8(<vscale x 32 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 32 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16>, i8, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwmaccus_vx_i32mf2(<vscale x 1 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32>, i16, <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwmaccus_vx_i32m1(<vscale x 2 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32>, i16, <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwmaccus_vx_i32m2(<vscale x 4 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 
# | ...
# `---data was truncated (10240/39226) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed9a5c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ed9a5c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ed9a5c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7764b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7764b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7764b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7764b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed9a55ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ed9a55ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ed9a5438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ed9a1f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ed9a1f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7764b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7764b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7764b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed9a1f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c (1610 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c309c02eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c309bffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c309c0362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6ada505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6ada55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6ada505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6ada4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c309b98bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c309b98a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c309b7d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c30982ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c30982cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6ada4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6ada4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6ada4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c30982ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c (1611 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_i64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_u64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_i64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_u64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("
# | ...
# `---data was truncated (10240/18506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556629fd7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556629fd4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556629fd862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f80a1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f80a1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f80a1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f80a1b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556629f6dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556629f6da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556629f528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556629c01e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556629c01b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f80a1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f80a1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f80a1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556629c01a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c (1612 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1sb_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1sb_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sb_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1sb_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1sb_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sb_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1sb_vnum_s16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1sb_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i8> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sb_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i8> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1sb_vnum_u16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1sb_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x
# | ...
# `---data was truncated (10240/11944) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055bc05eaaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bc05ea7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bc05eab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f13def33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13def8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f13def33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f13def1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bc05e40bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bc05e40a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bc05e258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bc05ad4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bc05ad4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f13def1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13def1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13def1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bc05ad4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c (1613 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vzip_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vzip_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vzip_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vzip_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vzip_vv_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vzip_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vzip_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vzip_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscal
# | ...
# `---data was truncated (10240/235596) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563a40ec6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563a40ec3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563a40ec762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f38b6449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f38b64a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f38b6449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f38b6431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a40e5cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563a40e5ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563a40e418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563a40af0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563a40af0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f38b6432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f38b64330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f38b64330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a40af0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/neon-fp16fml.c (1614 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-fp16fml.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +v8.2a -target-feature +neon -target-feature +fp16fml  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +v8.2a -target-feature +neon -target-feature +fp16fml -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vfmlal_low_f16(<2 x float> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vfmlal_low.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vfmlal_low1.i = bitcast <8 x i8> %4 to <4 x half>
# |   %vfmlal_low2.i = bitcast <8 x i8> %5 to <4 x half>
# |   %vfmlal_low3.i = call <2 x float> @llvm.aarch64.neon.fmlal.v2f32.v4f16(<2 x float> %vfmlal_low.i, <4 x half> %vfmlal_low1.i, <4 x half> %vfmlal_low2.i)
# |   store <2 x float> %vfmlal_low3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vfmlsl_low_f16(<2 x float> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vfmlsl_low.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vfmlsl_low1.i = bitcast <8 x i8> %4 to <4 x half>
# |   %vfmlsl_low2.i = bitcast <8 x i8> %5 to <4 x half>
# |   %vfmlsl_low3.i = call <2 x float> @llvm.aarch64.neon.fmlsl.v2f32.v4f16(<2 x float> %vfmlsl_low.i, <4 x half> %vfmlsl_low1.i, <4 x half> %vfmlsl_low2.i)
# |   store <2 x float> %vfmlsl_low3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vfmlal_high_f16(<2 x float> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vfmlal_high.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vfmlal_high1.i = bitcast <8 x i8> %4 to <4 x half>
# |   %vfmlal_high2.i = bitcast <8 x i8> %5 to <4 x half>
# |   %vfmlal_high3.i = call <2 x float> @llvm.aarch64.neon.fmlal2.v2f32.v4f16(<2 x float> %vfmlal_high.i, <4 x half> %vfmlal_high1.i, <4 x half> %vfmlal_high2.i)
# |   store <2 x float> %vfmlal_high3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vfmlsl_high_f16(<2 x float> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vfmlsl_high.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vfmlsl_high1.i = bitcast <8 x i8> %4 to <4 x half>
# |   %vfmlsl_high2.i = bitcast <8 x i8> %5 to <4 x half>
# |   %vfmlsl_high3.i = call <2 x float> @llvm.aarch64.neon.fmlsl2.v2f32.v4f16(<2 x float> %vfmlsl_high.i, <4 x half> %vfmlsl_high1.i, <4 x half> %vfmlsl_high2.i)
# |   store <2 x float> %vfmlsl_high3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vfmlalq_low_f16(<4 x float> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vfmlal_low.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vfmlal_low1.i = bitcast <16 x i8> %4 to <8 x half>
# |   %vfmlal_low2.i = bitcast <16 x i8> %5 to <8 x half>
# |   %vfmlal_low3.i = call <4 x float> @llvm.aarch64.neon.fmlal.v4f32.v8f16(<4 x float> %vfmlal_low.i, <8 x half> %vfmlal_low1.i, <8 x half> %vfmlal_low2.i)
# |   store <4 x float> %vfmlal_low3.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vfmlslq_low_f16(<4 x float> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vfmlsl_low.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vfmlsl_low1.i = bitcast <16 x i8> %4 to <8 x half>
# |   %vfmlsl_low2.i = bitcast <16 x i8> %5 to <8 x half>
# |   %vfmlsl_low3.i = call <4 x float> @llvm.aarch64.neon.fmlsl.v4f32.v8f16(<4 x float> %vfmlsl_low.i, <8 x half> %vfmlsl_low1.i, <8 x half> %vfmlsl_low2.i)
# |   store <4 x float> %vfmlsl_low3.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vfmlalq_high_f16(<4 x float> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = allo
# | ...
# `---data was truncated (10240/162735) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005646251a8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005646251a5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005646251a962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb92c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb92c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb92c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb92c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056462513ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056462513ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005646251238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564624dd2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564624dd2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb92c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb92c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb92c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564624dd2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c (1615 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", 
# | ...
# `---data was truncated (10240/16800) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c6ad8e2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c6ad8dfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c6ad8e362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc1fc733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc1fc78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc1fc733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc1fc71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c6ad878bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c6ad878a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c6ad85d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c6ad50ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c6ad50cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc1fc71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc1fc71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc1fc71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c6ad50ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c (1616 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f16m1x7(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f32m1x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f64m1x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i64> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b8602c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b8602c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b8602c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e0d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e0d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e0d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e0d431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b86025ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b86025ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b8602438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b85fef2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b85fef2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6e0d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e0d4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e0d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b85fef2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c (1617 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_f32mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_f32m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_i32mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_i32m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_u32mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_u32m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_i32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_i32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry
# | ...
# `---data was truncated (10240/14002) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056458bbd3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056458bbd0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056458bbd462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f90a1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f90a1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f90a1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f90a1d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056458bb69bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056458bb69a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056458bb4e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056458b7fde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056458b7fdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f90a1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f90a1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f90a1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056458b7fda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c (1618 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nx
# | ...
# `---data was truncated (10240/18660) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558c456aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558c456a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558c456ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2dfda1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2dfda725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2dfda1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2dfda03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c45642bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558c45642a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558c456278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558c452d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558c452d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2dfda04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2dfda050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2dfda050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c452d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c (1619 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f16m1x8(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f32m1x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f64m1x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i64> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d84732eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558d8472fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558d8473362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f306b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f306b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f306b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f306b71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d846c8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558d846c8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558d846ad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558d8435ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558d8435cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f306b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f306b71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f306b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d8435ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c (1620 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_f16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_f16mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_f16m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_f16m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_i16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_i16mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_i16m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_i16m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_u16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   s
# | ...
# `---data was truncated (10240/30826) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d528069eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d528066e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d52806a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe38dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe38dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe38dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe38dc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d527fffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d527fffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d527fe48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d527c93e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d527c93b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe38dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe38dc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe38dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d527c93a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c (1621 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesem_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesem.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesem.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesem_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesem_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesem_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesem_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesem_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesem_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind w
# | ...
# `---data was truncated (10240/20198) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055997b483eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055997b480e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055997b48462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f35e7305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f35e735c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f35e7305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f35e72ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055997b419bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055997b419a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055997b3fe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055997b0ade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055997b0adb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f35e72eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f35e72ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f35e72ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055997b0ada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c (1622 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei64_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556f22ea6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556f22ea3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556f22ea762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fad5cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fad5cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fad5cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fad5cb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556f22e3cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556f22e3ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556f22e218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556f22ad0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556f22ad0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fad5cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fad5cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fad5cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556f22ad0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c (1623 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_f64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_f64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_f64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_i64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_i64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_i64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_u64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_u64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv
# | ...
# `---data was truncated (10240/53548) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055df07306eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055df07303e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055df0730762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe784e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe784ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe784e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe784e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055df0729cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055df0729ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055df072818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055df06f30e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055df06f30b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe784e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe784e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe784e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055df06f30a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c (1624 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf4_f32m1(<vscale x 1 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float>, <vscale x 1 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf2_f32m1(<vscale x 2 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m1_f32m1(<vscale x 4 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float>, <vscale x 4 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m2_f32m1(<vscale x 8 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float>, <vscale x 8 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m4_f32m1(<vscale x 16 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float>, <vscale x 16 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m8_f32m1(<vscale x 32 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float>, <vscale x 32 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32mf2_f64m1(<vscale x 1 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m1_f64m1(<vscale x 2 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64(<vscale x 1 x double>, <vscale x 2 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m2_f64m1(<vscale x 4 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2
# | ...
# `---data was truncated (10240/50524) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005626b3f36eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005626b3f33e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005626b3f3762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efdcd049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efdcd0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efdcd049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efdcd031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005626b3eccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005626b3ecca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005626b3eb18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005626b3b60e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005626b3b60b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efdcd032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efdcd0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efdcd0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005626b3b60a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c (1625 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dcdc631eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dcdc62ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dcdc63262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd768f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd768f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd768f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd768f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dcdc5c7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dcdc5c7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dcdc5ac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dcdc25be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dcdc25bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd768f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd768f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd768f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dcdc25ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c (1626 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16mf4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16mf4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = loa
# | ...
# `---data was truncated (10240/33443) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563e40950eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563e4094de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563e4095162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fed77933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fed7798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fed77933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fed7791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e408e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563e408e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563e408cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563e4057ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563e4057ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fed7791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fed7791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fed7791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e4057aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c (1627 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdiv_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdiv_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdiv_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdiv_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdiv_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdiv_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdiv_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdiv_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdiv_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/222483) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dd470c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dd470c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dd470c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b1d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b1d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b1d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b1d91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd4705abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dd4705aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dd4703f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dd46ceee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dd46ceeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2b1d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b1d91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b1d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd46ceea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c (1628 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f16m1x4(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f16m2x4(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f32m1x4(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f32m2x4(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f64m1x4(ptr noundef %base, <vscale x 1 x i16> %binde
# | ...
# `---data was truncated (10240/99754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f72340eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564f7233de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564f7234162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff53505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff5355c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff53505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff534ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f722d6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564f722d6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564f722bb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564f71f6ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564f71f6ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007eff534eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff534ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff534ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f71f6aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-v8.2a-neon-intrinsics-generic.c (1629 of 27911)
******************** TEST 'Clang :: CodeGen/arm-v8.2a-neon-intrinsics-generic.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-linux-gnu -target-abi apcs-gnu -target-feature +neon -target-feature -fullfp16  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c --check-prefixes=CHECK-NOFP16
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-linux-gnu -target-abi apcs-gnu -target-feature +neon -target-feature -fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
# | target triple = "armv8.2a-unknown-linux-gnu"
# | 
# | %struct.float16x4x2_t = type { [2 x <4 x half>] }
# | %struct.float16x8x2_t = type { [2 x <8 x half>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vbsl_f16(<4 x i16> noundef %a, <2 x i32> noundef %b.coerce, <2 x i32> noundef %c.coerce) #0 {
# | entry:
# |   %retval.i = alloca <4 x half>, align 8
# |   %__p1.i = alloca <4 x half>, align 8
# |   %__p2.i = alloca <4 x half>, align 8
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %retval = alloca <4 x half>, align 8
# |   %b = alloca <4 x half>, align 8
# |   %c = alloca <4 x half>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   %coerce = alloca <4 x half>, align 8
# |   %coerce3 = alloca <4 x half>, align 8
# |   %coerce4 = alloca <4 x half>, align 8
# |   store <2 x i32> %b.coerce, ptr %b, align 8
# |   %b1 = load <4 x half>, ptr %b, align 8
# |   store <2 x i32> %c.coerce, ptr %c, align 8
# |   %c2 = load <4 x half>, ptr %c, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x half> %b1, ptr %b.addr, align 8
# |   store <4 x half> %c2, ptr %c.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x half> %1, ptr %coerce, align 8
# |   %3 = load <2 x i32>, ptr %coerce, align 8
# |   store <4 x half> %2, ptr %coerce3, align 8
# |   %4 = load <2 x i32>, ptr %coerce3, align 8
# |   store <2 x i32> %3, ptr %__p1.i, align 8
# |   %__p11.i = load <4 x half>, ptr %__p1.i, align 8
# |   store <2 x i32> %4, ptr %__p2.i, align 8
# |   %__p22.i = load <4 x half>, ptr %__p2.i, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %__p11.i, ptr %__p1.addr.i, align 8
# |   store <4 x half> %__p22.i, ptr %__p2.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %6 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %7 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vbsl_v.i = call <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8> %5, <8 x i8> %6, <8 x i8> %7)
# |   store <8 x i8> %vbsl_v.i, ptr %ref.tmp.i, align 8
# |   %8 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %8, ptr %__ret.i, align 8
# |   %9 = load <4 x half>, ptr %__ret.i, align 8
# |   store <4 x half> %9, ptr %retval.i, align 8
# |   %10 = load <2 x i32>, ptr %retval.i, align 8
# |   store <2 x i32> %10, ptr %coerce4, align 8
# |   %11 = load <4 x half>, ptr %coerce4, align 8
# |   store <4 x half> %11, ptr %retval, align 8
# |   %12 = load <2 x i32>, ptr %retval, align 8
# |   ret <2 x i32> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vbslq_f16(<8 x i16> noundef %a, <4 x i32> noundef %b.coerce, <4 x i32> noundef %c.coerce) #0 {
# | entry:
# |   %retval.i = alloca <8 x half>, align 16
# |   %__p1.i = alloca <8 x half>, align 16
# |   %__p2.i = alloca <8 x half>, align 16
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %retval = alloca <8 x half>, align 16
# |   %b = alloca <8 x half>, align 16
# |   %c = alloca <8 x half>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   %coerce = alloca <8 x half>, align 16
# |   %coerce3 = alloca <8 x half>, align 16
# |   %coerce4 = alloca <8 x half>, align 16
# |   store <4 x i32> %b.coerce, ptr %b, align 16
# |   %b1 = load <8 x half>, ptr %b, align 16
# |   store <4 x i32> %c.coerce, ptr %c, align 16
# |   %c2 = load <8 x half>, ptr %c, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x half> %b1, ptr %b.addr, align 16
# |   store <8 x half> %c2, ptr %c.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <8 x half> %1, ptr %coerce, align 16
# |   %3 = load <4 x i32>, ptr %coerce, align 16
# |   store <8 x half> %2, ptr %coerce3, align 16
# |   %4 = load <4 x i32>, ptr %coerce3, align 16
# |   store <4 x i32> %3, ptr %__p1.i, align 16
# |   %__p11.i = load <8 x half>, ptr %__p1.i, align 16
# |   store <4 x i32> %4, ptr %__p2.i, align 16
# |   %__p22.i = load <8 x half>, ptr %__p2.i, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %__p11.i, ptr %__p1.addr.i, align 16
# |   store <8 x half> %__p22.i, ptr %__p2.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %7 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vbslq_v.i = call <16 x i8> @llvm.arm.neon.vbsl.v16i8(<16 x i8> %5, <16 x i8> %6, <16 x i8> %7)
# |   store <16 x i8> %vbslq_v.i, ptr %ref.tmp.i, align 16
# |   %8 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %8, ptr %__ret.i, align 16
# |   %9 = load <8 x half>, ptr %__ret.i, align 16
# |   store <8 x half> %9, ptr %retval.i, align 16
# |   %10 = load <4 x i32>, ptr %retval.i, align 16
# |   store <4 x i32> %10, ptr %coerce4, align 16
# |   %11 = load <8 x half>, ptr %coerce4, align 16
# |   store <8 x half> %11, ptr %retval, align 16
# |   %12 = load <4 x i32>, ptr %retval, align 16
# |   ret <4 x i32> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vzip_f16(ptr dead_on_unwind noalias writable sret(%struct.float16x4x2_t) align 8 %agg.result, <2 x i32> noundef %a.coerce, <2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %__p0.i = alloca <4 x half>, align 8
# |   %__p1.i = alloca <4 x half>, align 8
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %a = alloca <4 x half>, align 8
# |   %b = alloca <4 x half>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %coerce = alloca <4 x half>, align 8
# |   %coerce3 = alloca <4 x half>, align 8
# |   store <2 x i32> %a.coerce, ptr %a, align 8
# |   %a1 = load <4 x half>, ptr %a, align 8
# |   store <2 x i32> %b.coerce, ptr %b, align 8
# |   %b2 = load <4 x half>, ptr %b, align 8
# |   store <4 x half> %a1, ptr %a.addr, align 8
# |   store <4 x half> %b2, ptr %b.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %0, ptr %coerce, align 8
# |   %2 = load <2 x i32>, ptr %coerce, align 8
# |   store <4 x half> %1, ptr %coerce3, align 8
# |   %3 = load <2 x i32>, ptr %coerce3, align 8
# |   call void @llvm.experimental.noalias.scope.decl(metadata !3)
# |   store <2 x i32> %2, ptr %__p0.i, align 8, !noalias !3
# |   %__p01.i = load <4 x half>, ptr %__p0.i, align 8, !noalias !3
# |   store <2 x i32> %3, ptr %__p1.i, align 8, !noalias !3
# |   %__p12.i = load <4 x half>, ptr %__p1.i, align 8, !noalias !3
# |   store <4 x half> %__p01.i, ptr %__p0.addr.i, align 8, !noalias !3
# |   store <4 x half> %__p12.i, ptr %__p1.addr.i, align 8, !noalias !3
# |   %4 = load <8 x i8>, ptr %__p0.addr.i, align 8, !noalias !3
# |   %5 = load <8 x i8>, ptr %__p1.addr.i, align 8, !noalias !3
# |   %6 = bitcast <8 x i8> %4 to <4 x i16>
# |   %7 = bitcast <8 x i8> %5 to <4 x i16>
# |   %vzip.i = shufflevector <4 x i16> %6, <4 x i16> %7, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
# |   store <4 x i16> %vzip.i, ptr %agg.result, align 4, !alias.scope !3
# |   %8 = getelementptr inbounds <4 x i16>, ptr %agg.result, i32 1
# |   %vzip3.i = shufflevector <4 x i16> %6, <4 x i16> %7, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
# |   store <4 x i16> %vzip3.i, ptr %8, align 4, !alias.scope !3
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vzipq_f16(ptr dead_on_unwind noalias writable sret(%struct.float16x8x2_t) align 16 %agg.result, <4 x i32> noundef %a.coerce, <4 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %__p0.i = alloca <8 x half>, align 16
# |   %__p1.i = alloca <8 x half>, align 16
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %a = alloca <8 x half>, align 16
# |   %b = alloca <8 x half>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %coerce = alloca <8 x half>, align 16
# |   %coerce3 = alloca <8 x half>, align 16
# |   store <4 x i32> %a.coerce, ptr %a, align 16
# |   %a1 = load <8 x half>, ptr %a, align 16
# |   store <4 x i32> %b.coerce, ptr %b, align 16
# |   %b2 = load <8 x half>, ptr %b, align 16
# |   store <8 x half> %a1, ptr %a.addr, align 16
# |   store <8 x half> %b2, ptr %b.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %0, ptr %coerce, align 16
# |   %2 = load <4 x i32>, ptr %coerce, align 16
# |   store <8 x half> %1, ptr %coerce3, align 16
# |   %3 = load <4 x i32>, ptr %coerce3, align 16
# |   call void @llvm.experimental.noalias.scope.decl(metadata !6)
# |   store <4 x i32> %2, ptr %__p0.i, align 16, !noalias !6
# |   %__p01.i = load <8 x half>, ptr %__p0.i, align 16, !noalias !6
# |   store <4 x i32> %3, ptr %__p1.i, align 16, !noalias !6
# |   %__p12.i = load <8 x half>, ptr %__p1.i, align 16, !noalias !6
# |   store <8 x half> %__p01.i, ptr %__p0.addr.i, align 16, !noalias !6
# |   store <8 x half> %__p12.i, ptr %__p1.addr.i, align 16, !noalias !6
# |   %4 = load <16 x i8>, ptr %__p0.addr.i, align 16, !noalias !6
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16, !noalias !6
# |   %6 = bitcast <16 x i8> %4 to <8 x i16>
# |   %7 = bitcast <16 x i8> %5 to <8 x i16>
# |   %vzip.i = shufflevector <8 x i16> %6, <8 x i16> %7, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
# |   store <8 x i16> %vzip.i, ptr %agg.result, align 4, !alias.scope !6
# |   %8 = getelementptr inbounds <8 x i16>, ptr %agg.result, i32 1
# |   %vzip3.i = shufflevector <8 x i16> %6, <8 x i16> %7, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
# |   store <8 x i16> %vzip3.i, ptr %8, align 4, !alias.scope !6
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vuzp_f16(ptr dead_on_unwind noalias writable sret(%struct.float16x4x2_t) align 8 %agg.result, <2 x i32> noundef
# | ...
# `---data was truncated (10240/35874) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x0000557f02caeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557f02cabe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557f02caf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b12849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b128a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b12849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b12831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f02c44bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557f02c44a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557f02c298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557f028d8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557f028d8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3b12832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b128330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b128330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f028d8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c --check-prefixes=CHECK-NOFP16
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c --check-prefixes=CHECK-NOFP16
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c (1630 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf4_f16m1(<vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf2_f16m1(<vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m1_f16m1(<vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m2_f16m1(<vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m4_f16m1(<vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m8_f16m1(<vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32mf2_f32m1(<vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m1_f32m1(<vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m2_f32m1(<vscale x 4 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> 
# | ...
# `---data was truncated (10240/68054) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b11e463eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b11e460e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b11e46462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f21b4e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f21b4ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f21b4e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f21b4e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b11e3f9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b11e3f9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b11e3de8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b11e08de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b11e08db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f21b4e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f21b4e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f21b4e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b11e08da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c (1631 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f16m1x3(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_f16m2x3(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f32m1x3(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_f32m2x3(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f64m1x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/87892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056428da00eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056428d9fde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056428da0162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ae3733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ae378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ae3733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ae371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056428d996bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056428d996a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056428d97b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056428d62ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056428d62ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3ae371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ae371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ae371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056428d62aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c (1632 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vv_bf16mf4_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vf_bf16mf4_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vv_bf16mf2_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vf_bf16mf2_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vv_bf16m1_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vf_bf16m1_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vv_bf16m2_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vf_bf16m2_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.
# | ...
# `---data was truncated (10240/51804) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561ca07cceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561ca07c9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561ca07cd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff7a7533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff7a758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff7a7533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff7a751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561ca0762bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561ca0762a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561ca07478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561ca03f6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561ca03f6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff7a751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff7a751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff7a751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561ca03f6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c (1633 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_i32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_i32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_u32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_u32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_f32mf2x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple"
# | ...
# `---data was truncated (10240/35929) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005641625f7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005641625f4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005641625f862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f42ffe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42ffea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f42ffe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f42ffe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056416258dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056416258da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005641625728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564162221e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564162221b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f42ffe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42ffe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42ffe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564162221a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/neon-ldst-one-rcpc3.c (1634 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-ldst-one-rcpc3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon   -target-feature +rcpc3 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +rcpc3 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vldap1q_lane_u64(ptr noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <2 x i64>, align 16
# |   %__ret = alloca <2 x i64>, align 16
# |   %__s1 = alloca <2 x i64>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x i64>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %__s1, align 16
# |   %3 = bitcast <16 x i8> %2 to <2 x i64>
# |   %4 = load atomic i64, ptr %1 acquire, align 8
# |   %vldap1_lane = insertelement <2 x i64> %3, i64 %4, i32 1
# |   store <2 x i64> %vldap1_lane, ptr %ref.tmp, align 16
# |   %5 = load <2 x i64>, ptr %ref.tmp, align 16
# |   store <2 x i64> %5, ptr %__ret, align 16
# |   %6 = load <2 x i64>, ptr %__ret, align 16
# |   store <2 x i64> %6, ptr %tmp, align 16
# |   %7 = load <2 x i64>, ptr %tmp, align 16
# |   ret <2 x i64> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vldap1q_lane_s64(ptr noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <2 x i64>, align 16
# |   %__ret = alloca <2 x i64>, align 16
# |   %__s1 = alloca <2 x i64>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x i64>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %__s1, align 16
# |   %3 = bitcast <16 x i8> %2 to <2 x i64>
# |   %4 = load atomic i64, ptr %1 acquire, align 8
# |   %vldap1_lane = insertelement <2 x i64> %3, i64 %4, i32 1
# |   store <2 x i64> %vldap1_lane, ptr %ref.tmp, align 16
# |   %5 = load <2 x i64>, ptr %ref.tmp, align 16
# |   store <2 x i64> %5, ptr %__ret, align 16
# |   %6 = load <2 x i64>, ptr %__ret, align 16
# |   store <2 x i64> %6, ptr %tmp, align 16
# |   %7 = load <2 x i64>, ptr %tmp, align 16
# |   ret <2 x i64> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vldap1q_lane_f64(ptr noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <2 x double>, align 16
# |   %__ret = alloca <2 x double>, align 16
# |   %__s1 = alloca <2 x double>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x double>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <2 x double>, ptr %b.addr, align 16
# |   store <2 x double> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %__s1, align 16
# |   %3 = bitcast <16 x i8> %2 to <2 x double>
# |   %4 = load atomic double, ptr %1 acquire, align 8
# |   %vldap1_lane = insertelement <2 x double> %3, double %4, i32 1
# |   store <2 x double> %vldap1_lane, ptr %ref.tmp, align 16
# |   %5 = load <2 x double>, ptr %ref.tmp, align 16
# |   store <2 x double> %5, ptr %__ret, align 16
# |   %6 = load <2 x double>, ptr %__ret, align 16
# |   store <2 x double> %6, ptr %tmp, align 16
# |   %7 = load <2 x double>, ptr %tmp, align 16
# |   ret <2 x double> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vldap1q_lane_p64(ptr noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <2 x i64>, align 16
# |   %__ret = alloca <2 x i64>, align 16
# |   %__s1 = alloca <2 x i64>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x i64>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %__s1, align 16
# |   %3 = bitcast <16 x i8> %2 to <2 x i64>
# |   %4 = load atomic i64, ptr %1 acquire, align 8
# |   %vldap1_lane = insertelement <2 x i64> %3, i64 %4, i32 1
# |   store <2 x i64> %vldap1_lane, ptr %ref.tmp, align 16
# |   %5 = load <2 x i64>, ptr %ref.tmp, align 16
# |   store <2 x i64> %5, ptr %__ret, align 16
# |   %6 = load <2 x i64>, ptr %__ret, align 16
# |   store <2 x i64> %6, ptr %tmp, align 16
# |   %7 = load <2 x i64>, ptr %tmp, align 16
# |   ret <2 x i64> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vldap1_lane_u64(ptr noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   %__ret = alloca <1 x i64>, align 8
# |   %__s1 = alloca <1 x i64>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x i64>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <1 x i64>
# |   %4 = load atomic i64, ptr %1 acquire, align 8
# |   %vldap1_lane = insertelement <1 x i64> %3, i64 %4, i32 0
# |   store <1 x i64> %vldap1_lane, ptr %ref.tmp, align 8
# |   %5 = load <1 x i64>, ptr %ref.tmp, align 8
# |   store <1 x i64> %5, ptr %__ret, align 8
# |   %6 = load <1 x i64>, ptr %__ret, align 8
# |   store <1 x i64> %6, ptr %tmp, align 8
# |   %7 = load <1 x i64>, ptr %tmp, align 8
# |   ret <1 x i64> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vldap1_lane_s64(ptr noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   %__ret = alloca <1 x i64>, align 8
# |   %__s1 = alloca <1 x i64>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x i64>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <1 x i64>
# |   %4 = load atomic i64, ptr %1 acquire, align 8
# |   %vldap1_lane = insertelement <1 x i64> %3, i64 %4, i32 0
# |   store <1 x i64> %vldap1_lane, ptr %ref.tmp, align 8
# |   %5 = load <1 x i64>, ptr %ref.tmp, align 8
# |   store <1 x i64> %5, ptr %__ret, align 8
# |   %6 = load <1 x i64>, ptr %__ret, align 8
# |   store <1 x i64> %6, ptr %tmp, align 8
# |   %7 = load <1 x i64>, ptr %tmp, align 8
# |   ret <1 x i64> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vldap1_lane_f64(ptr noundef %a, <1 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %__ret = alloca <1 x double>, align 8
# |   %__s1 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x double>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   %0 = load <1 x double>, ptr %b.addr, align 8
# |   store <1 x double> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <1 x double>
# |   %4 = load atomic double, ptr %1 acquire, align 8
# |   %vldap1_lane = insertelement <1 x double> %3, double %4, i32 0
# |   store <1 x double> %vldap1_lane, ptr %ref.tmp, align 8
# |   %5 = load <1 x double>, ptr %ref.tmp, align 8
# |   store <1 x double> %5, ptr %__ret, align 8
# |   %6 = load <1 x double>, ptr %__ret, align 8
# |   store <1 x double> %6, ptr %tmp, align 8
# |   %7 = load <1 x double>, ptr %tmp, align 8
# |   ret <1 x double> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vldap1_lane_p64(ptr noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   %__ret = alloca <1 x i64>, align 8
# |   %__s1 = alloca <1 x i64>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x i64>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <1 x i64>
# |   %4 = load atomic i64, ptr %1 acquire, align 8
# |   %vldap1_lane = insertelement <1 x i64> %3, i64 %4, i32 0
# |   store <1 x i64> %vldap1_lane, ptr %ref.tmp, align 8
# |   %5 = load <1 x i64>, ptr %ref.tmp, align 8
# |   store <1 x i64> %5, ptr %__ret, align 8
# |   %6 = load <1 x i64>, ptr %__ret, align 8
# |   store <1 x i64> %6, ptr %tmp, align 8
# |   %7 = load <1 x i64>, ptr %tmp, align 8
# |   ret <1 x i64> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vstl1q_lane_u64(ptr noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <2 x i64>, align 16
# |   %__s1 = alloca <2 x i64>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %__s1, align 16
# |   %3 = bitcast <16 x i8> %2 to <2 x i64>
# |   %4 = extractelement <2 x i64> %3, i32 1
# |   store atomic i64 %4, ptr %1 release, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vstl1q_lane_s64(ptr noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <2 x i64>, align 16
# |   %__s1 = alloca <2 x i64>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %__s1, align 16
# |   %3 = bitcast <16 x i8> %2 to <2 x i64>
# |   %4 = extractelement <2 x i64> %3, i32 1
# |   store atomic i64 %4, ptr %1 release, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vstl1q_lane_f64(ptr noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca 
# | ...
# `---data was truncated (10240/14230) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055a1ea862eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a1ea85fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a1ea86362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3927249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f39272a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3927249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3927231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a1ea7f8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a1ea7f8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a1ea7dd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a1ea48ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a1ea48cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3927232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f39272330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f39272330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a1ea48ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c (1635 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind
# | ...
# `---data was truncated (10240/365431) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d24c644eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d24c641e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d24c64562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcfb4049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcfb40a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcfb4049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcfb4031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d24c5dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d24c5daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d24c5bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d24c26ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d24c26eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcfb4032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcfb40330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcfb40330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d24c26ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c (1636 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f16m1x6(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f32m1x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f64m1x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i32> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e814f52eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e814f4fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e814f5362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0b1cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0b1cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0b1cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0b1cb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e814ee8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e814ee8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e814ecd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e814b7ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e814b7cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0b1cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0b1cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0b1cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e814b7ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c (1637 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vandn_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vandn_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vandn_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vandn_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vandn_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vandn_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vandn_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vandn_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vandn_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, al
# | ...
# `---data was truncated (10240/223137) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee3632deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ee3632ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ee3632e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0ea7d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0ea7d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0ea7d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0ea7d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee362c3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ee362c3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ee362a88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ee35f57e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ee35f57b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0ea7d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0ea7d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0ea7d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee35f57a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c (1638 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_i64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_i64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_u64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_u64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562e4c5c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562e4c5bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562e4c5c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efffb249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efffb2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efffb249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efffb231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562e4c556bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562e4c556a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562e4c53b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562e4c1eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562e4c1eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efffb232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efffb2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efffb2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562e4c1eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c (1639 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrsub_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrsub_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrsub_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrsub_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrsub_vx_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vrsub_vx_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vrsub_vx_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vrsub_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i16, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vrsub_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i16, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vsc
# | ...
# `---data was truncated (10240/207075) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055662d80feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055662d80ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055662d81062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f5d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f5d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f5d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f5d91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055662d7a5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055662d7a5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055662d78a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055662d439e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055662d439b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1f5d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f5d91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f5d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055662d439a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c (1640 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulu_vv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulu_vx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulu_vv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulu_vx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulu_vv_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulu_vx_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulu_vv_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulu_vx_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulu_vv_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>,
# | ...
# `---data was truncated (10240/154207) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561005e58eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561005e55e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561005e5962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7f15333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7f1538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7f15333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7f1531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561005deebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561005deea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561005dd38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561005a82e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561005a82b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7f1531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7f1531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7f1531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561005a82a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c (1641 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_f16m1x2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_f16m2x2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_f32m1x2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_f32m2x2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei64_v_f32m4x2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8
# | ...
# `---data was truncated (10240/96911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555fbfa4deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555fbfa4ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555fbfa4e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7a71d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7a71d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7a71d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7a71d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555fbf9e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555fbf9e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555fbf9c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555fbf677e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555fbf677b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7a71d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7a71d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7a71d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555fbf677a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c (1642 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055592fd8feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055592fd8ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055592fd9062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8884049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f88840a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8884049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8884031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055592fd25bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055592fd25a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055592fd0a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055592f9b9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055592f9b9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8884032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f88840330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f88840330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055592f9b9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c (1643 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei32_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei32_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei32_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, <vscale x 8 x i1>, i64, i64 immarg) #
# | ...
# `---data was truncated (10240/12075) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558250957eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558250954e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055825095862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f2521bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f252725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f2521ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f25203507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005582508edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005582508eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005582508d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558250581e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558250581b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2f25204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f252050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f252050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558250581a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c (1644 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhu_vv_u64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhu_vx_u64m1(<vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulhu_vv_u64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulhu_vx_u64m2(<vscale x 2 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulhu_vv_u64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 4 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulhu_vx_u64m4(<vscale x 4 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulhu_vv_u64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 8 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulhu_vx_u64m8(<vscale x 8 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhu_vv_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhu_vx_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load i64, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.
# | ...
# `---data was truncated (10240/18641) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a84a289eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a84a286e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a84a28a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff06ef05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff06ef5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff06ef05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff06eeed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a84a21fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a84a21fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a84a2048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a849eb3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a849eb3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff06eeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff06eeef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff06eeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a849eb3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c (1645 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwi
# | ...
# `---data was truncated (10240/44369) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561e9f876eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561e9f873e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561e9f87762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcab7649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcab76a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcab7649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcab7631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561e9f80cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561e9f80ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561e9f7f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561e9f4a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561e9f4a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcab7632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcab76330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcab76330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561e9f4a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c (1646 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei8_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vect
# | ...
# `---data was truncated (10240/31946) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cfdda64eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cfdda61e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cfdda6562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb53ce1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb53ce725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb53ce1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb53ce03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cfdd9fabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cfdd9faa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cfdd9df8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cfdd68ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cfdd68eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb53ce04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb53ce050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb53ce050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cfdd68ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c (1647 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulsu_vv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulsu_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulsu_vv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulsu_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulsu_vv_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulsu_vx_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulsu_vv_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulsu_vx_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulsu_vv_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op
# | ...
# `---data was truncated (10240/154517) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562e6c170eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562e6c16de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562e6c17162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4357d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4357d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4357d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4357d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562e6c106bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562e6c106a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562e6c0eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562e6bd9ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562e6bd9ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4357d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4357d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4357d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562e6bd9aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c (1648 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_i32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_i32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_u32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_u32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_f32mf2x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple"
# | ...
# `---data was truncated (10240/35929) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aee1c37eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aee1c34e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aee1c3862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff4fc505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff4fc55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff4fc505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff4fc4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aee1bcdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aee1bcda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aee1bb28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aee1861e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aee1861b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff4fc4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff4fc4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff4fc4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aee1861a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c (1649 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsub_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsub_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsub_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsub_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsub_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsub_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsub_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsub_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | ...
# `---data was truncated (10240/302389) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055958b45beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055958b458e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055958b45c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5f6b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5f6b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5f6b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5f6b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055958b3f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055958b3f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055958b3d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055958b085e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055958b085b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5f6b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5f6b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5f6b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055958b085a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c (1650 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei16_v_i8mf8x7
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556cafbe0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556cafbdde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556cafbe162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc95ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc95ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc95ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc95ed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556cafb76bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556cafb76a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556cafb5b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556caf80ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556caf80ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc95ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc95ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc95ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556caf80aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c (1651 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vunzipo_v_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 2 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(<vscale x 1 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(<vscale x 1 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vunzipo_v_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 4 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(<vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(<vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vunzipo_v_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 8 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vunzipo_v_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 16 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(<vscale x 8 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(<vscale x 8 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vunzipo_v_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 32 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(<vscale x 16 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(<vscale x 16 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vunzipo_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 2 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(<vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(<vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vunzipo_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 4 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(<vscale x 2 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vunzipo_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 8 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(<vscale x 4 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(<vscale x 4 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vunzipo_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 16 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(<vscale x 8 x float> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(<vscale x 8 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vunzipo_v_f64m1_tu(<vscale x 1 x double> %vd, <vscale x 2 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x double>, ptr %vs.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscal
# | ...
# `---data was truncated (10240/44426) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b06c4dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b06c4dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b06c4e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4210d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4210d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4210d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4210d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b06c475bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b06c475a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b06c45a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b06c109e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b06c109b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4210d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4210d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4210d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b06c109a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c (1652 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_v
# | ...
# `---data was truncated (10240/228865) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005607dc4a3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005607dc4a0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005607dc4a462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc902705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc90275c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc902705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc9026ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607dc439bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005607dc439a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005607dc41e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005607dc0cde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005607dc0cdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc9026eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc9026ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc9026ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607dc0cda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c (1653 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f16m1x6(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f32m1x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f64m1x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i16> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005571dfc32eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005571dfc2fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005571dfc3362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbad2449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbad24a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbad2449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbad2431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005571dfbc8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005571dfbc8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005571dfbad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005571df85ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005571df85cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbad2432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbad24330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbad24330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005571df85ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c (1654 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_f32mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_f32m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_i32mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_i32m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_u32mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_u32m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_i32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_i32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %
# | ...
# `---data was truncated (10240/14001) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dd62824eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dd62821e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dd6282562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f83ad933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83ad98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f83ad933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f83ad91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd627babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dd627baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dd6279f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dd6244ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dd6244eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f83ad91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83ad91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83ad91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd6244ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c (1655 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba9bc3eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ba9bc3be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ba9bc3f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4cc5305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4cc535c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4cc5305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4cc52ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba9bbd4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ba9bbd4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ba9bbb98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ba9b868e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ba9b868b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4cc52eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4cc52ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4cc52ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba9b868a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c (1656 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlsseg3e8_v_i8mf8x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e8_v_i8mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e8_v_i8mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e8_v_i8m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e8_v_i8m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlsseg3e8_v_u8mf8x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e8_v_u8mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e8_v_u8mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e8_v_u8m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e8_v_u8m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_
# | ...
# `---data was truncated (10240/23574) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563f65279eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563f65276e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563f6527a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3bfc933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3bfc98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3bfc933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3bfc91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563f6520fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563f6520fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563f651f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563f64ea3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563f64ea3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3bfc91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3bfc91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3bfc91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563f64ea3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c (1657 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaeskf1_vi_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaeskf1_vi_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaeskf1_vi_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaeskf1_vi_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaeskf1_vi_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556659088eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556659085e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055665908962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff24c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff24c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff24c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff24c631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055665901ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055665901ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005566590038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556658cb2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556658cb2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff24c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff24c6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff24c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556658cb2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c (1658 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaaddu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaaddu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaaddu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaaddu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaaddu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaaddu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaaddu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaaddu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaaddu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaaddu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vsc
# | ...
# `---data was truncated (10240/99843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b60ca44eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b60ca41e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b60ca4562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc33fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc33fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc33fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc33fd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b60c9dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b60c9daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b60c9bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b60c66ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b60c66eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc33fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc33fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc33fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b60c66ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/attr-counted-by-issue200014.c (1659 of 27911)
******************** TEST 'Clang :: CodeGen/attr-counted-by-issue200014.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 11
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -O0 -Wno-missing-declarations    -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c    | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c --check-prefix=FRONTEND
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -O0 -Wno-missing-declarations -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | %struct.annotated_flex = type { i64, i8, [0 x i8] }
# | 
# | @gaf = global { i64, i8, [15 x i8] } { i64 10, i8 0, [15 x i8] c"i am very long\00" }, align 8
# | @sink = external global i64, align 8
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @local_fam(i64 noundef %n) #0 {
# | entry:
# |   %n.addr = alloca i64, align 8
# |   %af = alloca %struct.annotated_flex, align 8
# |   store i64 %n, ptr %n.addr, align 8
# |   %count = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 0
# |   %0 = load i64, ptr %n.addr, align 8
# |   store i64 %0, ptr %count, align 8
# |   %induce_padding = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 1
# |   store i8 0, ptr %induce_padding, align 8
# |   %1 = getelementptr i8, ptr %af, i64 9
# |   call void @llvm.memset.p0.i64(ptr align 1 %1, i8 0, i64 7, i1 false)
# |   %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2
# |   %arraydecay = getelementptr inbounds [0 x i8], ptr %fam, i64 0, i64 0
# |   %2 = ptrtoint ptr %arraydecay to i64
# |   store i64 %2, ptr @sink, align 8
# |   %fam1 = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2
# |   %arraydecay2 = getelementptr inbounds [0 x i8], ptr %fam1, i64 0, i64 0
# |   %counted_by.gep = getelementptr inbounds i8, ptr %af, i64 0
# |   %counted_by.load = load i64, ptr %counted_by.gep, align 4
# |   %flexible_array_member_size = mul nuw i64 %counted_by.load, 1
# |   %3 = icmp sgt i64 %flexible_array_member_size, -1
# |   %4 = select i1 %3, i64 %flexible_array_member_size, i64 0
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.memset.p0.i64(ptr writeonly captures(none), i8, i64, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @local_subscript(i64 noundef %n) #0 {
# | entry:
# |   %n.addr = alloca i64, align 8
# |   %af = alloca %struct.annotated_flex, align 8
# |   store i64 %n, ptr %n.addr, align 8
# |   %count = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 0
# |   %0 = load i64, ptr %n.addr, align 8
# |   store i64 %0, ptr %count, align 8
# |   %induce_padding = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 1
# |   store i8 0, ptr %induce_padding, align 8
# |   %1 = getelementptr i8, ptr %af, i64 9
# |   call void @llvm.memset.p0.i64(ptr align 1 %1, i8 0, i64 7, i1 false)
# |   %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2
# |   %arrayidx = getelementptr inbounds [0 x i8], ptr %fam, i64 0, i64 2
# |   %2 = ptrtoint ptr %arrayidx to i64
# |   store i64 %2, ptr @sink, align 8
# |   %fam1 = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2
# |   %arrayidx2 = getelementptr inbounds [0 x i8], ptr %fam1, i64 0, i64 2
# |   %counted_by.gep = getelementptr inbounds i8, ptr %af, i64 0
# |   %counted_by.load = load i64, ptr %counted_by.gep, align 4
# |   %flexible_array_member_size = mul nuw i64 %counted_by.load, 1
# |   %result = sub nuw i64 %flexible_array_member_size, 2
# |   %3 = icmp sgt i64 %result, -1
# |   %4 = and i1 true, %3
# |   %5 = select i1 %4, i64 %result, i64 0
# |   ret i64 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @local_addrof(i64 noundef %n) #0 {
# | entry:
# |   %n.addr = alloca i64, align 8
# |   %af = alloca %struct.annotated_flex, align 8
# |   store i64 %n, ptr %n.addr, align 8
# |   %count = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 0
# |   %0 = load i64, ptr %n.addr, align 8
# |   store i64 %0, ptr %count, align 8
# |   %induce_padding = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 1
# |   store i8 0, ptr %induce_padding, align 8
# |   %1 = getelementptr i8, ptr %af, i64 9
# |   call void @llvm.memset.p0.i64(ptr align 1 %1, i8 0, i64 7, i1 false)
# |   %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2
# |   %2 = ptrtoint ptr %fam to i64
# |   store i64 %2, ptr @sink, align 8
# |   %fam1 = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2
# |   %3 = call i64 @llvm.objectsize.i64.p0(ptr %fam1, i1 false, i1 true, i1 true)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.objectsize.i64.p0(ptr, i1 immarg, i1 immarg, i1 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @global_fam() #0 {
# | entry:
# |   %counted_by.load = load i64, ptr @gaf, align 4
# |   %flexible_array_member_size = mul nuw i64 %counted_by.load, 1
# |   %0 = icmp sgt i64 %flexible_array_member_size, -1
# |   %1 = select i1 %0, i64 %flexible_array_member_size, i64 0
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @global_subscript() #0 {
# | entry:
# |   %counted_by.load = load i64, ptr @gaf, align 4
# |   %flexible_array_member_size = mul nuw i64 %counted_by.load, 1
# |   %result = sub nuw i64 %flexible_array_member_size, 3
# |   %0 = icmp sgt i64 %result, -1
# |   %1 = and i1 true, %0
# |   %2 = select i1 %1, i64 %result, i64 0
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @global_addrof() #0 {
# | entry:
# |   %0 = call i64 @llvm.objectsize.i64.p0(ptr getelementptr inbounds nuw (i8, ptr @gaf, i64 9), i1 false, i1 true, i1 true)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @ptr_fam(ptr noundef %p) #0 {
# | entry:
# |   %p.addr = alloca ptr, align 8
# |   store ptr %p, ptr %p.addr, align 8
# |   %0 = load ptr, ptr %p.addr, align 8
# |   %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %0, i32 0, i32 2
# |   %arraydecay = getelementptr inbounds [0 x i8], ptr %fam, i64 0, i64 0
# |   %1 = load ptr, ptr %p.addr, align 8
# |   %counted_by.gep = getelementptr inbounds i8, ptr %1, i64 0
# |   %counted_by.load = load i64, ptr %counted_by.gep, align 4
# |   %flexible_array_member_size = mul nuw i64 %counted_by.load, 1
# |   %2 = icmp sgt i64 %flexible_array_member_size, -1
# |   %3 = select i1 %2, i64 %flexible_array_member_size, i64 0
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @ptr_subscript(ptr noundef %p) #0 {
# | entry:
# |   %p.addr = alloca ptr, align 8
# |   store ptr %p, ptr %p.addr, align 8
# |   %0 = load ptr, ptr %p.addr, align 8
# |   %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %0, i32 0, i32 2
# |   %arrayidx = getelementptr inbounds [0 x i8], ptr %fam, i64 0, i64 3
# |   %1 = load ptr, ptr %p.addr, align 8
# |   %counted_by.gep = getelementptr inbounds i8, ptr %1, i64 0
# |   %counted_by.load = load i64, ptr %counted_by.gep, align 4
# |   %flexible_array_member_size = mul nuw i64 %counted_by.load, 1
# |   %result = sub nuw i64 %flexible_array_member_size, 3
# |   %2 = icmp sgt i64 %result, -1
# |   %3 = and i1 true, %2
# |   %4 = select i1 %3, i64 %result, i64 0
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @ptr_addrof(ptr noundef %p) #0 {
# | entry:
# |   %p.addr = alloca ptr, align 8
# |   store ptr %p, ptr %p.addr, align 8
# |   %0 = load ptr, ptr %p.addr, align 8
# |   %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %0, i32 0, i32 2
# |   %1 = call i64 @llvm.objectsize.i64.p0(ptr %fam, i1 false, i1 true, i1 true)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000559fcc76deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559fcc76ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559fcc76e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7f0c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7f0c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7f0c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7f0c031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559fcc703bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559fcc703a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559fcc6e88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559fcc397e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559fcc397b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7f0c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7f0c0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7f0c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559fcc397a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c --check-prefix=FRONTEND
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c --check-prefix=FRONTEND
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c (1660 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsqrt7_v_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsqrt7_v_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsqrt7_v_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsqrt7_v_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsqrt7_v_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrsqrt7_v_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsqrt7_v_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsqrt7_v_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsqrt7_v_bf16m1_tum(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqr
# | ...
# `---data was truncated (10240/28170) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a1a20a0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a1a209de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a1a20a162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc783533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc78358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc783533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc78351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a1a2036bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a1a2036a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a1a201b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a1a1ccae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a1a1ccab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc78351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc78351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc78351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a1a1ccaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c (1661 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabdu_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabdu_vx_u8mf8(<vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabdu_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabdu_vx_u8mf4(<vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabdu_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabdu_vx_u8mf2(<vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabdu_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabdu_vx_u8m1(<vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabdu_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabdu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabdu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabdu_vx_u8m2(<vscale x 16 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabdu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabdu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vabdu_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>
# | ...
# `---data was truncated (10240/97514) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559906768eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559906765e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055990676962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e79d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e79d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e79d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e79d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005599066febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005599066fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005599066e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559906392e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559906392b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0e79d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e79d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e79d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559906392a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c (1662 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f    -target-feature +xsfvfexp32e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexp_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexp_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexp_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexp_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32.i64(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfexp_v_f32m8_tu(<vscale x 16 x float> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32.i64(<vscale x 16 x float> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexp_v_f32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(<vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexp_v_f32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(<vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexp_v_f32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(<vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexp_v_f32m4_tum(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(<vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(<vscale x 8 x float>, <v
# | ...
# `---data was truncated (10240/22290) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005598059c3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005598059c0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005598059c462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd17b21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd17b2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd17b21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd17b203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559805959bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559805959a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055980593e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005598055ede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005598055edb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd17b204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd17b2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd17b2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005598055eda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c (1663 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlse16_v_f16mf4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16.p0.i64(<vscale x 1 x half> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlse16_v_f16mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16.p0.i64(<vscale x 2 x half> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlse16_v_f16m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16.p0.i64(<vscale x 4 x half> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlse16_v_f16m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16.p0.i64(<vscale x 8 x half> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlse16_v_f16m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16.p0.i64(<vscale x 16 x half> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlse16_v_f16m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16.p0.i64(<vscale x 32 x half> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vlse16_v_i16mf4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16.p0.i64(<vscale x 1 x i16> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vlse16_v_i16mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16.p0.i64(<vscale x 2 x i16> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vlse16_v_i16m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vlse.nxv4i16.p0.i64(<vscale x 4 x i16> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i16> @llvm.riscv.vlse.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vlse16_v_i16m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vlse.nxv8i16.p0.i64(<vscale x 8 x i16> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i16> @llvm.riscv.vlse.nxv8i16.p0.i64(<vscale x 8 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vlse16_v_i16m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vlse.nxv16i16.p0.i64(<vscale x 16 x i16> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x i16> @llvm.riscv.vlse.nxv16i16.p0.i64(<vscale x 16 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vlse16_v_
# | ...
# `---data was truncated (10240/35087) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005627d2184eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005627d2181e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005627d218562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe8d9f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe8d9f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe8d9f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe8d9eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005627d211abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005627d211aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005627d20ff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005627d1daee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005627d1daeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe8d9eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe8d9eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe8d9eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005627d1daea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c (1664 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmslt_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmslt_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmslt_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmslt_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmslt_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmslt_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmslt_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmslt_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmslt_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmslt_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmslt_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8.nxv32i8.i64(<vscale x 32 x 
# | ...
# `---data was truncated (10240/95089) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d053e75eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d053e72e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d053e7662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f519fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f519fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f519fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f519fc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d053e0bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d053e0ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d053df08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d053a9fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d053a9fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f519fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f519fc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f519fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d053a9fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c (1665 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vv_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vf_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wv_bf16mf4_f32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wf_bf16_f32mf2(<vscale x 1 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vv_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vf_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wv_bf16mf2_f32m1(<vscale x 2 x float> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wf_bf16_f32m1(<vscale x 2 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwsub_vv_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwsub_vf_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# | 
# | ...
# `---data was truncated (10240/86100) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055caa68d1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055caa68cee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055caa68d262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7275733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f727578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7275733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f727571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055caa6867bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055caa6867a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055caa684c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055caa64fbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055caa64fbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f727571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f727571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f727571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055caa64fba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c (1666 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vsext_vf2_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vsext_vf2_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vsext_vf2_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vsext_vf2_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vsext_vf2_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vsext_vf2_i16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf2_i32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf2_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf2_i32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vsext_vf2_i32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallbac
# | ...
# `---data was truncated (10240/66028) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562710b3eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562710b3be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562710b3f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ce9533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ce958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ce9533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ce951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562710ad4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562710ad4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562710ab98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562710768e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562710768b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4ce951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ce951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ce951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562710768a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c (1667 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv1i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv1i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8ff_v_i8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8ff_v_i8mf2x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8ff_v_i8m1x8_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_u8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv1i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8ff_v_u8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8ff_v_u8mf2x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>,
# | ...
# `---data was truncated (10240/12668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f9dafe5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f9dafe2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f9dafe662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f738c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f738c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f738c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f738c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f9daf7bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f9daf7ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f9daf608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f9dac0fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f9dac0fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f738c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f738c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f738c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f9dac0fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c (1668 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556121374eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556121371e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055612137562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4dd8449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4dd84a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4dd8449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4dd8431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055612130abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055612130aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005561212ef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556120f9ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556120f9eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4dd8432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4dd84330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4dd84330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556120f9ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c (1669 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563155091eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056315508ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056315509262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc1bc849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc1bc8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc1bc849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc1bc831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563155027bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563155027a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056315500c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563154cbbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563154cbbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc1bc832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc1bc8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc1bc8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563154cbba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c (1670 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfne_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfne_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfne_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/66557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055614fa3beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055614fa38e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055614fa3c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2e46449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2e464a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2e46449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2e46431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055614f9d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055614f9d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055614f9b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055614f665e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055614f665b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2e46432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2e464330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2e464330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055614f665a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c (1671 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_f32mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_f32m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_f32m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_f32m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_i32mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_i32m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_i32m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_i32m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_u32mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_u32m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define d
# | ...
# `---data was truncated (10240/26976) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d261d45eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d261d42e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d261d4662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e56e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e56ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e56e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e56e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d261cdbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d261cdba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d261cc08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d26196fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d26196fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7e56e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e56e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e56e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d26196fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c (1672 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   s
# | ...
# `---data was truncated (10240/223359) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564fe271beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564fe2718e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564fe271c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc22181bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc2218725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc22181ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc221803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564fe26b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564fe26b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564fe26968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564fe2345e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564fe2345b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc221804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc2218050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc2218050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564fe2345a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c (1673 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nx
# | ...
# `---data was truncated (10240/18660) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f311d34eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f311d31e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f311d3562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc138533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc13858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc138533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc13851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f311ccabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f311ccaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f311caf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f31195ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f31195eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc13851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc13851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc13851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f31195ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c (1674 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsub_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsub_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsub_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsub_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsub_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsub_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsub_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsub_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsub_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsub_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsub.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i
# | ...
# `---data was truncated (10240/125641) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005588b4198eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005588b4195e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005588b419962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4011c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4011c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4011c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4011c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005588b412ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005588b412ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005588b41138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005588b3dc2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005588b3dc2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4011c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4011c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4011c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005588b3dc2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c (1675 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8ff_v_i8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8ff_v_i8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8ff_v_i8m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_u8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8ff_v_u8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8ff_v_u8mf2
# | ...
# `---data was truncated (10240/54694) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558116e5aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558116e57e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558116e5b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9b04f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9b04f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9b04f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9b04f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558116df0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558116df0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558116dd58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558116a84e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558116a84b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9b04f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9b04f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9b04f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558116a84a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c (1676 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwcvt_x_x_v_i16mf4(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwcvt_x_x_v_i16mf2(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwcvt_x_x_v_i16m1(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwcvt_x_x_v_i16m2(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwcvt_x_x_v_i16m4(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwcvt_x_x_v_i16m8(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwcvt_x_x_v_i32mf2(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwcvt_x_x_v_i32m1(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwcvt_x_x_v_i32m2(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vwcvt_x_x_v_i32m4(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vwcvt_x_x_v_i32m8(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vwadd.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vwadd.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vwcvt_x_x_v_i64m1(<vscale x 1 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> %0, i32 0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i32, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vwcvt_x_x_v_i64m2(<vscale x 2 x i32> %src, i64
# | ...
# `---data was truncated (10240/29175) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de21cf0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055de21cede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055de21cf162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd332449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd3324a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd332449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd332431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de21c86bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055de21c86a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055de21c6b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055de2191ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055de2191ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd332432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd3324330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd3324330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de2191aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c (1677 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_bf16m1x4_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function 
# | ...
# `---data was truncated (10240/22115) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005632c59b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005632c59b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005632c59b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b8e61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b8e6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b8e61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b8e603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005632c5949bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005632c5949a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005632c592e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005632c55dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005632c55ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3b8e604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b8e6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b8e6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005632c55dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c (1678 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsll_vv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsll_vx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsll_vv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsll_vx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsll_vv_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsll_vx_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vwsll_vv_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vwsll_vx_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vwsll_vv_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>
# | ...
# `---data was truncated (10240/153805) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056474252ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564742529e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056474252d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd6ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd6cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd6ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd6ce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005647424c2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005647424c2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005647424a78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564742156e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564742156b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbd6ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd6ce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd6ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564742156a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c (1679 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16mf4(ptr noundef %base, <vscale x 1 x i16> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16mf2(ptr noundef %base, <vscale x 2 x i16> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16m1(ptr noundef %base, <vscale x 4 x i16> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16m2(ptr noundef %base, <vscale x 8 x i16> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16m4(ptr noundef %base, <vscale x 16 x i16> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16m8(ptr noundef %base, <vscale x 32 x i16> %bindex, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> %2, ptr %0, <vscale x 32 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f32mf2(ptr noundef %base, <vscale x 1 x i16> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f32m1(ptr noundef %base, <vscale x 2 x i16> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f32m2(ptr noundef %base, <vscale x 4 x i16> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i16> %1, i6
# | ...
# `---data was truncated (10240/132470) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563e7e1dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563e7e1dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563e7e1e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f10f0733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f10f078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f10f0733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f10f071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e7e175bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563e7e175a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563e7e15a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563e7de09e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563e7de09b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f10f071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f10f071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f10f071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e7de09a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c (1680 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_f16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_f16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_f16m1x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_i16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_i16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_i16m1x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_u16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_u16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_u16m1x8_m(<vs
# | ...
# `---data was truncated (10240/11851) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558a53f95eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558a53f92e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558a53f9662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e5fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e5faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e5fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e5fa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a53f2bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558a53f2ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558a53f108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558a53bbfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558a53bbfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4e5fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e5fa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e5fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a53bbfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c (1681 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i64> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %3, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, <vscale x 8 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-feature
# | ...
# `---data was truncated (10240/10692) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055989c76eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055989c76be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055989c76f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb03d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb03d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb03d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb03d31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055989c704bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055989c704a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055989c6e98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055989c398e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055989c398b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb03d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb03d31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb03d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055989c398a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c (1682 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfgt_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfgt_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfgt_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 32 x bflo
# | ...
# `---data was truncated (10240/27786) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d5d9428eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d5d9425e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d5d942962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f87aa41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87aa4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f87aa41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87aa403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d5d93bebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d5d93bea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d5d93a38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d5d9052e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d5d9052b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f87aa404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87aa4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87aa4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d5d9052a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c (1683 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 
# | ...
# `---data was truncated (10240/296951) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005589a3439eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005589a3436e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005589a343a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f797a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f797a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f797a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f797a631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589a33cfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005589a33cfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005589a33b48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005589a3063e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005589a3063b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f797a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f797a6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f797a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005589a3063a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c (1684 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_f16mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_f16mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_f16m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_i16mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_i16mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_i16m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_u16mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_u16mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_u16m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_f16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsse
# | ...
# `---data was truncated (10240/20441) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d3de02aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d3de027e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d3de02b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6308133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f630818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6308133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f630811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d3ddfc0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d3ddfc0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d3ddfa58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d3ddc54e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d3ddc54b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f630811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f630811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f630811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d3ddc54a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c (1685 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_rtz_x_f_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_rtz_x_f_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_rtz_x_f_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_rtz_x_f_v_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_rtz_x_f_v_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_rtz_x_f_v_i16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_rtz_xu_f_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_rtz_xu_f_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_rtz_xu_f_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_rtz_xu_f_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/135337) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c3f3f4feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c3f3f4ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c3f3f5062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba69333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba6938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba69333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba6931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c3f3ee5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c3f3ee5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c3f3eca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c3f3b79e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c3f3b79b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fba6931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba6931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba6931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c3f3b79a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c (1686 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f16m1x7(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f32m1x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f64m1x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i64> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056511c218eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056511c215e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056511c21962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f535b105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f535b15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f535b105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f535b0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056511c1aebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056511c1aea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056511c1938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056511be42e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056511be42b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f535b0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f535b0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f535b0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056511be42a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c (1687 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_i16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_i16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 
# | ...
# `---data was truncated (10240/80500) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558dca993eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558dca990e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558dca99462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd376649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd3766a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd376649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd376631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558dca929bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558dca929a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558dca90e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558dca5bde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558dca5bdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd376632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd3766330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd3766330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558dca5bda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c (1688 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_bf16mf2x8(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_bf16m1x8(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b8f09dbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b8f09d8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b8f09dc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f198d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f198d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f198d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f198d11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b8f0971bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b8f0971a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b8f09568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b8f0605e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b8f0605b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f198d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f198d11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f198d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b8f0605a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c (1689 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_bf16mf2x6(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_bf16m1x6(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056314b616eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056314b613e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056314b61762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f94b9c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f94b9ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f94b9c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f94b9c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056314b5acbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056314b5aca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056314b5918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056314b240e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056314b240b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f94b9c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f94b9c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f94b9c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056314b240a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c (1690 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32mf2(ptr noundef %base, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1f32.p0.i64(<vscale x 1 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32m1(ptr noundef %base, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2f32.p0.i64(<vscale x 2 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32m2(ptr noundef %base, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4f32.p0.i64(<vscale x 4 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32m4(ptr noundef %base, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8f32.p0.i64(<vscale x 8 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32m8(ptr noundef %base, <vscale x 16 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16f32.p0.i64(<vscale x 16 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32mf2(ptr noundef %base, <vscale x 1 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i32.p0.i64(<vscale x 1 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32m1(ptr noundef %base, <vscale x 2 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i32.p0.i64(<vscale x 2 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32m2(ptr noundef %base, <vscale x 4 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i32.p0.i64(<vscale x 4 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32m4(ptr noundef %base, <vscale x 8 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i32.p0.i64(<vscale x 8 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32m8(ptr noundef %base, <vscale x 16 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16i32.p0.i64(<vscale x 16 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16i32.p0.i64(<vscale x 16 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_u32mf2(ptr noundef %base, <vscale x 1 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i32.p0.i64(<vscale x 1 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_u32m1(ptr noundef %base, <vscale x 2 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i32.p0.i64(<vscale x 2 x i32> %1,
# | ...
# `---data was truncated (10240/28354) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c2f2b2beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c2f2b28e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c2f2b2c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f559db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f559db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f559db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f559db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c2f2ac1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c2f2ac1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c2f2aa68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c2f2755e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c2f2755b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f559db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f559db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f559db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c2f2755a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c (1691 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vunzipe_v_f16mf4(<vscale x 2 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(<vscale x 1 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(<vscale x 1 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vunzipe_v_f16mf2(<vscale x 4 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(<vscale x 2 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(<vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vunzipe_v_f16m1(<vscale x 8 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vunzipe_v_f16m2(<vscale x 16 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(<vscale x 8 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(<vscale x 8 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vunzipe_v_f16m4(<vscale x 32 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(<vscale x 16 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(<vscale x 16 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vunzipe_v_f32mf2(<vscale x 2 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(<vscale x 1 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(<vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vunzipe_v_f32m1(<vscale x 4 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vunzipe_v_f32m2(<vscale x 8 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(<vscale x 4 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(<vscale x 4 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vunzipe_v_f32m4(<vscale x 16 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(<vscale x 8 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(<vscale x 8 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vunzipe_v_f64m1(<vscale x 2 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64(<vscale x 1 x double>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vunzipe_v_f64m2(<vscale x 4 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.vunzipe.nxv2f64.nxv4f64.i64(<vscale x 2 x double> poison, <vscale x 4 x double> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vunzipe.nxv2f64.nxv4f64.i64(<vscale x 2 x double>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vunzipe_v_f64m4(<vscale x 8 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.vunzipe.nxv4f64.nxv8f64.i64(<vscale x 4 x double> poison, <vscale x 8 x double> %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.vunzipe.nxv4f64.nxv8f64.i64(<vscale x 4 x double>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1
# | ...
# `---data was truncated (10240/35782) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c41dedaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c41ded7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c41dedb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f018f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f018f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f018f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f018f91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c41de70bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c41de70a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c41de558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c41db04e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c41db04b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f018f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f018f91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f018f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c41db04a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminvq.c (1692 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminvq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc signext i8 @test_vminvq_s8(i8 noundef signext %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load i8, ptr %a.addr, align 1
# |   %1 = zext i8 %0 to i32
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.minv.v16i8(i32 %1, <16 x i8> %2, i32 0)
# |   %4 = trunc i32 %3 to i8
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.minv.v16i8(i32, <16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc signext i16 @test_vminvq_s16(i16 noundef signext %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load i16, ptr %a.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.minv.v8i16(i32 %1, <8 x i16> %2, i32 0)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.minv.v8i16(i32, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vminvq_s32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call i32 @llvm.arm.mve.minv.v4i32(i32 %0, <4 x i32> %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.minv.v4i32(i32, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vminvq_u8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load i8, ptr %a.addr, align 1
# |   %1 = zext i8 %0 to i32
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.minv.v16i8(i32 %1, <16 x i8> %2, i32 1)
# |   %4 = trunc i32 %3 to i8
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vminvq_u16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load i16, ptr %a.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.minv.v8i16(i32 %1, <8 x i16> %2, i32 1)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vminvq_u32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call i32 @llvm.arm.mve.minv.v4i32(i32 %0, <4 x i32> %1, i32 1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc signext i8 @test_vmaxvq_s8(i8 noundef signext %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load i8, ptr %a.addr, align 1
# |   %1 = zext i8 %0 to i32
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.maxv.v16i8(i32 %1, <16 x i8> %2, i32 0)
# |   %4 = trunc i32 %3 to i8
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.maxv.v16i8(i32, <16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc signext i16 @test_vmaxvq_s16(i16 noundef signext %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load i16, ptr %a.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.maxv.v8i16(i32 %1, <8 x i16> %2, i32 0)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.maxv.v8i16(i32, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmaxvq_s32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call i32 @llvm.arm.mve.maxv.v4i32(i32 %0, <4 x i32> %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.maxv.v4i32(i32, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vmaxvq_u8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load i8, ptr %a.addr, align 1
# |   %1 = zext i8 %0 to i32
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.maxv.v16i8(i32 %1, <16 x i8> %2, i32 1)
# |   %4 = trunc i32 %3 to i8
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vmaxvq_u16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load i16, ptr %a.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.maxv.v8i16(i32 %1, <8 x i16> %2, i32 1)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmaxvq_u32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call i32 @llvm.arm.mve.maxv.v4i32(i32 %0, <4 x i32> %1, i32 1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vminavq_s8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load i8, ptr %a.addr, align 1
# |   %1 = zext i8 %0 to i32
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.minav.v16i8(i32 %1, <16 x i8> %2)
# |   %4 = trunc i32 %3 to i8
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.minav.v16i8(i32, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vminavq_s16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load i16, ptr %a.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.minav.v8i16(i32 %1, <8 x i16> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.minav.v8i16(i32, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vminavq_s32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call i32 @llvm.arm.mve.minav.v4i32(i32 %0, <4 x i32> %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.minav.v4i32(i32, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vmaxavq_s8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load i8, ptr %a.addr, align 1
# |   %1 = zext i8 %0 to i32
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.maxav.v16i8(i32 %1, <16 x i8> %2)
# |   %4 = trunc i32 %3 to i8
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.maxav.v16i8(i32, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vmaxavq_s16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load i16, ptr %a.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.maxav.v8i16(i32 %1, <8 x i16> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 
# | ...
# `---data was truncated (10240/39417) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055ac098b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ac098b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ac098b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb5c3e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb5c3ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb5c3e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb5c3e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac0984bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ac0984ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ac098308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ac094dfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ac094dfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb5c3e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb5c3e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb5c3e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac094dfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-vls-shift-ops.c (1693 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-shift-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d  -target-feature +f -target-feature +d -disable-O0-optnone  -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c |  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @lshift_i8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %shl = shl <32 x i8> %0, %1
# |   store <32 x i8> %shl, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8>, <32 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @rshift_i8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %shr = ashr <32 x i8> %0, %1
# |   store <32 x i8> %shr, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @lshift_u8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %shl = shl <32 x i8> %0, %1
# |   store <32 x i8> %shl, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @rshift_u8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %shr = lshr <32 x i8> %0, %1
# |   store <32 x i8> %shr, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @lshift_i16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %shl = shl <16 x i16> %0, %1
# |   store <16 x i16> %shl, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16>, <16 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @rshift_i16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %shr = ashr <16 x i16> %0, %1
# |   store <16 x i16> %shr, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @lshift_u16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %shl = shl <16 x i16> %0, %1
# |   store <16 x i16> %shl, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @rshift_u16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %shr = lshr <16 x i16> %0, %1
# |   store <16 x i16> %shr, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @lshift_i32(<vscale x 2 x i32> noundef %a.coerce, <vscale x 2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i32>, align 8
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca <8 x i32>, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %b.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i32>, ptr %b.addr, align 8
# |   %shl = shl <8 x i32> %0, %1
# |   store <8 x i32> %shl, ptr %retval, align 8
# |   %2 = load <8 x i32>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> %2, i64 0)
# |   ret <vscale x 2 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32>, <8 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @rshift_i32(<vscale x 2 x i32> noundef %a.coerce, <vscale x 2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %r
# | ...
# `---data was truncated (10240/50943) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055b18ff9feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b18ff9ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b18ffa062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f204a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f204a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f204a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f204a11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b18ff35bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b18ff35a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b18ff1a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b18fbc9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b18fbc9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f204a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f204a11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f204a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b18fbc9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqdmullbq.c (1694 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqdmullbq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %1, i32 0)
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_m_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_m_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <2 x i64>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <2 x i64> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3)
# |   %5 = load <2 x i64>, ptr %inactive.addr, align 8
# |   %6 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %1, i32 0, <2 x i1> %4, <2 x i64> %5)
# |   ret <2 x i64> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32>, <4 x i32>, i32, <2 x i1>, <2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %.splat, i32 0)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %.splat, i32 0)
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_m_n_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %.splat, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_m_n_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <2 x i64>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store <2 x i64> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3)
# |   %5 = load <2 x i64>, ptr %inactive.addr, align 8
# |   %6 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %.splat, i32 0, <2 x i1> %4, <2 x i64> %5)
# |   ret <2 x i64> %6
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec0a921eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ec0a91ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ec0a92262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb815a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb815aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb815a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb815a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec0a8b7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ec0a8b7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ec0a89c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ec0a54be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ec0a54bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb815a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb815a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb815a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec0a54ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbkx.c (1695 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbkx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkx -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c  -check-prefix=RV32ZBKX
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkx -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @xperm8_32(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.xperm8.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @xperm4_32(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.xperm4.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.xperm8.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.xperm4.i32(i32, i32) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbkx" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zbkx1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555f1b83feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555f1b83ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555f1b84062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fed10505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fed1055c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fed10505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fed104ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f1b7d5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555f1b7d5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555f1b7ba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555f1b469e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555f1b469b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fed104eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fed104ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fed104ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f1b469a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c -check-prefix=RV32ZBKX
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c -check-prefix=RV32ZBKX
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c (1696 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfge_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfge_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfge_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/66557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560f60bbaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560f60bb7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560f60bbb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0f3fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0f3fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0f3fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0f3fd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f60b50bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560f60b50a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560f60b358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560f607e4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560f607e4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0f3fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0f3fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0f3fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f607e4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c (1697 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_i32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_i32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_u32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_u32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_f32mf2x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple,
# | ...
# `---data was truncated (10240/40726) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560f2574feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560f2574ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560f2575062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9e4e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9e4e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9e4e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9e4e231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f256e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560f256e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560f256ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560f25379e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560f25379b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9e4e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9e4e2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9e4e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f25379a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c (1698 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsrl_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsrl_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsrl_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsrl_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsrl_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsrl_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsrl_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsrl_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsrl_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 
# | ...
# `---data was truncated (10240/223863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005635866d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005635866d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005635866d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9ab1049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9ab10a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9ab1049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9ab1031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056358666bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056358666ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005635866508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005635862ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005635862ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9ab1032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9ab10330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9ab10330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005635862ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c (1699 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f16m1x3(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f16m2x3(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f32m1x3(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f32m2x3(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f64m1x3(ptr noundef %base, <vscale x 1 x i16
# | ...
# `---data was truncated (10240/99762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c1cc9d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c1cc9d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c1cc9d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbdd5449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbdd54a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbdd5449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbdd5431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c1cc96cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c1cc96ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c1cc9518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c1cc600e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c1cc600b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbdd5432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbdd54330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbdd54330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c1cc600a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c (1700 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmnor_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmnor.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmnor.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmnor_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmnor.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmnor.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmnor_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmnor.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmnor.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmnor_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmnor.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmnor.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmnor_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmnor.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmnor.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmnor_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmnor.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmnor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmnor_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmnor.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmnor.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005593cfa3beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005593cfa38e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005593cfa3c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb4df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb4df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb4df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb4df1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005593cf9d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005593cf9d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005593cf9b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005593cf665e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005593cf665b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffb4df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb4df1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb4df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005593cf665a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c (1701 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 8 x i64>, ptr %rs2.addr
# | ...
# `---data was truncated (10240/20623) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d43c48feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d43c48ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d43c49062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f611a01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f611a0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f611a01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f611a003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d43c425bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d43c425a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d43c40a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d43c0b9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d43c0b9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f611a004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f611a0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f611a0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d43c0b9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c (1702 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nx
# | ...
# `---data was truncated (10240/18660) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055594d8dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055594d8dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055594d8e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f219fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f219fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f219fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f219fe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055594d875bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055594d875a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055594d85a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055594d509e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055594d509b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f219fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f219fe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f219fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055594d509a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c (1703 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c  -check-prefix=RV64ZKND
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @aes64dsm(i64 noundef %rs1, i64 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %__y.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %rs2.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   store i64 %1, ptr %__y.addr.i, align 8
# |   %2 = load i64, ptr %__x.addr.i, align 8
# |   %3 = load i64, ptr %__y.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.aes64dsm(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @aes64ds(i64 noundef %rs1, i64 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %__y.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %rs2.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   store i64 %1, ptr %__y.addr.i, align 8
# |   %2 = load i64, ptr %__x.addr.i, align 8
# |   %3 = load i64, ptr %__y.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.aes64ds(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @aes64im(i64 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   %1 = load i64, ptr %__x.addr.i, align 8
# |   %2 = call i64 @llvm.riscv.aes64im(i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.aes64dsm(i64, i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.aes64ds(i64, i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.aes64im(i64) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zknd" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zknd1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558e9eef1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558e9eeeee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558e9eef262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd99b305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd99b35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd99b305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd99b2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558e9ee87bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558e9ee87a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558e9ee6c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558e9eb1be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558e9eb1bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd99b2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd99b2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd99b2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558e9eb1ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c -check-prefix=RV64ZKND
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c -check-prefix=RV64ZKND
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c (1704 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f16m1x7(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f32m1x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f64m1x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005645bd44ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005645bd449e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005645bd44d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd5dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd5dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd5dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd5dd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005645bd3e2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005645bd3e2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005645bd3c78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005645bd076e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005645bd076b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdd5dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd5dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd5dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005645bd076a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c (1705 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfne_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfne_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfne_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64
# | ...
# `---data was truncated (10240/66565) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c513aeceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c513ae9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c513aed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd2b0933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd2b098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd2b0933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd2b091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c513a82bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c513a82a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c513a678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c513716e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c513716b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd2b091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd2b091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd2b091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c513716a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c (1706 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560c1484feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560c1484ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560c1485062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff045649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff0456a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff045649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff045631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c147e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560c147e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560c147ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560c14479e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560c14479b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff045632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff0456330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff0456330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c14479a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c (1707 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zvfhmin -target-feature +zvfbfmin    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste16_bf16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.sf.vste16.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste16_f16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste16_i16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste16_u16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvfbfmin,+zvfhmin,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfhmin1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558c4ff03eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558c4ff00e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558c4ff0462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbe3db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbe3db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbe3db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbe3db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c4fe99bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558c4fe99a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558c4fe7e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558c4fb2de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558c4fb2db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbe3db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbe3db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbe3db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c4fb2da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c (1708 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { ta
# | ...
# `---data was truncated (10240/27858) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b26ff52eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b26ff4fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b26ff5362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f85bda1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f85bda725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f85bda1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f85bda03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b26fee8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b26fee8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b26fecd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b26fb7ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b26fb7cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f85bda04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f85bda050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f85bda050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b26fb7ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c (1709 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_i8mf8x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_i8mf4x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_i8mf2x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8_v_i8m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_u8mf8x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_u8mf4x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_u8mf2x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8_v_u8m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_i8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_i8mf2x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = c
# | ...
# `---data was truncated (10240/16451) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565324d99eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565324d96e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000565324d9a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f30d4249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f30d42a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f30d4249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f30d4231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565324d2fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565324d2fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000565324d148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005653249c3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005653249c3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f30d4232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f30d42330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f30d42330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005653249c3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c (1710 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_f32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_i32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_i32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_i32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_u32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base
# | ...
# `---data was truncated (10240/60683) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560b4244aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560b42447e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560b4244b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f87c9133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87c918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f87c9133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87c911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b423e0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560b423e0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560b423c58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560b42074e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560b42074b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f87c911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87c911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87c911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b42074a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c (1711 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vslide1down_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vslide1down_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vslide1down_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vslide1down_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vslide1down_vx_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vslide1down_vx_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vslide1down_vx_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vslide1down_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i16, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vslide1down_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, 
# | ...
# `---data was truncated (10240/211231) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f111ed9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f111ed6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f111eda62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f64fed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f64fed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f64fed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f64fed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f111e6fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f111e6fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f111e548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f111b03e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f111b03b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f64fed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f64fed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f64fed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f111b03a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c (1712 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmaxu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmaxu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmaxu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmaxu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmaxu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmaxu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmaxu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmaxu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmaxu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x
# | ...
# `---data was truncated (10240/222925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c8cb144eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c8cb141e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c8cb14562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2e5e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2e5e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2e5e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2e5e831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c8cb0dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c8cb0daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c8cb0bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c8cad6ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c8cad6eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2e5e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2e5e8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2e5e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c8cad6ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c (1713 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556a952f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556a952f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556a952fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa511649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa5116a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa511649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa511631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556a9528fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556a9528fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556a952748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556a94f23e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556a94f23b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa511632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa5116330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa5116330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556a94f23a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c (1714 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadd_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadd_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadd_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadd_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadd_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadd_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadd_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadd_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vadd_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vadd_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vadd_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/175155) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005622ff6a9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005622ff6a6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005622ff6aa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f897bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f897bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f897bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f897bb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005622ff63fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005622ff63fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005622ff6248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005622ff2d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005622ff2d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f897bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f897bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f897bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005622ff2d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c (1715 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4r_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4r.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4r.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4r_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4r_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4r_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm4r_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4r_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4r_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare 
# | ...
# `---data was truncated (10240/20139) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005644d4602eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005644d45ffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005644d460362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7750733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f775078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7750733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f775071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005644d4598bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005644d4598a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005644d457d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005644d422ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005644d422cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f775071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f775071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f775071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005644d422ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c (1716 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_f16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_f16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_f16m1x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_i16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_i16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_i16m1x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_u16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("ri
# | ...
# `---data was truncated (10240/13634) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561b43491eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561b4348ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561b4349262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe79ab05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe79ab5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe79ab05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe79aaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561b43427bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561b43427a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561b4340c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561b430bbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561b430bbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe79aaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe79aaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe79aaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561b430bba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/cplusplus.cpp (1717 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/cplusplus.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc noundef <8 x i16> @_Z16test_vbicq_n_s1617__simd128_int16_t(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = and <8 x i16> %0, splat (i16 11007)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc noundef <4 x i32> @_Z16test_vbicq_n_u3218__simd128_uint32_t(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = and <4 x i32> %0, splat (i32 -8193)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc noundef <4 x i32> @_Z16test_vorrq_n_s3217__simd128_int32_t(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = or <4 x i32> %0, splat (i32 65536)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc noundef <8 x i16> @_Z16test_vorrq_n_u1618__simd128_uint16_t(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = or <8 x i16> %0, splat (i16 -4096)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc noundef zeroext i16 @_Z16test_vcmpeqq_f1619__simd128_float16_tS_(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = fcmp oeq <8 x half> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>) #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc noundef zeroext i16 @_Z18test_vcmpeqq_n_f1619__simd128_float16_tDh(<8 x half> noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca half, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load half, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x half> poison, half %1, i64 0
# |   %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
# |   %2 = fcmp oeq <8 x half> %0, %.splat
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc noundef <8 x i16> @_Z14test_vld1q_u16PKt(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x i16>, ptr %0, align 2
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc void @_Z16test_vst1q_p_s32Pi17__simd128_int32_tt(ptr noundef %base, <4 x i32> noundef %value, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %value.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store <4 x i32> %value, ptr %value.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %value.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 4
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   call void @llvm.masked.store.v4i32.p0(<4 x i32> %0, ptr align 4 %1, <4 x i1> %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr captures(none), <4 x i1>) #2
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc noundef <2 x i64> @_Z30test_vldrdq_gather_base_wb_s64P18__simd128_uint64_t(ptr noundef %addr) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = load <2 x i64>, ptr %0, align 8
# |   %2 = call { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.v2i64.v2i64(<2 x i64> %1, i32 576)
# |   %3 = extractvalue { <2 x i64>, <2 x i64> } %2, 1
# |   store <2 x i64> %3, ptr %0, align 8
# |   %4 = extractvalue { <2 x i64>, <2 x i64> } %2, 0
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.v2i64.v2i64(<2 x i64>, i32) #3
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc void @_Z31test_vstrwq_scatter_base_wb_u32P18__simd128_uint32_tS_(ptr noundef %addr, <4 x i32> noundef %value) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   %value.addr = alloca <4 x i32>, align 8
# |   store ptr %addr, ptr %addr.addr, align 4
# |   store <4 x i32> %value, ptr %value.addr, align 8
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = load <4 x i32>, ptr %0, align 8
# |   %2 = load <4 x i32>, ptr %value.addr, align 8
# |   %3 = call <4 x i32> @llvm.arm.mve.vstr.scatter.base.wb.v4i32.v4i32(<4 x i32> %1, i32 64, <4 x i32> %2)
# |   store <4 x i32> %3, ptr %0, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare <4 x i32> @llvm.arm.mve.vstr.scatter.base.wb.v4i32.v4i32(<4 x i32>, i32, <4 x i32>) #4
# | 
# | attributes #0 = { mustprogress noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | attributes #3 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | attributes #4 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f169214eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f169211e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f16921562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f03b6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03b618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f03b6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f03b611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f1691aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f1691aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f16918f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f168e3ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f168e3eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f03b611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03b611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03b611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f168e3ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c (1718 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f16m1x6(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f32m1x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f64m1x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/69980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555e8e681eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555e8e67ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555e8e68262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9f89049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9f890a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9f89049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9f89031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555e8e617bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555e8e617a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555e8e5fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555e8e2abe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555e8e2abb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9f89032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9f890330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9f890330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555e8e2aba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c (1719 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005634cfa93eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005634cfa90e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005634cfa9462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fed38249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fed382a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fed38249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fed38231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005634cfa29bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005634cfa29a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005634cfa0e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005634cf6bde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005634cf6bdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fed38232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fed382330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fed382330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005634cf6bda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c (1720 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wf_bf16_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wf_bf16_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 
# | ...
# `---data was truncated (10240/199596) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f614632eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f61462fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f61463362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff3b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff3b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff3b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff3b71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f6145c8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f6145c8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f6145ad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f61425ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f61425cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007eff3b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff3b71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff3b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f61425ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c (1721 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_f32mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_f32m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_i32mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_i32m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_u32mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_u32m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs:
# | ...
# `---data was truncated (10240/16382) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005609eeb09eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005609eeb06e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005609eeb0a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f60a2933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f60a298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f60a2933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f60a291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005609eea9fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005609eea9fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005609eea848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005609ee733e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005609ee733b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f60a291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f60a291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f60a291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005609ee733a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c (1722 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmacc_4x8x4_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmacc_4x8x4_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmacc_4x8x4_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmacc_4x8x4_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c21d644eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c21d641e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c21d64562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e7c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e7c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e7c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e7c51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c21d5dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c21d5daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c21d5bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c21d26ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c21d26eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7e7c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e7c51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e7c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c21d26ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c (1723 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmin_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmin_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmin_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmin_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmin_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmin_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmin_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmin_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Funct
# | ...
# `---data was truncated (10240/64950) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555891fcceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555891fc9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555891fcd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f595e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f595e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f595e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f595e71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555891f62bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555891f62a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555891f478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555891bf6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555891bf6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f595e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f595e71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f595e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555891bf6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c (1724 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmadd_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmadd_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmadd_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmadd_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmadd_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmadd_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmadd_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmadd_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <
# | ...
# `---data was truncated (10240/34430) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005627a3683eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005627a3680e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005627a368462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f30733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f3078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f30733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f3071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005627a3619bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005627a3619a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005627a35fe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005627a32ade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005627a32adb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6f3071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f3071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f3071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005627a32ada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c (1725 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasub_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasub_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasub_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasub_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasub_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasub_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasub_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasub_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasub_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasub_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vasub_vv_i8
# | ...
# `---data was truncated (10240/99577) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556b0915deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556b0915ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556b0915e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1b60f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1b60f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1b60f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1b60f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b090f3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556b090f3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556b090d88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556b08d87e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556b08d87b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1b60f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1b60f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1b60f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b08d87a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c (1726 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_i8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_i8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8_v_i8m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_u8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_u8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_u8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8_v_u8m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_i8mf8x5_tum(<vscale x 1 x 
# | ...
# `---data was truncated (10240/43119) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f3979b0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f3979ade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f3979b162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f16b5f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f16b5f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f16b5f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f16b5f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f397946bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f397946a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f39792b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f3975dae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f3975dab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f16b5f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f16b5f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f16b5f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f3975daa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c (1727 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_u64m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056022a815eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056022a812e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056022a81662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6411733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f641178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6411733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f641171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056022a7abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056022a7aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056022a7908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056022a43fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056022a43fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f641171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f641171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f641171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056022a43fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c (1728 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_x_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_x_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_x_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_x_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_x_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_x_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_xu_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_xu_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_xu_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_xu_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nx
# | ...
# `---data was truncated (10240/75125) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055babd14deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055babd14ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055babd14e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab81533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab8158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab81533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab8151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055babd0e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055babd0e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055babd0c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055babcd77e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055babcd77b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fab8151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab8151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab8151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055babcd77a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c (1729 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-ZVF /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005569dc256eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005569dc253e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005569dc25762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f946e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f946e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f946e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f946e631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005569dc1ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005569dc1eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005569dc1d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005569dbe80e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005569dbe80b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f946e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f946e6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f946e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005569dbe80a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-ZVF /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-ZVF /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c (1730 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_f16m1x2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_f16m2x2(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei8_v_f16m4x2(ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_f32m1x2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_f32m2x2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x
# | ...
# `---data was truncated (10240/113019) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005644d3803eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005644d3800e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005644d380462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa66b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa66b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa66b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa66b71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005644d3799bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005644d3799a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005644d377e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005644d342de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005644d342db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa66b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa66b71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa66b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005644d342da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c (1731 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f16m1x5(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f32m1x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f64m1x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei16_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560cb178beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560cb1788e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560cb178c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6513049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f65130a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6513049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6513031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560cb1721bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560cb1721a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560cb17068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560cb13b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560cb13b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6513032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f65130330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f65130330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560cb13b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c (1732 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_f64m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_f64m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_i64m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_i64m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_u64m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_u64m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>,
# | ...
# `---data was truncated (10240/16424) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056026ef4ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056026ef49e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056026ef4d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fea76c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fea76ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fea76c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fea76c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056026eee2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056026eee2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056026eec78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056026eb76e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056026eb76b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fea76c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fea76c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fea76c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056026eb76a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c (1733 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulh_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulh_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulh_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulh_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulh_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulh_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulh_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulh_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulh_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulh_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmulh_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/97913) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dbd0cc8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dbd0cc5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dbd0cc962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f59b1f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f59b1f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f59b1f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f59b1f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dbd0c5ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dbd0c5ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dbd0c438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dbd08f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dbd08f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f59b1f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f59b1f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f59b1f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dbd08f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c (1734 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8mf8x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_u8mf8x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_u8mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_u8mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_u8m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |  
# | ...
# `---data was truncated (10240/26713) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005652b14afeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005652b14ace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005652b14b062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff64a905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff64a95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff64a905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff64a8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005652b1445bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005652b1445a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005652b142a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005652b10d9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005652b10d9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff64a8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff64a8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff64a8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005652b10d9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c (1735 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_f16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_f16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_f16m1x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_i16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_i16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_i16m1x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_u16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("ri
# | ...
# `---data was truncated (10240/13634) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563839294eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563839291e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056383929562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca70905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca7095c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca70905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca708ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056383922abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056383922aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056383920f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563838ebee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563838ebeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fca708eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca708ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca708ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563838ebea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c (1736 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005607041a4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005607041a1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005607041a562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efd5ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efd5cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efd5ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efd5ce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056070413abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056070413aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056070411f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560703dcee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560703dceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efd5ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efd5ce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efd5ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560703dcea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c (1737 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei8_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8
# | ...
# `---data was truncated (10240/160141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560bbcbd7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560bbcbd4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560bbcbd862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8bf8249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8bf82a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8bf8249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8bf8231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560bbcb6dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560bbcb6da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560bbcb528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560bbc801e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560bbc801b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8bf8232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8bf82330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8bf82330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560bbc801a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/neon-tbl.c (1738 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-tbl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon  -disable-O0-optnone  -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | %struct.int8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.int8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.int8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.int8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.int8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.int8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.uint8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.uint8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.uint8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.uint8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.uint8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.uint8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.poly8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.poly8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.poly8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.poly8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.poly8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.poly8x16x4_t = type { [4 x <16 x i8>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vtbl1_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vtbl1.i = shufflevector <8 x i8> %2, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   %vtbl11.i = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %vtbl1.i, <8 x i8> %3)
# |   store <8 x i8> %vtbl11.i, ptr %ref.tmp.i, align 8
# |   %4 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %4, ptr %__ret.i, align 8
# |   %5 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vqtbl1_s8(<16 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vtbl1.i = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %2, <8 x i8> %3)
# |   store <8 x i8> %vtbl1.i, ptr %ref.tmp.i, align 8
# |   %4 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %4, ptr %__ret.i, align 8
# |   %5 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vtbl2_s8([2 x <8 x i8>] alignstack(8) %a.coerce, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.i = alloca %struct.int8x8x2_t, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a = alloca %struct.int8x8x2_t, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %coerce.dive = getelementptr inbounds nuw %struct.int8x8x2_t, ptr %a, i32 0, i32 0
# |   store [2 x <8 x i8>] %a.coerce, ptr %coerce.dive, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %b.addr, align 8
# |   %coerce.dive1 = getelementptr inbounds nuw %struct.int8x8x2_t, ptr %a, i32 0, i32 0
# |   %1 = load [2 x <8 x i8>], ptr %coerce.dive1, align 8
# |   store [2 x <8 x i8>] %1, ptr %__p0.i, align 8
# |   store <8 x i8> %0, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.i, align 8
# |   %arrayidx2.i = getelementptr inbounds [2 x <8 x i8>], ptr %__p0.i, i64 0, i64 1
# |   %3 = load <8 x i8>, ptr %arrayidx2.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vtbl1.i = shufflevector <8 x i8> %2, <8 x i8> %3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   %vtbl13.i = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %vtbl1.i, <8 x i8> %4)
# |   store <8 x i8> %vtbl13.i, ptr %ref.tmp.i, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %5, ptr %__ret.i, align 8
# |   %6 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vqtbl2_s8([2 x <16 x i8>] alignstack(16) %a.coerce, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.i = alloca %struct.int8x16x2_t, align 16
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a = alloca %struct.int8x16x2_t, align 16
# |   %b.addr = alloca <8 x i8>, align 8
# |   %coerce.dive = getelementptr inbounds nuw %struct.int8x16x2_t, ptr %a, i32 0, i32 0
# |   store [2 x <16 x i8>] %a.coerce, ptr %coerce.dive, align 16
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %b.addr, align 8
# |   %coerce.dive1 = getelementptr inbounds nuw %struct.int8x16x2_t, ptr %a, i32 0, i32 0
# |   %1 = load [2 x <16 x i8>], ptr %coerce.dive1, align 16
# |   store [2 x <16 x i8>] %1, ptr %__p0.i, align 16
# |   store <8 x i8> %0, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.i, align 16
# |   %arrayidx2.i = getelementptr inbounds [2 x <16 x i8>], ptr %__p0.i, i64 0, i64 1
# |   %3 = load <16 x i8>, ptr %arrayidx2.i, align 16
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vtbl2.i = call <8 x i8> @llvm.aarch64.neon.tbl2.v8i8(<16 x i8> %2, <16 x i8> %3, <8 x i8> %4)
# |   store <8 x i8> %vtbl2.i, ptr %ref.tmp.i, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %5, ptr %__ret.i, align 8
# |   %6 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vtbl3_s8([3 x <8 x i8>] alignstack(8) %a.coerce, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.i = alloca %struct.int8x8x3_t, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a = alloca %struct.int8x8x3_t, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %coerce.dive = getelementptr inbounds nuw %struct.int8x8x3_t, ptr %a, i32 0, i32 0
# |   store [3 x <8 x i8>] %a.coerce, ptr %coerce.dive, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %b.addr, align 8
# |   %coerce.dive1 = getelementptr inbounds nuw %struct.int8x8x3_t, ptr %a, i32 0, i32 0
# |   %1 = load [3 x <8 x i8>], ptr %coerce.dive1, align 8
# |   store [3 x <8 x i8>] %1, ptr %__p0.i, align 8
# |   store <8 x i8> %0, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.i, align 8
# |   %arrayidx2.i = getelementptr inbounds [3 x <8 x i8>], ptr %__p0.i, i64 0, i64 1
# |   %3 = load <8 x i8>, ptr %arrayidx2.i, align 8
# |   %arrayidx4.i = getelementptr inbounds [3 x <8 x i8>], ptr %__p0.i, i64 0, i64 2
# |   %4 = load <8 x i8>, ptr %arrayidx4.i, align 8
# |   %5 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vtbl2.i = shufflevector <8 x i8> %2, <8 x i8> %3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   %vtbl25.i = shufflevector <8 x i8> %4, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   %vtbl26.i = call <8 x i8> @llvm.aarch64.neon.tbl2.v8i8(<16 x i8> %vtbl2.i, <16 x i8> %vtbl25.i, <8 x i8> %5)
# |   store <8 x i8> %vtbl26.i, ptr %ref.tmp.i, align 8
# |   %6 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %6, ptr %__ret.i, align 8
# |   %7 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vqtbl3_s8([3 x <16 x i8>] alignstack(16) %a.coerce, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.i = alloca %struct.int8x16x3_t, align 16
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a = alloca %struct.int8x16x3_t, align 16
# |   %b.addr = alloca <8 x i8>, align 8
# |   %coerce.dive = getelementptr inbounds nuw %struct.int8x16x3_t, ptr %a, i32 0, i32 0
# |   store [3 x <16 x i8>] %a.coerce, ptr %coerce.dive, align 16
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %b.addr, align 8
# |   %coerce.dive1 = getelementptr inbounds nuw %struct.int8x16x3_t, ptr %a, i32 0, i32 0
# |   %1 = load [3 x <16 x i8>], ptr %coerce.dive1, align 16
# |   store [3 x <16 x i8>] %1, ptr %__p0.i, align 16
# |   store <8 x i8> %0, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.i, align 16
# |   %arrayidx2.i = getelementptr inbounds [3 x <16 x i8>], ptr %__p0.i, i64 0, i64 1
# |   %3 = load <16 x i8>, ptr %arrayidx2.i, align 16
# |   %arrayidx4.i = getelementptr inbounds [3 x <16 x i8>], ptr %__p0.i, i64 0, i64 2
# |   %4 = load <16 x i8>, ptr %arrayidx4.i, align 16
# |   %5 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vtbl3.i = call <8 x i8> @llvm.aarch64.neon.tbl3.v8i8(<16 x i8> %2, <16 x i8> %3, <16 x i8> %4, <8 x i8> %5)
# |   store <8 x i8> %vtbl3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %6, ptr %__ret.i, align 8
# |   %7 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vtbl4_s8([4 x <8 x i8>] alignstack(8) %a.coerce, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.i = alloca %struct.int8x8x4_t, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a = alloca %struct.int8x8x4_t, align 8
# |   %b.a
# | ...
# `---data was truncated (10240/125901) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e1c5cb9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e1c5cb6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e1c5cba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b5ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b5ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b5ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b5ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e1c5c4fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e1c5c4fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e1c5c348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e1c58e3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e1c58e3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2b5ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b5ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b5ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e1c58e3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c (1739 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ef1c267eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ef1c264e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ef1c26862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fed47933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fed4798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fed47933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fed4791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ef1c1fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ef1c1fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ef1c1e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ef1be91e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ef1be91b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fed4791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fed4791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fed4791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ef1be91a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c (1740 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_f64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_i64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_u64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b81458ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b814589e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b81458d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8f1f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8f1f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8f1f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8f1f51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b814522bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b814522a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b8145078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b8141b6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b8141b6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8f1f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8f1f51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8f1f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b8141b6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c (1741 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f16m1x3(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f16m2x3(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f32m1x3(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f32m2x3(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f64m1x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64
# | ...
# `---data was truncated (10240/99178) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cad2aefeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cad2aece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cad2af062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc29ea1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc29ea725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc29ea1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc29ea03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cad2a85bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cad2a85a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cad2a6a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cad2719e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cad2719b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc29ea04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc29ea050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc29ea050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cad2719a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c (1742 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei16_v_i8mf8x6
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005645b62f6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005645b62f3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005645b62f762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe055d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe055d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe055d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe055d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005645b628cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005645b628ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005645b62718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005645b5f20e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005645b5f20b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe055d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe055d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe055d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005645b5f20a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c (1743 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba88fe2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ba88fdfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ba88fe362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0422733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f042278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0422733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f042271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba88f78bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ba88f78a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ba88f5d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ba88c0ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ba88c0cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f042271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f042271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f042271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba88c0ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c (1744 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16_v_bf16mf4(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vle.nxv1bf16.p0.i64(<vscale x 1 x bfloat> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vle.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16_v_bf16mf2(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vle.nxv2bf16.p0.i64(<vscale x 2 x bfloat> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vle.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16_v_bf16m1(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vle.nxv4bf16.p0.i64(<vscale x 4 x bfloat> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vle.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16_v_bf16m2(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vle.nxv8bf16.p0.i64(<vscale x 8 x bfloat> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vle.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16_v_bf16m4(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vle.nxv16bf16.p0.i64(<vscale x 16 x bfloat> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vle.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16_v_bf16m8(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vle.nxv32bf16.p0.i64(<vscale x 32 x bfloat> poison, ptr %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vle.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vle.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vle.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16_v_bf16m4_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vle.mask.nxv16bf16.p0.i64(<vscale x 16 x bfloat> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vle.mask.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16_v_bf16m8_m(<vscale x 32 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 32 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %v
# | ...
# `---data was truncated (10240/11349) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564cf7365eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564cf7362e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564cf736662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf30849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf308a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf30849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf30831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564cf72fbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564cf72fba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564cf72e08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564cf6f8fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564cf6f8fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdf30832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf308330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf308330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564cf6f8fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c (1745 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f16m1x4(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_f16m2x4(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f32m1x4(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_f32m2x4(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f64m1x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.
# | ...
# `---data was truncated (10240/82975) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dd102ddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dd102dae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dd102de62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d66133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d6618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d66133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d6611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd10273bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dd10273a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dd102588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dd0ff07e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dd0ff07b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1d6611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d6611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d6611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd0ff07a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c (1746 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_f32mf2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_f32m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_f32m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_i32mf2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_i32m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_i32m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_u32mf2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_u32m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_u32m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_f32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_f32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_f32m2x4_m(<vscale x 4 x i1> %mask, ptr noun
# | ...
# `---data was truncated (10240/17567) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555f2ba69eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555f2ba66e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555f2ba6a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faf08849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faf088a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faf08849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faf08831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f2b9ffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555f2b9ffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555f2b9e48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555f2b693e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555f2b693b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faf08832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faf088330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faf088330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f2b693a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c (1747 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64ff_v_f64m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(<vscale x 1 x double> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x double>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x double>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(<vscale x 1 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64ff_v_f64m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(<vscale x 2 x double> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x double>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x double>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(<vscale x 2 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vle64ff_v_f64m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(<vscale x 4 x double> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x double>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x double>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(<vscale x 4 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vle64ff_v_f64m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(<vscale x 8 x double> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 8 x double>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 8 x double>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 8 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(<vscale x 8 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64ff_v_i64m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(<vscale x 1 x i64> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x i64>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x i64>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(<vscale x 1 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64ff_v_i64m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(<vscale x 2 x i64> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x i64>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i64>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(<vscale x 2 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64ff_v_i64m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(<vscale x 4 x i64> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x i64>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i64>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(<vscale x 4 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64ff_v_i64m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 8 x i64>, i64 } @llvm.riscv.vleff.nxv8i64.i64.p0(<vscale x 8 x i64> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 8 x i64>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 8 x i64>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x i64>, i64 } @llvm.riscv.vleff.nxv8i64.i64.p0(<vscale x 8 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64ff_v_u64m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(<vscale x 1 x i64> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x i64>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x i64>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64ff_v_u64m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(<vscale x 2 x i64> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x i64>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i64>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs
# | ...
# `---data was truncated (10240/26996) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c5ce27ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c5ce279e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c5ce27d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4a57449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4a574a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4a57449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4a57431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c5ce212bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c5ce212a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c5ce1f78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c5cdea6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c5cdea6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4a57432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4a574330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4a574330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c5cdea6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c (1748 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f16m1x4(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_f16m2x4(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f32m1x4(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_f32m2x4(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f64m1x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.
# | ...
# `---data was truncated (10240/82975) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f54c353eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f54c350e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f54c35462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7628933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f762898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7628933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f762891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f54c2e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f54c2e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f54c2ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f54bf7de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f54bf7db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f762891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f762891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f762891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f54bf7da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c (1749 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# | ...
# `---data was truncated (10240/18506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556a44599eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556a44596e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556a4459a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f48c8533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f48c858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f48c8533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f48c851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556a4452fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556a4452fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556a445148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556a441c3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556a441c3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f48c851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f48c851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f48c851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556a441c3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c (1750 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei16_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei16_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei16_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei16_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei16_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vloxei16_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, <vscale x 32 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei16_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei16_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none)
# | ...
# `---data was truncated (10240/30609) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cc248e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cc248e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cc248ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1eb9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1eb9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1eb9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1eb9f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc2487fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cc2487fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cc248648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cc24513e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cc24513b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1eb9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1eb9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1eb9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc24513a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c (1751 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnj_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnj_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnj_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnj_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnj_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnj_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnj_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnj_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <v
# | ...
# `---data was truncated (10240/65080) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c9a1d9beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c9a1d98e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c9a1d9c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5e92a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5e92aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5e92a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5e92a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9a1d31bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c9a1d31a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c9a1d168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c9a19c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c9a19c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5e92a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5e92a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5e92a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c9a19c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c (1752 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredand_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor
# | ...
# `---data was truncated (10240/113039) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005594e4ed7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005594e4ed4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005594e4ed862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7cc7133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7cc718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7cc7133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7cc711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005594e4e6dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005594e4e6da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005594e4e528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005594e4b01e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005594e4b01b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7cc711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7cc711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7cc711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005594e4b01a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c (1753 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wf_bf16_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wf_bf16_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x floa
# | ...
# `---data was truncated (10240/199588) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d63719eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d63719be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d63719f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f342e41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f342e4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f342e41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f342e403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d637134bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d637134a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d6371198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d636dc8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d636dc8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f342e404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f342e4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f342e4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d636dc8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c (1754 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vcreate_v_f16m1_f16m2(<vscale x 4 x half> %v0, <vscale x 4 x half> %v1) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 4 x half>, align 2
# |   %v1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %v0, ptr %v0.addr, align 2
# |   store <vscale x 4 x half> %v1, ptr %v1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %v1.addr, align 2
# |   %2 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   %3 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> %2, <vscale x 4 x half> %1, i64 4)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vcreate_v_f16m1_f16m4(<vscale x 4 x half> %v0, <vscale x 4 x half> %v1, <vscale x 4 x half> %v2, <vscale x 4 x half> %v3) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 4 x half>, align 2
# |   %v1.addr = alloca <vscale x 4 x half>, align 2
# |   %v2.addr = alloca <vscale x 4 x half>, align 2
# |   %v3.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %v0, ptr %v0.addr, align 2
# |   store <vscale x 4 x half> %v1, ptr %v1.addr, align 2
# |   store <vscale x 4 x half> %v2, ptr %v2.addr, align 2
# |   store <vscale x 4 x half> %v3, ptr %v3.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %v1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %v2.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %v3.addr, align 2
# |   %4 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   %5 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> %4, <vscale x 4 x half> %1, i64 4)
# |   %6 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> %5, <vscale x 4 x half> %2, i64 8)
# |   %7 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> %6, <vscale x 4 x half> %3, i64 12)
# |   ret <vscale x 16 x half> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vcreate_v_f16m1_f16m8(<vscale x 4 x half> %v0, <vscale x 4 x half> %v1, <vscale x 4 x half> %v2, <vscale x 4 x half> %v3, <vscale x 4 x half> %v4, <vscale x 4 x half> %v5, <vscale x 4 x half> %v6, <vscale x 4 x half> %v7) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 4 x half>, align 2
# |   %v1.addr = alloca <vscale x 4 x half>, align 2
# |   %v2.addr = alloca <vscale x 4 x half>, align 2
# |   %v3.addr = alloca <vscale x 4 x half>, align 2
# |   %v4.addr = alloca <vscale x 4 x half>, align 2
# |   %v5.addr = alloca <vscale x 4 x half>, align 2
# |   %v6.addr = alloca <vscale x 4 x half>, align 2
# |   %v7.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %v0, ptr %v0.addr, align 2
# |   store <vscale x 4 x half> %v1, ptr %v1.addr, align 2
# |   store <vscale x 4 x half> %v2, ptr %v2.addr, align 2
# |   store <vscale x 4 x half> %v3, ptr %v3.addr, align 2
# |   store <vscale x 4 x half> %v4, ptr %v4.addr, align 2
# |   store <vscale x 4 x half> %v5, ptr %v5.addr, align 2
# |   store <vscale x 4 x half> %v6, ptr %v6.addr, align 2
# |   store <vscale x 4 x half> %v7, ptr %v7.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %v1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %v2.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %v3.addr, align 2
# |   %4 = load <vscale x 4 x half>, ptr %v4.addr, align 2
# |   %5 = load <vscale x 4 x half>, ptr %v5.addr, align 2
# |   %6 = load <vscale x 4 x half>, ptr %v6.addr, align 2
# |   %7 = load <vscale x 4 x half>, ptr %v7.addr, align 2
# |   %8 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   %9 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %8, <vscale x 4 x half> %1, i64 4)
# |   %10 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %9, <vscale x 4 x half> %2, i64 8)
# |   %11 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %10, <vscale x 4 x half> %3, i64 12)
# |   %12 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %11, <vscale x 4 x half> %4, i64 16)
# |   %13 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %12, <vscale x 4 x half> %5, i64 20)
# |   %14 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %13, <vscale x 4 x half> %6, i64 24)
# |   %15 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %14, <vscale x 4 x half> %7, i64 28)
# |   ret <vscale x 32 x half> %15
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vcreate_v_f16m2_f16m4(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 8 x half>, align 2
# |   %v1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %v0, ptr %v0.addr, align 2
# |   store <vscale x 8 x half> %v1, ptr %v1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %v1.addr, align 2
# |   %2 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half> poison, <vscale x 8 x half> %0, i64 0)
# |   %3 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half> %2, <vscale x 8 x half> %1, i64 8)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vcreate_v_f16m2_f16m8(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x half> %v3) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 8 x half>, align 2
# |   %v1.addr = alloca <vscale x 8 x half>, align 2
# |   %v2.addr = alloca <vscale x 8 x half>, align 2
# |   %v3.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %v0, ptr %v0.addr, align 2
# |   store <vscale x 8 x half> %v1, ptr %v1.addr, align 2
# |   store <vscale x 8 x half> %v2, ptr %v2.addr, align 2
# |   store <vscale x 8 x half> %v3, ptr %v3.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %v1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %v2.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %v3.addr, align 2
# |   %4 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> poison, <vscale x 8 x half> %0, i64 0)
# |   %5 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> %4, <vscale x 8 x half> %1, i64 8)
# |   %6 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> %5, <vscale x 8 x half> %2, i64 16)
# |   %7 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> %6, <vscale x 8 x half> %3, i64 24)
# |   ret <vscale x 32 x half> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vcreate_v_f16m4_f16m8(<vscale x 16 x half> %v0, <vscale x 16 x half> %v1) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 16 x half>, align 2
# |   %v1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %v0, ptr %v0.addr, align 2
# |   store <vscale x 16 x half> %v1, ptr %v1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %v1.addr, align 2
# |   %2 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half> poison, <vscale x 16 x half> %0, i64 0)
# |   %3 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half> %2, <vscale x 16 x half> %1, i64 16)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half>, <vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vcreate_v_f32m1_f32m2(<vscale x 2 x float> %v0, <vscale x 2 x float> %v1) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 2 x float>, align 4
# |   %v1.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 2 x float> %v0, ptr %v0.addr, align 4
# |   store <vscale x 2 x float> %v1, ptr %v1.addr, align 4
# |   %0 = load <vscale x 2 x float>, ptr %v0.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %v1.addr, align 4
# |   %2 = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float> poison, <vscale x 2 x float> %0, i64 0)
# |   %3 = call <vscale x 4 x float> @llvm.
# | ...
# `---data was truncated (10240/593252) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560456c28eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560456c25e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560456c2962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f85b7b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f85b7b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f85b7b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f85b7b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560456bbebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560456bbea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560456ba38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560456852e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560456852b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f85b7b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f85b7b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f85b7b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560456852a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c (1755 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale
# | ...
# `---data was truncated (10240/32108) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dfadcb0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dfadcade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dfadcb162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faaa5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faaa52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faaa5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faaa5231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dfadc46bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dfadc46a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dfadc2b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dfad8dae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dfad8dab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faaa5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faaa52330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faaa52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dfad8daa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c (1756 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmerge_vfm_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmerge_vfm_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmerge_vfm_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmerge_vfm_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmerge_vfm_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, bfloat %1, <vscale x 16 x i1> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfmerge_vfm_bf16m8(<vscale x 32 x bfloat> %op1, bfloat noundef %op2, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, bfloat %1, <vscale x 32 x i1> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, <vscale x 32 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560bafa5ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560bafa59e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560bafa5d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5aecf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5aecf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5aecf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5aecf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560baf9f2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560baf9f2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560baf9d78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560baf686e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560baf686b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5aecf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5aecf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5aecf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560baf686a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c (1757 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_i32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_i32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_u32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_u32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_f32mf2x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_f32m1x5_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret ta
# | ...
# `---data was truncated (10240/32031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f60376feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f60376ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f60377062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a7dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a7dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a7dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a7dc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f603705bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f603705a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f6036ea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f603399e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f603399b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2a7dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a7dc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a7dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f603399a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c (1758 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_f32mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_f32m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_i32mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_i32m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_u32mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_u32m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_i32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_i32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %
# | ...
# `---data was truncated (10240/14001) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005568e8262eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005568e825fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005568e826362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c46449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c464a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c46449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c46431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005568e81f8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005568e81f8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005568e81dd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005568e7e8ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005568e7e8cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7c46432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c464330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c464330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005568e7e8ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c (1759 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulhu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulhu_vx_u8m4(<vscale x 32 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 64 x i8> @test_vmulhu_vv_u8m8(<vscale x 64 x i8> %op1, <vscale x 64 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %o
# | ...
# `---data was truncated (10240/65883) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005558b4fdbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005558b4fd8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005558b4fdc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5d5e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5d5e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5d5e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5d5e831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005558b4f71bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005558b4f71a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005558b4f568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005558b4c05e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005558b4c05b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5d5e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5d5e8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5d5e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005558b4c05a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c (1760 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vreinterpret_v_i16mf4_bf16mf4(<vscale x 1 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x i16> %0 to <vscale x 1 x bfloat>
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vreinterpret_v_i16mf2_bf16mf2(<vscale x 2 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x i16> %0 to <vscale x 2 x bfloat>
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vreinterpret_v_i16m1_bf16m1(<vscale x 4 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x i16> %0 to <vscale x 4 x bfloat>
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vreinterpret_v_i16m2_bf16m2(<vscale x 8 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 8 x bfloat>
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vreinterpret_v_i16m4_bf16m4(<vscale x 16 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x i16> %0 to <vscale x 16 x bfloat>
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vreinterpret_v_i16m8_bf16m8(<vscale x 32 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 32 x i16> %0 to <vscale x 32 x bfloat>
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vreinterpret_v_u16mf4_bf16mf4(<vscale x 1 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x i16> %0 to <vscale x 1 x bfloat>
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vreinterpret_v_u16mf2_bf16mf2(<vscale x 2 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x i16> %0 to <vscale x 2 x bfloat>
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vreinterpret_v_u16m1_bf16m1(<vscale x 4 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x i16> %0 to <vscale x 4 x bfloat>
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vreinterpret_v_u16m2_bf16m2(<vscale x 8 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 8 x bfloat>
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vreinterpret_v_u16m4_bf16m4(<vscale x 16 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x i16> %0 to <vscale x 16 x bfloat>
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vreinterpret_v_u16m8_bf16m8(<vscale x 32 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 32 x i16> %0 to <vscale x 32 x bfloat>
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i16> @test_vreinterpret_v_bf16mf4_i16mf4(<vscale x 1 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x bfloat> %0 to <vscale x 1 x i16>
# |   ret <vscale x 1 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i16> @test_vreinterpret_v_bf16mf2_i16mf2(<vscale x 2 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x bfloat> %0 to <vscale x 2 x i16>
# |   ret <vscale x 2 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i16> @test_vreinterpret_v_bf16m1_i16m1(<vscale x 4 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x bfloat> %0 to <vscale x 4 x i16>
# |   ret <vscale x 4 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i16> @test_vreinterpret_v_bf16m2_i16m2(<vscale x 8 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x bfloat> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i16> @test_vreinterpret_v_bf16m4_i16m4(<vscale x 16 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x bfloat> %0 to <vscale x 16 x i16>
# |   ret <vscale x 16 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i16> @test_vreinterpret_v_bf16m8_i16m8(<vscale x 32 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 32 x bfloat> %0 to <vscale x 32 x i16>
# |   ret <vscale x 32 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i16> @test_vreinterpret_v_bf16mf4_u16mf4(<vscale x 1 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x bfloat> %0 to <vscale x 1 x i16>
# |   ret <vscale x 1 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i16> @test_vreinterpret_v_bf16mf2_u16mf2(<vscale x 2 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x bfloat> %0 to <vscale x 2 x i16>
# |   ret <vscale x 2 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i16> @test_vreinterpret_v_bf16m1_u16m1(<vscale x 4 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x bfloat> %0 to <vscale x 4 x i16>
# |   ret <vscale x 4 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i16> @test_vreinterpret_v_bf16m2_u16m2(<vscale x 8 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x bfloat> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i16> @test_vreinterpret_v_bf16m4_u16m4(<vscale x 16 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x bfloat> %0 
# | ...
# `---data was truncated (10240/11237) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557fa6950eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557fa694de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557fa695162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce34f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce34f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce34f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce34f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557fa68e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557fa68e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557fa68cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557fa657ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557fa657ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fce34f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce34f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce34f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557fa657aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c (1761 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m1(ptr noundef %base, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x double>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1f64.p0.i64(<vscale x 1 x double> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m2(ptr noundef %base, <vscale x 2 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x double>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2f64.p0.i64(<vscale x 2 x double> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m4(ptr noundef %base, <vscale x 4 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x double>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4f64.p0.i64(<vscale x 4 x double> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m8(ptr noundef %base, <vscale x 8 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x double>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8f64.p0.i64(<vscale x 8 x double> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_i64m1(ptr noundef %base, <vscale x 1 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i64.p0.i64(<vscale x 1 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_i64m2(ptr noundef %base, <vscale x 2 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i64.p0.i64(<vscale x 2 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_i64m4(ptr noundef %base, <vscale x 4 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i64.p0.i64(<vscale x 4 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_i64m8(ptr noundef %base, <vscale x 8 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i64.p0.i64(<vscale x 8 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_u64m1(ptr noundef %base, <vscale x 1 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i64.p0.i64(<vscale x 1 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_u64m2(ptr noundef %base, <vscale x 2 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i64.p0.i64(<vscale x 2 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_u64m4(ptr noundef %base, <vscale x 4 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i64.p0.i64(<vscale x 4 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_u64m8(ptr noundef %base, <vscale x 8 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i64.p0.i64(<vscale x 8 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x double>
# | ...
# `---data was truncated (10240/22898) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c066d35eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c066d32e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c066d3662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa47d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa47d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa47d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa47d91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c066ccbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c066ccba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c066cb08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c06695fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c06695fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa47d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa47d91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa47d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c06695fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c (1762 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_bf16mf4x7(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_bf16mf2x7(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_bf16m1x7(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e6b5c94eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e6b5c91e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e6b5c9562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0597105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f059715c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0597105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f05970ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e6b5c2abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e6b5c2aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e6b5c0f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e6b58bee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e6b58beb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f05970eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f05970ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f05970ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e6b58bea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c (1763 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_u_s_w4_u8m8_i8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.u.s.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.u.s.i64.nxv64i8.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005646c9ac5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005646c9ac2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005646c9ac662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcba9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcba9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcba9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcba9f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005646c9a5bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005646c9a5ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005646c9a408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005646c96efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005646c96efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcba9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcba9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcba9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005646c96efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c (1764 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei16_v_f16mf4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei16_v_f16mf2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei16_v_f16m1(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei16_v_f16m2(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei16_v_f16m4(ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vloxei16_v_f16m8(ptr noundef %base, <vscale x 32 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> poison, ptr %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei16_v_f32mf2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei16_v_f32m1(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei16_v_f32m2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei16_v_f32m4(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i16.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i16.i64(<vscale x 
# | ...
# `---data was truncated (10240/118164) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005641e895ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005641e8959e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005641e895d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a1c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a1c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a1c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a1c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005641e88f2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005641e88f2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005641e88d78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005641e8586e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005641e8586b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2a1c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a1c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a1c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005641e8586a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c (1765 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i8> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, <vscale x
# | ...
# `---data was truncated (10240/15615) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055abea584eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055abea581e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055abea58562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7337049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f73370a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7337049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7337031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055abea51abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055abea51aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055abea4ff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055abea1aee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055abea1aeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7337032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73370330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73370330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055abea1aea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c (1766 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfle
# | ...
# `---data was truncated (10240/18668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564df40d9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564df40d6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564df40da62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1bb4c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1bb4ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1bb4c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1bb4c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564df406fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564df406fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564df40548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564df3d03e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564df3d03b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1bb4c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1bb4c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1bb4c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564df3d03a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c (1767 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vslide1up_vx_i8mf8(<vscale x 1 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vslide1up_vx_i8mf4(<vscale x 2 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vslide1up_vx_i8mf2(<vscale x 4 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vslide1up_vx_i8m1(<vscale x 8 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vslide1up_vx_i8m2(<vscale x 16 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vslide1up_vx_i8m4(<vscale x 32 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vslide1up_vx_i8m8(<vscale x 64 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vslide1up_vx_i16mf4(<vscale x 1 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vslide1up_vx_i16mf2(<vscale x 2 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vslide1up.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vslide1up.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vslide1up_vx_i16m1(<vscale x 4 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vslide1up.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vslide1up.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vslide1up_vx_i16m2(<vscale x 8 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.add
# | ...
# `---data was truncated (10240/86739) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e35333feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e35333ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e35334062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcf11f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcf11f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcf11f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcf11eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e3532d5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e3532d5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e3532ba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e352f69e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e352f69b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcf11eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcf11eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcf11eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e352f69a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c (1768 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei16_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aebe9a4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aebe9a1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aebe9a562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f79eb449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f79eb4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f79eb449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f79eb431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aebe93abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aebe93aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aebe91f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aebe5cee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aebe5ceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f79eb432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f79eb4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f79eb4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aebe5cea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c (1769 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmax_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmax_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmax_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmax_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmax_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmax_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmax_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmax_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmax_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfmax.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmax.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmax_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %o
# | ...
# `---data was truncated (10240/29054) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055576fcfeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055576fcfbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055576fcff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6316049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f63160a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6316049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6316031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055576fc94bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055576fc94a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055576fc798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055576f928e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055576f928b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6316032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f63160330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f63160330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055576f928a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c (1770 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfge_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfge_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfge_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 3
# | ...
# `---data was truncated (10240/27794) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558111157eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558111154e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055811115862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9322e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9322e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9322e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9322e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005581110edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005581110eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005581110d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558110d81e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558110d81b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9322e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9322e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9322e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558110d81a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c (1771 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vzip_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vzip_vv_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloc
# | ...
# `---data was truncated (10240/27533) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e0feae7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e0feae4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e0feae862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1b3f61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1b3f6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1b3f61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1b3f603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e0fea7dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e0fea7da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e0fea628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e0fe711e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e0fe711b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1b3f604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1b3f6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1b3f6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e0fe711a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c (1772 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16mf4x4(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16mf2x4(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16m1x4(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16m2x4(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale
# | ...
# `---data was truncated (10240/10790) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055945bfb9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055945bfb6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055945bfba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f40533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f4058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f40533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f4051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055945bf4fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055945bf4fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055945bf348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055945bbe3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055945bbe3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2f4051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f4051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f4051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055945bbe3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c (1773 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2ch_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2ch_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2ch_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2ch_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2ch_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2ch_vv_u64m1_tu(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2ch_vv_u64m2_tu(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2ch_vv_u64m4_tu(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscal
# | ...
# `---data was truncated (10240/12235) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b5f2eeaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b5f2ee7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b5f2eeb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f640ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f640aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f640ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f640ac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b5f2e80bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b5f2e80a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b5f2e658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b5f2b14e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b5f2b14b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f640ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f640ac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f640ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b5f2b14a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c (1774 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_f16mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_f16mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_f16m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_i16mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_i16mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_i16m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_u16mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_u16mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_u16m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_f16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.ri
# | ...
# `---data was truncated (10240/20449) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564059edfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564059edce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564059ee062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f330d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f330d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f330d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f330d91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564059e75bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564059e75a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564059e5a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564059b09e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564059b09b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f330d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f330d91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f330d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564059b09a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c (1775 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei16_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b1e81abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b1e81a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b1e81ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f74a0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f74a08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f74a0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f74a0831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b1e8141bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b1e8141a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b1e81268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b1e7dd5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b1e7dd5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f74a0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f74a08330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f74a08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b1e7dd5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c (1776 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmin_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmin_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmin_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmin_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmin_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmin_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmin_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmin_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmin_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/222483) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005647ca612eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005647ca60fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005647ca61362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb65601bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb6560725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb65601ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb656003507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005647ca5a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005647ca5a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005647ca58d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005647ca23ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005647ca23cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb656004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb6560050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb6560050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005647ca23ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c (1777 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfslide1down_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfslide1down_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfslide1down_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfslide1down_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfslide1down_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfslide1down_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfslide1down_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load float, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfslide1down_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load float, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfslide1down_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %src, float noundef %value, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/78328) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005610ac272eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005610ac26fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005610ac27362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c97249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c972a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c97249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c97231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005610ac208bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005610ac208a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005610ac1ed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005610abe9ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005610abe9cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7c97232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c972330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c972330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005610abe9ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c (1778 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_w_bf16mf4_f8e4m3mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_w_bf16mf4_f8e4m3mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_w_bf16mf2_f8e4m3mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_w_bf16mf2_f8e4m3mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_w_bf16m1_f8e4m3mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_sat_f_f_w_bf16m1_f8e4m3mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_f_f_w_bf16m2_f8e4m3m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_sat_f_f_w_bf16m2_f8e4m3m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_f_f_w_bf16m4_f8e4m3m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_sat_f_f_w_bf16m4_f8e4m3m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, ali
# | ...
# `---data was truncated (10240/201234) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f55c41eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f55c41be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f55c41f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c36333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c3638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c36333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c3631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f55c3b4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f55c3b4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f55c3998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f55c048e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f55c048b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1c3631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c3631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c3631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f55c048a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics.c (1779 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcgezh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp oge half %1, 0.000000e+00
# |   %vcgez = sext i1 %2 to i16
# |   store i16 %vcgez, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcgtzh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp ogt half %1, 0.000000e+00
# |   %vcgtz = sext i1 %2 to i16
# |   store i16 %vcgtz, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vclezh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp ole half %1, 0.000000e+00
# |   %vclez = sext i1 %2 to i16
# |   store i16 %vclez, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcltzh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp olt half %1, 0.000000e+00
# |   %vcltz = sext i1 %2 to i16
# |   store i16 %vcltz, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_s16(i16 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i16, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %__s0, align 2
# |   %1 = load i16, ptr %__s0, align 2
# |   %2 = sitofp i16 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_s32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i32, align 4
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__s0, align 4
# |   %1 = load i32, ptr %__s0, align 4
# |   %2 = sitofp i32 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_s64(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i64, align 8
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   store i64 %0, ptr %__s0, align 8
# |   %1 = load i64, ptr %__s0, align 8
# |   %2 = sitofp i64 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_u16(i16 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i16, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %__s0, align 2
# |   %1 = load i16, ptr %__s0, align 2
# |   %2 = uitofp i16 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_u32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i32, align 4
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__s0, align 4
# |   %1 = load i32, ptr %__s0, align 4
# |   %2 = uitofp i32 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_u64(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i64, align 8
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   store i64 %0, ptr %__s0, align 8
# |   %1 = load i64, ptr %__s0, align 8
# |   %2 = uitofp i64 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcvth_s16_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vcvth_s16_f16 = call i16 @llvm.fptosi.sat.i16.f16(half %1)
# |   store i16 %vcvth_s16_f16, ptr %ref.tmp, align 2
# |   %2 = load i16, ptr %ref.tmp, align 2
# |   store i16 %2, ptr %__ret, align 2
# |   %3 = load i16, ptr %__ret, align 2
# |   store i16 %3, ptr %tmp, align 2
# |   %4 = load i16, ptr %tmp, align 2
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.fptosi.sat.i16.f16(half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_vcvth_s32_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vcvth_s32_f16 = call i32 @llvm.fptosi.sat.i32.f16(half %1)
# |   store i32 %vcvth_s32_f16, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.fptosi.sat.i32.f16(half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_vcvth_s64_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i64, align 8
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vcvth_s64_f16 = call i64 @llvm.fptosi.sat.i64.f16(half %1)
# |   store i64 %vcvth_s64_f16, ptr %ref.tmp, align 8
# |   %2 = load i64, ptr %ref.tmp, align 8
# |   store i64 %2, ptr %__ret, align 8
# |   %3 = load i64, ptr %__ret, align 8
# |   store i64 %3, ptr %tmp, align 8
# |   %4 = load i64, ptr %tmp, align 8
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.fptosi.sat.i64.f16(half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcvth_u16_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   st
# | ...
# `---data was truncated (10240/53064) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b1e3c38eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b1e3c35e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b1e3c3962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb41a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb41a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb41a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb41a631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b1e3bcebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b1e3bcea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b1e3bb38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b1e3862e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b1e3862b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb41a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb41a6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb41a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b1e3862a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c (1780 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_f32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_f32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_f32m2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_i32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_i32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_i32m2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_u32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractval
# | ...
# `---data was truncated (10240/13669) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557bf2a59eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557bf2a56e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557bf2a5a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f22b1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f22b1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f22b1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f22b1b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557bf29efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557bf29efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557bf29d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557bf2683e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557bf2683b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f22b1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f22b1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f22b1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557bf2683a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c (1781 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557d1e3a1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557d1e39ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557d1e3a262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdca8b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdca8b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdca8b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdca8aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557d1e337bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557d1e337a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557d1e31c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557d1dfcbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557d1dfcbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdca8aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdca8aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdca8aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557d1dfcba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c (1782 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b202b19eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b202b16e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b202b1a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff270b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff270b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff270b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff270b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b202aafbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b202aafa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b202a948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b202743e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b202743b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff270b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff270b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff270b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b202743a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c (1783 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmacc_2x8x2_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmacc_2x8x2_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmacc_2x8x2_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmacc_2x8x2_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a9a941feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a9a941ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a9a942062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd3fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd3faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd3fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd3fa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a9a93b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a9a93b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a9a939a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a9a9049e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a9a9049b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbd3fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd3fa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd3fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a9a9049a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c (1784 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055afdfec6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055afdfec3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055afdfec762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fddbb333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fddbb38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fddbb333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fddbb31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055afdfe5cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055afdfe5ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055afdfe418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055afdfaf0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055afdfaf0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fddbb31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fddbb31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fddbb31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055afdfaf0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c (1785 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmslt_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmslt_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmslt_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmslt_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmslt_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmslt_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmslt_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmslt_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmslt_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmslt_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmslt_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> %0, 
# | ...
# `---data was truncated (10240/95081) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055761bda6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055761bda3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055761bda762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe047b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe047b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe047b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe047b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055761bd3cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055761bd3ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055761bd218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055761b9d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055761b9d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe047b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe047b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe047b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055761b9d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c (1786 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cf4c2e6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cf4c2e3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cf4c2e762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d8a049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d8a0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d8a049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d8a031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf4c27cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cf4c27ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cf4c2618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cf4bf10e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cf4bf10b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1d8a032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d8a0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d8a0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf4bf10a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c (1787 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf8_i16m1(<vscale x 1 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> poison, <vscale x 1 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16>, <vscale x 1 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf4_i16m1(<vscale x 2 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> poison, <vscale x 2 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16>, <vscale x 2 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf2_i16m1(<vscale x 4 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m1_i16m1(<vscale x 8 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> poison, <vscale x 8 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16>, <vscale x 8 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m2_i16m1(<vscale x 16 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> poison, <vscale x 16 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16>, <vscale x 16 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m4_i16m1(<vscale x 32 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> poison, <vscale x 32 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16>, <vscale x 32 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m8_i16m1(<vscale x 64 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> poison, <vscale x 64 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16>, <vscale x 64 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16mf4_i32m1(<vscale x 1 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(<vscale x 2 x i32> poison, <vscale x 1 x i16> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(<vscale x 2 x i32>, <vscale x 1 x i16>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16mf2_i32m1(<vscale x 2 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16m1_i32m1(<vscale x 4 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca 
# | ...
# `---data was truncated (10240/43515) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fe3804deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fe3804ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fe3804e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe429849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe4298a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe429849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe429831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fe37fe3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fe37fe3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fe37fc88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fe37c77e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fe37c77b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe429832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe4298330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe4298330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fe37c77a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c (1788 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563aeb1d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563aeb1d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563aeb1d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f81c9649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f81c96a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f81c9649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f81c9631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563aeb16cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563aeb16ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563aeb1518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563aeae00e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563aeae00b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f81c9632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f81c96330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f81c96330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563aeae00a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c (1789 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_f16m1x2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_f16m2x2(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_f16m4x2(ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_f32m1x2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_f32m2x2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vect
# | ...
# `---data was truncated (10240/113765) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005582a6de5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005582a6de2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005582a6de662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f723d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f723d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f723d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f723d631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005582a6d7bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005582a6d7ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005582a6d608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005582a6a0fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005582a6a0fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f723d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f723d6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f723d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005582a6a0fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c (1790 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8ff_v_i8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8ff_v_i8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8ff_v_i8mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8ff_v_i8m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8ff_v_i8m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8ff_v_u8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { targe
# | ...
# `---data was truncated (10240/68233) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562a7101feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562a7101ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562a7102062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f361ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f361aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f361ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f361ac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562a70fb5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562a70fb5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562a70f9a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562a70c49e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562a70c49b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f361ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f361ac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f361ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562a70c49a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c (1791 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlsseg2e8_v_i8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e8_v_i8mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e8_v_i8mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e8_v_i8m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e8_v_i8m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e8_v_i8m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlsseg2e8_v_u8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, al
# | ...
# `---data was truncated (10240/72135) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557271c1beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557271c18e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557271c1c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d76249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d762a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d76249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d76231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557271bb1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557271bb1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557271b968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557271845e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557271845b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8d76232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d762330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d762330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557271845a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c (1792 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfwcvt_f_x_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfwcvt_f_x_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfwcvt_f_x_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfwcvt_f_x_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfwcvt_f_x_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfwcvt_f_x_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfwcvt_f_xu_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfwcvt_f_xu_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfwcvt_f_xu_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfwcvt_f_xu_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %sr
# | ...
# `---data was truncated (10240/288111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c9af64eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563c9af61e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563c9af6562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faddbc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faddbca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faddbc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faddbc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c9aefabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563c9aefaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563c9aedf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563c9ab8ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563c9ab8eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faddbc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faddbc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faddbc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c9ab8ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c (1793 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vle16ff_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(<vscale x 1 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(<vscale x 1 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vle16ff_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(<vscale x 2 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 2 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(<vscale x 2 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vle16ff_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(<vscale x 4 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 4 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(<vscale x 4 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vle16ff_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(<vscale x 8 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(<vscale x 8 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vle16ff_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(<vscale x 16 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 16 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 16 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(<vscale x 16 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vle16ff_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(<vscale x 32 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 32 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 32 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(<vscale x 32 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16ff_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(<vscale x 1 x i16> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i16>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i16>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 1 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(<vscale x 1 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16ff_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(<vscale x 2 x i16> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x i16>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i16>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 2 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(<vscale x 2 x i16
# | ...
# `---data was truncated (10240/93458) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560616389eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560616386e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056061638a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0362305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f036235c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0362305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f03622ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056061631fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056061631fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005606163048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560615fb3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560615fb3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f03622eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03622ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03622ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560615fb3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c (1794 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f16m1x5(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f32m1x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f64m1x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i64> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d6d3af3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d6d3af0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d6d3af462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff587f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff587f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff587f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff587eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d6d3a89bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d6d3a89a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d6d3a6e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d6d371de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d6d371db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff587eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff587eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff587eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d6d371da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c (1795 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsof_m_b1_mu(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %maskedoff, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %2, <vscale x 64 x i1> %0, i64 %3)
# |   ret <vscale x 64 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsof_m_b2_mu(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %maskedoff, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %2, <vscale x 32 x i1> %0, i64 %3)
# |   ret <vscale x 32 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsof_m_b4_mu(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %maskedoff, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %2, <vscale x 16 x i1> %0, i64 %3)
# |   ret <vscale x 16 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsof_m_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %2, <vscale x 8 x i1> %0, i64 %3)
# |   ret <vscale x 8 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsof_m_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %2, <vscale x 4 x i1> %0, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsof_m_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %2, <vscale x 2 x i1> %0, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsof_m_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1.i64(<vscale x 1 x i1> %1, <vscale x 1 x i1> %2, <vscale x 1 x i1> %0, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ce21c76eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ce21c73e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ce21c7762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb04701bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb0470725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb04701ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb047003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ce21c0cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ce21c0ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ce21bf18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ce218a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ce218a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb047004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb0470050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb0470050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ce218a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c (1796 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfwmacc_4x4x4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 4 x bfloat>, <vscale x 1 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfwmacc_4x4x4_f32m1(<vscale x 2 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 4 x bfloat>, <vscale x 2 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfwmacc_4x4x4_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfwmacc_4x4x4_f32m4(<vscale x 8 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfwmacc_4x4x4_f32m8(<vscale x 16 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(<vscale x 16 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 4 x bfloat>, <vscale x 16 x bfloat>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvfwmaccqqq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvfwmaccqqq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056377592ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563775929e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056377592d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd7df333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd7df38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd7df333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd7df31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005637758c2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005637758c2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005637758a78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563775556e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563775556b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd7df31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd7df31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd7df31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563775556a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c (1797 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vminu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vminu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vminu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vminu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vminu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vminu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vminu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vminu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vminu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op
# | ...
# `---data was truncated (10240/222917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562f20979eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562f20976e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562f2097a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7fce449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7fce4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7fce449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7fce431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562f2090fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562f2090fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562f208f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562f205a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562f205a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7fce432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7fce4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7fce4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562f205a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c (1798 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmadd_vv_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmadd_vx_i8mf8_tu(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmadd_vv_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmadd_vx_i8mf4_tu(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmadd_vv_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmadd_vx_i8mf2_tu(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmadd_vv_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmadd_vx_i8m1_tu(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmadd_vv_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %
# | ...
# `---data was truncated (10240/414517) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561766270eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056176626de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056176627162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa8ece49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa8ecea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa8ece49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa8ece31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561766206bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561766206a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005617661eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561765e9ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561765e9ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa8ece32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa8ece330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa8ece330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561765e9aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c (1799 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557c3951beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557c39518e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557c3951c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1277649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f12776a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1277649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1277631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557c394b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557c394b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557c394968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557c39145e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557c39145b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1277632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f12776330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f12776330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557c39145a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c (1800 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dotsu_vv_i32mf2(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dotsu_vv_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dotsu_vv_i32m2(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dotsu_vv_i32m4(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dotsu_vv_i32m8(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dotsu_vv_i64m1(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dotsu_vv_i64m2(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dotsu_vv_i64m4(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotsu.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4
# | ...
# `---data was truncated (10240/25575) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560e2356ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560e23569e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560e2356d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd09ee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd09eea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd09ee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd09ee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e23502bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560e23502a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560e234e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560e23196e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560e23196b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd09ee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd09ee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd09ee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e23196a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c (1801 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_f64m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_f64m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_i64m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_i64m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_u64m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_u64m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>,
# | ...
# `---data was truncated (10240/16424) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a2c67d0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a2c67cde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a2c67d162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec77733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec7778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec77733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec7771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a2c6766bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a2c6766a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a2c674b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a2c63fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a2c63fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fec7771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec7771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec7771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a2c63faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c (1802 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xtheadbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c  -check-prefix=RV32XTHEADBB
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xtheadbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clz_32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call i32 @llvm.ctlz.i32(i32 %0, i1 false)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.ctlz.i32(i32, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clo_32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %not = xor i32 %0, -1
# |   %1 = call i32 @llvm.ctlz.i32(i32 %not, i1 false)
# |   ret i32 %1
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+xtheadbb" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_xtheadbb1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560dcc202eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560dcc1ffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560dcc20362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8dee133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8dee18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8dee133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8dee11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560dcc198bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560dcc198a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560dcc17d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560dcbe2ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560dcbe2cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8dee11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8dee11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8dee11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560dcbe2ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c -check-prefix=RV32XTHEADBB
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c -check-prefix=RV32XTHEADBB
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c (1803 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpairo_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vpairo.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpairo.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpairo_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vpairo.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpairo.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpairo_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vpairo.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vpairo.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vpairo_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vpairo.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vpairo.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vpairo_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vpairo.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vpairo.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vpairo_vv_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, <vscale x 32 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vpairo.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vpairo.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpairo_vv_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vpairo.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpairo.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpairo_vv_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2
# | ...
# `---data was truncated (10240/32654) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005622d5002eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005622d4fffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005622d500362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc21cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc21cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc21cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc21cf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005622d4f98bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005622d4f98a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005622d4f7d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005622d4c2ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005622d4c2cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc21cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc21cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc21cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005622d4c2ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c (1804 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_f16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_f16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_f16m1x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_i16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_i16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_i16m1x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_u16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_u16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_u16m1x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_
# | ...
# `---data was truncated (10240/10396) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556536007eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556536004e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055653600862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9a62b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9a62b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9a62b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9a62aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556535f9dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556535f9da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556535f828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556535c31e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556535c31b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9a62aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9a62aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9a62aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556535c31a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c (1805 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vv_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vf_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wv_bf16mf4_f32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wf_bf16_f32mf2(<vscale x 1 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vv_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vf_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wv_bf16mf2_f32m1(<vscale x 2 x float> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wf_bf16_f32m1(<vscale x 2 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwadd_vv_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwadd_vf_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# | 
# | ...
# `---data was truncated (10240/86100) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005569f1563eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005569f1560e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005569f156462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f87ace49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87acea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f87ace49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87ace31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005569f14f9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005569f14f9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005569f14de8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005569f118de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005569f118db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f87ace32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87ace330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87ace330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005569f118da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c (1806 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.
# | ...
# `---data was truncated (10240/101402) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cac7d44eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cac7d41e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cac7d4562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f571b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f571b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f571b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f571b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cac7cdabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cac7cdaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cac7cbf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cac796ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cac796eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f571b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f571b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f571b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cac796ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c (1807 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f16m1x3(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_f16m2x3(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f32m1x3(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_f32m2x3(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f64m1x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.
# | ...
# `---data was truncated (10240/87884) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fda6b61eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fda6b5ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fda6b6262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8508449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f85084a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8508449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8508431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fda6af7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fda6af7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fda6adc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fda678be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fda678bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8508432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f85084330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f85084330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fda678ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c (1808 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), pt
# | ...
# `---data was truncated (10240/19484) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cbc59dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cbc59dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cbc59e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa1d3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa1d338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa1d3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa1d331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cbc5975bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cbc5975a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cbc595a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cbc5609e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cbc5609b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa1d331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa1d331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa1d331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cbc5609a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c (1809 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_bf16mf4x6(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_bf16mf2x6(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_bf16m1x6(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f55d04beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f55d048e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f55d04c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f69f4449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f69f44a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f69f4449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f69f4431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f55cfe1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f55cfe1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f55cfc68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f55cc75e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f55cc75b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f69f4432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f69f44330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f69f44330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f55cc75a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c (1810 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmerge_vvm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmerge_vxm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmerge_vvm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmerge_vxm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmerge_vvm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmerge_vxm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmerge_vvm_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | de
# | ...
# `---data was truncated (10240/148020) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e0bcb97eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e0bcb94e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e0bcb9862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f17bd533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f17bd58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f17bd533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f17bd51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e0bcb2dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e0bcb2da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e0bcb128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e0bc7c1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e0bc7c1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f17bd51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f17bd51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f17bd51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e0bc7c1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c (1811 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsaddu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsaddu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsaddu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsaddu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsaddu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsaddu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsaddu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsaddu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsaddu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsaddu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsaddu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsaddu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsaddu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsaddu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsaddu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = allo
# | ...
# `---data was truncated (10240/98179) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557387770eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055738776de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055738777162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8be5049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8be50a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8be5049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8be5031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557387706bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557387706a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005573876eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055738739ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055738739ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8be5032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8be50330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8be50330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055738739aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c (1812 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i16> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i
# | ...
# `---data was truncated (10240/15699) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056281351feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056281351ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056281352062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2ae8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2ae818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2ae8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2ae811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005628134b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005628134b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056281349a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562813149e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562813149b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2ae811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2ae811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2ae811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562813149a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/distributed-thin-lto/cfi-devirt.ll (1813 of 27911)
******************** TEST 'Clang :: CodeGen/distributed-thin-lto/cfi-devirt.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 7
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi-devirt.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi-devirt.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi-devirt.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi-devirt.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi-devirt.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi-devirt.ll
# |  #0 0x0000564356726eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564356723e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056435672762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9d40c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9d40ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9d40c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9d40c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005643566bcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005643566bca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005643566a18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564356350e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564356350b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9d40c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9d40c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9d40c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564356350a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c (1814 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.
# | ...
# `---data was truncated (10240/16808) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bf5254aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bf52547e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bf5254b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f808cf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f808cf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f808cf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f808ceed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bf524e0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bf524e0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bf524c58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bf52174e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bf52174b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f808ceeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f808ceef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f808ceef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bf52174a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c (1815 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfabs_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfabs_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfabs_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfabs_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfabs_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfabs_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfabs_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfabs_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfabs_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfabs_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfsgnjx.nxv8f32.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfsgnjx.nxv8f32.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfabs_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfsgnjx.nxv16f32.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfsgnjx.nxv16f32.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfabs_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, al
# | ...
# `---data was truncated (10240/30861) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c8a741aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c8a7417e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c8a741b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe38c105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe38c15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe38c105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe38c0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c8a73b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c8a73b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c8a73958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c8a7044e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c8a7044b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe38c0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe38c0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe38c0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c8a7044a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c (1816 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vle32_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vle.nxv1f32.p0.i64(<vscale x 1 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x float> @llvm.riscv.vle.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vle32_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vle.nxv2f32.p0.i64(<vscale x 2 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x float> @llvm.riscv.vle.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vle32_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vle.nxv4f32.p0.i64(<vscale x 4 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.riscv.vle.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vle32_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vle.nxv8f32.p0.i64(<vscale x 8 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x float> @llvm.riscv.vle.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vle32_v_f32m8_tu(<vscale x 16 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.p0.i64(<vscale x 16 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.p0.i64(<vscale x 1 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.p0.i64(<vscale x 2 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.p0.i64(<vscale x 4 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vle32_v_i32m4_tu(<vscale x 8 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32.p0.i64(<vscale x 8 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vle32_v_i32m8_tu(<vscale x 16 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.p0.i64(<vscale x 16 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.p0.i64(<vscale x 16 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32_v_u32mf2_tu(<vscale x 1 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %bas
# | ...
# `---data was truncated (10240/60209) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558580e44eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558580e41e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558580e4562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f07d9649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f07d96a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f07d9649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f07d9631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558580ddabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558580ddaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558580dbf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558580a6ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558580a6eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f07d9632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f07d96330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f07d96330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558580a6ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c (1817 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs1, <vsc
# | ...
# `---data was truncated (10240/148835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005630772afeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005630772ace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005630772b062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5cbb649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5cbb6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5cbb649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5cbb631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563077245bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563077245a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056307722a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563076ed9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563076ed9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5cbb632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5cbb6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5cbb6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563076ed9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c (1818 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vle16ff_v_f16mf4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(<vscale x 1 x half> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x half>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x half>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(<vscale x 1 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vle16ff_v_f16mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(<vscale x 2 x half> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x half>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x half>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(<vscale x 2 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vle16ff_v_f16m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(<vscale x 4 x half> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x half>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x half>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(<vscale x 4 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vle16ff_v_f16m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(<vscale x 8 x half> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 8 x half>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 8 x half>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(<vscale x 8 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vle16ff_v_f16m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(<vscale x 16 x half> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 16 x half>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 16 x half>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(<vscale x 16 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vle16ff_v_f16m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(<vscale x 32 x half> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 32 x half>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 32 x half>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(<vscale x 32 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16ff_v_i16mf4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(<vscale x 1 x i16> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x i16>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x i16>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(<vscale x 1 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16ff_v_i16mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(<vscale x 2 x i16> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x i16>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i16>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(<vscale x 2 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vle16ff_v_i16m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.nxv4i16.i64.p0(<vscale x 4 x i16> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x i16>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i16>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.nxv4i16.i64.p0(<vscale x 4 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vle16ff_v_i16m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 8 x i16>, i64 } @llvm.riscv.vleff.nxv8i16.i64.p0(<vscale x 8 x i16> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale 
# | ...
# `---data was truncated (10240/39900) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c9ff39ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c9ff399e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c9ff39d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f03fd649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03fd6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f03fd649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f03fd631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9ff332bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c9ff332a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c9ff3178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c9fefc6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c9fefc6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f03fd632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03fd6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03fd6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c9fefc6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c (1819 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vand_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vand_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vand_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vand_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vand_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vand_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vand_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vand_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vand_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vand_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vand_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/175155) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c97ef98eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c97ef95e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c97ef9962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f969c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f969c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f969c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f969c31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c97ef2ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c97ef2ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c97ef138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c97ebc2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c97ebc2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f969c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f969c31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f969c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c97ebc2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGenCXX/inline-then-fold-variadics.cpp (1820 of 27911)
******************** TEST 'Clang :: CodeGenCXX/inline-then-fold-variadics.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp -triple wasm32-unknown-unknown -Wno-varargs -O1 -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S --passes='module(expand-variadics,default<O1>)' --expand-variadics-override=optimize -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp -triple wasm32-unknown-unknown -Wno-varargs -O1 -emit-llvm -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp"
# | target datalayout = "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-i128:128-n32:64-S128-ni:1:10:20"
# | target triple = "wasm32-unknown-unknown"
# | 
# | %struct.asc = type { i8, i16, i32, i32, float, double }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef i32 @first_pair_i32(i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
# | entry:
# |   %call = tail call noundef i32 (...) @_ZL5firstIiiET_z(i32 noundef %x, i32 noundef %y)
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef i32 @_ZL5firstIiiET_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur, i32 4
# |   store ptr %argp.next, ptr %va, align 4
# |   %0 = load i32, ptr %argp.cur, align 4, !tbaa !6
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef i32 @second_pair_i32(i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
# | entry:
# |   %call = tail call noundef i32 (...) @_ZL6secondIiiET0_z(i32 noundef %x, i32 noundef %y)
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef i32 @_ZL6secondIiiET0_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur, i32 4
# |   %argp.next2 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 8
# |   store ptr %argp.next2, ptr %va, align 4
# |   %0 = load i32, ptr %argp.next, align 4, !tbaa !6
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef double @first_pair_f64(double noundef %x, double noundef %y) local_unnamed_addr #0 {
# | entry:
# |   %call = tail call noundef double (...) @_ZL5firstIddET_z(double noundef %x, double noundef %y)
# |   ret double %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef double @_ZL5firstIddET_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 7
# |   %argp.cur.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8)
# |   %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 8
# |   store ptr %argp.next, ptr %va, align 4
# |   %1 = load double, ptr %argp.cur.aligned, align 8, !tbaa !7
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret double %1
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef double @second_pair_f64(double noundef %x, double noundef %y) local_unnamed_addr #0 {
# | entry:
# |   %call = tail call noundef double (...) @_ZL6secondIddET0_z(double noundef %x, double noundef %y)
# |   ret double %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef double @_ZL6secondIddET0_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 7
# |   %argp.cur.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8)
# |   %1 = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 8
# |   %argp.next2 = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 16
# |   store ptr %argp.next2, ptr %va, align 4
# |   %2 = load double, ptr %1, align 8, !tbaa !7
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret double %2
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef i32 @first_i32_f64(i32 noundef %x, double noundef %y) local_unnamed_addr #0 {
# | entry:
# |   %call = tail call noundef i32 (...) @_ZL5firstIidET_z(i32 noundef %x, double noundef %y)
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef i32 @_ZL5firstIidET_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur, i32 4
# |   store ptr %argp.next, ptr %va, align 4
# |   %0 = load i32, ptr %argp.cur, align 4, !tbaa !6
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef double @second_i32_f64(i32 noundef %x, double noundef %y) local_unnamed_addr #0 {
# | entry:
# |   %call = tail call noundef double (...) @_ZL6secondIidET0_z(i32 noundef %x, double noundef %y)
# |   ret double %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef double @_ZL6secondIidET0_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 11
# |   %argp.cur1.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8)
# |   %argp.next2 = getelementptr inbounds nuw i8, ptr %argp.cur1.aligned, i32 8
# |   store ptr %argp.next2, ptr %va, align 4
# |   %1 = load double, ptr %argp.cur1.aligned, align 8, !tbaa !7
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret double %1
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef double @first_f64_i32(double noundef %x, i32 noundef %y) local_unnamed_addr #0 {
# | entry:
# |   %call = tail call noundef double (...) @_ZL5firstIdiET_z(double noundef %x, i32 noundef %y)
# |   ret double %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef double @_ZL5firstIdiET_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 7
# |   %argp.cur.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8)
# |   %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 8
# |   store ptr %argp.next, ptr %va, align 4
# |   %1 = load double, ptr %argp.cur.aligned, align 8, !tbaa !7
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret double %1
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef i32 @second_f64_i32(double noundef %x, i32 noundef %y) local_unnamed_addr #0 {
# | entry:
# |   %call = tail call noundef i32 (...) @_ZL6secondIdiET0_z(double noundef %x, i32 noundef %y)
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef i32 @_ZL6secondIdiET0_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 7
# |   %argp.cur.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8)
# |   %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 8
# |   %argp.next2 = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 12
# |   store ptr %argp.next2, ptr %va, align 4
# |   %1 = load i32, ptr %argp.next, align 8, !tbaa !6
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef i32 @first_i32_ulong2(i32 noundef %x, ptr nofree noundef readonly captures(none) %y) local_unnamed_addr #0 {
# | entry:
# |   %0 = load <2 x i64>, ptr %y, align 16, !tbaa !9
# |   %call = tail call noundef i32 (...) @_ZL5firstIiDv2_yET_z(i32 noundef %x, <2 x i64> noundef %0)
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef i32 @_ZL5firstIiDv2_yET_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur, i32 4
# |   store ptr %argp.next, ptr %va, align 4
# |   %0 = load i32, ptr %argp.cur, align 4, !tbaa !6
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define void @second_i32_ulong2(i32 noundef %x, ptr nofree noundef readonly captures(none) %y, ptr nofree noundef writeonly captures(none) initializes((0, 16)) %r) local_unnamed_addr #0 {
# | entry:
# |   %0 = load <2 x i64>, ptr %y, align 16, !tbaa !9
# |   %call = tail call noundef <2 x i64> (...) @_ZL6secondIiDv2_yET0_z(i32 noundef %x, <2 x i64> noundef %0)
# |   store <2 x i64> %call, ptr %r, align 16, !tbaa !9
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef <2 x i64> @_ZL6secondIiDv2_yET0_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr n
# | ...
# `---data was truncated (10240/20646) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S '--passes=module(expand-variadics,default<O1>)' --expand-variadics-override=optimize -o -
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S --passes=module(expand-variadics,default<O1>) --expand-variadics-override=optimize -o -
# |  #0 0x0000563e999d0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563e999cde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563e999d162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f40a1449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f40a14a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f40a1449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f40a1431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e99966bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563e99966a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563e9994b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563e995fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563e995fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f40a1432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f40a14330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f40a14330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e995faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c (1821 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_x_f_v_i32mf2(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_x_f_v_i32m1(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_x_f_v_i32m2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_x_f_v_i32m4(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_x_f_v_i32m8(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_xu_f_v_u32mf2(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_xu_f_v_u32m1(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_xu_f_v_u32m2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_xu_f_v_u32m4(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_xu_f_v_u32m8(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vfwcvt_rtz_x_f_v_i64m1(<vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x i64>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vfwcvt_rtz_x_f_v_i64m2(<vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm
# | ...
# `---data was truncated (10240/35597) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056523071ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565230719e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056523071d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f11f1249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f11f12a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f11f1249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f11f1231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005652306b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005652306b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005652306978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565230346e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565230346b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f11f1232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f11f12330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f11f12330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565230346a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c (1822 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vf_f32mf2(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vf_f32m1(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vf_f32m2(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vf_f32m4(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x fl
# | ...
# `---data was truncated (10240/90693) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005639e61b0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005639e61ade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005639e61b162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1762705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f176275c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1762705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f17626ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005639e6146bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005639e6146a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005639e612b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005639e5ddae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005639e5ddab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f17626eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f17626ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f17626ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639e5ddaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c (1823 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf4_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> %0, <vscale x 1 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float>, <vscale x 1 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 4 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> %0, <vscale x 4 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float>, <vscale x 4 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 8 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> %0, <vscale x 8 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float>, <vscale x 8 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m4_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 16 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> %0, <vscale x 16 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float>, <vscale x 16 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m8_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 32 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float>, <vscale x 32 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32mf2_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 1 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x double> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m1_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 2 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, ali
# | ...
# `---data was truncated (10240/60334) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561670b64eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561670b61e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561670b6562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f34fc649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f34fc6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f34fc649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f34fc631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561670afabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561670afaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561670adf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056167078ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056167078eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f34fc632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f34fc6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f34fc6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056167078ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c (1824 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558b09b53eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558b09b50e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558b09b5462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffa6ba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffa6baa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffa6ba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffa6ba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558b09ae9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558b09ae9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558b09ace8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558b0977de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558b0977db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffa6ba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffa6ba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffa6ba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558b0977da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c (1825 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgather_vv_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgather_vx_bf16mf4(<vscale x 1 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgather_vv_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgather_vx_bf16mf2(<vscale x 2 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgather_vv_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgather_vx_bf16m1(<vscale x 4 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgather_vv_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgather_vx_bf16m2(<vscale x 8 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgather_vv_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vrgather.vv.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vrgather.vv.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgather_vx_bf16m4(<vscale x 16 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vrga
# | ...
# `---data was truncated (10240/28435) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561f2a1eceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561f2a1e9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561f2a1ed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcb6c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcb6c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcb6c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcb6c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f2a182bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561f2a182a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561f2a1678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561f29e16e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561f29e16b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcb6c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcb6c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcb6c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f29e16a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/linker-diagnostic.ll (1826 of 27911)
******************** TEST 'Clang :: CodeGen/linker-diagnostic.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 2
mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp
# executed command: mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp/foo.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/linker-diagnostic.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp/foo.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/linker-diagnostic.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp/foo.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/linker-diagnostic.ll
# |  #0 0x000055774333aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557743337e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055774333b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f03b8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03b818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f03b8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f03b811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005577432d0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005577432d0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005577432b58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557742f64e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557742f64b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f03b811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03b811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03b811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557742f64a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c (1827 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_vv_u16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_vx_u16mf4(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_wv_u16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_wx_u16mf4(<vscale x 1 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_vv_u16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_vx_u16mf2(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_wv_u16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_wx_u16mf2(<vscale x 2 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwaddu_vv_u16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwaddu_vx_u16m1(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscal
# | ...
# `---data was truncated (10240/134927) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b8aa531eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b8aa52ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b8aa53262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1761933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f176198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1761933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f176191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b8aa4c7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b8aa4c7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b8aa4ac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b8aa15be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b8aa15bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f176191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f176191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f176191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b8aa15ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c (1828 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vlse32_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32.p0.i64(<vscale x 1 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vlse32_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32.p0.i64(<vscale x 2 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vlse32_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32.p0.i64(<vscale x 4 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vlse32_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32.p0.i64(<vscale x 8 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vlse32_v_f32m8_tu(<vscale x 16 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32.p0.i64(<vscale x 16 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 16 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vlse32_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.p0.i64(<vscale x 1 x i32> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vlse32_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32.p0.i64(<vscale x 2 x i32> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vlse32_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32.p0.i64(<vscale x 4 x i32> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vlse32_v_i32m4_tu(<vscale x 8 x i32> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32.p0.i64(<vscale x 8 x i32> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vsc
# | ...
# `---data was truncated (10240/69951) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f7a290beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f7a2908e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f7a290c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f43a521bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f43a52725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f43a521ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f43a5203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f7a28a1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f7a28a1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f7a28868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f7a2535e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f7a2535b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f43a5204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f43a52050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f43a52050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f7a2535a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c (1829 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.
# | ...
# `---data was truncated (10240/18498) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556fd1c90eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556fd1c8de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556fd1c9162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb21c505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb21c55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb21c505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb21c4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556fd1c26bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556fd1c26a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556fd1c0b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556fd18bae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556fd18bab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb21c4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb21c4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb21c4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556fd18baa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c (1830 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4k_vi_u32mf2(<vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i64.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4k_vi_u32m1(<vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i64.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4k_vi_u32m2(<vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i64.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4k_vi_u32m4(<vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i64.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm4k_vi_u32m8(<vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i64.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005607a99e6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005607a99e3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005607a99e762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8f5bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8f5bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8f5bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8f5bd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607a997cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005607a997ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005607a99618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005607a9610e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005607a9610b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8f5bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8f5bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8f5bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607a9610a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c (1831 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_v
# | ...
# `---data was truncated (10240/216258) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ae1ca65eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ae1ca62e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ae1ca6662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f76b7905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f76b795c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f76b7905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f76b78ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ae1c9fbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ae1c9fba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ae1c9e08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ae1c68fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ae1c68fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f76b78eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f76b78ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f76b78ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ae1c68fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c (1832 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmadd_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmadd_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmadd_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmadd_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmadd_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmadd_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmadd_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmadd_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3
# | ...
# `---data was truncated (10240/64366) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555dd918deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555dd918ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555dd918e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fefbd649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fefbd6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fefbd649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fefbd631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555dd9123bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555dd9123a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555dd91088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555dd8db7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555dd8db7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fefbd632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fefbd6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fefbd6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555dd8db7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c (1833 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_vv_u16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_vx_u16mf4(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_wv_u16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_wx_u16mf4(<vscale x 1 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_vv_u16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_vx_u16mf2(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_wv_u16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_wx_u16mf2(<vscale x 2 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsubu_vv_u16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsubu_vx_u16m1(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x 
# | ...
# `---data was truncated (10240/134919) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556ecad5eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556ecad5be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556ecad5f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa033d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa033d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa033d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa033d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ecacf4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556ecacf4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556ecacd98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556eca988e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556eca988b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa033d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa033d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa033d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556eca988a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c (1834 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulhsu_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulhsu_vx_i8m4(<vscale x 32 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 64 x i8> @test_vmulhsu_vv_i8m8(<vscale x 64 x i8> %op1, <vscale x 64 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %
# | ...
# `---data was truncated (10240/66087) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005601e583beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005601e5838e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005601e583c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f535b81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f535b8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f535b81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f535b803507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005601e57d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005601e57d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005601e57b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005601e5465e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005601e5465b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f535b804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f535b8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f535b8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005601e5465a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c (1835 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssrl_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssrl_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssrl_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssrl_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssrl_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssrl_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssrl_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssrl_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssrl_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, al
# | ...
# `---data was truncated (10240/226593) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e164ae5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e164ae2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e164ae662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f220dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f220dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f220dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f220dd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e164a7bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e164a7ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e164a608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e16470fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e16470fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f220dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f220dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f220dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e16470fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c (1836 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei64_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561d9e32ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561d9e329e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561d9e32d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f50e0249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f50e02a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f50e0249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f50e0231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561d9e2c2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561d9e2c2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561d9e2a78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561d9df56e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561d9df56b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f50e0232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f50e02330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f50e02330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561d9df56a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c (1837 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei8_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8
# | ...
# `---data was truncated (10240/160141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055755bc3beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055755bc38e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055755bc3c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc36c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc36ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc36c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc36c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055755bbd1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055755bbd1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055755bbb68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055755b865e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055755b865b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdc36c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc36c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc36c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055755b865a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c (1838 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_i64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_i64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_u64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_u64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c75081ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c750819e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c75081d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc684e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc684ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc684e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc684e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c7507b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c7507b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c7507978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c750446e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c750446b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc684e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc684e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc684e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c750446a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c (1839 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vsc
# | ...
# `---data was truncated (10240/11789) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eb5e059eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eb5e056e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eb5e05a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f727d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f727d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f727d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f727d91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb5dfefbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eb5dfefa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eb5dfd48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eb5dc83e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eb5dc83b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f727d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f727d91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f727d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb5dc83a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c (1840 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vset_v_f16m1_f16m2(<vscale x 8 x half> %dest, i64 noundef %index, <vscale x 4 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 8 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 0)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vset_v_f16m1_f16m4(<vscale x 16 x half> %dest, i64 noundef %index, <vscale x 4 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 16 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 0)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vset_v_f16m2_f16m4(<vscale x 16 x half> %dest, i64 noundef %index, <vscale x 8 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 16 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half> %0, <vscale x 8 x half> %1, i64 0)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vset_v_f16m1_f16m8(<vscale x 32 x half> %dest, i64 noundef %index, <vscale x 4 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 0)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vset_v_f16m2_f16m8(<vscale x 32 x half> %dest, i64 noundef %index, <vscale x 8 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> %0, <vscale x 8 x half> %1, i64 0)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vset_v_f16m4_f16m8(<vscale x 32 x half> %dest, i64 noundef %index, <vscale x 16 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 16 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half> %0, <vscale x 16 x half> %1, i64 0)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half>, <vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vset_v_f32m1_f32m2(<vscale x 4 x float> %dest, i64 noundef %index, <vscale x 2 x float> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 4 x float> %dest, ptr %dest.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 2 x float> %val, ptr %val.addr, align 4
# |   %0 = load <vscale x 4 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %val.addr, align 4
# |   %2 = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 0)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float>, <vscale x 2 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vset_v_f32m1_f32m4(<vscale x 8 x float> %dest, i64 noundef %index, <vscale x 2 x float> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 8 x float> %dest, ptr %dest.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 2 x float> %val, ptr %val.addr, align 4
# |   %0 = load <vscale x 8 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %val.addr, align 4
# |   %2 = call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv2f32(<vscale x 8 x float> %0, <vscale x 2 x float> %1, i64 0)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv2f32(<vscale x 8 x float>, <vscale x 2 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vset_v_f32m2_f32m4(<vscale x 8 x float> %dest, i64 noundef %index, <vscale x 4 x float> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 4 x float>, align 4
# |   store <vscale x 8 x float> %dest, ptr %dest.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x float> %val, ptr %val.addr, align 4
# |   %0 = load <vscale x 8 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %val.addr, align 4
# |   %2 = call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv4f32(<vscale x 8 x float> %0, <vscale x 4 x float> %1, i64 0)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv4f32(<vscale x 8 x float>, <vscale x 4 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vset_v_f32m1_f32m8(<vscale x 16 x float> %dest, i64 noundef %index, <vscale x 2 x float> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 16 x float> %dest, ptr %dest.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 2 x float> %val, ptr %val.addr, align 4
# |   %0 = load <vscale x 16 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %val.addr, align 4
# |   %2 = call <vscale x 16 x float> @llvm.vector.insert.nxv16f32.nxv2f32(<vscale x 16 x float> %0, <vscale x 2 x float> %1, i64 0)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16
# | ...
# `---data was truncated (10240/338692) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563de3283eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563de3280e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563de328462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f08b9e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f08b9ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f08b9e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f08b9e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563de3219bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563de3219a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563de31fe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563de2eade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563de2eadb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f08b9e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f08b9e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f08b9e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563de2eada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c (1841 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f16m1x3(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f16m2x3(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f32m1x3(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f32m2x3(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f64m1x3(ptr noundef %base, <vscale x 1 x i64
# | ...
# `---data was truncated (10240/94235) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a31ddb1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a31ddaee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a31ddb262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcbf7449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcbf74a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcbf7449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcbf7431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a31dd47bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a31dd47a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a31dd2c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a31d9dbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a31d9dbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcbf7432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcbf74330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcbf74330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a31d9dba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c (1842 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f16m1x6(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f32m1x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f64m1x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei16_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562bb5ee9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562bb5ee6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562bb5eea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fde37905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fde3795c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fde37905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fde378ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562bb5e7fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562bb5e7fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562bb5e648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562bb5b13e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562bb5b13b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fde378eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fde378ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fde378ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562bb5b13a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c (1843 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredsum_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredsum_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredsum_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 
# | ...
# `---data was truncated (10240/94379) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565068820eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056506881de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056506882162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c29c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c29ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c29c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c29c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005650687b6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005650687b6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056506879b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056506844ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056506844ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8c29c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c29c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c29c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056506844aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c (1844 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf4_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf4_i32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vsext_vf4_i32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vsext_vf4_i32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf4_i64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf4_i64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf4_i64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf4_i64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i32> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call
# | ...
# `---data was truncated (10240/39914) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a5021cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a5021c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a5021cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0fc7e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0fc7ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0fc7e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0fc7e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a502161bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a502161a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a5021468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a501df5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a501df5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0fc7e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0fc7e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0fc7e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a501df5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c (1845 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_f32mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_f32m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_i32mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_i32m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_u32mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_u32m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_i32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_i32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/14010) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d37d551eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d37d54ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d37d55262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9025333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f902538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9025333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f902531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d37d4e7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d37d4e7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d37d4cc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d37d17be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d37d17bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f902531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f902531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f902531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d37d17ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c (1846 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei16_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005581963a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005581963a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005581963a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0014e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0014ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0014e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0014e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055819633dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055819633da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005581963228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558195fd1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558195fd1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0014e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0014e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0014e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558195fd1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c (1847 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560f554aeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560f554abe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560f554af62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efdb4533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efdb458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efdb4533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efdb451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f55444bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560f55444a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560f554298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560f550d8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560f550d8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efdb451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efdb451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efdb451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f550d8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c (1848 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsub_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsub_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsub_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsub_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsub_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrsub_vf_bf16m8(<vscale x 32 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsub_vf_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsub_vf_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsub.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsub.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsub_vf_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsub.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsub.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i
# | ...
# `---data was truncated (10240/14788) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005622b0bd3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005622b0bd0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005622b0bd462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9585733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f958578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9585733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f958571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005622b0b69bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005622b0b69a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005622b0b4e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005622b07fde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005622b07fdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f958571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f958571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f958571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005622b07fda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c (1849 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556e87b7feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556e87b7ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556e87b8062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0075d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0075d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0075d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0075d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e87b15bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556e87b15a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556e87afa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556e877a9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556e877a9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0075d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0075d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0075d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e877a9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c (1850 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfle_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfle_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfle_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/66557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558791080eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055879107de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055879108162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f086ca1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f086ca725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f086ca1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f086ca03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558791016bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558791016a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558790ffb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558790caae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558790caab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f086ca04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f086ca050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f086ca050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558790caaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c (1851 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmadd_vv_i8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmadd_vx_i8mf8(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmadd_vv_i8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmadd_vx_i8mf4(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmadd_vv_i8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmadd_vx_i8mf2(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmadd_vv_i8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmadd_vx_i8m1(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmadd_vv_i8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |  
# | ...
# `---data was truncated (10240/207749) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557a88b25eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557a88b22e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557a88b2662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7aa9b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7aa9b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7aa9b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7aa9aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557a88abbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557a88abba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557a88aa08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557a8874fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557a8874fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7aa9aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7aa9aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7aa9aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557a8874fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/bf16-lane-intrinsics.c (1852 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/bf16-lane-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vcopy_lane_bf16_v1(<4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   %b.addr = alloca <4 x bfloat>, align 8
# |   %__ret_322 = alloca <4 x bfloat>, align 8
# |   %__s0_322 = alloca <4 x bfloat>, align 8
# |   %__s2_322 = alloca <4 x bfloat>, align 8
# |   %__ret = alloca <4 x bfloat>, align 8
# |   %__s0 = alloca bfloat, align 2
# |   %__ret1 = alloca bfloat, align 2
# |   %__s02 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca bfloat, align 2
# |   %tmp = alloca bfloat, align 2
# |   %__s1 = alloca <4 x bfloat>, align 8
# |   %ref.tmp3 = alloca <4 x bfloat>, align 8
# |   %tmp4 = alloca <4 x bfloat>, align 8
# |   %tmp5 = alloca <4 x bfloat>, align 8
# |   store <4 x bfloat> %a, ptr %a.addr, align 8
# |   store <4 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <4 x bfloat>, ptr %a.addr, align 8
# |   store <4 x bfloat> %0, ptr %__s0_322, align 8
# |   %1 = load <4 x bfloat>, ptr %b.addr, align 8
# |   store <4 x bfloat> %1, ptr %__s2_322, align 8
# |   %2 = load <4 x bfloat>, ptr %__s2_322, align 8
# |   store <4 x bfloat> %2, ptr %__s02, align 8
# |   %3 = load <4 x bfloat>, ptr %__s02, align 8
# |   %vget_lane = extractelement <4 x bfloat> %3, i32 3
# |   store bfloat %vget_lane, ptr %ref.tmp, align 2
# |   %4 = load bfloat, ptr %ref.tmp, align 2
# |   store bfloat %4, ptr %__ret1, align 2
# |   %5 = load bfloat, ptr %__ret1, align 2
# |   store bfloat %5, ptr %tmp, align 2
# |   %6 = load bfloat, ptr %tmp, align 2
# |   store bfloat %6, ptr %__s0, align 2
# |   %7 = load <4 x bfloat>, ptr %__s0_322, align 8
# |   store <4 x bfloat> %7, ptr %__s1, align 8
# |   %8 = load bfloat, ptr %__s0, align 2
# |   %9 = load <4 x bfloat>, ptr %__s1, align 8
# |   %vset_lane = insertelement <4 x bfloat> %9, bfloat %8, i32 1
# |   store <4 x bfloat> %vset_lane, ptr %ref.tmp3, align 8
# |   %10 = load <4 x bfloat>, ptr %ref.tmp3, align 8
# |   store <4 x bfloat> %10, ptr %__ret, align 8
# |   %11 = load <4 x bfloat>, ptr %__ret, align 8
# |   store <4 x bfloat> %11, ptr %tmp4, align 8
# |   %12 = load <4 x bfloat>, ptr %tmp4, align 8
# |   store <4 x bfloat> %12, ptr %__ret_322, align 8
# |   %13 = load <4 x bfloat>, ptr %__ret_322, align 8
# |   store <4 x bfloat> %13, ptr %tmp5, align 8
# |   %14 = load <4 x bfloat>, ptr %tmp5, align 8
# |   ret <4 x bfloat> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vcopy_lane_bf16_v2(<4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   %b.addr = alloca <4 x bfloat>, align 8
# |   %__ret_322 = alloca <4 x bfloat>, align 8
# |   %__s0_322 = alloca <4 x bfloat>, align 8
# |   %__s2_322 = alloca <4 x bfloat>, align 8
# |   %__ret = alloca <4 x bfloat>, align 8
# |   %__s0 = alloca bfloat, align 2
# |   %__ret1 = alloca bfloat, align 2
# |   %__s02 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca bfloat, align 2
# |   %tmp = alloca bfloat, align 2
# |   %__s1 = alloca <4 x bfloat>, align 8
# |   %ref.tmp3 = alloca <4 x bfloat>, align 8
# |   %tmp4 = alloca <4 x bfloat>, align 8
# |   %tmp5 = alloca <4 x bfloat>, align 8
# |   store <4 x bfloat> %a, ptr %a.addr, align 8
# |   store <4 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <4 x bfloat>, ptr %a.addr, align 8
# |   store <4 x bfloat> %0, ptr %__s0_322, align 8
# |   %1 = load <4 x bfloat>, ptr %b.addr, align 8
# |   store <4 x bfloat> %1, ptr %__s2_322, align 8
# |   %2 = load <4 x bfloat>, ptr %__s2_322, align 8
# |   store <4 x bfloat> %2, ptr %__s02, align 8
# |   %3 = load <4 x bfloat>, ptr %__s02, align 8
# |   %vget_lane = extractelement <4 x bfloat> %3, i32 0
# |   store bfloat %vget_lane, ptr %ref.tmp, align 2
# |   %4 = load bfloat, ptr %ref.tmp, align 2
# |   store bfloat %4, ptr %__ret1, align 2
# |   %5 = load bfloat, ptr %__ret1, align 2
# |   store bfloat %5, ptr %tmp, align 2
# |   %6 = load bfloat, ptr %tmp, align 2
# |   store bfloat %6, ptr %__s0, align 2
# |   %7 = load <4 x bfloat>, ptr %__s0_322, align 8
# |   store <4 x bfloat> %7, ptr %__s1, align 8
# |   %8 = load bfloat, ptr %__s0, align 2
# |   %9 = load <4 x bfloat>, ptr %__s1, align 8
# |   %vset_lane = insertelement <4 x bfloat> %9, bfloat %8, i32 2
# |   store <4 x bfloat> %vset_lane, ptr %ref.tmp3, align 8
# |   %10 = load <4 x bfloat>, ptr %ref.tmp3, align 8
# |   store <4 x bfloat> %10, ptr %__ret, align 8
# |   %11 = load <4 x bfloat>, ptr %__ret, align 8
# |   store <4 x bfloat> %11, ptr %tmp4, align 8
# |   %12 = load <4 x bfloat>, ptr %tmp4, align 8
# |   store <4 x bfloat> %12, ptr %__ret_322, align 8
# |   %13 = load <4 x bfloat>, ptr %__ret_322, align 8
# |   store <4 x bfloat> %13, ptr %tmp5, align 8
# |   %14 = load <4 x bfloat>, ptr %tmp5, align 8
# |   ret <4 x bfloat> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcopyq_lane_bf16_v1(<8 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x bfloat>, align 16
# |   %b.addr = alloca <4 x bfloat>, align 8
# |   %__ret_298 = alloca <8 x bfloat>, align 16
# |   %__s0_298 = alloca <8 x bfloat>, align 16
# |   %__s2_298 = alloca <4 x bfloat>, align 8
# |   %__ret = alloca <8 x bfloat>, align 16
# |   %__s0 = alloca bfloat, align 2
# |   %__ret1 = alloca bfloat, align 2
# |   %__s02 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca bfloat, align 2
# |   %tmp = alloca bfloat, align 2
# |   %__s1 = alloca <8 x bfloat>, align 16
# |   %ref.tmp3 = alloca <8 x bfloat>, align 16
# |   %tmp4 = alloca <8 x bfloat>, align 16
# |   %tmp5 = alloca <8 x bfloat>, align 16
# |   store <8 x bfloat> %a, ptr %a.addr, align 16
# |   store <4 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <8 x bfloat>, ptr %a.addr, align 16
# |   store <8 x bfloat> %0, ptr %__s0_298, align 16
# |   %1 = load <4 x bfloat>, ptr %b.addr, align 8
# |   store <4 x bfloat> %1, ptr %__s2_298, align 8
# |   %2 = load <4 x bfloat>, ptr %__s2_298, align 8
# |   store <4 x bfloat> %2, ptr %__s02, align 8
# |   %3 = load <4 x bfloat>, ptr %__s02, align 8
# |   %vget_lane = extractelement <4 x bfloat> %3, i32 2
# |   store bfloat %vget_lane, ptr %ref.tmp, align 2
# |   %4 = load bfloat, ptr %ref.tmp, align 2
# |   store bfloat %4, ptr %__ret1, align 2
# |   %5 = load bfloat, ptr %__ret1, align 2
# |   store bfloat %5, ptr %tmp, align 2
# |   %6 = load bfloat, ptr %tmp, align 2
# |   store bfloat %6, ptr %__s0, align 2
# |   %7 = load <8 x bfloat>, ptr %__s0_298, align 16
# |   store <8 x bfloat> %7, ptr %__s1, align 16
# |   %8 = load bfloat, ptr %__s0, align 2
# |   %9 = load <8 x bfloat>, ptr %__s1, align 16
# |   %vset_lane = insertelement <8 x bfloat> %9, bfloat %8, i32 0
# |   store <8 x bfloat> %vset_lane, ptr %ref.tmp3, align 16
# |   %10 = load <8 x bfloat>, ptr %ref.tmp3, align 16
# |   store <8 x bfloat> %10, ptr %__ret, align 16
# |   %11 = load <8 x bfloat>, ptr %__ret, align 16
# |   store <8 x bfloat> %11, ptr %tmp4, align 16
# |   %12 = load <8 x bfloat>, ptr %tmp4, align 16
# |   store <8 x bfloat> %12, ptr %__ret_298, align 16
# |   %13 = load <8 x bfloat>, ptr %__ret_298, align 16
# |   store <8 x bfloat> %13, ptr %tmp5, align 16
# |   %14 = load <8 x bfloat>, ptr %tmp5, align 16
# |   ret <8 x bfloat> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcopyq_lane_bf16_v2(<8 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x bfloat>, align 16
# |   %b.addr = alloca <4 x bfloat>, align 8
# |   %__ret_298 = alloca <8 x bfloat>, align 16
# |   %__s0_298 = alloca <8 x bfloat>, align 16
# |   %__s2_298 = alloca <4 x bfloat>, align 8
# |   %__ret = alloca <8 x bfloat>, align 16
# |   %__s0 = alloca bfloat, align 2
# |   %__ret1 = alloca bfloat, align 2
# |   %__s02 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca bfloat, align 2
# |   %tmp = alloca bfloat, align 2
# |   %__s1 = alloca <8 x bfloat>, align 16
# |   %ref.tmp3 = alloca <8 x bfloat>, align 16
# |   %tmp4 = alloca <8 x bfloat>, align 16
# |   %tmp5 = alloca <8 x bfloat>, align 16
# |   store <8 x bfloat> %a, ptr %a.addr, align 16
# |   store <4 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <8 x bfloat>, ptr %a.addr, align 16
# |   store <8 x bfloat> %0, ptr %__s0_298, align 16
# |   %1 = load <4 x bfloat>, ptr %b.addr, align 8
# |   store <4 x bfloat> %1, ptr %__s2_298, align 8
# |   %2 = load <4 x bfloat>, ptr %__s2_298, align 8
# |   store <4 x bfloat> %2, ptr %__s02, align 8
# |   %3 = load <4 x bfloat>, ptr %__s02, align 8
# |   %vget_lane = extractelement <4 x bfloat> %3, i32 0
# |   store bfloat %vget_lane, ptr %ref.tmp, align 2
# |   %4 = load bfloat, ptr %ref.tmp, align 2
# |   store bfloat %4, ptr %__ret1, align 2
# |   %5 = load bfloat, ptr %__ret1, align 2
# |   store bfloat %5, ptr %tmp, align 2
# |   %6 = load bfloat, ptr %tmp, align 2
# |   store bfloat %6, ptr %__s0, align 2
# |   %7 = load <8 x bfloat>, ptr %__s0_298, align 16
# |   store <8 x bfloat> %7, ptr %__s1, align 16
# |   %8 = load bfloat, ptr %__s0, align 2
# |   %9 = load <8 x bfloat>, ptr %__s1, align 16
# |   %vset_lane = insertelement <8 x bfloat> %9, bfloat %8, i32 6
# |   store <8 x bfloat> %vset_lane, ptr %ref.tmp3, align 16
# |   %10 = load <8 x bfloat>, ptr %ref.tmp3, align 16
# |   store <8 x bfloat> %10, ptr %__ret, align 16
# |   %11 = load <8 x bfloat>, ptr %__ret, align 16
# |   store <8 x bfloat> %11, ptr %tmp4, align 16
# |   %12 = load <8 x bfloat>, ptr %tmp4, align 16
# |   store <8 x bfloat> %12, ptr %__ret_298, align 16
# |   %13 = load <8 x bfloat>, ptr %__ret_298, align 16
# |   store <8 x bfloat> %13, ptr %tmp5, align 16
# |   %14 = load <8 x bfloat>, ptr %tmp5, align 16
# |   ret <8 x bfloat> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vcopy_laneq_bf16_v1(<4 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   %b.addr = alloca <8 x bfloat>, align 16
# |   %__ret_374 = alloca <4 x bfloat>, align 8
# |   %__s0_374 = alloca <4 x bfloat>, align 8
# |   %__s2_374 = alloca <8 x bfloat>, align 16
# |   %__ret = alloca <4 x bfloat>, align 8
# |   %__s0 = alloca bfloat, align 2
# |   %__ret1 = alloca bfloat, align 2
# |   %__s02 = alloca <8 x bfloat>, align 16
# |   %ref.tmp = alloca bfloat, align 2
# |   %tmp = alloca bfloat, align 2
# |   %__s1 = alloca <4 x bfloat>, align 8
# |   %ref.tmp3 = alloca <4 x bfloat>, align 8
# |   %tmp4 = alloca <4 x bfloat>, align 8
# |   %tmp5 = alloca <4 x bfloat>, align 8
# |   store <4 x bfloat> %a, ptr %a.addr, align 8
# |   store <8 x bfloat> %b, ptr %b.add
# | ...
# `---data was truncated (10240/18871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a012f10eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a012f0de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a012f1162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce1e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce1e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce1e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce1e91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a012ea6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a012ea6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a012e8b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a012b3ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a012b3ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fce1e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce1e91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce1e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a012b3aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c (1853 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_f32mf2x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_f32m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_i32mf2x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_i32m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_u32mf2x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_u32m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_i32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_i32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_u32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8
# | ...
# `---data was truncated (10240/12059) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557cb2184eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557cb2181e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557cb218562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f46a1449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f46a14a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f46a1449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f46a1431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557cb211abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557cb211aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557cb20ff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557cb1daee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557cb1daeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f46a1432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f46a14330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f46a14330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557cb1daea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c (1854 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrdiv_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrdiv_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfrdiv.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrdiv.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrdiv_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfrdiv.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrdiv.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrdiv_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfrdiv.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrdiv.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrdiv_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfrdiv.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrdiv.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrdiv_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfrdiv.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrdiv.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrdiv_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrdiv_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfrdiv.nxv2f32.f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrdiv.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrdiv_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = all
# | ...
# `---data was truncated (10240/147390) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056101927deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056101927ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056101927e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6c5d705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6c5d75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6c5d705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6c5d6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561019213bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561019213a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005610191f88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561018ea7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561018ea7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6c5d6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6c5d6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6c5d6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561018ea7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c (1855 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmacc_vv_i16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmacc_vx_i16mf4(<vscale x 1 x i16> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmacc_vv_i16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmacc_vx_i16mf2(<vscale x 2 x i16> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmacc_vv_i16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmacc_vx_i16m1(<vscale x 4 x i16> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmacc_vv_i16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmacc_vx_i16m2(<vscale x 8 x i16> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmacc_vv_i16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale
# | ...
# `---data was truncated (10240/79489) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cb4d0aeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cb4d0abe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cb4d0af62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f08d5933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f08d598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f08d5933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f08d591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb4d044bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cb4d044a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cb4d0298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cb4ccd8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cb4ccd8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f08d591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f08d591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f08d591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb4ccd8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c (1856 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005640a0b56eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005640a0b53e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005640a0b5762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f365281bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f36528725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f365281ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3652803507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005640a0aecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005640a0aeca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005640a0ad18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005640a0780e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005640a0780b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3652804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f36528050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f36528050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005640a0780a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c (1857 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_i8mf8x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8ff_v_i8mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8ff_v_i8mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8ff_v_i8m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_u8mf8x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8ff_v_u8mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8ff_v_u8mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8ff_v_u8m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %m
# | ...
# `---data was truncated (10240/22258) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559e5a71beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559e5a718e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559e5a71c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f16de933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f16de98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f16de933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f16de91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e5a6b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559e5a6b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559e5a6968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559e5a345e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559e5a345b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f16de91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f16de91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f16de91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e5a345a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c (1858 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmul_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmul_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmul_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmul_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmul_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmul_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmul_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmul_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.r
# | ...
# `---data was truncated (10240/65582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556f1d1cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556f1d1c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556f1d1cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f92e8b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f92e8b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f92e8b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f92e8b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556f1d161bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556f1d161a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556f1d1468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556f1cdf5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556f1cdf5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f92e8b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f92e8b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f92e8b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556f1cdf5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c (1859 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dotu_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dotu_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dotu_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dotu_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dotu_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dotu_vv_u64m1(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dotu_vv_u64m2(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dotu_vv_u64m4(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv
# | ...
# `---data was truncated (10240/25519) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bc58682eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bc5867fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bc5868362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2396733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f239678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2396733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f239671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bc58618bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bc58618a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bc585fd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bc582ace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bc582acb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f239671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f239671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f239671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bc582aca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vhaddq.c (1860 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vhaddq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhaddq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vhadd.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vhadd.v16i8(<16 x i8>, <16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhaddq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vhadd.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vhadd.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhaddq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vhadd.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vhadd.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhaddq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.hadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.hadd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhaddq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.hadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.hadd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhaddq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.hadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.hadd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhaddq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.hadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhaddq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.hadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhaddq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.hadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhaddq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = call <16 x i8> @llvm.arm.mve.vhadd.v16i8(<16 x i8> %0, <16 x i8> %.splat, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhaddq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = call <8 x i16> @llvm.arm.mve.vhadd.v8i16(<8 x i16> %0, <8 x i16> %.splat, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhaddq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> 
# | ...
# `---data was truncated (10240/16951) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aa5baa2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aa5ba9fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aa5baa362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd966333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd96638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd966333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd96631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa5ba38bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aa5ba38a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aa5ba1d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aa5b6cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aa5b6ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd96631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd96631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd96631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa5b6cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c (1861 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vbrev8_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vbrev8_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vbrev8_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vbrev8_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vbrev8_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vbrev8_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vbrev8_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vbrev8_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vbrev8_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vbrev8_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vbrev8_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vbrev8.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vbrev8.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vbrev8_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vbrev8.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vbrev8.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vbrev8_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vbrev8.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i
# | ...
# `---data was truncated (10240/40929) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005584f0825eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005584f0822e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005584f082662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb571d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb571d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb571d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb571d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005584f07bbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005584f07bba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005584f07a08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005584f044fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005584f044fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb571d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb571d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb571d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005584f044fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c (1862 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_v
# | ...
# `---data was truncated (10240/228865) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bba7106eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bba7103e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bba710762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3621f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3621f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3621f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3621eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bba709cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bba709ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bba70818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bba6d30e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bba6d30b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3621eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3621eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3621eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bba6d30a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c (1863 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c9ff14eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563c9ff11e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563c9ff1562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcaf2449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcaf24a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcaf2449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcaf2431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c9feaabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563c9feaaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563c9fe8f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563c9fb3ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563c9fb3eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcaf2432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcaf24330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcaf24330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c9fb3ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c (1864 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsltu_vv_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsltu_vx_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsltu_vv_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsltu_vx_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsltu_vv_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsltu_vx_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsltu_vv_u8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8
# | ...
# `---data was truncated (10240/63713) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e234cc8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e234cc5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e234cc962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff108049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff1080a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff108049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff108031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e234c5ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e234c5ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e234c438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e2348f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e2348f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff108032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff1080330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff1080330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2348f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c (1865 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_f64m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_f64m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_f64m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_i64m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_i64m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_i64m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_u64m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_u64m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_u64m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_f64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: wri
# | ...
# `---data was truncated (10240/20523) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056003acf3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056003acf0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056003acf462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff544e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff544ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff544e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff544e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056003ac89bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056003ac89a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056003ac6e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056003a91de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056003a91db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff544e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff544e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff544e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056003a91da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c (1866 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwi
# | ...
# `---data was truncated (10240/44369) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005562e2744eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005562e2741e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005562e274562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5f08b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5f08b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5f08b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5f08b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005562e26dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005562e26daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005562e26bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005562e236ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005562e236eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5f08b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5f08b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5f08b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005562e236ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c (1867 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmv_v_f_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmv.v.f.nxv1bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmv.v.f.nxv1bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmv_v_f_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmv.v.f.nxv2bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmv.v.f.nxv2bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmv_v_f_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmv.v.f.nxv4bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmv.v.f.nxv4bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmv_v_f_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmv.v.f.nxv8bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmv.v.f.nxv8bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmv_v_f_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfmv.v.f.nxv16bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmv.v.f.nxv16bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfmv_v_f_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfmv.v.f.nxv32bf16.i64(<vscale x 32 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfmv.v.f.nxv32bf16.i64(<vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmv_s_f_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmv.s.f.nxv1bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmv.s.f.nxv1bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmv_s_f_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmv.s.f.nxv2bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmv.s.f.nxv2bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmv_s_f_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmv.s.f.nxv4bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmv.s.f.nxv4bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmv_s_f_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmv.s.f.nxv8bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmv.s.f.nxv8bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmv_s_f_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %ma
# | ...
# `---data was truncated (10240/12656) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c300e0deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c300e0ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c300e0e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007febcef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007febcef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007febcef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007febcef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c300da3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c300da3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c300d888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c300a37e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c300a37b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007febcef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007febcef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007febcef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c300a37a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c (1868 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vslide1down_vx_i8mf8(<vscale x 1 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vslide1down_vx_i8mf4(<vscale x 2 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vslide1down_vx_i8mf2(<vscale x 4 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vslide1down_vx_i8m1(<vscale x 8 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vslide1down_vx_i8m2(<vscale x 16 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vslide1down_vx_i8m4(<vscale x 32 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vslide1down_vx_i8m8(<vscale x 64 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vslide1down_vx_i16mf4(<vscale x 1 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vslide1down_vx_i16mf2(<vscale x 2 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vslide1down.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vslide1down.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vslide1down_vx_i16m1(<vscale x 4 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vslide1down.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vslide1down.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vslide1down_vx_i16m2(<vscale x 8 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1
# | ...
# `---data was truncated (10240/87183) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056353df5feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056353df5ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056353df6062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdac2b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdac2b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdac2b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdac2b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056353def5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056353def5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056353deda8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056353db89e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056353db89b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdac2b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdac2b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdac2b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056353db89a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c (1869 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f16m1x5(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f32m1x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f64m1x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei32_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a4e9e4aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a4e9e47e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a4e9e4b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb1e4f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb1e4f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb1e4f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb1e4f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a4e9de0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a4e9de0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a4e9dc58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a4e9a74e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a4e9a74b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb1e4f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb1e4f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb1e4f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a4e9a74a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c (1870 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_f32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_f32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_f32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_i32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_i32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_i32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_u32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_u32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_u32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.v
# | ...
# `---data was truncated (10240/23413) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558b776a8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558b776a5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558b776a962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5635905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f563595c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5635905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f56358ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558b7763ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558b7763ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558b776238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558b772d2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558b772d2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f56358eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56358ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56358ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558b772d2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c (1871 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_f16mf4x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_f16mf2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_f16m1x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_f16m2x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_i16mf4x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_i16mf2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_i16m1x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_i16m2x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_u16mf4x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_u16mf2x4_m(<vscale x 2 x i1> %mask, ptr nound
# | ...
# `---data was truncated (10240/13515) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563a79e3aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563a79e37e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563a79e3b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9802933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f980298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9802933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f980291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a79dd0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563a79dd0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563a79db58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563a79a64e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563a79a64b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f980291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f980291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f980291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a79a64a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c (1872 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555736b80eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555736b7de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555736b8162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f18b4249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f18b42a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f18b4249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f18b4231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555736b16bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555736b16a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555736afb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005557367aae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005557367aab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f18b4232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f18b42330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f18b42330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005557367aaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c (1873 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vunzipe_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 2 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vunzipe_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 4 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vunzipe_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 8 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vunzipe_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 16 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vunzipe_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 32 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005652e85f5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005652e85f2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005652e85f662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa71fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa71fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa71fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa71fe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005652e858bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005652e858ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005652e85708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005652e821fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005652e821fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa71fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa71fe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa71fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005652e821fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c (1874 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8ff_v_i8mf8x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv1i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv1i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8ff_v_i8mf4x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8ff_v_i8mf2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8ff_v_i8m1x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8ff_v_i8m2x3_m(<vscale x 16 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8ff_v_u8mf8x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv1i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8ff_v_u8mf4x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %ba
# | ...
# `---data was truncated (10240/15594) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563bf8aefeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563bf8aece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563bf8af062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f49b9449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f49b94a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f49b9449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f49b9431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563bf8a85bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563bf8a85a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563bf8a6a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563bf8719e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563bf8719b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f49b9432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f49b94330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f49b94330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563bf8719a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c (1875 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i16> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i16> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i16> %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> %2, ptr %0, <vscale x 32 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vsca
# | ...
# `---data was truncated (10240/15622) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558c9102beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558c91028e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558c9102c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f21f3d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f21f3d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f21f3d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f21f3d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c90fc1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558c90fc1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558c90fa68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558c90c55e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558c90c55b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f21f3d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f21f3d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f21f3d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c90c55a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c (1876 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4e
# | ...
# `---data was truncated (10240/216250) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005653135f0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005653135ede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005653135f162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8596c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8596ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8596c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8596c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565313586bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565313586a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056531356b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056531321ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056531321ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8596c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8596c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8596c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056531321aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c (1877 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmadc_vvm_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmadc_vxm_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmadc_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmadc_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmadc_vvm_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmadc_vxm_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmadc_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmadc_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmadc_vvm_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmadc_vxm_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, al
# | ...
# `---data was truncated (10240/169925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005590fef61eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005590fef5ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005590fef6262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f07c6733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f07c678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f07c6733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f07c671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005590feef7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005590feef7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005590feedc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005590feb8be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005590feb8bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f07c671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f07c671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f07c671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005590feb8ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c (1878 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_f16mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_f16mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_f16m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_i16mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_i16mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_i16m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_u16mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_u16mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_u16m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, pt
# | ...
# `---data was truncated (10240/24016) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a982f5aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a982f57e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a982f5b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b0cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b0cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b0cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b0cc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a982ef0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a982ef0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a982ed58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a982b84e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a982b84b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2b0cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b0cc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b0cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a982b84a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c (1879 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh    -target-feature +xsfvfexpa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexpa_v_f16mf4(<vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexpa_v_f16mf2(<vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexpa_v_f16m1(<vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexpa_v_f16m2(<vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexpa_v_f16m4(<vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vfexpa_v_f16m8(<vscale x 32 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexpa_v_f32mf2(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexpa_v_f32m1(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexpa_v_f32m2(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexpa_v_f32m4(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfexpa_v_f32m8(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.sf.vfexpa.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfexpa.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexpa_v_f16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.sf.vfexpa.mask.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexpa.mask.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vsc
# | ...
# `---data was truncated (10240/21473) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a4edf5deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a4edf5ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a4edf5e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd106649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd1066a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd106649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd106631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a4edef3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a4edef3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a4eded88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a4edb87e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a4edb87b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd106632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd1066330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd1066330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a4edb87a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c (1880 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vluxei16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> poison, ptr %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca 
# | ...
# `---data was truncated (10240/14311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056359b943eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056359b940e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056359b94462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f67ddb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f67ddb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f67ddb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f67ddb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056359b8d9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056359b8d9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056359b8be8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056359b56de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056359b56db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f67ddb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67ddb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67ddb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056359b56da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c (1881 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16mf4_f16m1(<vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16mf2_f16m1(<vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m1_f16m1(<vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m2_f16m1(<vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m4_f16m1(<vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m8_f16m1(<vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32mf2_f32m1(<vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32m1_f32m1(<vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32m2_f32m1(<vscale x 4 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_loc
# | ...
# `---data was truncated (10240/37556) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005617051b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005617051b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005617051b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7ee2b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7ee2b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7ee2b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7ee2aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561705149bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561705149a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056170512e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561704ddde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561704dddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7ee2aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7ee2aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7ee2aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561704ddda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c (1882 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_i64m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_u64m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c956606eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c956603e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c95660762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f11dbb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f11dbb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f11dbb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f11dbb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c95659cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c95659ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c9565818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c956230e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c956230b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f11dbb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f11dbb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f11dbb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c956230a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c (1883 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_i64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_u64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_f64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_i64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_u64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vsca
# | ...
# `---data was truncated (10240/20895) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b53eb17eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b53eb14e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b53eb1862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcb0a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcb0a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcb0a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcb0a231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b53eaadbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b53eaada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b53ea928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b53e741e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b53e741b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcb0a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcb0a2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcb0a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b53e741a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c (1884 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_f64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_f64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_i64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_i64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_u64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_u64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs
# | ...
# `---data was truncated (10240/15978) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056516f2b2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056516f2afe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056516f2b362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f18cc133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f18cc18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f18cc133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f18cc11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056516f248bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056516f248a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056516f22d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056516eedce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056516eedcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f18cc11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f18cc11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f18cc11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056516eedca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c (1885 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgt_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgt_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgt_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgt_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgt_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgt_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgt_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgt_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgt_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgt_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsgt_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsgt.nxv32i8.nxv32i8.i64(<vscale x 32 x 
# | ...
# `---data was truncated (10240/95089) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ad931c9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ad931c6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ad931ca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f14a6c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f14a6ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f14a6c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f14a6c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad9315fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ad9315fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ad931448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ad92df3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ad92df3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f14a6c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f14a6c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f14a6c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad92df3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c (1886 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_bf16m1x4_tum(<v
# | ...
# `---data was truncated (10240/25687) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f391959eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f391956e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f39195a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5147733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f514778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5147733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f514771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f3918efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f3918efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f3918d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f391583e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f391583b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f514771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f514771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f514771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f391583a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c (1887 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8ff_v_i8mf8x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv1i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv1i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8ff_v_i8mf4x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8ff_v_i8mf2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8ff_v_i8m1x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8ff_v_i8m2x4_m(<vscale x 16 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8ff_v_u8mf8x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv1i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8ff_v_u8mf4x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %ba
# | ...
# `---data was truncated (10240/15594) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056218f3a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056218f3a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056218f3a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1b2f01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1b2f0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1b2f01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1b2f003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056218f33dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056218f33da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056218f3228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056218efd1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056218efd1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1b2f004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1b2f0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1b2f0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056218efd1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c (1888 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561e8dbc9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561e8dbc6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561e8dbca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1297449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f12974a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1297449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1297431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561e8db5fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561e8db5fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561e8db448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561e8d7f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561e8d7f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1297432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f12974330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f12974330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561e8d7f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c (1889 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei8_v_f16mf4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei8_v_f16mf2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei8_v_f16m1(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei8_v_f16m2(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei8_v_f16m4(ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vloxei8_v_f16m8(ptr noundef %base, <vscale x 32 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> poison, ptr %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei8_v_f32mf2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei8_v_f32m1(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei8_v_f32m2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei8_v_f32m4(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i8.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i8.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vsc
# | ...
# `---data was truncated (10240/121179) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558fe0697eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558fe0694e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558fe069862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8145305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f814535c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8145305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f81452ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558fe062dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558fe062da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558fe06128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558fe02c1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558fe02c1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f81452eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f81452ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f81452ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558fe02c1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c (1890 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_i8mf8(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_i8mf4(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_i8mf2(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_i8m1(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_i8m2(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vncvt_x_x_w_i8m4(<vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8> poison, <vscale x 32 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8>, <vscale x 32 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_u8mf8(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_u8mf4(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_u8mf2(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_u8m1(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_u8m2(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vncvt_x_x_w_u8m4(<vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8> poison, <vscale x 32 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vncvt_x_x_w_i16mf4(<vscale x 1 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i64.i64(<vscale x 1 x i16> poison, <vscale x 1 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i64.i64(<vscale x 1 x i16>, <vscale x 1 x i32>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vncvt_x_x_w_i16mf2(<vscale x 2 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vnsrl.nxv2i16.nxv2i32.i64.i64(<vscale x 2 x i16> poison, <v
# | ...
# `---data was truncated (10240/50890) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556a82908eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556a82905e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556a8290962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0d69e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0d69ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0d69e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0d69e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556a8289ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556a8289ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556a828838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556a82532e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556a82532b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0d69e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0d69e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0d69e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556a82532a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c (1891 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4asu_vv_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4asu_vv_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 
# | ...
# `---data was truncated (10240/26572) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558727378eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558727375e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055872737962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d48f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d48f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d48f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d48f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055872730ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055872730ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005587272f38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558726fa2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558726fa2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8d48f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d48f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d48f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558726fa2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c (1892 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4(<vscale x 16 x half> %vd, <vscale x 16 x half> %v
# | ...
# `---data was truncated (10240/148843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558153915eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558153912e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055815391662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b4bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b4bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b4bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b4bd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005581538abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005581538aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005581538908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055815353fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055815353fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5b4bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b4bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b4bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055815353fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c (1893 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_i32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_i32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_u32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_u32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_f32mf2x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_f32m1x8_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret ta
# | ...
# `---data was truncated (10240/32031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563297b52eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563297b4fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563297b5362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5a95849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5a958a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5a95849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5a95831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563297ae8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563297ae8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563297acd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056329777ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056329777cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5a95832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5a958330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5a958330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056329777ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c (1894 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f16m1x4(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_f16m2x4(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f32m1x4(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_f32m2x4(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f64m1x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/82983) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560e079abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560e079a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560e079ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fafb7b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fafb7b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fafb7b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fafb7aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e07941bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560e07941a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560e079268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560e075d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560e075d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fafb7aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fafb7aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fafb7aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e075d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c (1895 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vgmul_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vgmul_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vgmul_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vgmul_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vgmul_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560495a5beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560495a58e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560495a5c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d0a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d0a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d0a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d0a11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005604959f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005604959f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005604959d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560495685e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560495685b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1d0a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d0a11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d0a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560495685a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c (1896 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f16m1x8(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f32m1x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f64m1x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/69980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559342115eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559342112e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055934211662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fceb5733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fceb578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fceb5733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fceb571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005593420abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005593420aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005593420908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559341d3fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559341d3fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fceb571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fceb571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fceb571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559341d3fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c (1897 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_f32m2x3_tu(target("riscv.vector.tuple", <vs
# | ...
# `---data was truncated (10240/227771) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cfac5c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cfac5bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cfac5c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c1c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c1c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c1c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c1c31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cfac558bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cfac558a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cfac53d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cfac1ece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cfac1ecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8c1c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c1c31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c1c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cfac1eca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c (1898 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4(<vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_f_f_w_f16mf2(<vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfncvt_f_f_w_f16m1(<vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfncvt_f_f_w_f16m2(<vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfncvt_f_f_w_f16m4(<vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfncvt_f_f_w_f32mf2(<vscale x 1 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> poison, <vscale x 1 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfncvt_f_f_w_f32m1(<vscale x 2 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> poison, <vscale x 2 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float>, <vscale x 2 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfncvt_f_f_w_f32m2(<vscale x 4 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> poison, <vscale x 4 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float>, <vscale x 4 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfncvt_f_f_w_f32m4(<vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> poison, <vscale x 8 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float>, <vscale x 8 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_f_f_w_f16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg)
# | ...
# `---data was truncated (10240/32178) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b2ee46eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b2ee46be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b2ee46f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe789849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe7898a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe789849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe789831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b2ee404bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b2ee404a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b2ee3e98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b2ee098e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b2ee098b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe789832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe7898330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe7898330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b2ee098a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c (1899 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3e
# | ...
# `---data was truncated (10240/228857) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d3a73c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d3a73bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d3a73c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe417733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe41778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe417733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe41771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d3a7358bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d3a7358a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d3a733d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d3a6fece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d3a6fecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe41771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe41771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe41771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d3a6feca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c (1900 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmv_v_f_f16mf4(half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load half, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16.i64(<vscale x 1 x half> poison, half %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmv_v_f_f16mf2(half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load half, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16.i64(<vscale x 2 x half> poison, half %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmv_v_f_f16m1(half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load half, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16.i64(<vscale x 4 x half> poison, half %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmv_v_f_f16m2(half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load half, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16.i64(<vscale x 8 x half> poison, half %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmv_v_f_f16m4(half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load half, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16.i64(<vscale x 16 x half> poison, half %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfmv_v_f_f16m8(half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load half, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16.i64(<vscale x 32 x half> poison, half %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16.i64(<vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfmv_v_f_f32mf2(float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load float, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.i64(<vscale x 1 x float> poison, float %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.i64(<vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfmv_v_f_f32m1(float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load float, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.i64(<vscale x 2 x float> poison, float %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.i64(<vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfmv_v_f_f32m2(float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load float, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32.i64(<vscale x 4 x float> poison, float %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32.i64(<vscale x 4 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfmv_v_f_f32m4(float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load float, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32.i64(<vscale x 8 x float> poison, float %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32.i64(<vscale x 8 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfmv_v_f_f32m8(float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load float, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfmv.v.f.nxv16f32.i64(<vscale x 16 x float> poison, float %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfmv.v.f.nxv16f32.i64(<vscale x 16 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfmv_v_f_f64m1(double noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca double, align 8
# |   %vl.addr = alloca i64, align 8
# |   store double %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load double, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64.i64(<vscale x 1 x double> poison, double %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64.i64(<vscale x 1 x double>, double, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vfmv_v_f_f64m2(double noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca double, align 8
# |   %vl.addr = alloca i64, align 8
# |   store double %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load double, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.vfmv.v.f.nxv2f64.i64(<vscale x 2 x double> poison, double %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vfmv.v.f.nxv2f64.i64(<vscale x 2 x double>, double, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vfmv_v_f_f64m4(double noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca double, align 8
# |   %vl.addr = alloca i64, align 8
# |   store double %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load double, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.vfmv.v.f.nxv4f64.i64(<vscale x 4 x double> poison, double %0, i64 %1)
# |   
# | ...
# `---data was truncated (10240/30849) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556ac384ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556ac3849e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556ac384d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7434e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7434ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7434e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7434e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ac37e2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556ac37e2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556ac37c78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556ac3476e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556ac3476b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7434e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7434e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7434e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556ac3476a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c (1901 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulu_vv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulu_vx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulu_vv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulu_vx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulu_vv_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulu_vx_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulu_vv_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulu_vx_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulu_vv_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1
# | ...
# `---data was truncated (10240/154215) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005566e881feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005566e881ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005566e882062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7ba1305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7ba135c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7ba1305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7ba12ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005566e87b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005566e87b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005566e879a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005566e8449e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005566e8449b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7ba12eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7ba12ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7ba12ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005566e8449a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c (1902 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e37cc23eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e37cc20e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e37cc2462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc39db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc39db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc39db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc39db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e37cbb9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e37cbb9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e37cb9e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e37c84de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e37c84db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc39db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc39db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc39db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e37c84da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqdmlad.c (1903 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqdmlad.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmladhq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 0, i32 0, i32 0)
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8>, <16 x i8>, <16 x i8>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmladhq_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %1 = load <8 x i16>, ptr %a.addr, align 8
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2, i32 0, i32 0, i32 0)
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16>, <8 x i16>, <8 x i16>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmladhq_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x i32>, ptr %a.addr, align 8
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 0, i32 0, i32 0)
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32>, <4 x i32>, <4 x i32>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmladhxq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 1, i32 0, i32 0)
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmladhxq_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %1 = load <8 x i16>, ptr %a.addr, align 8
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2, i32 1, i32 0, i32 0)
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmladhxq_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x i32>, ptr %a.addr, align 8
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 1, i32 0, i32 0)
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmlsdhq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 0, i32 0, i32 1)
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmlsdhq_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %1 = load <8 x i16>, ptr %a.addr, align 8
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2, i32 0, i32 0, i32 1)
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmlsdhq_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x i32>, ptr %a.addr, align 8
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 0, i32 0, i32 1)
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmlsdhxq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 1, i32 0, i32 1)
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmlsdhxq_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %1 = load <8 x i16>, ptr %a.addr, align 8
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2, i32 1, i32 0, i32 1)
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmlsdhxq_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x i32>, ptr %a.addr, align 8
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 1, i32 0, i32 1)
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmladhq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 0, i32 1, i32 0)
# |   r
# | ...
# `---data was truncated (10240/43005) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056069e948eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056069e945e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056069e94962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa3ff733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa3ff78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa3ff733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa3ff71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056069e8debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056069e8dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056069e8c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056069e572e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056069e572b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa3ff71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa3ff71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa3ff71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056069e572a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c (1904 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f16m1x4(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_f16m2x4(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f32m1x4(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_f32m2x4(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f64m1x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), p
# | ...
# `---data was truncated (10240/87316) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f1e8971eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f1e896ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f1e897262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0215333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f021538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0215333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f021531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f1e8907bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f1e8907a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f1e88ec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f1e859be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f1e859bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f021531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f021531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f021531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f1e859ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c (1905 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vcpop_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vcpop_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vcpopv.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vcpopv.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vcpop_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vcpopv.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vcpopv.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vcpop_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vcpopv.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vcpopv.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vcpop_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vcpopv.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vcpopv.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vcpop_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vcpopv.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vcpopv.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vcpop_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vcpopv.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vcpopv.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vcpop_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vcpopv.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vcpopv.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vcpop_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vcpopv.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vcpopv.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vcpop_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vcpopv.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vcpopv.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_ran
# | ...
# `---data was truncated (10240/95347) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555de8842eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555de883fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555de884362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff00a21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff00a2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff00a21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff00a203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555de87d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555de87d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555de87bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555de846ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555de846cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff00a204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff00a2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff00a2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555de846ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c (1906 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabdau_vv_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabdau_vx_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabdau_vv_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabdau_vx_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabdau_vv_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabdau_vx_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabdau_vv_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabdau_vx_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwabdau_vv_u16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x 
# | ...
# `---data was truncated (10240/58468) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005587794e1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005587794dee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005587794e262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3fc5649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3fc56a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3fc5649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3fc5631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558779477bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558779477a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055877945c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055877910be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055877910bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3fc5632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3fc56330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3fc56330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055877910ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c (1907 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055776f5c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055776f5c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055776f5c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9c92d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9c92d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9c92d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9c92d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055776f55abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055776f55aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055776f53f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055776f1eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055776f1eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9c92d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9c92d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9c92d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055776f1eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c (1908 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4a_vv_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4a_vv_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 
# | ...
# `---data was truncated (10240/14429) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e6aadc1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e6aadbee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e6aadc262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e2a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e2a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e2a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e2a631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e6aad57bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e6aad57a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e6aad3c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e6aa9ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e6aa9ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1e2a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e2a6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e2a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e6aa9eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c (1909 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrec7_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrec7_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrec7_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrec7_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrec7_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrec7_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrec7_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrec7_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrec7_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrec7_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, al
# | ...
# `---data was truncated (10240/128416) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558a218b9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558a218b6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558a218ba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7049b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7049b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7049b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7049b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a2184fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558a2184fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558a218348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558a214e3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558a214e3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7049b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7049b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7049b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a214e3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c (1910 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsne_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsne_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsne_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsne_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsne_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsne_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsne_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsne_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsne_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsne_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsne_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8.nxv32i8.i64(<vscale x 32 x 
# | ...
# `---data was truncated (10240/171389) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d002b2beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d002b28e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d002b2c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbc56533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbc5658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbc56533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbc5651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d002ac1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d002ac1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d002aa68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d002755e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d002755b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbc5651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbc5651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbc5651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d002755a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/thinlto-opaque-typed-mix.ll (1911 of 27911)
******************** TEST 'Clang :: CodeGen/thinlto-opaque-typed-mix.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 4
mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp
# executed command: mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp/typed.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-opaque-typed-mix.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp/typed.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-opaque-typed-mix.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp/typed.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-opaque-typed-mix.ll
# |  #0 0x000055bac425ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bac4259e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bac425d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd181333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd18138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd181333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd18131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bac41f2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bac41f2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bac41d78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bac3e86e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bac3e86b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd18131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd18131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd18131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bac3e86a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c (1912 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei8_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = loa
# | ...
# `---data was truncated (10240/14529) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e3f17d9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e3f17d6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e3f17da62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe7f5649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe7f56a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe7f5649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe7f5631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e3f176fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e3f176fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e3f17548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e3f1403e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e3f1403b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe7f5632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe7f56330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe7f56330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e3f1403a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c (1913 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_f16mf4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_f16mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_f16m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16ff_v_f16m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16ff_v_f16m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_i16mf4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_i16mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_i16m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align
# | ...
# `---data was truncated (10240/39416) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555a04966eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555a04963e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555a0496762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc32b01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc32b0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc32b01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc32b003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555a048fcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555a048fca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555a048e18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555a04590e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555a04590b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc32b004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc32b0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc32b0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555a04590a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c (1914 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsub_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsub_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsub_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsub_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsub_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsub_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsub_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsub_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# | ...
# `---data was truncated (10240/34438) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005654776b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005654776b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005654776b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd8ee933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd8ee98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd8ee933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd8ee91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056547764bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056547764ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005654776308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005654772dfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005654772dfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd8ee91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd8ee91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd8ee91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005654772dfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c (1915 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svscale_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fscale.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fscale.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svscale_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fscale.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fscale.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svscale_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fscale.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fscale.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x i64>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svscale_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fscale.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svscale_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fscale.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svscale_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.fscale.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svscale_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fscale.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svscale_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fscale.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svscale_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbo
# | ...
# `---data was truncated (10240/21216) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055f076353eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f076350e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f07635462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4552049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f45520a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4552049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4552031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f0762e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f0762e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f0762ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f075f7de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f075f7db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4552032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f45520330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f45520330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f075f7da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c (1916 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4(<vscale x 16 x half> %vd, <vsc
# | ...
# `---data was truncated (10240/149137) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555fcd8a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555fcd8a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555fcd8a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f81aab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f81aab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f81aab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f81aab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555fcd83cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555fcd83ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555fcd8218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555fcd4d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555fcd4d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f81aab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f81aab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f81aab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555fcd4d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c (1917 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_i32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_i32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_u32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_u32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_f32mf2x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_f32m1x7_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret ta
# | ...
# `---data was truncated (10240/32031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056206791aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562067917e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056206791b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd82fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd82faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd82fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd82fa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005620678b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005620678b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005620678958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562067544e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562067544b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd82fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd82fa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd82fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562067544a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c (1918 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgatherei16_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgatherei16_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgatherei16_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgatherei16_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgatherei16_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, <vscale x 16 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vrgatherei16_vv_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, <vscale x 32 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 32 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vrgatherei16_vv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, <vscale x 1 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 1 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vrgatherei16_vv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, <vscale x 2 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 2 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vrgatherei16.vv.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %
# | ...
# `---data was truncated (10240/291999) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561df53deeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561df53dbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561df53df62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb504905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb50495c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb504905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb5048ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561df5374bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561df5374a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561df53598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561df5008e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561df5008b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb5048eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb5048ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb5048ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561df5008a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c (1919 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfadd_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfadd_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfadd_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfadd_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfadd_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfadd_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfadd_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfadd_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfadd.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i
# | ...
# `---data was truncated (10240/125641) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563a88a87eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563a88a84e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563a88a8862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa706c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa706ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa706c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa706c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a88a1dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563a88a1da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563a88a028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563a886b1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563a886b1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa706c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa706c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa706c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a886b1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c (1920 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f16m1x6(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f32m1x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f64m1x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei8_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vsca
# | ...
# `---data was truncated (10240/61665) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005596d4de3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005596d4de0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005596d4de462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9740133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f974018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9740133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f974011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005596d4d79bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005596d4d79a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005596d4d5e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005596d4a0de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005596d4a0db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f974011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f974011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f974011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005596d4a0da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c (1921 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vminu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vminu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vminu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vminu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vminu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vminu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vminu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vminu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vminu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vminu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vminu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr
# | ...
# `---data was truncated (10240/97905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055981e719eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055981e716e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055981e71a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdbb0505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdbb055c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdbb0505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdbb04ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055981e6afbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055981e6afa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055981e6948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055981e343e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055981e343b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdbb04eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdbb04ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdbb04ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055981e343a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c (1922 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f16m1x4(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_f16m2x4(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f32m1x4(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_f32m2x4(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f64m1x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.
# | ...
# `---data was truncated (10240/87884) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005631616c3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005631616c0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005631616c462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe755a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe755aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe755a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe755a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563161659bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563161659a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056316163e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005631612ede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005631612edb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe755a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe755a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe755a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005631612eda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c (1923 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vset_v_bf16m1_bf16m2(<vscale x 8 x bfloat> %dest, i64 noundef %index, <vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 0)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vset_v_bf16m1_bf16m4(<vscale x 16 x bfloat> %dest, i64 noundef %index, <vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 0)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vset_v_bf16m2_bf16m4(<vscale x 16 x bfloat> %dest, i64 noundef %index, <vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 0)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vset_v_bf16m1_bf16m8(<vscale x 32 x bfloat> %dest, i64 noundef %index, <vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 0)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vset_v_bf16m2_bf16m8(<vscale x 32 x bfloat> %dest, i64 noundef %index, <vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 0)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat>, <vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vset_v_bf16m4_bf16m8(<vscale x 32 x bfloat> %dest, i64 noundef %index, <vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv16bf16(<vscale x 32 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 0)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv16bf16(<vscale x 32 x bfloat>, <vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vset_v_bf16mf4_bf16mf4x2(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %dest, i64 noundef %index, <vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_2t.nxv1bf16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, <vscale x 1 x bfloat> %1, i32 0)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_2t.nxv1bf16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), <vscale x 1 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vset_v_bf16mf4_bf16mf4x3(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %dest, i64 noundef %index, <vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_3t.nxv1bf16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, <vscale x 1 x bfloat> %1, i32 0)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_3t.nxv1bf16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), <vscale x 1 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vset_v_bf16mf4_bf16mf4x4(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %dest, i64 noundef %index, <vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %2 = call target("riscv.vector.tuple", <vscale x
# | ...
# `---data was truncated (10240/41651) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c5c6757eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c5c6754e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c5c675862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd2fb933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd2fb98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd2fb933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd2fb91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c5c66edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c5c66eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c5c66d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c5c6381e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c5c6381b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd2fb91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd2fb91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd2fb91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c5c6381a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c (1924 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565434aa8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565434aa5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000565434aa962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7d1861bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7d186725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7d1861ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7d18603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565434a3ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565434a3ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000565434a238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005654346d2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005654346d2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7d18604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7d186050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7d186050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005654346d2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c (1925 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdm_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdm.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdm.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdm_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdm_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdm_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesdm_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdm_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdm_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind w
# | ...
# `---data was truncated (10240/20198) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555c6df93eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555c6df90e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555c6df9462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2cfb533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2cfb58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2cfb533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2cfb51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555c6df29bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555c6df29a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555c6df0e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555c6dbbde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555c6dbbdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2cfb51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2cfb51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2cfb51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555c6dbbda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c (1926 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005608c0ff8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005608c0ff5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005608c0ff962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fabe4905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fabe495c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fabe4905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fabe48ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005608c0f8ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005608c0f8ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005608c0f738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005608c0c22e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005608c0c22b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fabe48eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fabe48ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fabe48ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005608c0c22a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c (1927 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhsu_vv_i64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhsu_vx_i64m1(<vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulhsu_vv_i64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulhsu_vx_i64m2(<vscale x 2 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulhsu_vv_i64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 4 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulhsu_vx_i64m4(<vscale x 4 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulhsu_vv_i64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 8 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulhsu_vx_i64m8(<vscale x 8 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhsu_vv_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhsu_vx_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load i64, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <
# | ...
# `---data was truncated (10240/18691) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562f25489eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562f25486e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562f2548a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f569cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f569cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f569cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f569cb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562f2541fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562f2541fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562f254048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562f250b3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562f250b3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f569cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f569cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f569cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562f250b3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c (1928 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vlse32_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32.p0.i64(<vscale x 1 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vlse32_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32.p0.i64(<vscale x 2 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vlse32_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32.p0.i64(<vscale x 4 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vlse32_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32.p0.i64(<vscale x 8 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vlse32_v_f32m8_tu(<vscale x 16 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32.p0.i64(<vscale x 16 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 16 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vlse32_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.p0.i64(<vscale x 1 x i32> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vlse32_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32.p0.i64(<vscale x 2 x i32> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vlse32_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32.p0.i64(<vscale x 4 x i32> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vlse32_v_i32m4_tu(<vscale x 8 x i32> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32.p0.i64(<vscale x 8 x i32> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 
# | ...
# `---data was truncated (10240/69943) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056386cba9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056386cba6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056386cbaa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe259449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe2594a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe259449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe259431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056386cb3fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056386cb3fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056386cb248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056386c7d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056386c7d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe259432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe2594330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe2594330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056386c7d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c (1929 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d6442beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558d64428e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558d6442c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa5c2c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa5c2ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa5c2c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa5c2c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d643c1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558d643c1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558d643a68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558d64055e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558d64055b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa5c2c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa5c2c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa5c2c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d64055a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c (1930 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4(<vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2(<vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1(<vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfneg_v_bf16m2(<vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfneg_v_bf16m4(<vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfneg_v_bf16m8(<vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfneg_v_bf16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>
# | ...
# `---data was truncated (10240/13290) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564491cd2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564491ccfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564491cd362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f17849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f178a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f17849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f17831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564491c68bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564491c68a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564491c4d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005644918fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005644918fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4f17832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f178330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f178330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005644918fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c (1931 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vbrev8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vbrev8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vbrev8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vbrev8_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vbrev8_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vbrev8_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vbrev8_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vbrev8_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vbrev8_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vbrev8_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline
# | ...
# `---data was truncated (10240/95445) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ce6b194eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ce6b191e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ce6b19562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f53a7905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f53a795c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f53a7905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f53a78ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ce6b12abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ce6b12aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ce6b10f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ce6adbee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ce6adbeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f53a78eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f53a78ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f53a78ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ce6adbea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c (1932 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_tu(<vs
# | ...
# `---data was truncated (10240/295861) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f893ad0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f893acde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f893ad162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe52d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe52d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe52d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe52d831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f893a66bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f893a66a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f893a4b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f8936fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f8936fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe52d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe52d8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe52d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f8936faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c (1933 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsrl_wv_u8mf8(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsrl_wx_u8mf8(<vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsrl_wv_u8mf4(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsrl_wx_u8mf4(<vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsrl_wv_u8mf2(<vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsrl_wx_u8mf2(<vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsrl_wv_u8m1(<vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsrl_wx_u8m1(<vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsrl_wv_u8m2(<vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsrl_wx_u8m2(<vscale x 16 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8>, <vs
# | ...
# `---data was truncated (10240/68517) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b1eecabeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b1eeca8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b1eecac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcbc2849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcbc28a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcbc2849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcbc2831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b1eec41bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b1eec41a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b1eec268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b1ee8d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b1ee8d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcbc2832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcbc28330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcbc28330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b1ee8d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c (1934 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_f32mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_f32m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_i32mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_i32m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_u32mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_u32m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_i32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_i32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry
# | ...
# `---data was truncated (10240/14002) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ff30cefeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ff30cece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ff30cf062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f151c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f151c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f151c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f151c631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ff30c85bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ff30c85a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ff30c6a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ff30919e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ff30919b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f151c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f151c6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f151c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ff30919a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c (1935 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvsintload -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vlnu8_v_u8m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vlnu8_v_u8m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i8> @test_nds_vlnu8_v_u8m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_nds_vlnu8_v_u8m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vlnu8_v_u8m1_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.nds.vlnu.mask.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vlnu.mask.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vlnu8_v_u8m2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.nds.vlnu.mask.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | ...
# `---data was truncated (10240/12958) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb920a1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fb9209ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fb920a262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa208a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa208aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa208a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa208a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb92037bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fb92037a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fb9201c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fb91ccbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fb91ccbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa208a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa208a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa208a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb91ccba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c (1936 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmin_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmin_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmin_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmin_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmin_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmin_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmin_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmin_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmin_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmin_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmin_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/97639) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559537e2deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559537e2ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559537e2e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f73a4133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f73a418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f73a4133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f73a411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559537dc3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559537dc3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559537da88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559537a57e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559537a57b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f73a411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73a411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73a411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559537a57a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c (1937 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dc82e96eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dc82e93e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dc82e9762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f54d4649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54d46a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f54d4649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f54d4631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc82e2cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dc82e2ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dc82e118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dc82ac0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dc82ac0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f54d4632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54d46330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54d46330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc82ac0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c (1938 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrsub_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrsub_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrsub_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrsub_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrsub_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrsub_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrsub_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrsub_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrsub_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = all
# | ...
# `---data was truncated (10240/147390) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005616ebba5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005616ebba2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005616ebba662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f81af305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f81af35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f81af305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f81af2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005616ebb3bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005616ebb3ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005616ebb208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005616eb7cfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005616eb7cfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f81af2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f81af2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f81af2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005616eb7cfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c (1939 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccus_vx_i16mf4_tu(<vscale x 1 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccus_vx_i16mf2_tu(<vscale x 2 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccus_vx_i16m1_tu(<vscale x 4 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccus_vx_i16m2_tu(<vscale x 8 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccus_vx_i16m4_tu(<vscale x 16 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16>, i8, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwmaccus_vx_i16m8_tu(<vscale x 32 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 32 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16>, i8, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwmaccus_vx_i32mf2_tu(<vscale x 1 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32>, i16, <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwmaccus_vx_i32m1_tu(<vscale x 2 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32>, i16, <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwmaccus_vx_i32m2_tu(<vscale x 4 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.a
# | ...
# `---data was truncated (10240/73947) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558a3ec4eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558a3ec4be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558a3ec4f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf8d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf8d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf8d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf8d231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a3ebe4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558a3ebe4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558a3ebc98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558a3e878e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558a3e878b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdf8d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf8d2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf8d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a3e878a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c (1940 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_f32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_i32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_i32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_i32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_u32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_u32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tupl
# | ...
# `---data was truncated (10240/53454) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055563e6a8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055563e6a5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055563e6a962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff91933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff9198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff91933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff9191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055563e63ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055563e63ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055563e6238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055563e2d2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055563e2d2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007eff9191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff9191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff9191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055563e2d2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c (1941 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4au_vx_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4au_vx_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nou
# | ...
# `---data was truncated (10240/25034) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e1c7af9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e1c7af6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e1c7afa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9ce7049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9ce70a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9ce7049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9ce7031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e1c7a8fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e1c7a8fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e1c7a748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e1c7723e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e1c7723b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9ce7032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9ce70330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9ce70330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e1c7723a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c (1942 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh    -target-feature +xsfvfexp16e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexp_v_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexp_v_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexp_v_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexp_v_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vfexp_v_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 32 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexp_v_f16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(<vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexp_v_f16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(<vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexp_v_f16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(<vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexp_v_f16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(<vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define d
# | ...
# `---data was truncated (10240/25350) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005582b7c77eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005582b7c74e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005582b7c7862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9de0d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9de0d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9de0d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9de0d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005582b7c0dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005582b7c0da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005582b7bf28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005582b78a1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005582b78a1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9de0d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9de0d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9de0d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005582b78a1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c (1943 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsll_vv_u16mf4(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsll_vx_u16mf4(<vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsll_vv_u16mf2(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsll_vx_u16mf2(<vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsll_vv_u16m1(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsll_vx_u16m1(<vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vwsll_vv_u16m2(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vwsll_vx_u16m2(<vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vwsll_vv_u16m4(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vwsll_vx_u16m4(<vscale x 16 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.i64.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.i64.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounw
# | ...
# `---data was truncated (10240/68141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563943b8feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563943b8ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563943b9062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa792105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa79215c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa792105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa7920ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563943b25bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563943b25a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563943b0a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005639437b9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005639437b9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa7920eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa7920ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa7920ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639437b9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c (1944 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558345bfaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558345bf7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558345bfb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe5dfd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe5dfd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe5dfd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe5dfd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558345b90bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558345b90a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558345b758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558345824e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558345824b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe5dfd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe5dfd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe5dfd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558345824a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c (1945 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_f32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_i32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_i32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_i32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_u32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_u32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_u32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i6
# | ...
# `---data was truncated (10240/47604) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005639b2261eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005639b225ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005639b226262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2d23f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2d23f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2d23f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2d23f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005639b21f7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005639b21f7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005639b21dc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005639b1e8be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005639b1e8bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2d23f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2d23f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2d23f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639b1e8ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c (1946 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563270157eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563270154e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056327015862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd5c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd5c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd5c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd5c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005632700edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005632700eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005632700d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056326fd81e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056326fd81b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdd5c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd5c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd5c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056326fd81a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vaddq.c (1947 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vaddq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vaddq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = add <4 x i32> %0, %1
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vaddq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = fadd <8 x half> %0, %1
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vaddq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.add.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.add.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vaddq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x float>, ptr %inactive.addr, align 8
# |   %6 = call <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4, <4 x float> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vaddq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vaddq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x half> @llvm.arm.mve.add.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4, <8 x half> undef)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.add.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vaddq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = add <4 x i32> %0, %.splat
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vaddq_n_f16(<8 x half> noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca half, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load half, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x half> poison, half %1, i64 0
# |   %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
# |   %2 = fadd <8 x half> %0, %.splat
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vaddq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.add.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vaddq_m_n_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, float noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca float, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store float %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load float, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x float> poison, float %1, i64 0
# |   %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x float>, ptr %inactive.addr, align 8
# |   %6 = call <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %.splat, <4 x i1> %4, <4 x float> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vaddq_x_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @t
# | ...
# `---data was truncated (10240/11617) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x00005568a8c93eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005568a8c90e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005568a8c9462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f05c4849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f05c48a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f05c4849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f05c4831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005568a8c29bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005568a8c29a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005568a8c0e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005568a88bde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005568a88bdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f05c4832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f05c48330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f05c48330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005568a88bda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c (1948 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_bf16m1x3_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   s
# | ...
# `---data was truncated (10240/24381) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055980bd8beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055980bd88e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055980bd8c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f885a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f885a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f885a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f885a31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055980bd21bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055980bd21a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055980bd068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055980b9b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055980b9b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f885a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f885a31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f885a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055980b9b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm-neon-directed-rounding-constrained.c (1949 of 27911)
******************** TEST 'Clang :: CodeGen/arm-neon-directed-rounding-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57      -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c -o - |      /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8-unknown-linux-gnueabihf"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrndi_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndi_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrndi_v1.i = call <2 x float> @llvm.nearbyint.v2f32(<2 x float> %vrndi_v.i)
# |   store <2 x float> %vrndi_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndiq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndiq_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndiq_v1.i = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %vrndiq_v.i)
# |   store <4 x float> %vrndiq_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <2 x float> @llvm.nearbyint.v2f32(<2 x float>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.nearbyint.v4f32(<4 x float>) #1
# | 
# | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a57" "target-features"="+aes,+armv8-a,+crc,+d32,+dsp,+fp-armv8,+fp-armv8d16,+fp-armv8d16sp,+fp-armv8sp,+fp16,+fp64,+hwdiv,+hwdiv-arm,+neon,+sha2,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1}
# | !llvm.ident = !{!2}
# | 
# | !0 = !{i32 1, !"target-abi", !"aapcs-linux"}
# | !1 = !{i32 1, !"min_enum_size", i32 4}
# | !2 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000056074ff73eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056074ff70e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056074ff7462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f791c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f791c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f791c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f791c031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056074ff09bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056074ff09a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056074feee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056074fb9de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056074fb9db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f791c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f791c0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f791c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056074fb9da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c (1950 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsub_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsub_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsub_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsub_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsub_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsub_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsub_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsub_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsub_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsub_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsub.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, ha
# | ...
# `---data was truncated (10240/125649) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005594f5348eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005594f5345e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005594f534962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3375d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3375d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3375d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3375d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005594f52debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005594f52dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005594f52c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005594f4f72e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005594f4f72b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3375d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3375d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3375d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005594f4f72a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: Modules/pr93497.cppm (1951 of 27911)
******************** TEST 'Clang :: Modules/pr93497.cppm' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
rm -rf /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp
# executed command: rm -rf /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp
# RUN: at line 2
mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp
# executed command: mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp
# RUN: at line 3
split-file /usr/local/google/home/thakis/src/llvm-project/clang/test/Modules/pr93497.cppm /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp
# executed command: split-file /usr/local/google/home/thakis/src/llvm-project/clang/test/Modules/pr93497.cppm /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.cppm      -emit-module-interface -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.pcm
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.cppm -emit-module-interface -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.pcm
# RUN: at line 7
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp      -fmodule-file=mod=/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.pcm -emit-llvm      -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=simplifycfg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp -fmodule-file=mod=/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.pcm -emit-llvm -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | %struct.Thing = type { i32 }
# | %struct.C = type { i32 }
# | %struct.NonConstexprDtor = type { i32 }
# | 
# | $needed = comdat any
# | 
# | @_ZNW3mod5Thing3OneE = external global %struct.Thing, align 4
# | @_ZW3mod13ConstantValue = available_externally constant %struct.C { i32 1 }, align 4
# | @_ZW3mod11ConstantPtr = external global ptr, align 8
# | @_ZW3mod16NonConstantValue = external global %struct.C, align 4
# | @_ZW3mod21NonConstexprDtorValue = external global %struct.NonConstexprDtor, align 4
# | @llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 65535, ptr @_GLOBAL__sub_I_use.cpp, ptr null }]
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z3usev() #0 {
# | entry:
# |   %t1 = alloca %struct.Thing, align 4
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 4 %t1, ptr align 4 @_ZNW3mod5Thing3OneE, i64 4, i1 false)
# |   %raw = getelementptr inbounds nuw %struct.Thing, ptr %t1, i32 0, i32 0
# |   %0 = load i32, ptr %raw, align 4
# |   %call = call noundef i32 @_Z7consumei(i32 noundef %0)
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.memcpy.p0.p0.i64(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i64, i1 immarg) #1
# | 
# | declare noundef i32 @_Z7consumei(i32 noundef) #2
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z4use2v() #0 {
# | entry:
# |   %agg.tmp = alloca %struct.C, align 4
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 4 %agg.tmp, ptr align 4 @_ZW3mod13ConstantValue, i64 4, i1 false)
# |   %coerce.dive = getelementptr inbounds nuw %struct.C, ptr %agg.tmp, i32 0, i32 0
# |   %0 = load i32, ptr %coerce.dive, align 4
# |   %call = call noundef i32 @_Z8consumeCW3mod1C(i32 %0)
# |   ret i32 %call
# | }
# | 
# | declare noundef i32 @_Z8consumeCW3mod1C(i32) #2
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z4use3v() #0 {
# | entry:
# |   %retval = alloca i32, align 4
# |   %Ptr = alloca ptr, align 8
# |   %agg.tmp = alloca %struct.C, align 4
# |   %0 = load ptr, ptr @_ZW3mod11ConstantPtr, align 8
# |   store ptr %0, ptr %Ptr, align 8
# |   %1 = load ptr, ptr %Ptr, align 8
# |   %value = getelementptr inbounds nuw %struct.C, ptr %1, i32 0, i32 0
# |   %2 = load i32, ptr %value, align 4
# |   %tobool = icmp ne i32 %2, 0
# |   br i1 %tobool, label %if.then, label %if.end
# | 
# | if.then:                                          ; preds = %entry
# |   %3 = load ptr, ptr %Ptr, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 4 %agg.tmp, ptr align 4 %3, i64 4, i1 false)
# |   %coerce.dive = getelementptr inbounds nuw %struct.C, ptr %agg.tmp, i32 0, i32 0
# |   %4 = load i32, ptr %coerce.dive, align 4
# |   %call = call noundef i32 @_Z8consumeCW3mod1C(i32 %4)
# |   store i32 %call, ptr %retval, align 4
# |   br label %return
# | 
# | if.end:                                           ; preds = %entry
# |   %call1 = call i32 @needed()
# |   store i32 %call1, ptr %retval, align 4
# |   br label %return
# | 
# | return:                                           ; preds = %if.end, %if.then
# |   %5 = load i32, ptr %retval, align 4
# |   ret i32 %5
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define linkonce_odr i32 @needed() #0 comdat {
# | entry:
# |   %call = call noundef i32 @_Z7consumei(i32 noundef 43)
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z4use4v() #0 {
# | entry:
# |   %retval = alloca i32, align 4
# |   %Ref = alloca %struct.C, align 4
# |   %agg.tmp = alloca %struct.C, align 4
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 4 %Ref, ptr align 4 @_ZW3mod16NonConstantValue, i64 4, i1 false)
# |   %value = getelementptr inbounds nuw %struct.C, ptr %Ref, i32 0, i32 0
# |   %0 = load i32, ptr %value, align 4
# |   %tobool = icmp ne i32 %0, 0
# |   br i1 %tobool, label %if.then, label %if.end
# | 
# | if.then:                                          ; preds = %entry
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 4 %agg.tmp, ptr align 4 %Ref, i64 4, i1 false)
# |   %coerce.dive = getelementptr inbounds nuw %struct.C, ptr %agg.tmp, i32 0, i32 0
# |   %1 = load i32, ptr %coerce.dive, align 4
# |   %call = call noundef i32 @_Z8consumeCW3mod1C(i32 %1)
# |   store i32 %call, ptr %retval, align 4
# |   br label %return
# | 
# | if.end:                                           ; preds = %entry
# |   %call1 = call i32 @needed()
# |   store i32 %call1, ptr %retval, align 4
# |   br label %return
# | 
# | return:                                           ; preds = %if.end, %if.then
# |   %2 = load i32, ptr %retval, align 4
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z4use5v() #0 {
# | entry:
# |   %retval = alloca i32, align 4
# |   %V = alloca %struct.NonConstexprDtor, align 4
# |   %cleanup.dest.slot = alloca i32, align 4
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 4 %V, ptr align 4 @_ZW3mod21NonConstexprDtorValue, i64 4, i1 false)
# |   %raw = getelementptr inbounds nuw %struct.NonConstexprDtor, ptr %V, i32 0, i32 0
# |   %0 = load i32, ptr %raw, align 4
# |   %tobool = icmp ne i32 %0, 0
# |   br i1 %tobool, label %if.then, label %if.end
# | 
# | if.then:                                          ; preds = %entry
# |   %raw1 = getelementptr inbounds nuw %struct.NonConstexprDtor, ptr %V, i32 0, i32 0
# |   %1 = load i32, ptr %raw1, align 4
# |   %call = call noundef i32 @_Z7consumei(i32 noundef %1)
# |   store i32 %call, ptr %retval, align 4
# |   store i32 1, ptr %cleanup.dest.slot, align 4
# |   br label %cleanup
# | 
# | if.end:                                           ; preds = %entry
# |   %call2 = call i32 @needed()
# |   store i32 %call2, ptr %retval, align 4
# |   store i32 1, ptr %cleanup.dest.slot, align 4
# |   br label %cleanup
# | 
# | cleanup:                                          ; preds = %if.end, %if.then
# |   call void @_ZNW3mod16NonConstexprDtorD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) %V) #5
# |   %2 = load i32, ptr %retval, align 4
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @_ZNW3mod16NonConstexprDtorD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4)) unnamed_addr #3
# | 
# | declare void @_ZGIW3mod()
# | 
# | ; Function Attrs: noinline nounwind
# | define internal void @_GLOBAL__sub_I_use.cpp() #4 section ".text.startup" {
# | entry:
# |   call void @_ZGIW3mod()
# |   ret void
# | }
# | 
# | attributes #0 = { mustprogress noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
# | attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #3 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #4 = { noinline nounwind "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #5 = { nounwind }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=simplifycfg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=simplifycfg
# |  #0 0x0000562173b8aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562173b87e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562173b8b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe570f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe570f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe570f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe570f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562173b20bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562173b20a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562173b058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005621737b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005621737b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe570f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe570f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe570f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005621737b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c (1952 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmul_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmul_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmul_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmul_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmul_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmul_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmul_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmul_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmul_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfmul.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmul.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmul_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscal
# | ...
# `---data was truncated (10240/29510) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557857b68eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557857b65e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557857b6962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd40f705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd40f75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd40f705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd40f6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557857afebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557857afea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557857ae38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557857792e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557857792b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd40f6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd40f6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd40f6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557857792a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c (1953 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei64_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bfbe654eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bfbe651e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bfbe65562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7069533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f706958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7069533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f706951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bfbe5eabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bfbe5eaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bfbe5cf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bfbe27ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bfbe27eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f706951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f706951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f706951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bfbe27ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c (1954 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a640040eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a64003de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a64004162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf6e01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf6e0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf6e01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf6e003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a63ffd6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a63ffd6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a63ffbb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a63fc6ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a63fc6ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdf6e004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf6e0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf6e0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a63fc6aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c (1955 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_u8mf8_f8e4m3mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_u8mf4_f8e4m3mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u8mf2_f8e4m3mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_f8e4m3m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_f8e4m3m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_f8e4m3m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_f8e4m3m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_f8e4m3mf8_u8mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_f8e4m3mf4_u8mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_f8e4m3mf2_u8mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_f8e4m3m1_u8m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_f8e4m3m2_u8m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_f8e4m3m4_u8m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_f8e4m3m8_u8m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_u8mf8_f8e5m2mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_u8mf4_f8e5m2mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u8mf2_f8e5m2mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_f8e5m2m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_f8e5m2m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_f8e5m2m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_f8e5m2m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_f8e5m2mf8_u8mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_f8e5m2mf4_u8mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_f8e5m2mf2_u8mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_f8e5m2m1_u8m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_f8e5m2m2_u8m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_f8e5m2m4_u8m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_f8e5m2m8_u8m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 
# | ...
# `---data was truncated (10240/10944) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c24d67eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c24d67be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c24d67f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f514b01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f514b0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f514b01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f514b003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c24d614bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c24d614a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c24d5f98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c24d2a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c24d2a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f514b004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f514b0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f514b0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c24d2a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c (1956 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_f16m1x2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_f16m2x2(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei32_v_f16m4x2(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_f32m1x2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_f32m2x2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple
# | ...
# `---data was truncated (10240/108848) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d3fe45deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d3fe45ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d3fe45e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd132e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd132ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd132e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd132e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d3fe3f3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d3fe3f3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d3fe3d88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d3fe087e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d3fe087b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd132e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd132e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd132e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d3fe087a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c (1957 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfadd_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfadd_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfadd_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfadd_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfadd_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfadd_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | ...
# `---data was truncated (10240/302389) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f8a9f64eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f8a9f61e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f8a9f6562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff0f6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff0f618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff0f6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff0f611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f8a9efabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f8a9efaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f8a9edf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f8a9b8ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f8a9b8eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff0f611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff0f611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff0f611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f8a9b8ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c (1958 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_f_f_w_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfncvt_f_f_w_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfncvt_f_f_w_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfncvt_f_f_w_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> %0, <vscale x 16 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfncvt_f_f_w_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfncvt_f_f_w_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> %0, <vscale x 2 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float>, <vscale x 2 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfncvt_f_f_w_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> %0, <vscale x 4 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float>, <vscale x 4 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfncvt_f_f_w_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> %0, <vscale x 8 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float>, <vscale x 8 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x half> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl
# | ...
# `---data was truncated (10240/78896) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005576616edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005576616eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005576616ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b9e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b9e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b9e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b9e31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557661683bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557661683a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005576616688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557661317e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557661317b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8b9e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b9e31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b9e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557661317a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c (1959 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vzext_vf2_u16mf4(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vzext_vf2_u16mf2(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vzext_vf2_u16m1(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vzext_vf2_u16m2(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vzext_vf2_u16m4(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vzext_vf2_u16m8(<vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf2_u32mf2(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf2_u32m1(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf2_u32m2(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vzext_vf2_u32m4(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vzext_vf2_u32m8(<vscale x 16 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf2_u64m1(<vscale x 1 x i32> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf2_u64m2(<vscale x 2 x i32> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %op
# | ...
# `---data was truncated (10240/28563) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561212b60eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561212b5de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561212b6162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f028fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f028fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f028fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f028fd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561212af6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561212af6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561212adb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056121278ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056121278ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f028fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f028fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f028fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056121278aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c (1960 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_f16mf4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_f16mf2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_f16m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_f16m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_f16m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_i16mf4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_i16mf2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_i16m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_i16m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_i16m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_u16mf4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_u16mf2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline n
# | ...
# `---data was truncated (10240/28559) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561377007eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561377004e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056137700862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb286b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb286b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb286b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb286b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561376f9dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561376f9da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561376f828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561376c31e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561376c31b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb286b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb286b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb286b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561376c31a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c (1961 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vle.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vle.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vle.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vle.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vle.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vle.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vle.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vle.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vle.nxv16bf16.p0.i64(<vscale x 16 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vle.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vle.nxv32bf16.p0.i64(<vscale x 32 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vle.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16_v_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, 
# | ...
# `---data was truncated (10240/24959) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055956464ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559564649e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055956464d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f73c2849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f73c28a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f73c2849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f73c2831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005595645e2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005595645e2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005595645c78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559564276e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559564276b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f73c2832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73c28330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73c28330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559564276a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c (1962 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjx_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjx_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjx_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjx_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjx_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjx_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjx_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjx_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjx_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjx_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretur
# | ...
# `---data was truncated (10240/69677) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005642150e0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005642150dde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005642150e162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e20333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e2038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e20333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e2031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564215076bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564215076a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056421505b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564214d0ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564214d0ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6e2031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e2031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e2031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564214d0aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c (1963 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vid_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8.i64(<vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8.i64(<vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vid_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8.i64(<vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8.i64(<vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vid_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8.i64(<vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8.i64(<vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vid_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8.i64(<vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8.i64(<vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vid_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8.i64(<vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8.i64(<vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vid_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8.i64(<vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8.i64(<vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vid_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vid.nxv64i8.i64(<vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vid.nxv64i8.i64(<vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vid_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16.i64(<vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16.i64(<vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vid_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16.i64(<vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16.i64(<vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vid_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16.i64(<vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16.i64(<vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vid_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16.i64(<vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16.i64(<vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vid_v_u16m4_tu(<vscale x 16 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16.i64(<vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16.i64(<vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vid_v_u16m8_tu(<vscale x 32 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16.i64(<vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16.i64(<vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vid_v_u32mf2_tu(<vscale x 1 x i32
# | ...
# `---data was truncated (10240/75405) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561cb6181eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561cb617ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561cb618262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f62fd533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f62fd58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f62fd533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f62fd51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561cb6117bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561cb6117a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561cb60fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561cb5dabe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561cb5dabb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f62fd51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f62fd51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f62fd51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561cb5daba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c (1964 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnot_v_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnot_v_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnot_v_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnot_v_i8m1(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnot_v_i8m2(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vnot_v_i8m4(<vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vnot_v_i8m8(<vscale x 64 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vnot_v_i16mf4(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vnot_v_i16mf2(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vnot_v_i16m1(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vnot_v_i16m2(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vxor.nxv8i16.i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vxor.nxv8i16.i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vnot_v_i16m4(<vscale x 16 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vxor.nxv16i16.i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vxor.nxv16i16.i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vnot_v_i16m8(<vscale x 32 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale 
# | ...
# `---data was truncated (10240/72501) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005584bf87deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005584bf87ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005584bf87e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7a82d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7a82d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7a82d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7a82d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005584bf813bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005584bf813a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005584bf7f88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005584bf4a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005584bf4a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7a82d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7a82d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7a82d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005584bf4a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c (1965 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_x_f_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_x_f_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_x_f_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_x_f_v_i32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_x_f_v_i32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_xu_f_v_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_xu_f_v_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_xu_f_v_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_xu_f_v_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_xu_f_v_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %src, ptr %src.addr, a
# | ...
# `---data was truncated (10240/81515) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055efad287eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055efad284e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055efad28862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f13cb533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13cb58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f13cb533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f13cb51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055efad21dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055efad21da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055efad2028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055efaceb1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055efaceb1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f13cb51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13cb51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13cb51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055efaceb1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c (1966 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmax_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmax_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmax_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmax_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmax_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmax_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmax_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmax_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmax_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i6
# | ...
# `---data was truncated (10240/157165) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f9a69a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f9a69a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f9a69a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f38cff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f38cff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f38cff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f38cff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f9a693cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f9a693ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f9a69218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f9a65d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f9a65d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f38cff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f38cff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f38cff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f9a65d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c (1967 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfge_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfge_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfge_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 32 x bflo
# | ...
# `---data was truncated (10240/27786) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556b2e81beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556b2e818e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556b2e81c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa497449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa4974a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa497449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa497431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b2e7b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556b2e7b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556b2e7968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556b2e445e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556b2e445b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa497432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4974330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4974330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b2e445a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c (1968 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vslidedown_vx_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vslidedown_vx_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vslidedown_vx_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vslidedown_vx_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vslidedown_vx_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vslidedown_vx_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vslidedown_vx_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vslidedown_vx_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vslidedown_vx_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %src, i64 noundef %offset
# | ...
# `---data was truncated (10240/287213) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005613a74edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005613a74eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005613a74ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6524533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f652458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6524533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f652451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005613a7483bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005613a7483a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005613a74688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005613a7117e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005613a7117b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f652451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f652451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f652451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005613a7117a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c (1969 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_i8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e8_v_i8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e8_v_i8m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_u8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_u8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e8_v_u8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/48313) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555be7342eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555be733fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555be734362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa3cab05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa3cab5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa3cab05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa3caaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555be72d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555be72d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555be72bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555be6f6ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555be6f6cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa3caaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa3caaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa3caaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555be6f6ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c (1970 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmax_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmax_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmax_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmax_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmax_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmax_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmax_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmax_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmax_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, <vscale x 16 x half> 
# | ...
# `---data was truncated (10240/157173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055842ce68eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055842ce65e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055842ce6962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0a46705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0a4675c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0a46705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0a466ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055842cdfebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055842cdfea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055842cde38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055842ca92e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055842ca92b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0a466eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0a466ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0a466ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055842ca92a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c (1971 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfeq_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfeq_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfeq_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/66557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564e942e2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564e942dfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564e942e362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1743933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f174398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1743933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f174391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564e94278bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564e94278a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564e9425d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564e93f0ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564e93f0cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f174391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f174391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f174391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564e93f0ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c (1972 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vor_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vor_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vor_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vor_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vor_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vor_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vor_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vor_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vor_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vor_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vor_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.a
# | ...
# `---data was truncated (10240/174713) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eed8a97eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eed8a94e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eed8a9862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8444b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8444b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8444b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8444b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eed8a2dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eed8a2da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eed8a128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eed86c1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eed86c1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8444b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8444b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8444b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eed86c1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c (1973 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf8x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_u8mf8x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_u8mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_u8mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_u8m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, pt
# | ...
# `---data was truncated (10240/18980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005582dfa90eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005582dfa8de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005582dfa9162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb615a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb615aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb615a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb615a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005582dfa26bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005582dfa26a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005582dfa0b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005582df6bae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005582df6bab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb615a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb615a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb615a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005582df6baa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c (1974 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m1_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m8_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, al
# | ...
# `---data was truncated (10240/81312) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005578dd7a9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005578dd7a6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005578dd7aa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f569d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f569d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f569d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f569d231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005578dd73fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005578dd73fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005578dd7248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005578dd3d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005578dd3d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f569d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f569d2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f569d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005578dd3d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGenCXX/virtual-base-ctor.cpp (1975 of 27911)
******************** TEST 'Clang :: CodeGenCXX/virtual-base-ctor.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp -emit-llvm -triple x86_64-unknown-linux-gnu -o - -O2 | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp -emit-llvm -triple x86_64-unknown-linux-gnu -o - -O2
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | %struct.B = type { ptr, ptr, %struct.A }
# | %struct.A = type { i32 }
# | 
# | $_ZTV1B = comdat any
# | 
# | $_ZTI1B = comdat any
# | 
# | $_ZTS1B = comdat any
# | 
# | $_ZTI1A = comdat any
# | 
# | $_ZTS1A = comdat any
# | 
# | @y = local_unnamed_addr global i8 2, align 1
# | @x = local_unnamed_addr global %struct.B { ptr getelementptr inbounds inrange(-24, 0) (i8, ptr @_ZTV1B, i64 24), ptr null, %struct.A zeroinitializer }, align 8
# | @_ZTV1B = linkonce_odr constant { [3 x ptr] } { [3 x ptr] [ptr inttoptr (i64 16 to ptr), ptr null, ptr @_ZTI1B] }, comdat, align 8
# | @_ZTI1B = linkonce_odr constant { ptr, ptr, i32, i32, ptr, i64 } { ptr getelementptr inbounds (i8, ptr @_ZTVN10__cxxabiv121__vmi_class_type_infoE, i64 16), ptr @_ZTS1B, i32 0, i32 1, ptr @_ZTI1A, i64 -6141 }, comdat, align 8
# | @_ZTVN10__cxxabiv121__vmi_class_type_infoE = external global [0 x ptr]
# | @_ZTS1B = linkonce_odr constant [3 x i8] c"1B\00", comdat, align 1
# | @_ZTI1A = linkonce_odr constant { ptr, ptr } { ptr getelementptr inbounds (i8, ptr @_ZTVN10__cxxabiv117__class_type_infoE, i64 16), ptr @_ZTS1A }, comdat, align 8
# | @_ZTVN10__cxxabiv117__class_type_infoE = external global [0 x ptr]
# | @_ZTS1A = linkonce_odr constant [3 x i8] c"1A\00", comdat, align 1
# | @llvm.global_ctors = appending global [0 x { i32, ptr, ptr }] zeroinitializer
# | 
# | !llvm.ident = !{!0}
# | !llvm.errno.tbaa = !{!1}
# | 
# | !0 = !{!"clang version 24.0.0"}
# | !1 = !{!2, !3, i64 0}
# | !2 = !{!"__libc_errno", !3, i64 0}
# | !3 = !{!"int", !4, i64 0}
# | !4 = !{!"omnipotent char", !5, i64 0}
# | !5 = !{!"Simple C++ TBAA"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o -
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o -
# |  #0 0x000055dbe74d0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dbe74cde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dbe74d162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f840a049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f840a0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f840a049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f840a031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dbe7466bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dbe7466a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dbe744b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dbe70fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dbe70fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f840a032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f840a0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f840a0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dbe70faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c (1976 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f16m1x8(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f32m1x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f64m1x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/69980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565021b85eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565021b82e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000565021b8662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efebf449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efebf4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efebf449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efebf431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565021b1bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565021b1ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000565021b008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005650217afe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005650217afb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efebf432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efebf4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efebf4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005650217afa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c (1977 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2e
# | ...
# `---data was truncated (10240/253148) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d50ab4eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d50ab4be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d50ab4f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2eba61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2eba6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2eba61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2eba603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d50aae4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d50aae4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d50aac98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d50a778e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d50a778b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2eba604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2eba6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2eba6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d50a778a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c (1978 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2cl_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2cl_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2cl_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2cl_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2cl_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2cl_vv_u64m1_tu(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2cl_vv_u64m2_tu(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2cl_vv_u64m4_tu(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscal
# | ...
# `---data was truncated (10240/12235) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a50f767eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a50f764e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a50f76862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f667af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f667af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f667af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f667af1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a50f6fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a50f6fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a50f6e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a50f391e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a50f391b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f667af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f667af1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f667af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a50f391a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c (1979 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i64> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i64> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8_tum(<vscale x 8 x i1> %mask, <vscale x 8 x i64> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_tumu(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 
# | ...
# `---data was truncated (10240/18225) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005573c962beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005573c9628e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005573c962c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe141b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe141b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe141b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe141aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005573c95c1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005573c95c1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005573c95a68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005573c9255e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005573c9255b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe141aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe141aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe141aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005573c9255a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c (1980 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_i64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_u64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_i64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_u64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("
# | ...
# `---data was truncated (10240/18506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555f60814eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555f60811e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555f6081562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe300649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe3006a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe300649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe300631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f607aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555f607aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555f6078f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555f6043ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555f6043eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe300632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe3006330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe3006330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f6043ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c (1981 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccu_vv_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccu_vx_u16mf4_tu(<vscale x 1 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccu_vv_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccu_vx_u16mf2_tu(<vscale x 2 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccu_vv_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccu_vx_u16m1_tu(<vscale x 4 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccu_vv_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccu_vx_u16m2_tu(<vscale x 8 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccu_vv_u16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale 
# | ...
# `---data was truncated (10240/150951) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559389055eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559389052e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055938905662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9261133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f926118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9261133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f926111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559388febbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559388feba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559388fd08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559388c7fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559388c7fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f926111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f926111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f926111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559388c7fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c (1982 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f16m1x3(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f16m2x3(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f32m1x3(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f32m2x3(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f64m1x3(ptr noundef %base, <vscale x 1 x i32> %binde
# | ...
# `---data was truncated (10240/99754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056113c937eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056113c934e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056113c93862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b37133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b3718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b37133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b3711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056113c8cdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056113c8cda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056113c8b28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056113c561e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056113c561b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4b3711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b3711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b3711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056113c561a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c (1983 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvsintload -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vlnu8_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vlnu8_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(<vscale x 16 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i8> @test_nds_vlnu8_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(<vscale x 32 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_nds_vlnu8_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(<vscale x 64 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8> %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8> %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(<vscale x 4 x i8> %1, ptr %2, <vscale x 4 x i1> %0, i64 %3,
# | ...
# `---data was truncated (10240/29443) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055675599deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055675599ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055675599e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f011b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f011b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f011b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f011b11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556755933bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556755933a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005567559188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005567555c7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005567555c7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f011b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f011b11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f011b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005567555c7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c (1984 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f16m1x6(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f32m1x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f64m1x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei16_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d872aedeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d872aeae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d872aee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f620bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f620bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f620bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f620bb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d872a83bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d872a83a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d872a688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d872717e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d872717b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f620bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f620bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f620bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d872717a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c (1985 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulh_vv_i64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulh_vx_i64m1(<vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulh_vv_i64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulh_vx_i64m2(<vscale x 2 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulh_vv_i64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 4 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulh_vx_i64m4(<vscale x 4 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulh_vv_i64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 8 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulh_vx_i64m8(<vscale x 8 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulh_vv_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulh_vx_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load i64, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulh.mask.nxv1i64.i64.i64(<vscale x 1 x i64> poison
# | ...
# `---data was truncated (10240/18569) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005608aa2b2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005608aa2afe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005608aa2b362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f45f1449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f45f14a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f45f1449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f45f1431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005608aa248bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005608aa248a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005608aa22d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005608a9edce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005608a9edcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f45f1432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f45f14330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f45f14330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005608a9edca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c (1986 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vle16ff_v_f16mf4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.mask.nxv1f16.i64.p0(<vscale x 1 x half> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.mask.nxv1f16.i64.p0(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vle16ff_v_f16mf2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.mask.nxv2f16.i64.p0(<vscale x 2 x half> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 2 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.mask.nxv2f16.i64.p0(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vle16ff_v_f16m1_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.mask.nxv4f16.i64.p0(<vscale x 4 x half> poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 4 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.mask.nxv4f16.i64.p0(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vle16ff_v_f16m2_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.mask.nxv8f16.i64.p0(<vscale x 8 x half> poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 8 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.mask.nxv8f16.i64.p0(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vle16ff_v_f16m4_m(<vscale x 16 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.mask.nxv16f16.i64.p0(<vscale x 16 x half> poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 16 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 16 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.mask.nxv16f16.i64.p0(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vle16ff_v_f16m8_m(<vscale x 32 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.mask.nxv32f16.i64.p0(<vscale x 32 x half> poison, ptr %1, <vscale x 32 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 32 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 32 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.mask.nxv32f16.i64.p0(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16ff_v_i16mf4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.mask.nxv1i16.i64.p0(<vscale x 1 x i16> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x i16>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i16>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.mask.nxv1i16.i64.p0(<vscale x 1 x i16>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16ff_v_i16mf2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.mask.nxv2i16.i64.p0(<vscale x 2 x i16> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractva
# | ...
# `---data was truncated (10240/22708) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b4b52abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b4b52a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b4b52ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd6dbe1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd6dbe725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd6dbe1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd6dbe03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b4b5241bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b4b5241a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b4b52268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b4b4ed5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b4b4ed5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd6dbe04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd6dbe050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd6dbe050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b4b4ed5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c (1987 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_f16m1x2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_f16m2x2(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei32_v_f16m4x2(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_f32m1x2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_f32m2x2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vect
# | ...
# `---data was truncated (10240/108856) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ea0fd75eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ea0fd72e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ea0fd7662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f14c1a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f14c1a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f14c1a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f14c1a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ea0fd0bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ea0fd0ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ea0fcf08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ea0f99fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ea0f99fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f14c1a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f14c1a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f14c1a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ea0f99fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c (1988 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560e8f897eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560e8f894e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560e8f89862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f22ca533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f22ca58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f22ca533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f22ca51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e8f82dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560e8f82da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560e8f8128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560e8f4c1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560e8f4c1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f22ca51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f22ca51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f22ca51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e8f4c1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c (1989 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsub_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsub_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsub_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsub_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsub_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsub_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsub_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsub_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 
# | ...
# `---data was truncated (10240/64244) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558db249aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558db2497e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558db249b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdcb2b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdcb2b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdcb2b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdcb2b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558db2430bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558db2430a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558db24158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558db20c4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558db20c4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdcb2b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdcb2b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdcb2b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558db20c4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c (1990 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056452ef8deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056452ef8ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056452ef8e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9aceb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9aceb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9aceb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9aceaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056452ef23bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056452ef23a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056452ef088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056452ebb7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056452ebb7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9aceaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9aceaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9aceaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056452ebb7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/bf16-reinterpret-intrinsics.c (1991 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/bf16-reinterpret-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_s8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_s16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_s32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_u8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_u16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_u32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_p8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_p16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_u64(<1 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_s64(<1 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load 
# | ...
# `---data was truncated (10240/31171) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055da8f7b6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055da8f7b3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055da8f7b762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe558449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe5584a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe558449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe558431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da8f74cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055da8f74ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055da8f7318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055da8f3e0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055da8f3e0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe558432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe5584330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe5584330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da8f3e0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vclz.c (1992 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vclz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclzq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %0, i1 false)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclzq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %0, i1 false)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclzq_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %0, i1 false)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclzq_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %0, i1 false)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclzq_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %0, i1 false)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclzq_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %0, i1 false)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclsq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = call <16 x i8> @llvm.arm.mve.vcls.v16i8(<16 x i8> %0)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vcls.v16i8(<16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclsq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcls.v8i16(<8 x i16> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcls.v8i16(<8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclsq_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclsq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = call <16 x i8> @llvm.arm.mve.cls.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i1> %3, <16 x i8> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.cls.predicated.v16i8.v16i1(<16 x i8>, <16 x i1>, <16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclsq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.cls.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.cls.predicated.v8i16.v8i1(<8 x i16>, <8 x i1>, <8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclsq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = call <4 x i32> @llvm.arm.mve.cls.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i1> %3, <4 x i32> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.cls.predicated.v4i32.v4i1(<4 x i32>, <4 x i1>, <4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclzq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = call <16 x i8> @llvm.arm.mve.clz.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i1> %3, <16 x i8> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.clz.predicated.v16i8.v16i1(<16 x i8>, <16 x i1>, <16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclzq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.clz.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.clz.predicated.v8i16.v8i1(<8 x i16>, <8 x i1>, <8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclzq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = call <4 x i32> @llvm.arm.mve.clz.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i1> %3, <4 x i32> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x 
# | ...
# `---data was truncated (10240/18674) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005647d7a43eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005647d7a40e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005647d7a4462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f679dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f679dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f679dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f679dc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005647d79d9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005647d79d9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005647d79be8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005647d766de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005647d766db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f679dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f679dc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f679dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005647d766da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c (1993 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vget_v_bf16m2_bf16m1(<vscale x 8 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vget_v_bf16m4_bf16m1(<vscale x 16 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vget_v_bf16m8_bf16m1(<vscale x 32 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vget_v_bf16m4_bf16m2(<vscale x 16 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vget_v_bf16m8_bf16m2(<vscale x 32 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vget_v_bf16m8_bf16m4(<vscale x 32 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.extract.nxv16bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.extract.nxv16bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x2_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x3_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x4_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x5_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x6_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x7_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x 
# | ...
# `---data was truncated (10240/30682) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c67c325eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c67c322e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c67c32662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f136af05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f136af5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f136af05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f136aeed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c67c2bbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c67c2bba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c67c2a08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c67bf4fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c67bf4fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f136aeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f136aeef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f136aeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c67bf4fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c (1994 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f16m1x3(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f16m2x3(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f32m1x3(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f32m2x3(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f64m1x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tu
# | ...
# `---data was truncated (10240/99186) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005564e603aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005564e6037e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005564e603b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3aca449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3aca4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3aca449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3aca431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005564e5fd0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005564e5fd0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005564e5fb58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005564e5c64e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005564e5c64b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3aca432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3aca4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3aca4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005564e5c64a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c (1995 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsub_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsub_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsub_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsub_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsub_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsub_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsub_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsub_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsub_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsub.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsub.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsub_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   stor
# | ...
# `---data was truncated (10240/29518) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557c0df47eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557c0df44e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557c0df4862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f63a4a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f63a4aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f63a4a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f63a4a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557c0deddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557c0dedda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557c0dec28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557c0db71e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557c0db71b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f63a4a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f63a4a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f63a4a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557c0db71a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c (1996 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f16m1x8(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f32m1x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f64m1x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei32_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005632e8e28eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005632e8e25e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005632e8e2962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbba8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbba818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbba8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbba811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005632e8dbebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005632e8dbea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005632e8da38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005632e8a52e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005632e8a52b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbba811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbba811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbba811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005632e8a52a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c (1997 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei16_v_f16mf4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei16_v_f16mf2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei16_v_f16m1(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei16_v_f16m2(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei16_v_f16m4(ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vluxei16_v_f16m8(ptr noundef %base, <vscale x 32 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> poison, ptr %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei16_v_f32mf2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei16_v_f32m1(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei16_v_f32m2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei16_v_f32m4(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i16.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i16.i64(<vscale x 8 x floa
# | ...
# `---data was truncated (10240/118156) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563337a38eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563337a35e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563337a3962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0dd3533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0dd358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0dd3533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0dd351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005633379cebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005633379cea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005633379b38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563337662e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563337662b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0dd351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0dd351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0dd351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563337662a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c (1998 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_f32mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32ff_v_f32m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32ff_v_f32m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32ff_v_f32m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_i32mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32ff_v_i32m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32ff_v_i32m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32ff_v_i32m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_u32mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 nounde
# | ...
# `---data was truncated (10240/31748) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055961fcf6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055961fcf3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055961fcf762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2c07449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2c074a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2c07449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2c07431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055961fc8cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055961fc8ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055961fc718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055961f920e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055961f920b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2c07432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2c074330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2c074330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055961f920a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c (1999 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei8_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei8_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei8_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei8_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei8_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i8> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vloxei8_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, <vscale x 32 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i8> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei8_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei8_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Fu
# | ...
# `---data was truncated (10240/30423) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561a59e86eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561a59e83e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561a59e8762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4fd8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4fd898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4fd8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4fd891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a59e1cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561a59e1ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561a59e018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561a59ab0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561a59ab0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4fd891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4fd891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4fd891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a59ab0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c (2000 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16mf4x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16mf2x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m1x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m2x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m4x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, al
# | ...
# `---data was truncated (10240/13263) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564bd71adeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564bd71aae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564bd71ae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0514933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f051498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0514933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f051491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564bd7143bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564bd7143a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564bd71288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564bd6dd7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564bd6dd7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f051491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f051491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f051491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564bd6dd7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c (2001 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_f16mf4x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_f16mf2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_f16m1x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_f16m2x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_f16m4x2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_i16mf4x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_i16mf2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_i16m1x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |  
# | ...
# `---data was truncated (10240/19083) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564a485c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564a485c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564a485c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe98f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe98f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe98f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe98f831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564a4855ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564a4855ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564a485438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564a481f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564a481f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe98f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe98f8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe98f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564a481f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c (2002 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_f64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_f64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_i64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_i64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_u64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_u64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_f64m1x3_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("r
# | ...
# `---data was truncated (10240/36023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f2c936eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559f2c933e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559f2c93762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee9141bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee914725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee9141ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee91403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f2c8ccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559f2c8cca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559f2c8b18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559f2c560e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559f2c560b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fee91404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee914050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee914050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f2c560a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c (2003 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vcompress_vm_f16mf4(<vscale x 1 x half> %src, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vcompress_vm_f16mf2(<vscale x 2 x half> %src, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vcompress_vm_f16m1(<vscale x 4 x half> %src, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vcompress_vm_f16m2(<vscale x 8 x half> %src, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vcompress_vm_f16m4(<vscale x 16 x half> %src, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vcompress_vm_f16m8(<vscale x 32 x half> %src, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vcompress_vm_f32mf2(<vscale x 1 x float> %src, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vcompress_vm_f32m1(<vscale x 2 x float> %src, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vcompress.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vcompress.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vcompress_vm_f32m2(<vscale x 4 x float> %src, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vcompress.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vcompress.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vcompress_vm_f32m4(<vscale x 8 x float> %src, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load <vscale x 
# | ...
# `---data was truncated (10240/62956) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560b49484eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560b49481e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560b4948562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4a3601bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4a360725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4a3601ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4a36003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b4941abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560b4941aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560b493ff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560b490aee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560b490aeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4a36004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4a360050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4a360050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b490aea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c (2004 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16m1x2(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16m2x2(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16m4x2(ptr noundef %base, <vscale x 16 x i16> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f32m1x2(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f32m2x2(ptr noundef %base, <vscale x 4 x i16
# | ...
# `---data was truncated (10240/129182) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005623ed03deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005623ed03ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005623ed03e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6bef933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6bef98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6bef933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6bef91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005623ecfd3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005623ecfd3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005623ecfb88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005623ecc67e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005623ecc67b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6bef91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6bef91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6bef91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005623ecc67a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c (2005 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_i16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_i16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_i16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_u16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_u16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x 
# | ...
# `---data was truncated (10240/53338) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005606a8a3beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005606a8a38e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005606a8a3c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f89a8333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f89a838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f89a8333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f89a831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005606a89d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005606a89d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005606a89b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005606a8665e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005606a8665b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f89a831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f89a831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f89a831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005606a8665a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c (2006 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_2x8x2_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_2x8x2_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_2x8x2_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_2x8x2_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005612a27e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005612a27e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005612a27e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f88d0b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f88d0b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f88d0b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f88d0b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005612a2779bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005612a2779a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005612a275e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005612a240de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005612a240db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f88d0b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f88d0b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f88d0b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005612a240da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c (2007 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f16m1x3(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f16m2x3(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f32m1x3(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f32m2x3(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f64m1x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tu
# | ...
# `---data was truncated (10240/99186) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005559d2895eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005559d2892e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005559d289662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f82649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f826a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f82649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f82631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005559d282bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005559d282ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005559d28108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005559d24bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005559d24bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4f82632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f826330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f826330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005559d24bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c (2008 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005619b2067eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005619b2064e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005619b206862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa2ede49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa2edea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa2ede49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa2ede31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005619b1ffdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005619b1ffda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005619b1fe28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005619b1c91e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005619b1c91b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa2ede32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa2ede330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa2ede330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005619b1c91a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c (2009 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005568ad52feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005568ad52ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005568ad53062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f16c9e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f16c9ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f16c9e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f16c9e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005568ad4c5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005568ad4c5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005568ad4aa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005568ad159e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005568ad159b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f16c9e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f16c9e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f16c9e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005568ad159a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c (2010 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnj_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnj_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnj_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnj_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnj_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnj_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnj_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnj_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnj_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnj.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnj.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnj_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0
# | ...
# `---data was truncated (10240/29136) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561eb82c6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561eb82c3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561eb82c762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8826533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f882658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8826533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f882651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561eb825cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561eb825ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561eb82418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561eb7ef0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561eb7ef0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f882651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f882651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f882651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561eb7ef0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c (2011 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056047aed0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056047aecde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056047aed162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f619f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f619f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f619f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f619f831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056047ae66bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056047ae66a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056047ae4b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056047aafae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056047aafab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f619f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f619f8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f619f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056047aafaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c (2012 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslideup_vx_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vslideup.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslideup.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslideup_vx_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vslideup.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslideup.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslideup_vx_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vslideup.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslideup.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslideup_vx_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vslideup.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vslideup.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vslideup_vx_bf16m4(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vslideup.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vslideup.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vslideup_vx_bf16m8(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vslideup.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vslideup.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslideup_vx_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vslideup.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslideup.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslideup_vx_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vslideup.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslideup.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x 
# | ...
# `---data was truncated (10240/16529) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aebb10ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aebb109e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aebb10d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb4d2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb4d2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb4d2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb4d2f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aebb0a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aebb0a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aebb0878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aebad36e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aebad36b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb4d2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb4d2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb4d2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aebad36a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c (2013 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f16m1x7(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f32m1x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f64m1x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei8_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vsca
# | ...
# `---data was truncated (10240/61665) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005614881daeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005614881d7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005614881db62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0a43d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0a43d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0a43d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0a43ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561488170bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561488170a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005614881558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561487e04e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561487e04b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0a43ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0a43cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0a43cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561487e04a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c (2014 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_i32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_i32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_u32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_u32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_f32mf2x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_f32m1x8_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("ri
# | ...
# `---data was truncated (10240/32023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c9725eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c9725ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c9725ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e92533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e9258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e92533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e9251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c972584bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c972584a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c9725698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c972218e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c972218b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1e9251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e9251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e9251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c972218a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c (2015 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vslideup_vx_f16mf4(<vscale x 1 x half> %dest, <vscale x 1 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vslideup_vx_f16mf2(<vscale x 2 x half> %dest, <vscale x 2 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vslideup_vx_f16m1(<vscale x 4 x half> %dest, <vscale x 4 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vslideup_vx_f16m2(<vscale x 8 x half> %dest, <vscale x 8 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vslideup_vx_f16m4(<vscale x 16 x half> %dest, <vscale x 16 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vslideup_vx_f16m8(<vscale x 32 x half> %dest, <vscale x 32 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vslideup_vx_f32mf2(<vscale x 1 x float> %dest, <vscale x 1 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vslideup_vx_f32m1(<vscale x 2 x float> %dest, <vscale x 2 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vslideup_vx_f32m2(<vscale x 4 x float> %dest, <vscale x 4 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 4 x 
# | ...
# `---data was truncated (10240/142016) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558bbb9f5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558bbb9f2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558bbb9f662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f286c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f286c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f286c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f286c31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558bbb98bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558bbb98ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558bbb9708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558bbb61fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558bbb61fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f286c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f286c31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f286c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558bbb61fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c (2016 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564e06858eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564e06855e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564e0685962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7028733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f702878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7028733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f702871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564e067eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564e067eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564e067d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564e06482e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564e06482b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f702871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f702871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f702871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564e06482a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c (2017 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4e
# | ...
# `---data was truncated (10240/228857) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d12e2f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d12e2f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d12e2f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f28cf249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f28cf2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f28cf249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f28cf231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d12e28ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d12e28ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d12e2738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d12df22e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d12df22b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f28cf232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f28cf2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f28cf2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d12df22a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm_acle.c (2018 of 27911)
******************** TEST 'Clang :: CodeGen/arm_acle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple armv8a-none-eabi -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c -check-prefixes=ARM,AArch32
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple armv8a-none-eabi -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8a-unknown-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_dmb() #0 {
# | entry:
# |   call void @llvm.arm.dmb(i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.dmb(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_dsb() #0 {
# | entry:
# |   call void @llvm.arm.dsb(i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.dsb(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_isb() #0 {
# | entry:
# |   call void @llvm.arm.isb(i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.isb(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_yield() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.hint(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_wfe() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_wfi() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sev() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sevl() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_dbg() #0 {
# | entry:
# |   call void @llvm.arm.dbg(i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.dbg(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_swp(i32 noundef %x, ptr noundef %p) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__p.addr.i = alloca ptr, align 4
# |   %__v.i = alloca i32, align 4
# |   %.atomictmp.i = alloca i32, align 4
# |   %atomic-temp.i = alloca i32, align 4
# |   %x.addr = alloca i32, align 4
# |   %p.addr = alloca ptr, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   store ptr %p, ptr %p.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %1 = load ptr, ptr %p.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store ptr %1, ptr %__p.addr.i, align 4
# |   %2 = load ptr, ptr %__p.addr.i, align 4
# |   %3 = load i32, ptr %__x.addr.i, align 4
# |   store i32 %3, ptr %.atomictmp.i, align 4
# |   %4 = load i32, ptr %.atomictmp.i, align 4
# |   %5 = atomicrmw volatile xchg ptr %2, i32 %4 monotonic, align 4
# |   store i32 %5, ptr %atomic-temp.i, align 4
# |   %6 = load i32, ptr %atomic-temp.i, align 4
# |   store i32 %6, ptr %__v.i, align 4
# |   %7 = load i32, ptr %__v.i, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_pld() #0 {
# | entry:
# |   call void @llvm.prefetch.p0(ptr null, i32 0, i32 3, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.prefetch.p0(ptr readonly captures(none), i32 immarg range(i32 0, 2), i32 immarg range(i32 0, 4), i32 immarg range(i32 0, 2)) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_pldx() #0 {
# | entry:
# |   call void @llvm.prefetch.p0(ptr null, i32 1, i32 3, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_pli() #0 {
# | entry:
# |   call void @llvm.prefetch.p0(ptr null, i32 0, i32 3, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_plix() #0 {
# | entry:
# |   call void @llvm.prefetch.p0(ptr null, i32 0, i32 3, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_nop() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ror(i32 noundef %x, i32 noundef %y) #0 {
# | entry:
# |   %retval.i = alloca i32, align 4
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %x.addr = alloca i32, align 4
# |   %y.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   store i32 %y, ptr %y.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %1 = load i32, ptr %y.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__y.addr.i, align 4
# |   %rem.i = urem i32 %2, 32
# |   store i32 %rem.i, ptr %__y.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %cmp.i = icmp eq i32 %3, 0
# |   br i1 %cmp.i, label %if.then.i, label %if.end.i
# | 
# | if.then.i:                                        ; preds = %entry
# |   %4 = load i32, ptr %__x.addr.i, align 4
# |   store i32 %4, ptr %retval.i, align 4
# |   br label %__ror.exit
# | 
# | if.end.i:                                         ; preds = %entry
# |   %5 = load i32, ptr %__x.addr.i, align 4
# |   %6 = load i32, ptr %__y.addr.i, align 4
# |   %shr.i = lshr i32 %5, %6
# |   %7 = load i32, ptr %__x.addr.i, align 4
# |   %8 = load i32, ptr %__y.addr.i, align 4
# |   %sub.i = sub i32 32, %8
# |   %shl.i = shl i32 %7, %sub.i
# |   %or.i = or i32 %shr.i, %shl.i
# |   store i32 %or.i, ptr %retval.i, align 4
# |   br label %__ror.exit
# | 
# | __ror.exit:                                       ; preds = %if.then.i, %if.end.i
# |   %9 = load i32, ptr %retval.i, align 4
# |   ret i32 %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_rorl(i32 noundef %x, i32 noundef %y) #0 {
# | entry:
# |   %retval.i.i = alloca i32, align 4
# |   %__x.addr.i.i = alloca i32, align 4
# |   %__y.addr.i.i = alloca i32, align 4
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %x.addr = alloca i32, align 4
# |   %y.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   store i32 %y, ptr %y.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %1 = load i32, ptr %y.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   store i32 %2, ptr %__x.addr.i.i, align 4
# |   store i32 %3, ptr %__y.addr.i.i, align 4
# |   %4 = load i32, ptr %__y.addr.i.i, align 4
# |   %rem.i.i = urem i32 %4, 32
# |   store i32 %rem.i.i, ptr %__y.addr.i.i, align 4
# |   %5 = load i32, ptr %__y.addr.i.i, align 4
# |   %cmp.i.i = icmp eq i32 %5, 0
# |   br i1 %cmp.i.i, label %if.then.i.i, label %if.end.i.i
# | 
# | if.then.i.i:                                      ; preds = %entry
# |   %6 = load i32, ptr %__x.addr.i.i, align 4
# |   store i32 %6, ptr %retval.i.i, align 4
# |   br label %__rorl.exit
# | 
# | if.end.i.i:                                       ; preds = %entry
# |   %7 = load i32, ptr %__x.addr.i.i, align 4
# |   %8 = load i32, ptr %__y.addr.i.i, align 4
# |   %shr.i.i = lshr i32 %7, %8
# |   %9 = load i32, ptr %__x.addr.i.i, align 4
# |   %10 = load i32, ptr %__y.addr.i.i, align 4
# |   %sub.i.i = sub i32 32, %10
# |   %shl.i.i = shl i32 %9, %sub.i.i
# |   %or.i.i = or i32 %shr.i.i, %shl.i.i
# |   store i32 %or.i.i, ptr %retval.i.i, align 4
# |   br label %__rorl.exit
# | 
# | __rorl.exit:                                      ; preds = %if.then.i.i, %if.end.i.i
# |   %11 = load i32, ptr %retval.i.i, align 4
# |   ret i32 %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_rorll(i64 noundef %x, i32 noundef %y) #0 {
# | entry:
# |   %retval.i = alloca i64, align 8
# |   %__x.addr.i = alloca i64, align 8
# |   %__y.addr.i = alloca i32, align 4
# |   %x.addr = alloca i64, align 8
# |   %y.addr = alloca i32, align 4
# |   store i64 %x, ptr %x.addr, align 8
# |   store i32 %y, ptr %y.addr, align 4
# |   %0 = load i64, ptr %x.addr, align 8
# |   %1 = load i32, ptr %y.addr, align 4
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__y.addr.i, align 4
# |   %rem.i = urem i32 %2, 64
# |   store i32 %rem.i, ptr %__y.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %cmp.i = icmp eq i32 %3, 0
# |   br i1 %cmp.i, label %if.then.i, label %if.end.i
# | 
# | if.then.i:                                        ; preds = %entry
# |   %4 = load i64, ptr %__x.addr.i, align 8
# |   store i64 %4, ptr %retval.i, align 8
# |   br label %__rorll.exit
# | 
# | if.end.i:                                         ; preds = %entry
# |   %5 = load i64, ptr %__x.addr.i, align 8
# |   %6 = load i32, ptr %__y.addr.i, align 4
# |   %sh_prom.i = zext i32 %6 to i64
# |   %shr.i = lshr i64 %5, %sh_prom.i
# |   %7 = load i64, ptr %__x.addr.i, align 8
# |   %8 = load i32, ptr %__y.addr.i, align 4
# |   %sub.i = sub i32 64, %8
# |   %sh_prom1.i = zext i32 %sub.i to i64
# |   %shl.i = shl i64 %7, %sh_prom1.i
# |   %or.i = or i64 %shr.i, %shl.i
# |   store i64 %or.i, ptr %retval.i, align 8
# |   br label %__rorll.exit
# | 
# | __rorll.exit:                                     ; preds = %if.then.i, %if.end.i
# |   %9 = load i64, ptr %retval.i, align 8
# |   ret i64 %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_clz(i32 noundef %t) #0 {
# | entry:
# |   %__t.addr.i = alloca i32, align 4
# |   %t.addr = alloca i32, align 4
# |   store i32 %t, ptr %t.addr, align 4
# |   %0 = load i32, ptr %t.addr, align 4
# |   store i32 %0, ptr %__t.addr.i, align 4
# |   %1 = load i32, ptr %__t.addr.i, align 4
# |   %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_clzl(i32 noundef %t) #0 {
# | entry:
# |   %__t.addr.i = alloca i32, align 4
# |   %t.addr = alloca i32, align 4
# |   store i32 %t, ptr %t.addr, align 4
# |   %0 = load i32, ptr %t.addr, align 4
# |   store i32 %0, ptr %__t.addr.i, align 4
# |   %1 = load i32, ptr %__t.addr.i, align 4
# |   %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_clzll(i64 noundef %t) #0 {
# | entry:
# |   %__t.addr.i = alloca i64, align 8
# |   %t.addr = alloca i64, align 8
# |   store i64 %t, ptr %t.addr, align 8
# |   %0 = load i64, ptr %t.addr, align 8
# |   store i64 %0, ptr %__t.addr.i, align 8
# |   %1 = load i64, ptr %__t.addr.i, align 8
# |   %2 = call i64 @llvm.ctlz.i64(i64 %1, i1 false)
# |   %3 = trunc i64 %2 to i32
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_cls(i32 noundef %t) #0 {
# | entry:
# |   %__t.addr.i = alloca i32, align 4
# |   %t.addr = alloca i32, align 4
# |   store i32 %t, ptr %t.addr, align 4
# |   %0 = load i32, ptr %t.addr, align 4
# |   store i32 %0, ptr %__t.addr.i, align 4
# |   %1 = load i32, ptr %__t.addr.i, align 4
# |   %cls.i = call i32 @llvm.arm.cls(i32 %1)
# |   ret i32 %cls.i
# | }
# | 
# | ; Function Attrs: noinline
# | ...
# `---data was truncated (10240/86891) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e40df3beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e40df38e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e40df3c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb692333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb69238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb692333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb69231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e40ded1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e40ded1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e40deb68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e40db65e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e40db65b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb69231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb69231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb69231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e40db65a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c -check-prefixes=ARM,AArch32
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c -check-prefixes=ARM,AArch32
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c (2019 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf8x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_u8mf8x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_u8mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_u8mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_u8m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.
# | ...
# `---data was truncated (10240/18972) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a457881eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a45787ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a45788262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd7c8d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd7c8d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd7c8d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd7c8d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a457817bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a457817a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a4577fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a4574abe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a4574abb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd7c8d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd7c8d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd7c8d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a4574aba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c (2020 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei64_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005616e30caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005616e30c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005616e30cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc2e3849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc2e38a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc2e3849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc2e3831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005616e3060bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005616e3060a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005616e30458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005616e2cf4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005616e2cf4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc2e3832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc2e38330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc2e38330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005616e2cf4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c (2021 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmacc_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmacc_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmacc_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmacc_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmacc_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmacc_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmacc_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmacc_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | ...
# `---data was truncated (10240/34356) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b1b3e2aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b1b3e27e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b1b3e2b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f98ed933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f98ed98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f98ed933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f98ed91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b1b3dc0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b1b3dc0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b1b3da58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b1b3a54e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b1b3a54b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f98ed91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f98ed91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f98ed91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b1b3a54a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c (2022 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e77d34eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e77d34be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e77d34f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f23f9d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f23f9d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f23f9d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f23f9d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e77d2e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e77d2e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e77d2c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e77cf78e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e77cf78b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f23f9d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f23f9d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f23f9d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e77cf78a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c (2023 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_i32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_i32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_u32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_u32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056182ccf6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056182ccf3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056182ccf762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f74249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f742a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f74249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f74231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056182cc8cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056182cc8ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056182cc718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056182c920e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056182c920b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2f74232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f742330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f742330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056182c920a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c (2024 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16ff_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16ff_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 2 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16ff_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv4bf16.i64.p0(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 4 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv4bf16.i64.p0(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16ff_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv8bf16.i64.p0(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 8 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv8bf16.i64.p0(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16ff_v_bf16m4_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv16bf16.i64.p0(<vscale x 16 x bfloat> poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 16 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 16 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv16bf16.i64.p0(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16ff_v_bf16m8_m(<vscale x 32 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 32 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv32bf16.i64.p0(<vscale x 32 x bfloat> poison, ptr %1, <vscale x 32 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 32 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 32 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv32bf16.i64.p0(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005601e3666eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005601e3663e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005601e366762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff3b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff3b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff3b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff3b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005601e35fcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005601e35fca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005601e35e18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005601e3290e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005601e3290b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007eff3b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff3b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff3b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005601e3290a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c (2025 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16mf4x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16mf2x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16m1x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16m2x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca targ
# | ...
# `---data was truncated (10240/11920) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562d2922beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562d29228e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562d2922c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc7a7b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc7a7b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc7a7b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc7a7aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d291c1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562d291c1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562d291a68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562d28e55e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562d28e55b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc7a7aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc7a7aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc7a7aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d28e55a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c (2026 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounw
# | ...
# `---data was truncated (10240/12658) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056517e7fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056517e7f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056517e7fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8f98649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8f986a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8f98649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8f98631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056517e792bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056517e792a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056517e7778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056517e426e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056517e426b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8f98632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8f986330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8f986330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056517e426a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c (2027 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16mf4x3(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16mf2x3(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16m1x3(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16m2x3(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwin
# | ...
# `---data was truncated (10240/10798) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560f045eaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560f045e7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560f045eb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b66333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b6638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b66333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b6631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f04580bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560f04580a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560f045658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560f04214e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560f04214b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5b6631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b6631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b6631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f04214a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c (2028 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjn_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjn_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjn_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjn_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjn_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjn_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjn_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjn_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjn_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjn_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory
# | ...
# `---data was truncated (10240/69669) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563a3e91aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563a3e917e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563a3e91b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f44cf333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f44cf38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f44cf333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f44cf31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a3e8b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563a3e8b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563a3e8958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563a3e544e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563a3e544b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f44cf31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44cf31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44cf31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a3e544a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c (2029 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zvfhmin -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -target-feature +zve64d    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_bf16m8(i64 noundef %tss, <vscale x 32 x bfloat> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv32bf16.i64(i64 %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv32bf16.i64(i64, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_f16m8(i64 noundef %tss, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv32f16.i64(i64 %0, <vscale x 32 x half> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv32f16.i64(i64, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_f32m8(i64 noundef %tss, <vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv16f32.i64(i64 %0, <vscale x 16 x float> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv16f32.i64(i64, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_f64m8(i64 noundef %tss, <vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv8f64.i64(i64 %0, <vscale x 8 x double> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv8f64.i64(i64, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_i8m8(i64 noundef %tss, <vscale x 64 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_i16m8(i64 noundef %tss, <vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64 %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_i32m8(i64 noundef %tss, <vscale x 16 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 16 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64 %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64, <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_i64m8(i64 noundef %tss, <vscale x 8 x i64> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 8 x i64> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64 %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_u8m8(i64 noundef %tss, <vscale x 64 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_u16m8(i64 noundef %tss, <vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64 %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_u32m8(i64 noundef %tss, <vscale x 16 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 16 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64 %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_u64m8(i64 noundef %tss, <vscale x 8 x i64> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 8 x i64> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64 %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_f8e4m3m8(i64 noundef %tss, <vscale x 64 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, <vscale
# | ...
# `---data was truncated (10240/11640) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cc8155eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cc8155be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cc8155f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc5a9c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5a9ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc5a9c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc5a9c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc814f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cc814f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cc814d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cc81188e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cc81188b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc5a9c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5a9c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5a9c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc81188a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c (2030 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i16> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale
# | ...
# `---data was truncated (10240/15707) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560e69655eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560e69652e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560e6965662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb658e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb658ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb658e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb658e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e695ebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560e695eba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560e695d08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560e6927fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560e6927fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb658e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb658e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb658e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e6927fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c (2031 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmv_v_f_f16mf4_tu(<vscale x 1 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmv_v_f_f16mf2_tu(<vscale x 2 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmv_v_f_f16m1_tu(<vscale x 4 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmv_v_f_f16m2_tu(<vscale x 8 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmv_v_f_f16m4_tu(<vscale x 16 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfmv_v_f_f16m8_tu(<vscale x 32 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16.i64(<vscale x 32 x half> %0, half %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16.i64(<vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfmv_v_f_f32mf2_tu(<vscale x 1 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load float, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.i64(<vscale x 1 x float> %0, float %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.i64(<vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfmv_v_f_f32m1_tu(<vscale x 2 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load float, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.i64(<vscale x 2 x float> %0, float %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.i64(<vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfmv_v_f_f32m2_tu(<vscale x 4 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load float, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32.i64(<vscale x 4 x float> %0, float %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32.i64(<vscale x 4 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfmv_v_f_f32m4_tu(<vscale x 8 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load float, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32.i64(<vscale x 8 x float> %0, float %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32.i64(<vscale x 8 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfmv_v_f_f32m8_tu(<vscale x 16 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr
# | ...
# `---data was truncated (10240/29319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c4f86ffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c4f86fce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c4f870062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc5ee105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5ee15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc5ee105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc5ee0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c4f8695bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c4f8695a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c4f867a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c4f8329e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c4f8329b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc5ee0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5ee0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5ee0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c4f8329a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c (2032 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei64_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei64_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei64_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei64_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei64_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei64_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei64_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei64_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vluxei64_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %
# | ...
# `---data was truncated (10240/215941) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558a94fb8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558a94fb5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558a94fb962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f733f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f733f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f733f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f733f431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a94f4ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558a94f4ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558a94f338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558a94be2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558a94be2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f733f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f733f4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f733f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a94be2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c (2033 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005557da92ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005557da929e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005557da92d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fefb9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fefb9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fefb9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fefb9b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005557da8c2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005557da8c2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005557da8a78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005557da556e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005557da556b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fefb9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fefb9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fefb9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005557da556a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c (2034 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f16m1x3(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_f16m2x3(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f32m1x3(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_f32m2x3(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f64m1x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captu
# | ...
# `---data was truncated (10240/87308) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005627efbf8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005627efbf5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005627efbf962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc7f2049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc7f20a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc7f2049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc7f2031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005627efb8ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005627efb8ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005627efb738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005627ef822e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005627ef822b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc7f2032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc7f20330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc7f20330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005627ef822a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c (2035 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_i8mf8x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_i8mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e8_v_i8mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e8_v_i8m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_u8mf8x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_u8mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e8_v_u8mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e8_v_u8m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_i8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 
# | ...
# `---data was truncated (10240/19037) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565243995eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565243992e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056524399662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007facfa733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007facfa78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007facfa733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007facfa71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056524392bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056524392ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005652439108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005652435bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005652435bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007facfa71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007facfa71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007facfa71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005652435bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c (2036 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558a44c5feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558a44c5ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558a44c6062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e93f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e93f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e93f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e93f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a44bf5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558a44bf5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558a44bda8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558a44889e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558a44889b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4e93f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e93f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e93f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a44889a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c (2037 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_f64m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_i64m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_u64m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c900e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562c900e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562c900e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5568733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f556878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5568733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f556871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c90079bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562c90079a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562c9005e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562c8fd0de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562c8fd0db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f556871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f556871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f556871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c8fd0da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c (2038 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ddfcb47eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ddfcb44e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ddfcb4862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f52d3049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f52d30a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f52d3049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f52d3031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ddfcaddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ddfcadda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ddfcac28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ddfc771e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ddfc771b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f52d3032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f52d30330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f52d30330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ddfc771a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmaxnmaq.c (2039 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmaxnmaq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %0)
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %2)
# |   %4 = call <8 x half> @llvm.maxnum.v8f16(<8 x half> %1, <8 x half> %3)
# |   ret <8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.fabs.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.maxnum.v8f16(<8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmaq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %0)
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %2)
# |   %4 = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %1, <4 x float> %3)
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.fabs.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmaq_m_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x half> @llvm.arm.mve.vmaxnma.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vmaxnma.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmaq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x float> @llvm.arm.mve.vmaxnma.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4)
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vmaxnma.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>) #2
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d0ac2ddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d0ac2dae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d0ac2de62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0923d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0923d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0923d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0923d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0ac273bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d0ac273a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d0ac2588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d0abf07e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d0abf07b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0923d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0923d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0923d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d0abf07a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbc.c (2040 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbc -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c  -check-prefix=RV32ZBC
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbc -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clmul_32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.clmul.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clmulh_32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.clmulh.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clmulr_32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.clmulr.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.clmul.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.clmulh.i32(i32, i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.clmulr.i32(i32, i32) #2
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbc,+zbkc" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zbc1p0_zbkc1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ed242ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557ed2429e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557ed242d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc45d81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc45d8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc45d81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc45d803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ed23c2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557ed23c2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557ed23a78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557ed2056e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557ed2056b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc45d804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc45d8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc45d8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ed2056a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c -check-prefix=RV32ZBC
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c -check-prefix=RV32ZBC
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c (2041 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfabs_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfabs_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfabs_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfabs_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfabs_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfabs_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfabs_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfabs_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfabs_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfabs_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x f
# | ...
# `---data was truncated (10240/70110) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005611b252ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005611b2529e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005611b252d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe47dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe47dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe47dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe47dd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005611b24c2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005611b24c2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005611b24a78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005611b2156e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005611b2156b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe47dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe47dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe47dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005611b2156a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c (2042 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2ms_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2ms_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2ms_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2ms_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2ms_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2ms_vv_u64m1_tu(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2ms_vv_u64m2_tu(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2ms_vv_u64m4_tu(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(
# | ...
# `---data was truncated (10240/12227) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b3e4f78eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b3e4f75e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b3e4f7962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff171a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff171a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff171a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff171a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b3e4f0ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b3e4f0ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b3e4ef38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b3e4ba2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b3e4ba2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff171a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff171a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff171a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b3e4ba2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c (2043 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei8_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8
# | ...
# `---data was truncated (10240/160141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005614bd62beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005614bd628e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005614bd62c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f3341bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f334725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f3341ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f33403507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005614bd5c1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005614bd5c1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005614bd5a68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005614bd255e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005614bd255b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2f33404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f334050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f334050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005614bd255a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c (2044 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b32_m(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosy
# | ...
# `---data was truncated (10240/11958) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bdbe9f7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bdbe9f4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bdbe9f862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbfe2849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbfe28a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbfe2849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbfe2831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bdbe98dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bdbe98da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bdbe9728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bdbe621e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bdbe621b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbfe2832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbfe28330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbfe28330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bdbe621a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c (2045 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_x_f_w_i8mf8(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_x_f_w_i8mf4(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_x_f_w_i8mf2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_x_f_w_i8m1(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_x_f_w_i8m2(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_x_f_w_i8m4(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_xu_f_w_u8mf8(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_xu_f_w_u8mf4(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_xu_f_w_u8mf2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_xu_f_w_u8m1(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_xu_f_w_u8m2(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_xu_f_w_u8m4(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x ha
# | ...
# `---data was truncated (10240/58653) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005589ffa0beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005589ffa08e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005589ffa0c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fabdd333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fabdd38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fabdd333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fabdd31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589ff9a1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005589ff9a1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005589ff9868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005589ff635e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005589ff635b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fabdd31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fabdd31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fabdd31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005589ff635a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/riscv-xandesperf-rv64.c (2046 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesperf-rv64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c --check-prefix=CHECK-RV64
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_ffb(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %2 = call i64 @llvm.riscv.nds.ffb.i64(i64 %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i64 @llvm.riscv.nds.ffb.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_ffzmism(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %2 = call i64 @llvm.riscv.nds.ffzmism.i64(i64 %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i64 @llvm.riscv.nds.ffzmism.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_ffmism(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %2 = call i64 @llvm.riscv.nds.ffmism.i64(i64 %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i64 @llvm.riscv.nds.ffmism.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_flmism(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %2 = call i64 @llvm.riscv.nds.flmism.i64(i64 %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i64 @llvm.riscv.nds.flmism.i64(i64, i64) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xandesperf" }
# | attributes #1 = { nounwind speculatable memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_xandesperf5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557b0722aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557b07227e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557b0722b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe721733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe72178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe721733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe72171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b071c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557b071c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557b071a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557b06e54e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557b06e54b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe72171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe72171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe72171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b06e54a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c --check-prefix=CHECK-RV64
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c --check-prefix=CHECK-RV64
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c (2047 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_i16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_i16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_i16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_u16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_u16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x 
# | ...
# `---data was truncated (10240/53338) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555da7034eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555da7031e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555da703562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f59ee533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f59ee58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f59ee533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f59ee51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555da6fcabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555da6fcaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555da6faf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555da6c5ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555da6c5eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f59ee51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f59ee51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f59ee51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555da6c5ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c (2048 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsub_vv_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsub_vx_i8mf8_tu(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsub_vv_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsub_vx_i8mf4_tu(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsub_vv_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsub_vx_i8mf2_tu(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsub_vv_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsub_vx_i8m1_tu(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnmsub_vv_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   
# | ...
# `---data was truncated (10240/415319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005566de780eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005566de77de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005566de78162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9164733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f916478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9164733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f916471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005566de716bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005566de716a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005566de6fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005566de3aae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005566de3aab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f916471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f916471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f916471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005566de3aaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c (2049 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_e5m2_e4m3_w4_f8e5m2m8_f8e4m3m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559cf97fdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559cf97fae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559cf97fe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa931a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa931aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa931a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa931a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559cf9793bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559cf9793a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559cf97788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559cf9427e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559cf9427b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa931a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa931a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa931a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559cf9427a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c (2050 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e9d44c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e9d44bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e9d44c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa29241bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa2924725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa29241ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa292403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e9d4458bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e9d4458a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e9d443d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e9d40ece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e9d40ecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa292404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa2924050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa2924050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e9d40eca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c (2051 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmin_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmin_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmin_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 
# | ...
# `---data was truncated (10240/52607) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c068b70eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c068b6de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c068b7162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd36d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd36d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd36d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd36d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c068b06bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c068b06a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c068aeb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c06879ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c06879ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd36d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd36d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd36d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c06879aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c (2052 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf4(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf2(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvtbf16_f_f_w_bf16m1(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvtbf16_f_f_w_bf16m2(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvtbf16_f_f_w_bf16m4(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvtbf16_f_f_w_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %1, <vscale x 4 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvtbf16_f_f_w_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %1, <vscale x 8 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, <vscale x 8 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvtbf16_f_f_w_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %1, <vscale x 16 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @
# | ...
# `---data was truncated (10240/18570) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ff13d3aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ff13d37e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ff13d3b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ee8049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ee80a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ee8049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ee8031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ff13cd0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ff13cd0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ff13cb58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ff13964e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ff13964b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5ee8032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ee80330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ee80330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ff13964a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c (2053 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vget_v_f16m2_f16m1(<vscale x 8 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vget_v_f16m4_f16m1(<vscale x 16 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vget_v_f16m8_f16m1(<vscale x 32 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vget_v_f16m4_f16m2(<vscale x 16 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vget_v_f16m8_f16m2(<vscale x 32 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vget_v_f16m8_f16m4(<vscale x 32 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vget_v_f32m2_f32m1(<vscale x 4 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float> %0, i64 0)
# |   ret <vscale x 2 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vget_v_f32m4_f32m1(<vscale x 8 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv8f32(<vscale x 8 x float> %0, i64 0)
# |   ret <vscale x 2 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv8f32(<vscale x 8 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vget_v_f32m8_f32m1(<vscale x 16 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv16f32(<vscale x 16 x float> %0, i64 0)
# |   ret <vscale x 2 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv16f32(<vscale x 16 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vget_v_f32m4_f32m2(<vscale x 8 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv8f32(<vscale x 8 x float> %0, i64 0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv8f32(<vscale x 8 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vget_v_f32m8_f32m2(<vscale x 16 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv16f32(<vscale x 16 x float> %0, i64 0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv16f32(<vscale x 16 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vget_v_f32m8_f32m4(<vscale x 16 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 8 x float> @llvm.vector.extract.nxv8f32.nxv16f32(<vscale x 16 x float> %0, i64 0)
# |   ret <vscale x 8 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.vector.extract.nxv8f32.nxv16f32(<vscale x 16 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vget_v_f64m2_f64m1(<vscale x 2 x double> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %1 = call <vscale x 1 x double> @llvm.vector.extract.nxv1f64.nxv2f64(<vscale x 2 x double> %0, i64 0)
# |   ret <vscale x 1 x double> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.vector.extract.nxv1f64.nxv2f64(<vscale x 2 x double>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounw
# | ...
# `---data was truncated (10240/246606) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556d53f86eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556d53f83e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556d53f8762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6321b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6321b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6321b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6321b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556d53f1cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556d53f1ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556d53f018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556d53bb0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556d53bb0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6321b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6321b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6321b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556d53bb0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c (2054 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_bf16m1x3_tum(<v
# | ...
# `---data was truncated (10240/25687) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b297e6deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b297e6ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b297e6e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f81d901bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f81d90725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f81d901ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f81d9003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b297e03bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b297e03a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b297de88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b297a97e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b297a97b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f81d9004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f81d90050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f81d90050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b297a97a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c (2055 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f16m1x7(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f32m1x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f64m1x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei64_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b4cdad2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b4cdacfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b4cdad362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f91e3133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f91e318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f91e3133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f91e311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b4cda68bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b4cda68a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b4cda4d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b4cd6fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b4cd6fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f91e311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f91e311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f91e311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b4cd6fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c (2056 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsub_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsub_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsub_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsub_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsub_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsub_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsub_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsub_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range
# | ...
# `---data was truncated (10240/302397) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b951e0feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b951e0ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b951e1062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d4e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d4e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d4e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d4e631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b951da5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b951da5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b951d8a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b951a39e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b951a39b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4d4e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d4e6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d4e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b951a39a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c (2057 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16mf4x5(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16mf2x5(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16m1x5(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e238bd5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e238bd2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e238bd662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe013333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe01338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe013333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe01331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e238b6bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e238b6ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e238b508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e2387ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e2387ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe01331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe01331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe01331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2387ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c (2058 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555848e36eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555848e33e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555848e3762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb4fde1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb4fde725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb4fde1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb4fde03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555848dccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555848dcca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555848db18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555848a60e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555848a60b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb4fde04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb4fde050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb4fde050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555848a60a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c (2059 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i32> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale
# | ...
# `---data was truncated (10240/15707) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f3682aeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f3682abe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f3682af62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7995649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f79956a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7995649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7995631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f368244bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f368244a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f3682298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f367ed8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f367ed8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7995632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f79956330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f79956330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f367ed8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c (2060 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei8_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei8_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei8_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei8_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei8_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i8> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vluxei8_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, <vscale x 32 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i8> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei8_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei8_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function A
# | ...
# `---data was truncated (10240/30415) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e78b3beeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e78b3bbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e78b3bf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe7e6f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe7e6f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe7e6f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe7e6f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e78b354bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e78b354a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e78b3398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e78afe8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e78afe8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe7e6f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe7e6f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe7e6f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e78afe8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c (2061 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_f16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_f16mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_f16m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_f16m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_i16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_i16mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_i16m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_i16m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_u16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   s
# | ...
# `---data was truncated (10240/30826) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005613b5606eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005613b5603e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005613b560762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fde82449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fde824a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fde82449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fde82431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005613b559cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005613b559ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005613b55818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005613b5230e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005613b5230b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fde82432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fde824330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fde824330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005613b5230a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c (2062 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_f32mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_f32m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_f32m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_i32mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_i32m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_i32m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_u32mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_u32m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_u32m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1
# | ...
# `---data was truncated (10240/24058) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d0c4c6deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d0c4c6ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d0c4c6e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b2a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b2a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b2a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b2a31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0c4c03bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d0c4c03a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d0c4be88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d0c4897e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d0c4897b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2b2a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b2a31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b2a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d0c4897a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c (2063 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_i16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_i16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_i16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_i16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e1
# | ...
# `---data was truncated (10240/63053) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559150187eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559150184e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055915018862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4998a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4998a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4998a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4998a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055915011dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055915011da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005591501028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055914fdb1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055914fdb1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4998a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4998a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4998a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055914fdb1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c (2064 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vcompress_vm_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vcompress_vm_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vcompress_vm_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vcompress_vm_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vcompress_vm_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vcompress_vm_bf16m8(<vscale x 32 x bfloat> %vs2, <vscale x 32 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aef6b43eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aef6b40e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aef6b4462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f576b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f576b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f576b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f576b91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aef6ad9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aef6ad9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aef6abe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aef676de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aef676db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f576b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f576b91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f576b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aef676da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c (2065 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fda34f5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fda34f2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fda34f662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6de8049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6de80a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6de8049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6de8031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fda348bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fda348ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fda34708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fda311fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fda311fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6de8032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6de80330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6de80330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fda311fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c (2066 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccsu_vv_i16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccsu_vx_i16mf4(<vscale x 1 x i16> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccsu_vv_i16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccsu_vx_i16mf2(<vscale x 2 x i16> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccsu_vv_i16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccsu_vx_i16m1(<vscale x 4 x i16> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccsu_vv_i16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccsu_vx_i16m2(<vscale x 8 x i16> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccsu_vv_i16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale 
# | ...
# `---data was truncated (10240/79853) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556cb8b18eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556cb8b15e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556cb8b1962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f742a905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f742a95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f742a905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f742a8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556cb8aaebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556cb8aaea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556cb8a938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556cb8742e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556cb8742b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f742a8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f742a8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f742a8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556cb8742a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/thinlto_backend_local_name_conflict.ll (2067 of 27911)
******************** TEST 'Clang :: CodeGen/thinlto_backend_local_name_conflict.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 8
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -module-hash /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend_local_name_conflict.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend_local_name_conflict.ll.tmp.bc
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -module-hash /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend_local_name_conflict.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend_local_name_conflict.ll.tmp.bc
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -module-hash /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend_local_name_conflict.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend_local_name_conflict.ll.tmp.bc
# |  #0 0x000055da4d94feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055da4d94ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055da4d95062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007effad533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007effad58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007effad533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007effad51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da4d8e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055da4d8e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055da4d8ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055da4d579e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055da4d579b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007effad51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007effad51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007effad51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da4d579a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c (2068 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   st
# | ...
# `---data was truncated (10240/11797) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005567a935beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005567a9358e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005567a935c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1781333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f178138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1781333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f178131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005567a92f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005567a92f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005567a92d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005567a8f85e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005567a8f85b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f178131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f178131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f178131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005567a8f85a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c (2069 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulhsu_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulhsu_vx_i8m4(<vscale x 32 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 64 x i8> @test_vmulhsu_vv_i8m8(<vscale x 64 x i8> %op1, <vscale x 64 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 
# | ...
# `---data was truncated (10240/66065) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cf3ee84eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cf3ee81e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cf3ee8562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9a4121bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9a412725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9a4121ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9a41203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf3ee1abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cf3ee1aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cf3edff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cf3eaaee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cf3eaaeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9a41204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9a412050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9a412050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf3eaaea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c (2070 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmax_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmax_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmax_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmax_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmax_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmax_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmax_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmax_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Funct
# | ...
# `---data was truncated (10240/64950) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564d2e522eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564d2e51fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564d2e52362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f15e1049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f15e10a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f15e1049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f15e1031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d2e4b8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564d2e4b8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564d2e49d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564d2e14ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564d2e14cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f15e1032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15e10330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15e10330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d2e14ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c (2071 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrec7_v_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrec7_v_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrec7_v_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrec7_v_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrec7_v_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrec7_v_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrec7_v_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrec7_v_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrec7_v_bf16m1_tum(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, a
# | ...
# `---data was truncated (10240/28358) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555832bf4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555832bf1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555832bf562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e8b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e8b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e8b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e8b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555832b8abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555832b8aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555832b6f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055583281ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055583281eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8e8b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e8b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e8b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055583281ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c (2072 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bafdfa0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bafdf9de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bafdfa162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb41ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb41ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb41ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb41ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bafdf36bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bafdf36a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bafdf1b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bafdbcae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bafdbcab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb41ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb41ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb41ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bafdbcaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c (2073 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_f64m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_f64m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_f64m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_i64m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_i64m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_i64m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_u64m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_u64m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_u64m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %ba
# | ...
# `---data was truncated (10240/24100) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f65a4beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564f65a48e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564f65a4c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1167449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f11674a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1167449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1167431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f659e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564f659e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564f659c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564f65675e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564f65675b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1167432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f11674330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f11674330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f65675a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c (2074 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8mf8(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i8.p0.i64(<vscale x 1 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8mf4(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i8.p0.i64(<vscale x 2 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i8.p0.i64(<vscale x 4 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8m1(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8i8.p0.i64(<vscale x 8 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8m2(ptr noundef %base, i64 noundef %bstride, <vscale x 16 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 16 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv16i8.p0.i64(<vscale x 16 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8m4(ptr noundef %base, i64 noundef %bstride, <vscale x 32 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 32 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv32i8.p0.i64(<vscale x 32 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8m8(ptr noundef %base, i64 noundef %bstride, <vscale x 64 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 64 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 64 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv64i8.p0.i64(<vscale x 64 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_u8mf8(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i8.p0.i64(<vscale x 1 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_u8mf4(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i8.p0.i64(<vscale x 2 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_u8mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i8.p0.i64(<vscale x 4 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_u8m1(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %
# | ...
# `---data was truncated (10240/29809) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056211b8d7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056211b8d4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056211b8d862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd21a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd21a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd21a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd21a31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056211b86dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056211b86da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056211b8528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056211b501e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056211b501b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd21a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd21a31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd21a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056211b501a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c (2075 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), pt
# | ...
# `---data was truncated (10240/19484) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558630759eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558630756e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055863075a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fecf2449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fecf24a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fecf2449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fecf2431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005586306efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005586306efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005586306d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558630383e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558630383b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fecf2432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fecf24330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fecf24330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558630383a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c (2076 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei32_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei32_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i
# | ...
# `---data was truncated (10240/25624) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005611d3acbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005611d3ac8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005611d3acc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc5d5533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5d558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc5d5533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc5d551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005611d3a61bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005611d3a61a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005611d3a468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005611d36f5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005611d36f5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc5d551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5d551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5d551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005611d36f5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c (2077 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfslide1down_vf_f16mf4(<vscale x 1 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfslide1down_vf_f16mf2(<vscale x 2 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfslide1down_vf_f16m1(<vscale x 4 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfslide1down_vf_f16m2(<vscale x 8 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfslide1down_vf_f16m4(<vscale x 16 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfslide1down_vf_f16m8(<vscale x 32 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfslide1down_vf_f32mf2(<vscale x 1 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfslide1down_vf_f32m1(<vscale x 2 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfslide1down_vf_f32m2(<vscale x 4 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfslide1down.nxv4f32.f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, float %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfslide1down.nxv4f32.f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfslide1down_vf_f32m4(<vscale x 8 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfslide1down.nxv8f32.f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, float %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfslide1down.nxv8f32.f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, flo
# | ...
# `---data was truncated (10240/34773) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557cdd79beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557cdd798e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557cdd79c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f85ede49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f85edea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f85ede49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f85ede31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557cdd731bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557cdd731a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557cdd7168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557cdd3c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557cdd3c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f85ede32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f85ede330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f85ede330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557cdd3c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c (2078 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulhu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulhu_vx_u8m4(<vscale x 32 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 64 x i8> @test_vmulhu_vv_u8m8(<vscale x 64 x i8> %op1, <vscale x 64 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vsc
# | ...
# `---data was truncated (10240/65905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fee4af4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fee4af1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fee4af562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f462de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f462dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f462de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f462de31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fee4a8abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fee4a8aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fee4a6f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fee471ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fee471eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f462de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f462de330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f462de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fee471ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c (2079 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv1i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv1i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8ff_v_i8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8ff_v_i8mf2x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8ff_v_i8m1x5_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_u8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv1i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8ff_v_u8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8ff_v_u8mf2x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>,
# | ...
# `---data was truncated (10240/12668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055db0ac3ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055db0ac39e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055db0ac3d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd0eb449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd0eb4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd0eb449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd0eb431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055db0abd2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055db0abd2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055db0abb78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055db0a866e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055db0a866b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd0eb432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd0eb4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd0eb4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055db0a866a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm-v8.1a-neon-intrinsics.c (2080 of 27911)
******************** TEST 'Clang :: CodeGen/arm-v8.1a-neon-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.1a-linux-gnu -target-abi apcs-gnu -target-feature +neon   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S   | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c --check-prefix=CHECK-ARM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.1a-linux-gnu -target-abi apcs-gnu -target-feature +neon -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
# | target triple = "armv8.1a-unknown-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vqrdmlah_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__p2.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   %c.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   store <4 x i16> %c, ptr %c.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   %2 = load <4 x i16>, ptr %c.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   store <4 x i16> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vqrdmlah_s16.i = bitcast <8 x i8> %3 to <4 x i16>
# |   %vqrdmlah_s161.i = bitcast <8 x i8> %4 to <4 x i16>
# |   %vqrdmlah_s162.i = bitcast <8 x i8> %5 to <4 x i16>
# |   %vqrdmlah_s163.i = call <4 x i16> @llvm.arm.neon.vqrdmlah.v4i16(<4 x i16> %vqrdmlah_s16.i, <4 x i16> %vqrdmlah_s161.i, <4 x i16> %vqrdmlah_s162.i)
# |   %vqrdmlah_s164.i = bitcast <4 x i16> %vqrdmlah_s163.i to <8 x i8>
# |   store <8 x i8> %vqrdmlah_s164.i, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vqrdmlah_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <2 x i32> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__p2.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   %c.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   store <2 x i32> %c, ptr %c.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   %2 = load <2 x i32>, ptr %c.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   store <2 x i32> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vqrdmlah_s32.i = bitcast <8 x i8> %3 to <2 x i32>
# |   %vqrdmlah_s321.i = bitcast <8 x i8> %4 to <2 x i32>
# |   %vqrdmlah_s322.i = bitcast <8 x i8> %5 to <2 x i32>
# |   %vqrdmlah_s323.i = call <2 x i32> @llvm.arm.neon.vqrdmlah.v2i32(<2 x i32> %vqrdmlah_s32.i, <2 x i32> %vqrdmlah_s321.i, <2 x i32> %vqrdmlah_s322.i)
# |   %vqrdmlah_s324.i = bitcast <2 x i32> %vqrdmlah_s323.i to <8 x i8>
# |   store <8 x i8> %vqrdmlah_s324.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vqrdmlahq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__p2.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   %c.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x i16> %b, ptr %b.addr, align 16
# |   store <8 x i16> %c, ptr %c.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   %1 = load <8 x i16>, ptr %b.addr, align 16
# |   %2 = load <8 x i16>, ptr %c.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %1, ptr %__p1.addr.i, align 16
# |   store <8 x i16> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vqrdmlahq_s16.i = bitcast <16 x i8> %3 to <8 x i16>
# |   %vqrdmlahq_s161.i = bitcast <16 x i8> %4 to <8 x i16>
# |   %vqrdmlahq_s162.i = bitcast <16 x i8> %5 to <8 x i16>
# |   %vqrdmlahq_s163.i = call <8 x i16> @llvm.arm.neon.vqrdmlah.v8i16(<8 x i16> %vqrdmlahq_s16.i, <8 x i16> %vqrdmlahq_s161.i, <8 x i16> %vqrdmlahq_s162.i)
# |   %vqrdmlahq_s164.i = bitcast <8 x i16> %vqrdmlahq_s163.i to <16 x i8>
# |   store <16 x i8> %vqrdmlahq_s164.i, ptr %ref.tmp.i, align 16
# |   %6 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %6, ptr %__ret.i, align 16
# |   %7 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vqrdmlahq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <4 x i32>, align 16
# |   %__p2.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <4 x i32>, align 16
# |   %c.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <4 x i32> %b, ptr %b.addr, align 16
# |   store <4 x i32> %c, ptr %c.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   %1 = load <4 x i32>, ptr %b.addr, align 16
# |   %2 = load <4 x i32>, ptr %c.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <4 x i32> %1, ptr %__p1.addr.i, align 16
# |   store <4 x i32> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vqrdmlahq_s32.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vqrdmlahq_s321.i = bitcast <16 x i8> %4 to <4 x i32>
# |   %vqrdmlahq_s322.i = bitcast <16 x i8> %5 to <4 x i32>
# |   %vqrdmlahq_s323.i = call <4 x i32> @llvm.arm.neon.vqrdmlah.v4i32(<4 x i32> %vqrdmlahq_s32.i, <4 x i32> %vqrdmlahq_s321.i, <4 x i32> %vqrdmlahq_s322.i)
# |   %vqrdmlahq_s324.i = bitcast <4 x i32> %vqrdmlahq_s323.i to <16 x i8>
# |   store <16 x i8> %vqrdmlahq_s324.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vqrdmlah_lane_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__p2.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   %c.addr = alloca <4 x i16>, align 8
# |   %__ret_140 = alloca <4 x i16>, align 8
# |   %__s0_140 = alloca <4 x i16>, align 8
# |   %__s1_140 = alloca <4 x i16>, align 8
# |   %__s2_140 = alloca <4 x i16>, align 8
# |   %__ret = alloca <4 x i16>, align 8
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x i16>, align 8
# |   %tmp1 = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   store <4 x i16> %c, ptr %c.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__s0_140, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %1, ptr %__s1_140, align 8
# |   %2 = load <4 x i16>, ptr %c.addr, align 8
# |   store <4 x i16> %2, ptr %__s2_140, align 8
# |   %3 = load <4 x i16>, ptr %__s0_140, align 8
# |   %4 = load <4 x i16>, ptr %__s1_140, align 8
# |   %5 = load <4 x i16>, ptr %__s2_140, align 8
# |   store <4 x i16> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <4 x i16>
# |   %lane = shufflevector <4 x i16> %7, <4 x i16> %7, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
# |   store <4 x i16> %lane, ptr %ref.tmp, align 8
# |   %8 = load <4 x i16>, ptr %ref.tmp, align 8
# |   store <4 x i16> %8, ptr %__ret, align 8
# |   %9 = load <4 x i16>, ptr %__ret, align 8
# |   store <4 x i16> %9, ptr %tmp, align 8
# |   %10 = load <4 x i16>, ptr %tmp, align 8
# |   store <4 x i16> %3, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %4, ptr %__p1.addr.i, align 8
# |   store <4 x i16> %10, ptr %__p2.addr.i, align 8
# |   %11 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vqrdmlah_s16.i = bitcast <8 x i8> %11 to <4 x i16>
# |   %vqrdmlah_s161.i = bitcast <8 x i8> %12 to <4 x i16>
# |   %vqrdmlah_s162.i = bitcast <8 x i8> %13 to <4 x i16>
# |   %vqrdmlah_s163.i = call <4 x i16> @llvm.arm.neon.vqrdmlah.v4i16(<4 x i16> %vqrdmlah_s16.i, <4 x i16> %vqrdmlah_s161.i, <4 x i16> %vqrdmlah_s162.i)
# |   %vqrdmlah_s164.i = bitcast <4 x i16> %vqrdmlah_s163.i to <8 x i8>
# |   store <8 x i8> %vqrdmlah_s164.i, ptr %ref.tmp.i, align 8
# |   %14 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %14, ptr %__ret.i, align 8
# |   %15 = load <4 x i16>, ptr %__ret.i, align 8
# |   store <4 x i16> %15, ptr %__ret_140, align 8
# |   %16 = load <4 x i16>, ptr %__ret_140, align 8
# |   store <4 x i16> %16, ptr %tmp1, align 8
# |   %17 = load <4 x i16>, ptr %tmp1, align 8
# |   ret <4 x i16> %17
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vqrdmlah_lane_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <2 x i32> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__p2.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr
# | ...
# `---data was truncated (10240/38786) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S
# |  #0 0x000055a9646b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a9646b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a9646b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f48849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f488a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f48849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f48831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a96464dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a96464da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a9646328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a9642e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a9642e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2f48832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f488330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f488330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a9642e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c --check-prefix=CHECK-ARM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c --check-prefix=CHECK-ARM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c (2081 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f930edeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f930edbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f930edf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f445dc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f445dc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f445dc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f445dc03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f930e74bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f930e74a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f930e598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f930b08e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f930b08b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f445dc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f445dc050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f445dc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f930b08a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c (2082 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), pt
# | ...
# `---data was truncated (10240/19484) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055932ac10eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055932ac0de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055932ac1162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7cf781bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7cf78725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7cf781ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7cf7803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055932aba6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055932aba6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055932ab8b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055932a83ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055932a83ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7cf7804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7cf78050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7cf78050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055932a83aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c (2083 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c780438eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c780435e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c78043962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f158e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f158e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f158e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f158e51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c7803cebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c7803cea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c7803b38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c780062e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c780062b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f158e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f158e51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f158e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c780062a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c (2084 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounw
# | ...
# `---data was truncated (10240/12658) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561f1f3b0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561f1f3ade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561f1f3b162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fadfee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fadfeea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fadfee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fadfee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f1f346bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561f1f346a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561f1f32b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561f1efdae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561f1efdab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fadfee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fadfee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fadfee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f1efdaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c (2085 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vluxei16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> poison, ptr %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr =
# | ...
# `---data was truncated (10240/14319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d3ccabfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d3ccabce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d3ccac062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc6e7a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc6e7aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc6e7a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc6e7a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d3cca55bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d3cca55a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d3cca3a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d3cc6e9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d3cc6e9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc6e7a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc6e7a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc6e7a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d3cc6e9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c (2086 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_rod_f_f_w_f16mf4(<vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_rod_f_f_w_f16mf2(<vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfncvt_rod_f_f_w_f16m1(<vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfncvt_rod_f_f_w_f16m2(<vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfncvt_rod_f_f_w_f16m4(<vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfncvt_rod_f_f_w_f32mf2(<vscale x 1 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> poison, <vscale x 1 x double> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfncvt_rod_f_f_w_f32m1(<vscale x 2 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> poison, <vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfncvt_rod_f_f_w_f32m2(<vscale x 4 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> poison, <vscale x 4 x double> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfncvt_rod_f_f_w_f32m4(<vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> poison, <vscale x 8 x double> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_rod_f_f_w_f16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_rod_f_f_w_f16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_loca
# | ...
# `---data was truncated (10240/18587) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557b56633eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557b56630e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557b5663462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd0dec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd0deca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd0dec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd0dec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b565c9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557b565c9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557b565ae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557b5625de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557b5625db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd0dec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd0dec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd0dec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b5625da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c (2087 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrev8_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrev8_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vrev8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrev8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrev8_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vrev8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrev8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrev8_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vrev8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrev8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrev8_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vrev8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrev8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vrev8_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vrev8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrev8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vrev8_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vrev8.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrev8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vrev8_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vrev8.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrev8.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vrev8_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vrev8.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrev8.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vrev8_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vrev8.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrev8.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vrev8_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vrev8.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vrev8.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vrev8_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vrev8.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vrev8.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vrev8_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vrev8.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback n
# | ...
# `---data was truncated (10240/40795) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557a3e6f7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557a3e6f4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557a3e6f862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1545305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f154535c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1545305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f15452ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557a3e68dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557a3e68da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557a3e6728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557a3e321e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557a3e321b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f15452eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15452ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15452ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557a3e321a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmldav.c (2088 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmldav.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 0, i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vmldava.v16i8(i32, i32, i32, i32, <16 x i8>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 0, i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vmldava.v8i16(i32, i32, i32, i32, <8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load <4 x i32>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 0, i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vmldava.v4i32(i32, i32, i32, i32, <4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_u8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 1, i32 0, i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_u16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 1, i32 0, i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_u32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load <4 x i32>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 1, i32 0, i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaxq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 0, i32 1, i32 %0, <16 x i8> %1, <16 x i8> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaxq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 0, i32 1, i32 %0, <8 x i16> %1, <8 x i16> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaxq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load <4 x i32>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 0, i32 1, i32 %0, <4 x i32> %1, <4 x i32> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 1, i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 1, i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load <4 x i32>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 1, i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaxq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 1, i32 1, i32 %0, <16 x i8> %1, <16 x i8> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaxq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 1, i32 1, i32 %0, <8 x i16> %1, <8 x i16> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaxq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr
# | ...
# `---data was truncated (10240/44315) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000056347c8d7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056347c8d4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056347c8d862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe33161bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe3316725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe33161ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe331603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056347c86dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056347c86da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056347c8528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056347c501e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056347c501b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe331604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe3316050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe3316050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056347c501a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c (2089 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8_v_i8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8_v_i8mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8_v_i8mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8_v_i8m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8_v_i8m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8_v_i8m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8_v_u8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8_v_u8mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = l
# | ...
# `---data was truncated (10240/64341) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d535e1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558d535dee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558d535e262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c67449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c674a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c67449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c67431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d53577bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558d53577a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558d5355c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558d5320be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558d5320bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7c67432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c674330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c674330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d5320ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c (2090 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh    -target-feature +xsfvfexp16e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexp_v_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.sf.vfexp.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexp.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexp_v_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexp_v_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexp_v_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexp_v_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vfexp_v_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 32 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexp_v_f16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(<vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexp_v_f16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(<vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexp_v_f16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(<vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexp_v_f16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 
# | ...
# `---data was truncated (10240/26333) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557745836eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557745833e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055774583762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2ec7449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2ec74a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2ec7449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2ec7431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005577457ccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005577457cca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005577457b18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557745460e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557745460b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2ec7432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2ec74330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2ec74330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557745460a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c (2091 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_f16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_f16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_f16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_i16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_i16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_i16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_u16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_u16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_u16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", 
# | ...
# `---data was truncated (10240/23365) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005617a0a73eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005617a0a70e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005617a0a7462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3a95733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3a9578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3a95733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3a9571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005617a0a09bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005617a0a09a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005617a09ee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005617a069de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005617a069db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3a9571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3a9571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3a9571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005617a069da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c (2092 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf8_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> %0, <vscale x 1 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16>, <vscale x 1 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf4_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> %0, <vscale x 2 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16>, <vscale x 2 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf2_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m1_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> %0, <vscale x 8 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16>, <vscale x 8 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m2_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> %0, <vscale x 16 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16>, <vscale x 16 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m4_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> %0, <vscale x 32 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16>, <vscale x 32 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m8_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> %0, <vscale x 64 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16>, <vscale x 64 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsumu_vs_u16mf4_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i
# | ...
# `---data was truncated (10240/51303) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005616823c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005616823bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005616823c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca3f905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca3f95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca3f905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca3f8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561682358bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561682358a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056168233d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561681fece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561681fecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fca3f8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca3f8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca3f8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561681feca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c (2093 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_f32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_f32m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_i32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_i32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_i32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_i32m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x
# | ...
# `---data was truncated (10240/63177) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055747d271eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055747d26ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055747d27262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a7e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a7e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a7e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a7e91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055747d207bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055747d207a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055747d1ec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055747ce9be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055747ce9bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2a7e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a7e91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a7e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055747ce9ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c (2094 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei8_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_f32m1x2_tu(target("riscv
# | ...
# `---data was truncated (10240/295533) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005633ee23feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005633ee23ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005633ee24062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa140733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa14078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa140733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa14071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005633ee1d5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005633ee1d5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005633ee1ba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005633ede69e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005633ede69b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa14071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa14071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa14071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005633ede69a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c (2095 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559d97690eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559d9768de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559d9769162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd709333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd70938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd709333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd70931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559d97626bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559d97626a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559d9760b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559d972bae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559d972bab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd70931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd70931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd70931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559d972baa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c (2096 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_f32m2x4_tu(target("riscv.vector.tuple", <vs
# | ...
# `---data was truncated (10240/227771) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f91d192eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f91d18fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f91d19362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6d89933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6d8998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6d89933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6d8991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f91d128bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f91d128a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f91d10d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f91cdbce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f91cdbcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6d8991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6d8991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6d8991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f91cdbca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c (2097 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vx_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmul_vv_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmul_vx_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmul_vv_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmul_vx_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmul_vv_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmul_vx_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = all
# | ...
# `---data was truncated (10240/41587) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055622cf2deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055622cf2ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055622cf2e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f512b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f512b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f512b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f512b91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055622cec3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055622cec3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055622cea88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055622cb57e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055622cb57b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f512b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f512b91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f512b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055622cb57a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c (2098 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i32> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i32> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i
# | ...
# `---data was truncated (10240/13153) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555a56b95eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555a56b92e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555a56b9662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f94d6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f94d6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f94d6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f94d6b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555a56b2bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555a56b2ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555a56b108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555a567bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555a567bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f94d6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f94d6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f94d6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555a567bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c (2099 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei16_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei16_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei16_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei16_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei16_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vloxei16_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, <vscale x 32 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei16_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei16_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei16_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <v
# | ...
# `---data was truncated (10240/280163) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dfb85aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dfb85a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dfb85ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe945f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe945f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe945f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe945f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dfb8540bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dfb8540a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dfb85258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dfb81d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dfb81d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe945f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe945f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe945f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dfb81d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c (2100 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdivu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdivu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdivu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdivu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdivu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdivu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdivu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdivu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdivu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vdivu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vdivu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdivu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vdivu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vdivu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vdivu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/97913) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dfe0a72eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dfe0a6fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dfe0a7362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdaf4a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdaf4aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdaf4a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdaf4a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dfe0a08bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dfe0a08a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dfe09ed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dfe069ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dfe069cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdaf4a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdaf4a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdaf4a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dfe069ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c (2101 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f16m1x7(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f32m1x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f64m1x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei8_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vsca
# | ...
# `---data was truncated (10240/61665) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005562b7f2eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005562b7f2be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005562b7f2f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb251d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb251d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb251d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb251d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005562b7ec4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005562b7ec4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005562b7ea98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005562b7b58e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005562b7b58b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb251d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb251d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb251d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005562b7b58a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c (2102 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf4_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf4_i32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vsext_vf4_i32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vsext_vf4_i32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf4_i64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf4_i64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf4_i64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf4_i64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i32> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/39922) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a132ffceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a132ff9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a132ffd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f20fd733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f20fd78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f20fd733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f20fd71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a132f92bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a132f92a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a132f778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a132c26e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a132c26b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f20fd71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f20fd71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f20fd71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a132c26a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c (2103 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4asu_vx_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4asu_vx_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Fu
# | ...
# `---data was truncated (10240/25086) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559b7afdaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559b7afd7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559b7afdb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffa51f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffa51f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffa51f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffa51f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559b7af70bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559b7af70a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559b7af558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559b7ac04e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559b7ac04b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffa51f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffa51f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffa51f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559b7ac04a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c (2104 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vminu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vminu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vminu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vminu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vminu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vminu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vminu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vminu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vminu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vminu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vminu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/97913) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e397effeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e397efce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e397f0062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5a21705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5a2175c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5a21705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5a216ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e397e95bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e397e95a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e397e7a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e397b29e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e397b29b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5a216eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5a216ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5a216ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e397b29a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c (2105 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16mf4x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16mf2x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16m1x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16m2x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16m4x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("risc
# | ...
# `---data was truncated (10240/14659) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e559591eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e55958ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e55959262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f92ccb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f92ccb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f92ccb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f92ccaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e559527bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e559527a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e55950c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e5591bbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e5591bbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f92ccaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f92ccaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f92ccaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e5591bba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c (2106 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8ff_v_i8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8ff_v_i8mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8ff_v_i8mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8ff_v_i8m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8ff_v_i8m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8ff_v_i8m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue
# | ...
# `---data was truncated (10240/81764) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562f55c8beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562f55c88e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562f55c8c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2983249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f29832a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2983249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2983231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562f55c21bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562f55c21a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562f55c068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562f558b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562f558b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2983232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f29832330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f29832330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562f558b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c (2107 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_bf16mf4x8(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_bf16mf2x8(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_bf16m1x8(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005581c83e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005581c83e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005581c83e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe8f6c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe8f6ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe8f6c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe8f6c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005581c837abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005581c837aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005581c835f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005581c800ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005581c800eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe8f6c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe8f6c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe8f6c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005581c800ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c (2108 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4(<vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2(<vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1(<vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfabs_v_bf16m2(<vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfabs_v_bf16m4(<vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfabs_v_bf16m8(<vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfabs_v_bf16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscal
# | ...
# `---data was truncated (10240/13282) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac0e167eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ac0e164e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ac0e16862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3863533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f386358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3863533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f386351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac0e0fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ac0e0fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ac0e0e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ac0dd91e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ac0dd91b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f386351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f386351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f386351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac0dd91a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c (2109 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabd_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabd_vx_u8mf8(<vscale x 1 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabd_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabd_vx_u8mf4(<vscale x 2 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabd_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabd_vx_u8mf2(<vscale x 4 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabd_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabd_vx_u8m1(<vscale x 8 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabd_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabd_vx_u8m2(<vscale x 16 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vabd_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 
# | ...
# `---data was truncated (10240/97240) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b0b6645eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b0b6642e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b0b664662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb84f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb84f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb84f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb84f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b0b65dbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b0b65dba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b0b65c08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b0b626fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b0b626fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffb84f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb84f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb84f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b0b626fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c (2110 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_bf16m1x
# | ...
# `---data was truncated (10240/25695) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564de134beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564de1348e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564de134c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9e0d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9e0d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9e0d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9e0d431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564de12e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564de12e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564de12c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564de0f75e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564de0f75b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9e0d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9e0d4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9e0d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564de0f75a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c (2111 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei64_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei64_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei64_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei64_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei64_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei64_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei64_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei64_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vloxei64_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %
# | ...
# `---data was truncated (10240/215941) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a9eec33eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a9eec30e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a9eec3462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0687449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f06874a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0687449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0687431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a9eebc9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a9eebc9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a9eebae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a9ee85de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a9ee85db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0687432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f06874330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f06874330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a9ee85da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c (2112 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsbc_vvm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsbc_vxm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsbc_vvm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsbc_vxm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsbc_vvm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsbc_vxm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsbc_vvm_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 8 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 
# | ...
# `---data was truncated (10240/117397) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560d4345aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560d43457e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560d4345b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f529fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f529fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f529fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f529fc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560d433f0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560d433f0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560d433d58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560d43084e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560d43084b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f529fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f529fc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f529fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560d43084a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c (2113 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2ms_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2ms_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2ms_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2ms_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2ms_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2ms_vv_u64m1_tu(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2ms_vv_u64m2_tu(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2ms_vv_u64m4_tu(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscal
# | ...
# `---data was truncated (10240/12235) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563a853bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563a853b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563a853bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8316d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8316d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8316d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8316ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a85352bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563a85352a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563a853378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563a84fe6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563a84fe6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8316ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8316cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8316cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a84fe6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c (2114 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_bf16mf4_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_bf16mf4_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_bf16mf2_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_bf16mf2_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_bf16m1_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_bf16m1_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_bf16m2_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_bf16m2_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc
# | ...
# `---data was truncated (10240/51796) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562830726eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562830723e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056283072762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff942933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff94298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff942933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff94291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005628306bcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005628306bca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005628306a18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562830350e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562830350b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff94291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff94291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff94291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562830350a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c (2115 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnj_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnj_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnj_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnj_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnj_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnj_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnj_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnj_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 
# | ...
# `---data was truncated (10240/65072) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e601aa2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e601a9fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e601aa362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f70f0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f70f058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f70f0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f70f051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e601a38bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e601a38a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e601a1d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e6016cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e6016ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f70f051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f70f051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f70f051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e6016cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c (2116 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vror_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vror_vx_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vror_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vror_vx_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vror_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vror_vx_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vror_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vror_vx_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vror_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vror_vx_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vror_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = al
# | ...
# `---data was truncated (10240/97675) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559021365eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559021362e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055902136662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f54f7105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54f715c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f54f7105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f54f70ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005590212fbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005590212fba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005590212e08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559020f8fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559020f8fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f54f70eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54f70ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54f70ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559020f8fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c (2117 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei32_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba9ea51eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ba9ea4ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ba9ea5262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb252305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb25235c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb252305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb2522ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba9e9e7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ba9e9e7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ba9e9cc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ba9e67be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ba9e67bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb2522eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb2522ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb2522ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba9e67ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c (2118 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf4_i32m1(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf4_i32m2(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vsext_vf4_i32m4(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vsext_vf4_i32m8(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf4_i64m1(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf4_i64m2(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf4_i64m4(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf4_i64m8(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf4_i32m1_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf4_i32m2_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsext.mask.nxv4i32.nxv4i8.i64(<
# | ...
# `---data was truncated (10240/17495) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e02735eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e02735be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e02735f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8eb1305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8eb135c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8eb1305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8eb12ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e0272f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e0272f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e0272d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e026f88e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e026f88b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8eb12eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8eb12ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8eb12ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e026f88a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c (2119 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8(<vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4(<vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2(<vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1(<vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_xu_f_qf_u8m2(<vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | ...
# `---data was truncated (10240/12457) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005647b6509eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005647b6506e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005647b650a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2d03249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2d032a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2d03249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2d03231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005647b649fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005647b649fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005647b64848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005647b6133e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005647b6133b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2d03232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2d032330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2d032330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005647b6133a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c (2120 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_bf16mf4_i8mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_bf16mf2_i8mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_bf16m1_i8mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_bf16m2_i8m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_bf16m4_i8m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_bf16m8_i8m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> poison, <vscale x 32 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_bf16mf4_u8mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_bf16mf2_u8mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_bf16m1_u8mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_bf16m2_u8m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_xu_f_w_bf16m4_u8m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_xu_f_w_bf16m8_u8m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x 
# | ...
# `---data was truncated (10240/59787) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005607d2a1aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005607d2a17e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005607d2a1b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f89c6933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f89c698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f89c6933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f89c691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607d29b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005607d29b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005607d29958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005607d2644e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005607d2644b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f89c691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f89c691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f89c691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607d2644a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c (2121 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556db32d4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556db32d1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556db32d562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9b0a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9b0a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9b0a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9b0a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556db326abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556db326aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556db324f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556db2efee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556db2efeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9b0a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9b0a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9b0a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556db2efea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c (2122 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), pt
# | ...
# `---data was truncated (10240/19484) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b68aa5eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b68aa5be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b68aa5f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcae8249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcae82a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcae8249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcae8231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b68a9f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b68a9f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b68a9d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b68a688e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b68a688b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcae8232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcae82330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcae82330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b68a688a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c (2123 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8(<vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4(<vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2(<vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1(<vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_xu_f_qf_u8m2(<vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscal
# | ...
# `---data was truncated (10240/12471) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a6a86d9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a6a86d6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a6a86da62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f55e2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f55e2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f55e2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f55e2f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a6a866fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a6a866fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a6a86548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a6a8303e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a6a8303b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f55e2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f55e2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f55e2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a6a8303a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c (2124 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_4x8x4_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_4x8x4_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_4x8x4_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_4x8x4_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c225d5deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c225d5ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c225d5e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4c43705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4c4375c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4c43705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4c436ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c225cf3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c225cf3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c225cd88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c225987e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c225987b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4c436eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4c436ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4c436ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c225987a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c (2125 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vctz_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vctz_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vctz.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vctz.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vctz_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vctz.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vctz.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vctz_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vctz.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vctz.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vctz_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vctz.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vctz.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vctz_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vctz.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vctz.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vctz_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vctz.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vctz.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vctz_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vctz.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vctz.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vctz_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vctz.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vctz.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vctz_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vctz.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vctz.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vctz_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vctz.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vctz.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vctz_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vctz.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vctz.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vctz_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vctz.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | ...
# `---data was truncated (10240/40669) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558837a4eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558837a4be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558837a4f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2715533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f271558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2715533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f271551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005588379e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005588379e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005588379c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558837678e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558837678b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f271551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f271551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f271551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558837678a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c (2126 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_f64m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_f64m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_i64m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_i64m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_u64m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_u64m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_i64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_i64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64
# | ...
# `---data was truncated (10240/14036) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555604d63eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555604d60e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555604d6462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3551f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3551f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3551f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3551f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555604cf9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555604cf9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555604cde8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055560498de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055560498db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3551f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3551f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3551f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055560498da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c (2127 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_s_s_w4_i8m8_i8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.s.s.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.s.s.i64.nxv64i8.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056246061feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056246061ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056246062062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f7a01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f7a0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f7a01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f7a003507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005624605b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005624605b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056246059a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562460249e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562460249b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6f7a004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f7a0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f7a0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562460249a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c (2128 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f16m1x5(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f32m1x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f64m1x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563cd79e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563cd79e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563cd79e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1335b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1335b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1335b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1335aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563cd797bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563cd797ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563cd79608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563cd760fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563cd760fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1335aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1335aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1335aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563cd760fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c (2129 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vgmul_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vgmul_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vgmul_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vgmul_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vgmul_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a051586eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a051583e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a05158762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0fb7049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0fb70a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0fb7049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0fb7031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a05151cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a05151ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a0515018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a0511b0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a0511b0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0fb7032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0fb70330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0fb70330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a0511b0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c (2130 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_i8mf8x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_i8mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e8_v_i8mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e8_v_i8m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_u8mf8x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_u8mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e8_v_u8mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e8_v_u8m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_i8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 
# | ...
# `---data was truncated (10240/19037) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559a6797ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559a67979e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559a6797d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f52c7905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f52c795c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f52c7905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f52c78ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a67912bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559a67912a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559a678f78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559a675a6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559a675a6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f52c78eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f52c78ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f52c78ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a675a6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c (2131 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f16m1x5(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f32m1x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f64m1x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i32> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005607dc52aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005607dc527e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005607dc52b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe1b2449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe1b24a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe1b2449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe1b2431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607dc4c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005607dc4c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005607dc4a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005607dc154e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005607dc154b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe1b2432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe1b24330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe1b24330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607dc154a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c (2132 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8mf8x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8mf8x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @
# | ...
# `---data was truncated (10240/23479) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557f1306eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557f1306be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557f1306f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1ba9505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1ba955c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1ba9505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1ba94ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f13004bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557f13004a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557f12fe98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557f12c98e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557f12c98b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1ba94eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1ba94ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1ba94ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f12c98a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c (2133 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f16m1x4(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f16m2x4(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f32m1x4(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f32m2x4(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f64m1x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64
# | ...
# `---data was truncated (10240/99178) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056506ce57eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056506ce54e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056506ce5862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec91933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec9198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec91933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec9191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056506cdedbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056506cdeda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056506cdd28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056506ca81e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056506ca81b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fec9191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec9191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec9191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056506ca81a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c (2134 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_i8mf8x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_i8mf4x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_i8mf2x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8_v_i8m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_u8mf8x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_u8mf4x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_u8mf2x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8_v_u8m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_i8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_i8mf2x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = c
# | ...
# `---data was truncated (10240/16451) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559bdfb3beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559bdfb38e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559bdfb3c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff094d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff094d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff094d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff094d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559bdfad1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559bdfad1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559bdfab68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559bdf765e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559bdf765b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff094d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff094d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff094d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559bdf765a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c (2135 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlse16_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vlse.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vlse.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlse16_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vlse.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vlse.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlse16_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vlse.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vlse.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlse16_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vlse.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vlse.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlse16_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vlse.nxv16bf16.p0.i64(<vscale x 16 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vlse.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlse16_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vlse.nxv32bf16.p0.i64(<vscale x 32 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vlse.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlse16_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlse16_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlse16_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load p
# | ...
# `---data was truncated (10240/28353) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dd8a0f0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dd8a0ede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dd8a0f162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3e4d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3e4d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3e4d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3e4d71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd8a086bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dd8a086a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dd8a06b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dd89d1ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dd89d1ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3e4d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3e4d71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3e4d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd89d1aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c (2136 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_bf16mf4_i8mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_bf16mf2_i8mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_bf16m1_i8mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_bf16m2_i8m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_bf16m4_i8m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_bf16m8_i8m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> poison, <vscale x 32 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_bf16mf4_u8mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_bf16mf2_u8mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_bf16m1_u8mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_bf16m2_u8m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_xu_f_w_bf16m4_u8m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_xu_f_w_bf16m8_u8m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llv
# | ...
# `---data was truncated (10240/59779) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d45dc7aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d45dc77e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d45dc7b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc10dc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc10dc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc10dc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc10dc03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d45dc10bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d45dc10a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d45dbf58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d45d8a4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d45d8a4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc10dc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc10dc050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc10dc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d45d8a4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c (2137 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1down_vf_bf16mf4(<vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1down_vf_bf16mf2(<vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1down_vf_bf16m1(<vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfslide1down_vf_bf16m2(<vscale x 8 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfslide1down_vf_bf16m4(<vscale x 16 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfslide1down_vf_bf16m8(<vscale x 32 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1down_vf_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1down_vf_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1down_vf_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.
# | ...
# `---data was truncated (10240/14900) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005614fffb8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005614fffb5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005614fffb962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a40449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a404a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a40449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a40431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005614fff4ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005614fff4ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005614fff338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005614ffbe2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005614ffbe2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2a40432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a404330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a404330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005614ffbe2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c (2138 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_f32m2x3_tu(target("riscv.vector.tuple", <vscale x 1
# | ...
# `---data was truncated (10240/227763) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005581b57abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005581b57a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005581b57ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9a20933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9a2098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9a20933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9a2091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005581b5741bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005581b5741a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005581b57268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005581b53d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005581b53d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9a2091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9a2091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9a2091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005581b53d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c (2139 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_i16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_i16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 
# | ...
# `---data was truncated (10240/80500) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055874c7abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055874c7a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055874c7ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f074401bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f07440725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f074401ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0744003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055874c741bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055874c741a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055874c7268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055874c3d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055874c3d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0744004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f07440050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f07440050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055874c3d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c (2140 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_i16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_i16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_i16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_u16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_u16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_u16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ta
# | ...
# `---data was truncated (10240/47488) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560e2f9c9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560e2f9c6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560e2f9ca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8990049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f89900a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8990049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8990031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e2f95fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560e2f95fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560e2f9448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560e2f5f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560e2f5f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8990032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f89900330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f89900330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e2f5f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqdmulhq.c (2141 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqdmulhq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmulhq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vqdmulh.v16i8(<16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vqdmulh.v16i8(<16 x i8>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmulhq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vqdmulh.v8i16(<8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vqdmulh.v8i16(<8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulhq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vqdmulh.v4i32(<4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vqdmulh.v4i32(<4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmulhq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.qdmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.qdmulh.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmulhq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.qdmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.qdmulh.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulhq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.qdmulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.qdmulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmulhq_n_s8(<16 x i8> noundef %a, i8 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = call <16 x i8> @llvm.arm.mve.vqdmulh.v16i8(<16 x i8> %0, <16 x i8> %.splat)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmulhq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = call <8 x i16> @llvm.arm.mve.vqdmulh.v8i16(<8 x i16> %0, <8 x i16> %.splat)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulhq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = call <4 x i32> @llvm.arm.mve.vqdmulh.v4i32(<4 x i32> %0, <4 x i32> %.splat)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmulhq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.qdmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmulhq_m_n_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.qdmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs:
# | ...
# `---data was truncated (10240/11849) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564044b42eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564044b3fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564044b4362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f34e2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f34e2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f34e2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f34e2f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564044ad8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564044ad8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564044abd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056404476ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056404476cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f34e2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f34e2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f34e2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056404476ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c (2142 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f56297ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f562979e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f56297d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbb3e61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbb3e6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbb3e61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbb3e603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f562912bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f562912a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f5628f78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f5625a6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f5625a6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbb3e604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbb3e6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbb3e6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f5625a6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c (2143 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vghsh_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vghsh_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vghsh_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vghsh_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vghsh_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005610b9d82eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005610b9d7fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005610b9d8362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac31449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac314a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac31449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac31431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005610b9d18bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005610b9d18a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005610b9cfd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005610b99ace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005610b99acb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fac31432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac314330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac314330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005610b99aca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c (2144 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm3c_vi_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm3c_vi_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm3c_vi_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm3c_vi_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm3c_vi_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563325a26eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563325a23e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563325a2762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2452f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2452f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2452f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2452f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005633259bcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005633259bca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005633259a18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563325650e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563325650b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2452f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2452f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2452f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563325650a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c (2145 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_f32mf2x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_f32m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_i32mf2x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_i32m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_u32mf2x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_u32m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_i32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_i32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_u32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8
# | ...
# `---data was truncated (10240/12059) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b674e85eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b674e82e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b674e8662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f823b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f823b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f823b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f823b71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b674e1bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b674e1ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b674e008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b674aafe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b674aafb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f823b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f823b71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f823b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b674aafa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c (2146 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nx
# | ...
# `---data was truncated (10240/18660) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559ccdf95eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559ccdf92e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559ccdf9662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0edbe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0edbea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0edbe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0edbe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559ccdf2bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559ccdf2ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559ccdf108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559ccdbbfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559ccdbbfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0edbe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0edbe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0edbe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559ccdbbfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm-cde-vec.c (2147 of 27911)
******************** TEST 'Clang :: CodeGen/arm-cde-vec.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi    -target-feature +cdecp0 -target-feature +cdecp1    -target-feature +mve.fp    -mfloat-abi hard -O0 -disable-O0-optnone    -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +cdecp1 -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx1q_u8() #0 {
# | entry:
# |   %0 = call <16 x i8> @llvm.arm.cde.vcx1q(i32 0, i32 1111)
# |   ret <16 x i8> %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.cde.vcx1q(i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx1qa_1(<16 x i8> noundef %acc) #0 {
# | entry:
# |   %acc.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %acc, ptr %acc.addr, align 8
# |   %0 = load <16 x i8>, ptr %acc.addr, align 8
# |   %1 = call <16 x i8> @llvm.arm.cde.vcx1qa(i32 1, <16 x i8> %0, i32 1112)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.cde.vcx1qa(i32 immarg, <16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcx1qa_2(<4 x i32> noundef %acc) #0 {
# | entry:
# |   %acc.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %acc, ptr %acc.addr, align 8
# |   %0 = load <4 x i32>, ptr %acc.addr, align 8
# |   %1 = bitcast <4 x i32> %0 to <16 x i8>
# |   %2 = call <16 x i8> @llvm.arm.cde.vcx1qa(i32 0, <16 x i8> %1, i32 1113)
# |   %3 = bitcast <16 x i8> %2 to <4 x i32>
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx2q_u8(<8 x half> noundef %n) #0 {
# | entry:
# |   %n.addr = alloca <8 x half>, align 8
# |   store <8 x half> %n, ptr %n.addr, align 8
# |   %0 = load <8 x half>, ptr %n.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <16 x i8>
# |   %2 = call <16 x i8> @llvm.arm.cde.vcx2q(i32 1, <16 x i8> %1, i32 111)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.cde.vcx2q(i32 immarg, <16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcx2q(<4 x float> noundef %n) #0 {
# | entry:
# |   %n.addr = alloca <4 x float>, align 8
# |   store <4 x float> %n, ptr %n.addr, align 8
# |   %0 = load <4 x float>, ptr %n.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <16 x i8>
# |   %2 = call <16 x i8> @llvm.arm.cde.vcx2q(i32 1, <16 x i8> %1, i32 112)
# |   %3 = bitcast <16 x i8> %2 to <4 x float>
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcx2qa(<4 x float> noundef %acc, <2 x i64> noundef %n) #0 {
# | entry:
# |   %acc.addr = alloca <4 x float>, align 8
# |   %n.addr = alloca <2 x i64>, align 8
# |   store <4 x float> %acc, ptr %acc.addr, align 8
# |   store <2 x i64> %n, ptr %n.addr, align 8
# |   %0 = load <4 x float>, ptr %acc.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <16 x i8>
# |   %2 = load <2 x i64>, ptr %n.addr, align 8
# |   %3 = bitcast <2 x i64> %2 to <16 x i8>
# |   %4 = call <16 x i8> @llvm.arm.cde.vcx2qa(i32 0, <16 x i8> %1, <16 x i8> %3, i32 113)
# |   %5 = bitcast <16 x i8> %4 to <4 x float>
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.cde.vcx2qa(i32 immarg, <16 x i8>, <16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx3q_u8(<8 x i16> noundef %n, <4 x i32> noundef %m) #0 {
# | entry:
# |   %n.addr = alloca <8 x i16>, align 8
# |   %m.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %n, ptr %n.addr, align 8
# |   store <4 x i32> %m, ptr %m.addr, align 8
# |   %0 = load <8 x i16>, ptr %n.addr, align 8
# |   %1 = bitcast <8 x i16> %0 to <16 x i8>
# |   %2 = load <4 x i32>, ptr %m.addr, align 8
# |   %3 = bitcast <4 x i32> %2 to <16 x i8>
# |   %4 = call <16 x i8> @llvm.arm.cde.vcx3q(i32 0, <16 x i8> %1, <16 x i8> %3, i32 11)
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.cde.vcx3q(i32 immarg, <16 x i8>, <16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vcx3q(<2 x i64> noundef %n, <4 x float> noundef %m) #0 {
# | entry:
# |   %n.addr = alloca <2 x i64>, align 8
# |   %m.addr = alloca <4 x float>, align 8
# |   store <2 x i64> %n, ptr %n.addr, align 8
# |   store <4 x float> %m, ptr %m.addr, align 8
# |   %0 = load <2 x i64>, ptr %n.addr, align 8
# |   %1 = bitcast <2 x i64> %0 to <16 x i8>
# |   %2 = load <4 x float>, ptr %m.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <16 x i8>
# |   %4 = call <16 x i8> @llvm.arm.cde.vcx3q(i32 1, <16 x i8> %1, <16 x i8> %3, i32 12)
# |   %5 = bitcast <16 x i8> %4 to <2 x i64>
# |   ret <2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx3qa(<16 x i8> noundef %acc, <8 x i16> noundef %n, <4 x float> noundef %m) #0 {
# | entry:
# |   %acc.addr = alloca <16 x i8>, align 8
# |   %n.addr = alloca <8 x i16>, align 8
# |   %m.addr = alloca <4 x float>, align 8
# |   store <16 x i8> %acc, ptr %acc.addr, align 8
# |   store <8 x i16> %n, ptr %n.addr, align 8
# |   store <4 x float> %m, ptr %m.addr, align 8
# |   %0 = load <16 x i8>, ptr %acc.addr, align 8
# |   %1 = load <8 x i16>, ptr %n.addr, align 8
# |   %2 = bitcast <8 x i16> %1 to <16 x i8>
# |   %3 = load <4 x float>, ptr %m.addr, align 8
# |   %4 = bitcast <4 x float> %3 to <16 x i8>
# |   %5 = call <16 x i8> @llvm.arm.cde.vcx3qa(i32 1, <16 x i8> %0, <16 x i8> %2, <16 x i8> %4, i32 13)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.cde.vcx3qa(i32 immarg, <16 x i8>, <16 x i8>, <16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcx1q_m(<8 x i16> noundef %inactive, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = call <8 x i16> @llvm.arm.cde.vcx1q.predicated.v8i16.v8i1(i32 0, <8 x i16> %0, i32 1111, <8 x i1> %3)
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.cde.vcx1q.predicated.v8i16.v8i1(i32 immarg, <8 x i16>, i32 immarg, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx1qa_m(<16 x i8> noundef %acc, i16 noundef zeroext %p) #0 {
# | entry:
# |   %acc.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %acc, ptr %acc.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %acc.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = call <16 x i8> @llvm.arm.cde.vcx1qa.predicated.v16i8.v16i1(i32 1, <16 x i8> %0, i32 1112, <16 x i1> %3)
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.cde.vcx1qa.predicated.v16i8.v16i1(i32 immarg, <16 x i8>, i32 immarg, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcx2q_m(<4 x i32> noundef %inactive, <4 x float> noundef %n, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %n.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %n, ptr %n.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x float>, ptr %n.addr, align 8
# |   %2 = bitcast <4 x float> %1 to <16 x i8>
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call <4 x i32> @llvm.arm.cde.vcx2q.predicated.v4i32.v4i1(i32 0, <4 x i32> %0, <16 x i8> %2, i32 111, <4 x i1> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.cde.vcx2q.predicated.v4i32.v4i1(i32 immarg, <4 x i32>, <16 x i8>, i32 immarg, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcx2qa_m(<4 x float> noundef %acc, <8 x half> noundef %n, i16 noundef zeroext %p) #0 {
# | entry:
# |   %acc.addr = alloca <4 x float>, align 8
# |   %n.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %acc, ptr %acc.addr, align 8
# |   store <8 x half> %n, ptr %n.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %acc.addr, align 8
# |   %1 = load <8 x half>, ptr %n.addr, align 8
# |   %2 = bitcast <8 x half> %1 to <16 x i8>
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call <4 x float> @llvm.arm.cde.vcx2qa.predicated.v4f32.v4i1(i32 0, <4 x float> %0, <16 x i8> %2, i32 112, <4 x i1> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.cde.vcx2qa.predicated.v4f32.v4i1(i32 immarg, <4 x float>, <16 x i8>, i32 immarg, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vcx3q_m(<2 x i64> noundef %inactive, <4 x float> noundef %n, <16 x i8> noundef %m, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <2 x i64>, align 8
# |   %n.addr = alloca <4 x float>, align 8
# |   %m.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <2 x i64> %inactive, ptr %inactive.addr, align 8
# | ...
# `---data was truncated (10240/13030) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056452fe2eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056452fe2be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056452fe2f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb9f9333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb9f938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb9f9333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb9f931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056452fdc4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056452fdc4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056452fda98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056452fa58e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056452fa58b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb9f931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb9f931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb9f931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056452fa58a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c (2148 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# | ...
# `---data was truncated (10240/18506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558463f77eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558463f74e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558463f7862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd128933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd12898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd128933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd12891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558463f0dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558463f0da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558463ef28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558463ba1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558463ba1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd12891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd12891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd12891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558463ba1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c (2149 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f16m1x3(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_f16m2x3(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f32m1x3(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_f32m2x3(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f64m1x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), p
# | ...
# `---data was truncated (10240/87316) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563623d72eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563623d6fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563623d7362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc118933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc11898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc118933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc11891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563623d08bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563623d08a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563623ced8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056362399ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056362399cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc11891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc11891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc11891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056362399ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c (2150 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vror_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vror_vx_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vror_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vror_vx_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vror_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vror_vx_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vror_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vror_vx_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vror_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vror_vx_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vror_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.a
# | ...
# `---data was truncated (10240/97683) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559325b27eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559325b24e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559325b2862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f66bdc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f66bdc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f66bdc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f66bdc03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559325abdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559325abda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559325aa28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559325751e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559325751b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f66bdc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f66bdc050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f66bdc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559325751a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c (2151 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_u64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_u64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tu
# | ...
# `---data was truncated (10240/16560) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb9b1cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fb9b1c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fb9b1cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5454249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54542a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5454249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5454231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb9b161bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fb9b161a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fb9b1468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fb9adf5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fb9adf5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5454232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54542330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54542330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb9adf5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c (2152 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_f32mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_f32m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_i32mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_i32m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_u32mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_u32m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs:
# | ...
# `---data was truncated (10240/16382) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b3ee41feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b3ee41ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b3ee42062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5125133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f512518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5125133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f512511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b3ee3b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b3ee3b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b3ee39a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b3ee049e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b3ee049b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f512511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f512511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f512511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b3ee049a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c (2153 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vremu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vremu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vremu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vremu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vremu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vremu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vremu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vremu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vremu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op
# | ...
# `---data was truncated (10240/222917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561e5848beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561e58488e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561e5848c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f52c2d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f52c2d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f52c2d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f52c2d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561e58421bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561e58421a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561e584068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561e580b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561e580b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f52c2d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f52c2d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f52c2d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561e580b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c (2154 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f16m1x7(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f32m1x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f64m1x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei32_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005588c5366eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005588c5363e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005588c536762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb0f7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb0f778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb0f7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb0f771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005588c52fcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005588c52fca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005588c52e18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005588c4f90e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005588c4f90b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb0f771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb0f771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb0f771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005588c4f90a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c (2155 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsqrt_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsqrt_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsqrt_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsqrt_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsqrt_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfsqrt_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfsqrt_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfsqrt_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfsqrt_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfsqrt_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, al
# | ...
# `---data was truncated (10240/128416) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fba13c7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fba13c4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fba13c862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9ebd533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9ebd58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9ebd533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9ebd51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fba135dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fba135da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fba13428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fba0ff1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fba0ff1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9ebd51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9ebd51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9ebd51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fba0ff1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcmlaq.c (2156 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcmlaq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load <8 x half>, ptr %c.addr, align 8
# |   %3 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 0, <8 x half> %0, <8 x half> %1, <8 x half> %2)
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32, <8 x half>, <8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store <4 x float> %c, ptr %c.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load <4 x float>, ptr %c.addr, align 8
# |   %3 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 0, <4 x float> %0, <4 x float> %1, <4 x float> %2)
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32, <4 x float>, <4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot90_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load <8 x half>, ptr %c.addr, align 8
# |   %3 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 1, <8 x half> %0, <8 x half> %1, <8 x half> %2)
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot90_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store <4 x float> %c, ptr %c.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load <4 x float>, ptr %c.addr, align 8
# |   %3 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 1, <4 x float> %0, <4 x float> %1, <4 x float> %2)
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot180_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load <8 x half>, ptr %c.addr, align 8
# |   %3 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 2, <8 x half> %0, <8 x half> %1, <8 x half> %2)
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot180_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store <4 x float> %c, ptr %c.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load <4 x float>, ptr %c.addr, align 8
# |   %3 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 2, <4 x float> %0, <4 x float> %1, <4 x float> %2)
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot270_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load <8 x half>, ptr %c.addr, align 8
# |   %3 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 3, <8 x half> %0, <8 x half> %1, <8 x half> %2)
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot270_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store <4 x float> %c, ptr %c.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load <4 x float>, ptr %c.addr, align 8
# |   %3 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 3, <4 x float> %0, <4 x float> %1, <4 x float> %2)
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_m_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load <8 x half>, ptr %c.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
# |   %6 = call <8 x half> @llvm.arm.mve.vcmlaq.predicated.v8f16.v8i1(i32 0, <8 x half> %0, <8 x half> %1, <8 x half> %2, <8 x i1> %5)
# |   ret <8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vcmlaq.predicated.v8f16.v8i1(i32, <8 x half>, <8 x half>, <8 x half>, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store <4 x float> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load <4 x float>, ptr %c.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call <4 x float> @llvm.arm.mve.vcmlaq.predicated.v4f32.v4i1(i32 0, <4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x i1> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vcmlaq.predicated.v4f32.v4i1(i32, <4 x float>, <4 x float>, <4 x float>, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot90_m_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load <8 x half>, ptr %c.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
# |   %6 = call <8 x half> @llvm.arm.mve.vcmlaq.predicated.v8f16.v8i1(i32 1, <8 x half> %0, <8 x half> %1, <8 x half> %2, <8 x i1> %5)
# |   ret <8 x half> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot90_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store <4 x float> %
# | ...
# `---data was truncated (10240/15051) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559e7e2cceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559e7e2c9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559e7e2cd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb868a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb868aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb868a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb868a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e7e262bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559e7e262a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559e7e2478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559e7def6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559e7def6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb868a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb868a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb868a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e7def6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c (2157 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vclz_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vclz_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vclz.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vclz.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vclz_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vclz.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vclz.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vclz_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vclz.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vclz.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vclz_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vclz.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vclz.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vclz_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vclz.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vclz.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vclz_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vclz.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vclz.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vclz_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vclz.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vclz.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vclz_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vclz.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vclz.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vclz_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vclz.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vclz.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test
# | ...
# `---data was truncated (10240/94993) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563fa95f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563fa95f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563fa95f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4bc0b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4bc0b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4bc0b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4bc0b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563fa958ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563fa958ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563fa95738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563fa9222e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563fa9222b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4bc0b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4bc0b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4bc0b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563fa9222a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c (2158 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055df71c18eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055df71c15e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055df71c1962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1426733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f142678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1426733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f142671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055df71baebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055df71baea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055df71b938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055df71842e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055df71842b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f142671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f142671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f142671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055df71842a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c (2159 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_f32m2x3_tu(target("riscv.vector.tuple", <vs
# | ...
# `---data was truncated (10240/227771) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562d702cfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562d702cce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562d702d062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce3e21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce3e2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce3e21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce3e203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d70265bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562d70265a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562d7024a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562d6fef9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562d6fef9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fce3e204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce3e2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce3e2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d6fef9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c (2160 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16mf4x4(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16mf2x4(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16m1x4(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16m2x4(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwin
# | ...
# `---data was truncated (10240/10798) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005603642daeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005603642d7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005603642db62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe342c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe342ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe342c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe342c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560364270bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560364270a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005603642558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560363f04e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560363f04b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe342c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe342c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe342c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560363f04a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c (2161 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_i8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e8_v_i8mf2x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e8_v_i8m1x5_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_u8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_u8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e8_v_u8mf2x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e8_v_u8m1x5_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv8i1(target("riscv.vector.tup
# | ...
# `---data was truncated (10240/11031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a70d820eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a70d81de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a70d82162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd5fc449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd5fc4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd5fc449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd5fc431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a70d7b6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a70d7b6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a70d79b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a70d44ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a70d44ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd5fc432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd5fc4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd5fc4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a70d44aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c (2162 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei8_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %m
# | ...
# `---data was truncated (10240/160133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005606bb8d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005606bb8d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005606bb8d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f45a8e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f45a8ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f45a8e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f45a8e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005606bb86ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005606bb86ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005606bb8538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005606bb502e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005606bb502b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f45a8e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f45a8e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f45a8e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005606bb502a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c (2163 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlsseg4e8_v_i8mf8x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e8_v_i8mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e8_v_i8mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e8_v_i8m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e8_v_i8m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlsseg4e8_v_u8mf8x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e8_v_u8mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e8_v_u8mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e8_v_u8m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e8_v_u8m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_
# | ...
# `---data was truncated (10240/23574) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f7445a0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f74459de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f7445a162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb49e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb49e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb49e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb49e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f744536bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f744536a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f74451b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f7441cae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f7441cab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feb49e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb49e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb49e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f7441caa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c (2164 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmerge_vfm_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmerge_vfm_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmerge_vfm_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmerge_vfm_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmerge_vfm_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, half noundef %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4)
# |   ret <vscale x 16 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfmerge_vfm_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, half noundef %op2, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, <vscale x 32 x i1> %3, i64 %4)
# |   ret <vscale x 32 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfmerge_vfm_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, float noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: 
# | ...
# `---data was truncated (10240/22367) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056042e839eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056042e836e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056042e83a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f26449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f264a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f26449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f26431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056042e7cfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056042e7cfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056042e7b48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056042e463e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056042e463b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4f26432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f264330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f264330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056042e463a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c (2165 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgatherei16_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgatherei16_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgatherei16_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgatherei16_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgatherei16_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vrgatherei16_vv_f16m8(<vscale x 32 x half> %op1, <vscale x 32 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 32 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vrgatherei16_vv_f32mf2(<vscale x 1 x float> %op1, <vscale x 1 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vrgatherei16_vv_f32m1(<vscale x 2 x float> %op1, <vscale x 2 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vrgatherei16.vv.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vrgatherei16.vv.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vrgatherei16_vv_f32m2(<vscale x 4 x float> %op1, <vscale x 4 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %op2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 4 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vrgatherei16.vv.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vrgatherei16.vv.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vrgatherei16_vv_f32m4(<vscale x 8 x float> %op1, <vscale x 8 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %op2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store <vscal
# | ...
# `---data was truncated (10240/124036) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d4b8645eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d4b8642e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d4b864662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5403c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5403ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5403c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5403c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d4b85dbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d4b85dba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d4b85c08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d4b826fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d4b826fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5403c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5403c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5403c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d4b826fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c (2166 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_i16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_i16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_i16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_u16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_u16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6),
# | ...
# `---data was truncated (10240/53330) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f34c108eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f34c105e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f34c10962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbcb9305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbcb935c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbcb9305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbcb92ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f34c09ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f34c09ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f34c0838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f34bd32e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f34bd32b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbcb92eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbcb92ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbcb92ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f34bd32a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c (2167 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4au_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4au_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr
# | ...
# `---data was truncated (10240/14461) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561ca0a04eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561ca0a01e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561ca0a0562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff6cd133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff6cd18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff6cd133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff6cd11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561ca099abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561ca099aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561ca097f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561ca062ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561ca062eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff6cd11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff6cd11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff6cd11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561ca062ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c (2168 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16mf4(ptr noundef %base, <vscale x 1 x i32> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16mf2(ptr noundef %base, <vscale x 2 x i32> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16m1(ptr noundef %base, <vscale x 4 x i32> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16m2(ptr noundef %base, <vscale x 8 x i32> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16m4(ptr noundef %base, <vscale x 16 x i32> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f32mf2(ptr noundef %base, <vscale x 1 x i32> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f32m1(ptr noundef %base, <vscale x 2 x i32> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f32m2(ptr noundef %base, <vscale x 4 x i32> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f32m4(ptr noundef %base, <vscale x 8 x i32> %bindex, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   re
# | ...
# `---data was truncated (10240/120915) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055592470ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555924709e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055592470d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6636249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f66362a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6636249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6636231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005559246a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005559246a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005559246878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555924336e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555924336b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6636232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f66362330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f66362330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555924336a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c (2169 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_f64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_f64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_i64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_i64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_u64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_u64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_f64m1x3_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_f64m2x3_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %2, <vscale x 2 x i1> 
# | ...
# `---data was truncated (10240/32133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056325c905eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056325c902e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056325c90662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5c3d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5c3d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5c3d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5c3d31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056325c89bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056325c89ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056325c8808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056325c52fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056325c52fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5c3d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5c3d31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5c3d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056325c52fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vhsubq.c (2170 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vhsubq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhsubq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vhsub.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vhsub.v16i8(<16 x i8>, <16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhsubq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vhsub.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vhsub.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhsubq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vhsub.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vhsub.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhsubq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.hsub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.hsub.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhsubq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.hsub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.hsub.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhsubq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.hsub.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.hsub.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhsubq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = call <16 x i8> @llvm.arm.mve.vhsub.v16i8(<16 x i8> %0, <16 x i8> %.splat, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhsubq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = call <8 x i16> @llvm.arm.mve.vhsub.v8i16(<8 x i16> %0, <8 x i16> %.splat, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhsubq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = call <4 x i32> @llvm.arm.mve.vhsub.v4i32(<4 x i32> %0, <4 x i32> %.splat, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhsubq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.hsub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhsubq_m_n_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.hsub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, i32 1, <8 x i1> %4, <8 x i
# | ...
# `---data was truncated (10240/14644) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e98531deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e98531ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e98531e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f20ead33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f20ead8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f20ead33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f20ead1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e9852b3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e9852b3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e9852988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e984f47e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e984f47b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f20ead1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f20ead1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f20ead1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e984f47a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c (2171 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f16m1x5(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f32m1x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f64m1x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei64_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f556611eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f55660ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f55661262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3e91649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3e916a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3e91649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3e91631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f5565a7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f5565a7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f55658c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f55623be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f55623bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3e91632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3e916330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3e916330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f55623ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c (2172 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_i8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e8_v_i8mf2x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e8_v_i8m1x8_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_u8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_u8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e8_v_u8mf2x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e8_v_u8m1x8_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv8i1(target("riscv.vector.tup
# | ...
# `---data was truncated (10240/11031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561d7158beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561d71588e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561d7158c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fde46a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fde46a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fde46a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fde46a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561d71521bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561d71521a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561d715068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561d711b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561d711b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fde46a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fde46a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fde46a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561d711b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/bitwise-imm.c (2173 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/bitwise-imm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_n_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = and <8 x i16> %0, splat (i16 11007)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_n_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = and <4 x i32> %0, splat (i32 -252)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_n_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = and <8 x i16> %0, splat (i16 -243)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_n_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = and <4 x i32> %0, splat (i32 -8193)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_n_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = or <8 x i16> %0, splat (i16 195)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_n_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = or <4 x i32> %0, splat (i32 65536)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_n_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = or <8 x i16> %0, splat (i16 -4096)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_n_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = or <4 x i32> %0, splat (i32 8978432)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_n_s16() #0 {
# | entry:
# |   ret <8 x i16> splat (i16 27391)
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_n_s32() #0 {
# | entry:
# |   ret <4 x i32> splat (i32 -5570561)
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_n_u16() #0 {
# | entry:
# |   ret <8 x i16> splat (i16 -18689)
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_n_u32() #0 {
# | entry:
# |   ret <4 x i32> splat (i32 1023410175)
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_m_n_s16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load <8 x i16>, ptr %a.addr, align 8
# |   %4 = and <8 x i16> %3, splat (i16 -11265)
# |   %5 = select <8 x i1> %2, <8 x i16> %4, <8 x i16> %3
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_n_s32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load <4 x i32>, ptr %a.addr, align 8
# |   %4 = and <4 x i32> %3, splat (i32 -13893633)
# |   %5 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %3
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_m_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load <8 x i16>, ptr %a.addr, align 8
# |   %4 = and <8 x i16> %3, splat (i16 -37)
# |   %5 = select <8 x i1> %2, <8 x i16> %4, <8 x i16> %3
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_n_u32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load <4 x i32>, ptr %a.addr, align 8
# |   %4 = and <4 x i32> %3, splat (i32 -1644167169)
# |   %5 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %3
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_m_n_s16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load <8 x i16>, ptr %a.addr, align 8
# |   %4 = or <8 x i16> %3, splat (i16 13568)
# |   %5 = select <8 x i1> %2, <8 x i16> %4, <8 x i16> %3
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_n_s32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load <4 x i32>, ptr %a.addr, align 8
# |   %4 = or <4 x i32> %3, splat (i32 654311424)
# |   %5 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %3
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_m_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load <8 x i16>, ptr %a.addr, align 8
# |   %4 = or <8 x i16> %3, splat (i16 175)
# |   %5 = select <8 x i1> %2, <8 x i16> %4, <8 x i16> %3
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_n_u32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load <4 x i32>, ptr %a.addr, align 8
# |   %4 = or <4 x i32> %3, splat (i32 89)
# |   %5 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %3
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_n_s16(<8 x i16> noundef %inactive, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %4 = select <8 x i1> %2, <8 x i16> splat (i16 -3841), <8 x i16> %3
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_m_n_s32(<4 x i32> noundef %inactive, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %4 = select <4 x i1> %2, <4 x i32> splat (i32 -18945), <4 x i32> %3
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_n_u16(<8 x i16> noundef %inactive, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %4 = select <8 x i1> %
# | ...
# `---data was truncated (10240/13125) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b767564eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b767561e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b76756562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb1b9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb1b998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb1b9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb1b991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b7674fabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b7674faa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b7674df8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b76718ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b76718eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb1b991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb1b991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb1b991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b76718ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c (2174 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vslide1up_vx_i8mf8(<vscale x 1 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vslide1up_vx_i8mf4(<vscale x 2 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vslide1up_vx_i8mf2(<vscale x 4 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vslide1up_vx_i8m1(<vscale x 8 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vslide1up_vx_i8m2(<vscale x 16 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vslide1up_vx_i8m4(<vscale x 32 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vslide1up_vx_i8m8(<vscale x 64 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vslide1up_vx_i16mf4(<vscale x 1 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vslide1up_vx_i16mf2(<vscale x 2 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vslide1up.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vslide1up.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vslide1up_vx_i16m1(<vscale x 4 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vslide1up.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vslide1up.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vslide1up_vx_i16m2(<vscale x 8 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %v
# | ...
# `---data was truncated (10240/86747) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561776b13eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561776b10e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561776b1462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbafeb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbafeb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbafeb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbafeb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561776aa9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561776aa9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561776a8e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056177673de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056177673db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbafeb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbafeb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbafeb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056177673da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c (2175 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei64_v_i8mf8x8
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d8823a3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d8823a0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d8823a462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fed6e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fed6e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fed6e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fed6e231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d882339bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d882339a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d88231e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d881fcde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d881fcdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fed6e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fed6e2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fed6e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d881fcda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c (2176 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_bf16m1x4_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: n
# | ...
# `---data was truncated (10240/22107) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ced5f6eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ced5f6be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ced5f6f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa204133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa20418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa204133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa20411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ced5f04bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ced5f04a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ced5ee98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ced5b98e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ced5b98b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa20411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa20411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa20411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ced5b98a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c (2177 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmxor_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmxor.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmxor.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmxor_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmxor.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmxor.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmxor_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmxor.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmxor.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmxor_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmxor.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmxor.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmxor_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmxor.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmxor.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmxor_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmxor.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmxor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmxor_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmxor.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmxor.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c5ae24eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563c5ae21e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563c5ae2562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faf99e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faf99ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faf99e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faf99e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c5adbabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563c5adbaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563c5ad9f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563c5aa4ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563c5aa4eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faf99e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faf99e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faf99e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c5aa4ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c (2178 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16ff_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16ff_v_bf16m4x2_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b89b8efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b89b8ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b89b8f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd1ba21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd1ba2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd1ba21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd1ba203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b89b885bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b89b885a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b89b86a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b89b519e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b89b519b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd1ba204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd1ba2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd1ba2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b89b519a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c (2179 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m4_bf16m8(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x i8> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x i8> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vsca
# | ...
# `---data was truncated (10240/24214) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b79c6fdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b79c6fae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b79c6fe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb235f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb235f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb235f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb235f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b79c693bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b79c693a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b79c6788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b79c327e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b79c327b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb235f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb235f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb235f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b79c327a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c (2180 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_i8mf8x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_i8mf4x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_i8mf2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8_v_i8m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8_v_i8m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_u8mf8x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_u8mf4x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_u8mf2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8_v_u8m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8_v_u8m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_i8mf8x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_i8mf4x3_m(<vscale x 2 x i1> %mask, ptr noundef %bas
# | ...
# `---data was truncated (10240/20340) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bf6a2faeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bf6a2f7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bf6a2fb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fef46d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fef46d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fef46d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fef46d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bf6a290bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bf6a290a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bf6a2758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bf69f24e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bf69f24b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fef46d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fef46d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fef46d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bf69f24a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c (2181 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpaire_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vpaire.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpaire.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpaire_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vpaire.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpaire.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpaire_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vpaire.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vpaire.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vpaire_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vpaire.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vpaire.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vpaire_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vpaire.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vpaire.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vpaire_vv_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, <vscale x 32 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vpaire.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vpaire.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpaire_vv_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vpaire.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpaire.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpaire_vv_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, 
# | ...
# `---data was truncated (10240/32646) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560e170c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560e170bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560e170c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc8a2a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc8a2a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc8a2a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc8a2a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e17058bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560e17058a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560e1703d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560e16cece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560e16cecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc8a2a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc8a2a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc8a2a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e16ceca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c (2182 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsaddu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsaddu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsaddu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsaddu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsaddu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsaddu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsaddu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsaddu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsaddu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsaddu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsaddu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsaddu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsaddu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsaddu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsaddu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vsca
# | ...
# `---data was truncated (10240/98171) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e792102eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e7920ffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e79210362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f15dfc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f15dfca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f15dfc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f15dfc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e792098bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e792098a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e79207d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e791d2ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e791d2cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f15dfc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15dfc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15dfc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e791d2ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c (2183 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmul_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmul_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmul_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmul_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmul_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmul_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmul_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmul_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmul_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmul_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmul_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/175163) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005615e16f7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005615e16f4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005615e16f862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2da7933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2da798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2da7933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2da791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005615e168dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005615e168da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005615e16728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005615e1321e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005615e1321b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2da791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2da791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2da791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615e1321a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c (2184 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlsseg4e8_v_i8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e8_v_i8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e8_v_i8mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e8_v_i8m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e8_v_i8m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlsseg4e8_v_u8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e8_v_u8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @
# | ...
# `---data was truncated (10240/60228) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564190bdceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564190bd9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564190bdd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5660249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56602a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5660249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5660231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564190b72bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564190b72a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564190b578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564190806e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564190806b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5660232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56602330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56602330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564190806a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c (2185 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1up_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1up_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1up_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfslide1up_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfslide1up_vf_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfslide1up_vf_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1up_vf_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %3 = load bfloat, ptr %value.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1up_vf_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2
# | ...
# `---data was truncated (10240/32570) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055edd8442eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055edd843fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055edd844362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa909449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa9094a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa909449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa909431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055edd83d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055edd83d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055edd83bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055edd806ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055edd806cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa909432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa9094330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa9094330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055edd806ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c (2186 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei16_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei16_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei16_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei16_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei16_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vloxei16_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, <vscale x 32 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei16_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei16_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captur
# | ...
# `---data was truncated (10240/30617) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559ade295eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559ade292e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559ade29662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fea5f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fea5f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fea5f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fea5f31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559ade22bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559ade22ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559ade2108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559addebfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559addebfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fea5f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fea5f31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fea5f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559addebfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c (2187 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563a1ee2aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563a1ee27e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563a1ee2b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf1c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf1c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf1c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf1c91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a1edc0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563a1edc0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563a1eda58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563a1ea54e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563a1ea54b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdf1c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf1c91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf1c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a1ea54a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c (2188 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b1(ptr noundef %base, <vscale x 64 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 64 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 64 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv64i1.p0.i64(<vscale x 64 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv64i1.p0.i64(<vscale x 64 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b2(ptr noundef %base, <vscale x 32 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv32i1.p0.i64(<vscale x 32 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv32i1.p0.i64(<vscale x 32 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b4(ptr noundef %base, <vscale x 16 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv16i1.p0.i64(<vscale x 16 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv16i1.p0.i64(<vscale x 16 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b8(ptr noundef %base, <vscale x 8 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv8i1.p0.i64(<vscale x 8 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv8i1.p0.i64(<vscale x 8 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b16(ptr noundef %base, <vscale x 4 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv4i1.p0.i64(<vscale x 4 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv4i1.p0.i64(<vscale x 4 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b32(ptr noundef %base, <vscale x 2 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv2i1.p0.i64(<vscale x 2 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv2i1.p0.i64(<vscale x 2 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b64(ptr noundef %base, <vscale x 1 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv1i1.p0.i64(<vscale x 1 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv1i1.p0.i64(<vscale x 1 x i1>, ptr captures(none), i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005637a17c5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005637a17c2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005637a17c662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9494449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f94944a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9494449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9494431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005637a175bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005637a175ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005637a17408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005637a13efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005637a13efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9494432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f94944330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f94944330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005637a13efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c (2189 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558a3ef23eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558a3ef20e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558a3ef2462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1901249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f19012a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1901249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1901231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a3eeb9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558a3eeb9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558a3ee9e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558a3eb4de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558a3eb4db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1901232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f19012330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f19012330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a3eb4da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c (2190 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh    -target-feature +xsfvfexp16e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexp_v_f16mf4(<vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.sf.vfexp.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexp.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexp_v_f16mf2(<vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexp_v_f16m1(<vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexp_v_f16m2(<vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexp_v_f16m4(<vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vfexp_v_f16m8(<vscale x 32 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexp_v_f16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexp_v_f16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexp_v_f16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexp_v_f16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexp_v_f16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.sf.vfexp.mask.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <v
# | ...
# `---data was truncated (10240/12083) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055619ea0ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055619ea09e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055619ea0d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9de8849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9de88a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9de8849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9de8831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055619e9a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055619e9a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055619e9878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055619e636e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055619e636b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9de8832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9de88330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9de88330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055619e636a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c (2191 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_2x8x2_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_2x8x2_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_2x8x2_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_2x8x2_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005567472b4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005567472b1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005567472b562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc7d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc7d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc7d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc7d31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055674724abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055674724aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055674722f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556746edee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556746edeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efc7d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc7d31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc7d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556746edea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c (2192 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei8_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %m
# | ...
# `---data was truncated (10240/160133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056347d6c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056347d6bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056347d6c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f28ba21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f28ba2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f28ba21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f28ba203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056347d658bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056347d658a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056347d63d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056347d2ece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056347d2ecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f28ba204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f28ba2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f28ba2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056347d2eca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics.c (2193 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vabs_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vabs.i = bitcast <8 x i8> %1 to <4 x half>
# |   %vabs1.i = call <4 x half> @llvm.fabs.v4f16(<4 x half> %vabs.i)
# |   store <4 x half> %vabs1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vabsq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vabs.i = bitcast <16 x i8> %1 to <8 x half>
# |   %vabs1.i = call <8 x half> @llvm.fabs.v8f16(<8 x half> %vabs.i)
# |   store <8 x half> %vabs1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %2, ptr %__ret.i, align 16
# |   %3 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vceqz_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp oeq <4 x half> %2, zeroinitializer
# |   %vceqz.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vceqz.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vceqzq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp oeq <8 x half> %2, zeroinitializer
# |   %vceqz.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vceqz.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcgez_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp oge <4 x half> %2, zeroinitializer
# |   %vcgez.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vcgez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcgezq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp oge <8 x half> %2, zeroinitializer
# |   %vcgez.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vcgez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcgtz_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp ogt <4 x half> %2, zeroinitializer
# |   %vcgtz.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vcgtz.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcgtzq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp ogt <8 x half> %2, zeroinitializer
# |   %vcgtz.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vcgtz.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vclez_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp ole <4 x half> %2, zeroinitializer
# |   %vclez.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vclez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vclezq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp ole <8 x half> %2, zeroinitializer
# |   %vclez.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vclez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcltz_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp olt <4 x half> %2, zeroinitializer
# |   %vcltz.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vcltz.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcltzq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp olt <8 x half> %2, zeroinitializer
# |   %vcltz.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vcltz.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vcvt_f16_s16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>,
# | ...
# `---data was truncated (10240/159327) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000556df89fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556df89f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556df89fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3985c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3985c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3985c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3985c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556df8992bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556df8992a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556df89778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556df8626e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556df8626b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3985c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3985c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3985c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556df8626a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c (2194 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_i32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_i32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_u32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_u32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005597511faeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005597511f7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005597511fb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc7f4933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc7f498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc7f4933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc7f491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559751190bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559751190a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005597511758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559750e24e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559750e24b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc7f491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc7f491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc7f491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559750e24a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c (2195 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf8_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf4_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf2_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m1_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m2_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m4_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m8_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16mf4_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync 
# | ...
# `---data was truncated (10240/62063) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e86b162eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e86b15fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e86b16362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1655e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1655ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1655e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1655e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e86b0f8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e86b0f8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e86b0dd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e86ad8ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e86ad8cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1655e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1655e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1655e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e86ad8ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c (2196 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei8_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei8_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei8_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei8_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei8_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i8> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vluxei8_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, <vscale x 32 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i8> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei8_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei8_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Fu
# | ...
# `---data was truncated (10240/30423) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005569b1485eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005569b1482e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005569b148662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f10dbc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f10dbca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f10dbc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f10dbc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005569b141bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005569b141ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005569b14008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005569b10afe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005569b10afb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f10dbc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f10dbc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f10dbc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005569b10afa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c (2197 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a69fac3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a69fac0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a69fac462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7288249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f72882a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7288249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7288231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a69fa59bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a69fa59a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a69fa3e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a69f6ede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a69f6edb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7288232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f72882330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f72882330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a69f6eda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c (2198 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_f64m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_f64m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_i64m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_i64m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_u64m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_u64m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_i64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_i64m2x4_m(<vscale x 2 x i1
# | ...
# `---data was truncated (10240/14031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c08dbaeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c08dbabe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c08dbaf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e39d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e39d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e39d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e39d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c08db44bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c08db44a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c08db298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c08d7d8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c08d7d8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1e39d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e39d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e39d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c08d7d8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c (2199 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f16m1x5(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f32m1x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f64m1x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei8_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vsca
# | ...
# `---data was truncated (10240/61665) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555beac02eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555beabffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555beac0362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff0cc333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff0cc38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff0cc333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff0cc31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555beab98bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555beab98a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555beab7d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555bea82ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555bea82cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff0cc31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff0cc31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff0cc31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555bea82ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/aapcs-bitfield.c (2200 of 27911)
******************** TEST 'Clang :: CodeGen/aapcs-bitfield.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-eabi -fno-aapcs-bitfield-width -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c -check-prefix=LE
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-eabi -fno-aapcs-bitfield-width -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8-none-linux-eabi"
# | 
# | %struct.st6 = type { i16, i8, i8 }
# | %struct.st7b = type { i8, [3 x i8], %struct.st7a }
# | %struct.st7a = type { i8, i8, [2 x i8] }
# | %struct.st11 = type <{ i8, i16, i8 }>
# | %struct.st13 = type <{ i8, i32 }>
# | %struct.st16 = type { i32, i16, i32, i16 }
# | %struct.st17 = type <{ i32, i8 }>
# | %struct.zero_bitfield = type { i8, i8, [2 x i8] }
# | %struct.zero_bitfield_ok = type { i16, i32 }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st0_check_load(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load i8, ptr %0, align 2
# |   %bf.shl = shl i8 %bf.load, 1
# |   %bf.ashr = ashr i8 %bf.shl, 1
# |   %bf.cast = sext i8 %bf.ashr to i16
# |   %conv = sext i16 %bf.cast to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st0_check_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load i8, ptr %0, align 2
# |   %bf.clear = and i8 %bf.load, -128
# |   %bf.set = or i8 %bf.clear, 1
# |   store i8 %bf.set, ptr %0, align 2
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st1_check_load(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load i16, ptr %0, align 4
# |   %bf.ashr = ashr i16 %bf.load, 10
# |   %conv = sext i16 %bf.ashr to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st1_check_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load i16, ptr %0, align 4
# |   %bf.clear = and i16 %bf.load, 1023
# |   %bf.set = or i16 %bf.clear, 1024
# |   store i16 %bf.set, ptr %0, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st2_check_load(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load i32, ptr %0, align 4
# |   %bf.shl = shl i32 %bf.load, 9
# |   %bf.ashr = ashr i32 %bf.shl, 25
# |   %bf.cast = trunc i32 %bf.ashr to i16
# |   %conv = sext i16 %bf.cast to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st2_check_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load i32, ptr %0, align 4
# |   %bf.clear = and i32 %bf.load, -8323073
# |   %bf.set = or i32 %bf.clear, 65536
# |   store i32 %bf.set, ptr %0, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st3_check_load(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load volatile i8, ptr %0, align 2
# |   %bf.shl = shl i8 %bf.load, 1
# |   %bf.ashr = ashr i8 %bf.shl, 1
# |   %bf.cast = sext i8 %bf.ashr to i16
# |   %conv = sext i16 %bf.cast to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st3_check_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load volatile i8, ptr %0, align 2
# |   %bf.clear = and i8 %bf.load, -128
# |   %bf.set = or i8 %bf.clear, 1
# |   store volatile i8 %bf.set, ptr %0, align 2
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st4_check_load(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load volatile i16, ptr %0, align 4
# |   %bf.shl = shl i16 %bf.load, 2
# |   %bf.ashr = ashr i16 %bf.shl, 11
# |   %bf.cast = trunc i16 %bf.ashr to i8
# |   %conv = sext i8 %bf.cast to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st4_check_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load volatile i16, ptr %0, align 4
# |   %bf.clear = and i16 %bf.load, -15873
# |   %bf.set = or i16 %bf.clear, 512
# |   store volatile i16 %bf.set, ptr %0, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st4_check_nonv_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load i16, ptr %0, align 4
# |   %bf.clear = and i16 %bf.load, -512
# |   %bf.set = or i16 %bf.clear, 1
# |   store i16 %bf.set, ptr %0, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st5_check_load(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load volatile i32, ptr %0, align 4
# |   %bf.shl = shl i32 %bf.load, 11
# |   %bf.ashr = ashr i32 %bf.shl, 27
# |   %bf.cast = trunc i32 %bf.ashr to i8
# |   %conv = sext i8 %bf.cast to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st5_check_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load volatile i32, ptr %0, align 4
# |   %bf.clear = and i32 %bf.load, -2031617
# |   %bf.set = or i32 %bf.clear, 65536
# |   store volatile i32 %bf.set, ptr %0, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st6_check_load(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   %x = alloca i32, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load volatile i16, ptr %0, align 4
# |   %bf.shl = shl i16 %bf.load, 4
# |   %bf.ashr = ashr i16 %bf.shl, 4
# |   %bf.cast = sext i16 %bf.ashr to i32
# |   store i32 %bf.cast, ptr %x, align 4
# |   %1 = load ptr, ptr %m.addr, align 4
# |   %b = getelementptr inbounds nuw %struct.st6, ptr %1, i32 0, i32 1
# |   %2 = load volatile i8, ptr %b, align 2
# |   %conv = sext i8 %2 to i32
# |   %3 = load i32, ptr %x, align 4
# |   %add = add nsw i32 %3, %conv
# |   store i32 %add, ptr %x, align 4
# |   %4 = load ptr, ptr %m.addr, align 4
# |   %c = getelementptr inbounds nuw %struct.st6, ptr %4, i32 0, i32 2
# |   %bf.load1 = load volatile i8, ptr %c, align 1
# |   %bf.shl2 = shl i8 %bf.load1, 3
# |   %bf.ashr3 = ashr i8 %bf.shl2, 3
# |   %bf.cast4 = sext i8 %bf.ashr3 to i32
# |   %5 = load i32, ptr %x, align 4
# |   %add5 = add nsw i32 %5, %bf.cast4
# |   store i32 %add5, ptr %x, align 4
# |   %6 = load i32, ptr %x, align 4
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st6_check_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load i16, ptr %0, align 4
# |   %bf.clear = and i16 %bf.load, -4096
# |   %bf.set = or i16 %bf.clear, 1
# |   store i16 %bf.set, ptr %0, align 4
# |   %1 = load ptr, ptr %m.addr, align 4
# |   %b = getelementptr inbounds nuw %struct.st6, ptr %1, i32 0, i32 1
# |   store i8 2, ptr %b, align 2
# |   %2 = load ptr, ptr %m.addr, align 4
# |   %c = getelementptr inbounds nuw %struct.st6, ptr %2, i32 0, i32 2
# |   %bf.load1 = load i8, ptr %c, align 1
# |   %bf.clear2 = and i8 %bf.load1, -32
# |   %bf.set3 = or i8 %bf.clear2, 3
# |   store i8 %bf.set3, ptr %c, align 1
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st7_check_load(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   %r = alloca i32, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %x = getelementptr inbounds nuw %struct.st7b, ptr %0, i32 0, i32 0
# |   %1 = load i8, ptr %x, align 4
# |   %conv = sext i8 %1 to i32
# |   store i32 %conv, ptr %r, align 4
# |   %2 = load ptr, ptr %m.addr, align 4
# |   %y = getelementptr inbounds nuw %struct.st7b, ptr %2, i32 0, i32 2
# |   %a = getelementptr inbounds nuw %struct.st7a, ptr %y, i32 0, i32 0
# |   %3 = load volatile i8, ptr %a, align 4
# |   %conv1 = sext i8 %3 to i32
# |   %4 = load i32, ptr %r, align 4
# |   %add = add nsw i32 %4, %conv1
# |   store i32 %add, ptr %r, align 4
# |   %5 = load ptr, ptr %m.addr, align 4
# |   %y2 = getelementptr inbounds nuw %struct.st7b, ptr %5, i32 0, i32 2
# |   %b = getelementptr inbounds nuw %struct.st7a, ptr %y2, i32 0, i32 1
# |   %bf.load = load volatile i8, ptr %b, align 1
# |   %bf.shl = shl i8 %bf.load, 3
# |   %bf.ashr = ashr i8 %bf.shl, 3
# |   %bf.cast = sext i8 %bf.ashr to i32
# |   %6 = load i32, ptr %r, align 4
# |   %add3 = add nsw i32 %6, %bf.cast
# |   store i32 %add3, ptr %r, align 4
# |   %7 = load i32, ptr %r, align 4
# |   ret i32 %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st7_check_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %x = getelementptr inbounds nuw %struct.st7b, ptr %0, i32 0, i32 0
# |   store i8 1, ptr %x, align 4
# |   %1 = load ptr, ptr %m.addr, align 4
# |   %y = getelementptr inbounds nuw %struct.st7b, ptr %1, i32 0, i32 2
# |   %a = getelementptr inbounds nuw %struct.st7a, ptr %y, i32 0, i32 0
# |   store volatile i8 2, ptr %a, align 4
# |   %2 = load ptr, ptr %m.addr, align 4
# |   %y1 = getelementptr inbounds nuw %struct.st7b, ptr %2, i32 0, i32 2
# |   %b = getelementptr inbounds nuw %struct.st7a, ptr %y1, i32 0, i32 1
# |   %bf.load = load volatile i8, ptr %b, align 1
# |   %bf.clear = and i8 %bf.load, -32
# |   %bf.set = or i8 %bf.clear, 3
# |   store volatile i8 %bf.set, ptr %b, align 1
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st8_check_assignment(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   store i16 -1, ptr %0, align 4
# |   ret i32 65535
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @read_st9(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load volatile i8, ptr %0, align 4
# |   %bf.cast = sext i8 %bf.load to i32
# |   r
# | ...
# `---data was truncated (10240/24998) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560438751eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056043874ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056043875262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa8b821bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa8b82725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa8b821ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa8b8203507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005604386e7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005604386e7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005604386cc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056043837be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056043837bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa8b8204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa8b82050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa8b82050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056043837ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c -check-prefix=LE
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c -check-prefix=LE
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c (2201 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvtbf16_f_f_v_f32mf2(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvtbf16_f_f_v_f32m1(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvtbf16_f_f_v_f32m2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvtbf16_f_f_v_f32m4(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvtbf16_f_f_v_f32m8(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvtbf16_f_f_v_f32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvtbf16_f_f_v_f32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvtbf16_f_f_v_f32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvtbf16_f_f_v_f32m4_m(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvtbf16_f_f_v_f32m8_m(<vscale x 16 x i1> %vm, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,102
# | ...
# `---data was truncated (10240/10769) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de39c1beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055de39c18e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055de39c1c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd587133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd58718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd587133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd58711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de39bb1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055de39bb1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055de39b968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055de39845e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055de39845b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd58711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd58711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd58711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de39845a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vabdq.c (2202 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vabdq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vabdq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vabd.v16i8(<16 x i8> %0, <16 x i8> %1, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vabd.v16i8(<16 x i8>, <16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vabdq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vabd.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vabd.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vabdq_f32(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.arm.mve.vabd.v8f16(<8 x half> %0, <8 x half> %1, i32 0)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vabd.v8f16(<8 x half>, <8 x half>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vabdq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.abd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.abd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vabdq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.abd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.abd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vabdq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x float>, ptr %inactive.addr, align 8
# |   %6 = call <4 x float> @llvm.arm.mve.abd.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.abd.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vabdq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.abd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vabdq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.abd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.abd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vabdq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x half> @llvm.arm.mve.abd.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> undef)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.abd.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>, <8 x half>) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a2ec144eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a2ec141e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a2ec14562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fccda449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fccda4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fccda449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fccda431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a2ec0dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a2ec0daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a2ec0bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a2ebd6ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a2ebd6eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fccda432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fccda4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fccda4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a2ebd6ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c (2203 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_f16m1x2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_f16m2x2(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei16_v_f16m4x2(ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_f32m1x2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_f32m2x2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vect
# | ...
# `---data was truncated (10240/113765) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b44bd20eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b44bd1de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b44bd2162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe68ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe68ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe68ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe68ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b44bcb6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b44bcb6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b44bc9b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b44b94ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b44b94ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe68ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe68ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe68ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b44b94aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c (2204 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_bf16m1x4_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64
# | ...
# `---data was truncated (10240/24373) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005636d8f75eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005636d8f72e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005636d8f7662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ec4f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ec4f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ec4f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ec4f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005636d8f0bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005636d8f0ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005636d8ef08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005636d8b9fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005636d8b9fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8ec4f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ec4f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ec4f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005636d8b9fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c (2205 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_i8mf8(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_i8mf4(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_i8mf2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_i8m1(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_i8m2(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_i8m4(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_u8mf8(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_u8mf4(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_u8mf2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_u8m1(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_xu_f_w_u8m2(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_xu_f_w_u8m4(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x
# | ...
# `---data was truncated (10240/164783) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005614b7f8eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005614b7f8be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005614b7f8f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd6fec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd6feca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd6fec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd6fec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005614b7f24bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005614b7f24a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005614b7f098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005614b7bb8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005614b7bb8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd6fec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd6fec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd6fec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005614b7bb8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c (2206 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf8x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_u8mf8x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_u8mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_u8mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_u8m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.
# | ...
# `---data was truncated (10240/18972) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d31cee7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d31cee4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d31cee862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f894a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f894a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f894a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f894a631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d31ce7dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d31ce7da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d31ce628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d31cb11e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d31cb11b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f894a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f894a6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f894a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d31cb11a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c (2207 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), pt
# | ...
# `---data was truncated (10240/19484) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ce99579eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ce99576e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ce9957a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca41733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca4178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca41733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca4171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ce9950fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ce9950fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ce994f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ce991a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ce991a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fca4171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca4171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca4171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ce991a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c (2208 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f16m1x8(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f32m1x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f64m1x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei64_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a64d622eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a64d61fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a64d62362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ddc133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ddc18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ddc133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ddc11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a64d5b8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a64d5b8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a64d59d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a64d24ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a64d24cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3ddc11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ddc11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ddc11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a64d24ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c (2209 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmax_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmax_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmax_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmax_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmax_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmax_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmax_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmax_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmax_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/222483) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ab25850eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ab2584de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ab2585162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f42b1f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42b1f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f42b1f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f42b1f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ab257e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ab257e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ab257cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ab2547ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ab2547ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f42b1f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42b1f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42b1f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ab2547aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c (2210 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055db389a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055db389a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055db389a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f93d821bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f93d82725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f93d821ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f93d8203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055db3893cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055db3893ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055db389218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055db385d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055db385d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f93d8204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f93d82050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f93d82050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055db385d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c (2211 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005638c48a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005638c489fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005638c48a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fabd2049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fabd20a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fabd2049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fabd2031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005638c4838bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005638c4838a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005638c481d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005638c44cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005638c44ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fabd2032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fabd20330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fabd20330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005638c44cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c (2212 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dotu_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dotu_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dotu_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dotu_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dotu_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dotu_vv_u64m1_tu(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dotu_vv_u64m2_tu(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dotu_vv_u64m4_tu(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dotu.nxv4
# | ...
# `---data was truncated (10240/47636) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ce74c50eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ce74c4de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ce74c5162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8f33705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8f3375c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8f33705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8f336ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ce74be6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ce74be6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ce74bcb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ce7487ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ce7487ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8f336eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8f336ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8f336ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ce7487aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c (2213 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f    -target-feature +xsfvfexp32e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexp_v_f32mf2(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexp_v_f32m1(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexp_v_f32m2(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexp_v_f32m4(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfexp_v_f32m8(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexp_v_f32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexp_v_f32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexp_v_f32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexp_v_f32m4_m(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfexp_v_f32m8_m(<vscale x 16 x i1> %vm, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.sf.vfexp.mask.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfexp.mask.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfvfexp32e,+zicsr,+zve32f,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfvfexp32e0p5"}
# | !3 = !{i32 8, !"SmallDataLi
# | ...
# `---data was truncated (10240/10285) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562bbf9adeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562bbf9aae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562bbf9ae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faf20733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faf2078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faf20733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faf2071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562bbf943bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562bbf943a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562bbf9288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562bbf5d7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562bbf5d7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faf2071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faf2071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faf2071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562bbf5d7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c (2214 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005580ee498eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005580ee495e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005580ee49962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa226449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa2264a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa226449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa226431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005580ee42ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005580ee42ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005580ee4138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005580ee0c2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005580ee0c2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa226432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa2264330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa2264330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005580ee0c2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c (2215 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei16_v_i8mf8x5
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056154cf87eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056154cf84e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056154cf8862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f09d2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f09d2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f09d2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f09d2f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056154cf1dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056154cf1da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056154cf028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056154cbb1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056154cbb1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f09d2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f09d2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f09d2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056154cbb1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c (2216 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8(<vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4(<vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2(<vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1(<vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_xu_f_qf_u8m2(<vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 
# | ...
# `---data was truncated (10240/12465) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005646763f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005646763efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005646763f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5869a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5869aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5869a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5869a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564676388bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564676388a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056467636d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056467601ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056467601cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5869a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5869a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5869a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056467601ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c (2217 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmadd_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmadd_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmadd_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmadd_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmadd_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmadd_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmadd_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmadd_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7
# | ...
# `---data was truncated (10240/64374) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559e7cb45eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559e7cb42e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559e7cb4662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d0de1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d0de725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d0de1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d0de03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e7cadbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559e7cadba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559e7cac08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559e7c76fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559e7c76fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1d0de04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d0de050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d0de050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e7c76fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c (2218 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfwmacc_4x4x4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 4 x bfloat>, <vscale x 1 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfwmacc_4x4x4_f32m1(<vscale x 2 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 4 x bfloat>, <vscale x 2 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfwmacc_4x4x4_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfwmacc_4x4x4_f32m4(<vscale x 8 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfwmacc_4x4x4_f32m8(<vscale x 16 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(<vscale x 16 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 4 x bfloat>, <vscale x 16 x bfloat>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvfwmaccqqq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvfwmaccqqq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005587d9308eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005587d9305e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005587d930962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff422e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff422ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff422e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff422e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005587d929ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005587d929ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005587d92838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005587d8f32e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005587d8f32b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff422e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff422e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff422e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005587d8f32a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c (2219 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557250ee7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557250ee4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557250ee862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec0f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec0f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec0f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec0f51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557250e7dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557250e7da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557250e628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557250b11e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557250b11b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fec0f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec0f51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec0f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557250b11a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c (2220 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c310d8eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c310d8be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c310d8f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8019533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f801958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8019533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f801951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c310d24bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c310d24a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c310d098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c3109b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c3109b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f801951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f801951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f801951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c3109b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c (2221 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_bf16mf2x7(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_bf16m1x7(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b4133e0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b4133dde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b4133e162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac30f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac30f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac30f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac30f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b413376bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b413376a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b41335b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b41300ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b41300ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fac30f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac30f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac30f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b41300aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c (2222 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei64_v_i8mf8x7
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005636473bfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005636473bce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005636473c062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f95ee21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f95ee2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f95ee21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f95ee203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563647355bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563647355a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056364733a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563646fe9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563646fe9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f95ee204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f95ee2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f95ee2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563646fe9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c (2223 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vunzipe_v_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 2 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(<vscale x 1 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(<vscale x 1 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vunzipe_v_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 4 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(<vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(<vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vunzipe_v_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 8 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vunzipe_v_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 16 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(<vscale x 8 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(<vscale x 8 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vunzipe_v_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 32 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(<vscale x 16 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(<vscale x 16 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vunzipe_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 2 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(<vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(<vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vunzipe_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 4 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(<vscale x 2 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vunzipe_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 8 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(<vscale x 4 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(<vscale x 4 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vunzipe_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 16 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(<vscale x 8 x float> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(<vscale x 8 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vunzipe_v_f64m1_tu(<vscale x 1 x double> %vd, <vscale x 2 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x double>, ptr %vs.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declar
# | ...
# `---data was truncated (10240/44434) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056201724beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562017248e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056201724c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca93133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca9318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca93133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca9311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005620171e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005620171e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005620171c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562016e75e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562016e75b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fca9311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca9311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca9311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562016e75a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c (2224 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei64_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560617551eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056061754ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056061755262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f600b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f600b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f600b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f600b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005606174e7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005606174e7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005606174cc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056061717be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056061717bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f600b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f600b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f600b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056061717ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c (2225 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f16m1x5(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f32m1x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f64m1x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei8_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none
# | ...
# `---data was truncated (10240/61673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005582fda9deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005582fda9ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005582fda9e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faa1ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faa1ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faa1ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faa1ad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005582fda33bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005582fda33a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005582fda188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005582fd6c7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005582fd6c7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faa1ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faa1ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faa1ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005582fd6c7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c (2226 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_i64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_u64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_i64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_u64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.ve
# | ...
# `---data was truncated (10240/18498) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056004ea51eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056004ea4ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056004ea5262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe258905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe25895c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe258905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe2588ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056004e9e7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056004e9e7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056004e9cc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056004e67be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056004e67bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe2588eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe2588ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe2588ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056004e67ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c (2227 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f16m1x7(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f32m1x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f64m1x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e0fd1b8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e0fd1b5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e0fd1b962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fef61c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fef61ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fef61c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fef61c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e0fd14ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e0fd14ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e0fd1338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e0fcde2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e0fcde2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fef61c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fef61c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fef61c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e0fcde2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c (2228 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs1, <vsc
# | ...
# `---data was truncated (10240/148835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b8cebf2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b8cebefe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b8cebf362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9d17a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9d17aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9d17a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9d17a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b8ceb88bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b8ceb88a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b8ceb6d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b8ce81ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b8ce81cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9d17a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9d17a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9d17a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b8ce81ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c (2229 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_i16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_i16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_i16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_u16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca 
# | ...
# `---data was truncated (10240/60551) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ab54b38eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ab54b35e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ab54b3962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa70c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa70c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa70c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa70c91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ab54acebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ab54acea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ab54ab38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ab54762e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ab54762b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa70c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa70c91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa70c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ab54762a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c (2230 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnot_v_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnot_v_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnot_v_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnot_v_i8m1(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnot_v_i8m2(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vnot_v_i8m4(<vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vnot_v_i8m8(<vscale x 64 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vnot_v_i16mf4(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vnot_v_i16mf2(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vnot_v_i16m1(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vnot_v_i16m2(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vxor.nxv8i16.i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vxor.nxv8i16.i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vnot_v_i16m4(<vscale x 16 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vxor.nxv16i16.i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vxor.nxv16i16.i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vnot_v_i16m8(<vscale x 32 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i
# | ...
# `---data was truncated (10240/72493) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055839c56beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055839c568e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055839c56c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f43b9705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f43b975c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f43b9705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f43b96ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055839c501bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055839c501a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055839c4e68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055839c195e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055839c195b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f43b96eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f43b96ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f43b96ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055839c195a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c (2231 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_bf16mf4x4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_bf16mf2x4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_bf16m1x4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_bf16m2x4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tup
# | ...
# `---data was truncated (10240/11051) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564b6f5b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564b6f5b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564b6f5b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3da5c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3da5ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3da5c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3da5c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564b6f549bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564b6f549a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564b6f52e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564b6f1dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564b6f1ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3da5c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3da5c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3da5c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564b6f1dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c (2232 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vghsh_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vghsh_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vghsh_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vghsh_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vghsh_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005615ad6e7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005615ad6e4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005615ad6e862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff4a4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff4a438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff4a4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff4a431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005615ad67dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005615ad67da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005615ad6628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005615ad311e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005615ad311b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff4a431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff4a431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff4a431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615ad311a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c (2233 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_f64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_f64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_i64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_i64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_u64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_u64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_f64m1x3_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_f64m2x3_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %2, <vscale x 2 x i1> %0, i64 
# | ...
# `---data was truncated (10240/32125) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557a48538eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557a48535e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557a4853962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcddac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcddaca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcddac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcddac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557a484cebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557a484cea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557a484b38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557a48162e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557a48162b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcddac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcddac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcddac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557a48162a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c (2234 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f16m1x3(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f16m2x3(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f32m1x3(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f32m2x3(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f64m1x3(ptr noundef %base, <vscale x 1 x i16> %binde
# | ...
# `---data was truncated (10240/99754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558710b69eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558710b66e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558710b6a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc277449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc2774a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc277449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc277431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558710affbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558710affa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558710ae48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558710793e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558710793b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc277432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc2774330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc2774330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558710793a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c (2235 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_f32mf2x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_f32m1x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e32_v_f32m2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e32_v_f32m4x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_i32mf2x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_i32m1x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e32_v_i32m2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e32_v_i32m4x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.
# | ...
# `---data was truncated (10240/15486) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561a62f9ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561a62f99e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561a62f9d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb9b6333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb9b638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb9b6333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb9b631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a62f32bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561a62f32a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561a62f178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561a62bc6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561a62bc6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb9b631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb9b631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb9b631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a62bc6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c (2236 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredxor_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretu
# | ...
# `---data was truncated (10240/113047) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005622c8aaceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005622c8aa9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005622c8aad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0922533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f092258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0922533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f092251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005622c8a42bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005622c8a42a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005622c8a278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005622c86d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005622c86d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f092251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f092251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f092251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005622c86d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c (2237 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vv_bf16mf4_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vf_bf16mf4_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vv_bf16mf2_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vf_bf16mf2_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vv_bf16m1_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vf_bf16m1_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vv_bf16m2_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vf_bf16m2_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.bf16.nxv
# | ...
# `---data was truncated (10240/51702) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561aeed68eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561aeed65e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561aeed6962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff4ad133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff4ad18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff4ad133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff4ad11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561aeecfebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561aeecfea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561aeece38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561aee992e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561aee992b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff4ad11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff4ad11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff4ad11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561aee992a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c (2238 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf4_f16m1(<vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf2_f16m1(<vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m1_f16m1(<vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m2_f16m1(<vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m4_f16m1(<vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m8_f16m1(<vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32mf2_f32m1(<vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m1_f32m1(<vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m2_f32m1(<vscale x 4 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> 
# | ...
# `---data was truncated (10240/68054) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f65cba4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f65cba1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f65cba562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f40ee449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f40ee4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f40ee449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f40ee431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f65cb3abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f65cb3aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f65cb1f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f65c7cee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f65c7ceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f40ee432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f40ee4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f40ee4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f65c7cea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c (2239 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_f16mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_f16mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_f16m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_i16mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_i16mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_i16m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_u16mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_u16mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_u16m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_f16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.v
# | ...
# `---data was truncated (10240/20439) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556720ce7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556720ce4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556720ce862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9d07333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9d0738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9d07333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9d0731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556720c7dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556720c7da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556720c628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556720911e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556720911b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9d0731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9d0731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9d0731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556720911a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/veorq.c (2240 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/veorq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_veorq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = xor <16 x i8> %0, %1
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_veorq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = xor <8 x i16> %0, %1
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_veorq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = xor <4 x i32> %0, %1
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_veorq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = xor <4 x i32> %1, %3
# |   %5 = bitcast <4 x i32> %4 to <4 x float>
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_veorq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.eor.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.eor.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_veorq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_veorq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_veorq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <8 x i16>
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = bitcast <8 x half> %2 to <8 x i16>
# |   %4 = load i16, ptr %p.addr, align 2
# |   %5 = zext i16 %4 to i32
# |   %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5)
# |   %7 = load <8 x half>, ptr %inactive.addr, align 8
# |   %8 = bitcast <8 x half> %7 to <8 x i16>
# |   %9 = call <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8)
# |   %10 = bitcast <8 x i16> %9 to <8 x half>
# |   ret <8 x half> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_veorq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.eor.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_veorq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_veorq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_veorq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = load i16, ptr %p.addr, align 2
# |   %5 = zext i16 %4 to i32
# |   %6 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %5)
# |   %7 = call <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x
# | ...
# `---data was truncated (10240/10901) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d94c15ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d94c159e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d94c15d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f56d581bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56d58725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f56d581ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f56d5803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d94c0f2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d94c0f2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d94c0d78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d94bd86e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d94bd86b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f56d5804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56d58050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56d58050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d94bd86a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c (2241 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_x_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_x_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_x_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_x_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_x_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_x_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_xu_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_xu_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_xu_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_xu_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv
# | ...
# `---data was truncated (10240/75133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005606d80b2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005606d80afe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005606d80b362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb924449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb9244a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb924449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb924431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005606d8048bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005606d8048a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005606d802d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005606d7cdce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005606d7cdcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb924432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb9244330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb9244330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005606d7cdca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c (2242 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_f16mf4x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_f16mf2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_f16m1x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_f16m2x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_i16mf4x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_i16mf2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_i16m1x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_i16m2x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_u16mf4x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_u16mf2x3_m(<vscale x 2 x i1> %mask, ptr nound
# | ...
# `---data was truncated (10240/13515) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ad3ae28eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ad3ae25e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ad3ae2962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fef1f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fef1f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fef1f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fef1f51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad3adbebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ad3adbea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ad3ada38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ad3aa52e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ad3aa52b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fef1f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fef1f51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fef1f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad3aa52a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c (2243 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsleu_vv_u8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsleu_vx_u8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsleu_vv_u8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsleu_vx_u8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsleu_vv_u8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsleu_vx_u8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsleu_vv_u8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsleu_vx_u8m1_b8(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsleu_vv_u8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsleu_vx_u8m2_b4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsleu_vv_u8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsleu.nxv32i8.n
# | ...
# `---data was truncated (10240/95347) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f94573feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f94573ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f94574062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f66f1249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f66f12a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f66f1249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f66f1231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f9456d5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f9456d5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f9456ba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f945369e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f945369b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f66f1232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f66f12330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f66f12330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f945369a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c (2244 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vandn_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vandn_vx_u8mf8(<vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vandn_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vandn_vx_u8mf4(<vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vandn_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vandn_vx_u8mf2(<vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vandn_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vandn_vx_u8m1(<vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vandn_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vandn.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vandn.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vandn_vx_u8m2(<vscale x 16 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vandn.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vandn.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vandn_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/98117) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e6b7a77eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e6b7a74e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e6b7a7862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f13e121bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13e12725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f13e121ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f13e1203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e6b7a0dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e6b7a0da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e6b79f28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e6b76a1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e6b76a1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f13e1204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13e12050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13e12050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e6b76a1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c (2245 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfwma -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vf_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vf_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vf_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vf_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llv
# | ...
# `---data was truncated (10240/51751) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555efb67eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555efb67be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555efb67f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd9ed333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd9ed38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd9ed333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd9ed31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555efb614bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555efb614a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555efb5f98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555efb2a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555efb2a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd9ed31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd9ed31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd9ed31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555efb2a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c (2246 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmerge_vfm_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmerge_vfm_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmerge_vfm_f16m1(<vscale x 4 x half> %op1, half noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmerge_vfm_f16m2(<vscale x 8 x half> %op1, half noundef %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmerge_vfm_f16m4(<vscale x 16 x half> %op1, half noundef %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, <vscale x 16 x i1> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfmerge_vfm_f16m8(<vscale x 32 x half> %op1, half noundef %op2, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, <vscale x 32 x i1> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfmerge_vfm_f32mf2(<vscale x 1 x float> %op1, float noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfmerge_vfm_f32m1(<vscale x 2 x float> %op1, float noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfmerge.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfmerge.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfmerge_vfm_f32m2(<vscale x 4 x float> %op1, float noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %mask.addr = alloca <vscale x 4 x i1
# | ...
# `---data was truncated (10240/19049) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c7a40feeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c7a40fbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c7a40ff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd29ba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd29baa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd29ba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd29ba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c7a4094bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c7a4094a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c7a40798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c7a3d28e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c7a3d28b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd29ba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd29ba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd29ba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c7a3d28a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c (2247 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16mf4(ptr noundef %base, <vscale x 1 x i8> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16mf2(ptr noundef %base, <vscale x 2 x i8> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16m1(ptr noundef %base, <vscale x 4 x i8> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16m2(ptr noundef %base, <vscale x 8 x i8> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16m4(ptr noundef %base, <vscale x 16 x i8> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16m8(ptr noundef %base, <vscale x 32 x i8> %bindex, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> %2, ptr %0, <vscale x 32 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f32mf2(ptr noundef %base, <vscale x 1 x i8> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f32m1(ptr noundef %base, <vscale x 2 x i8> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f32m2(ptr noundef %base, <vscale x 4 x i8> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory
# | ...
# `---data was truncated (10240/135997) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565419c88eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565419c85e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000565419c8962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f383f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f383f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f383f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f383f831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565419c1ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565419c1ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000565419c038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005654198b2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005654198b2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f383f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f383f8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f383f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005654198b2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c (2248 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgather_vv_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgather_vx_bf16mf4(<vscale x 1 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgather_vv_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgather_vx_bf16mf2(<vscale x 2 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgather_vv_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgather_vx_bf16m1(<vscale x 4 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgather_vv_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgather_vx_bf16m2(<vscale x 8 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgather_vv_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vrgather.vv.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vrgather.vv.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgather_vx_bf16m4(<vscale x 16 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vrgather.vx.
# | ...
# `---data was truncated (10240/28427) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555a5c2e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555a5c2e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555a5c2e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab3aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab3aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab3aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab3aa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555a5c27bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555a5c27ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555a5c2608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555a5bf0fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555a5bf0fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fab3aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab3aa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab3aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555a5bf0fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c (2249 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f16m1x4(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f16m2x4(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f32m1x4(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f32m2x4(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f64m1x4(ptr noundef %base, <vscale x 1 x i32> %binde
# | ...
# `---data was truncated (10240/99754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bec9abceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bec9ab9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bec9abd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb6c8649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb6c86a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb6c8649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb6c8631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bec9a52bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bec9a52a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bec9a378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bec96e6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bec96e6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb6c8632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb6c86330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb6c86330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bec96e6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c (2250 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4aus_vx_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4aus_vx_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Functio
# | ...
# `---data was truncated (10240/13657) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ab9803eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557ab9800e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557ab980462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff311b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff311b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff311b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff311b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ab9799bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557ab9799a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557ab977e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557ab942de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557ab942db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff311b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff311b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff311b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ab942da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c (2251 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsac_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsac_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsac_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsac_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsac_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsac_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsac_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsac_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | ...
# `---data was truncated (10240/34356) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005609e256aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005609e2567e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005609e256b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0244449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f02444a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0244449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0244431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005609e2500bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005609e2500a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005609e24e58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005609e2194e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005609e2194b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0244432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f02444330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f02444330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005609e2194a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c (2252 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssra_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssra_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssra_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssra_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssra_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssra_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssra_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssra_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssra_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/226585) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba15f82eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ba15f7fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ba15f8362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff1bc649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff1bc6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff1bc649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff1bc631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba15f18bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ba15f18a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ba15efd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ba15bace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ba15bacb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff1bc632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff1bc6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff1bc6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba15baca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/distributed-thin-lto/basic.ll (2253 of 27911)
******************** TEST 'Clang :: CodeGen/distributed-thin-lto/basic.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/basic.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/basic.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/basic.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/basic.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/basic.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/basic.ll
# |  #0 0x0000556180e15eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556180e12e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556180e1662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff472449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff4724a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff472449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff472431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556180dabbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556180daba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556180d908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556180a3fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556180a3fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff472432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff4724330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff4724330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556180a3fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c (2254 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("risc
# | ...
# `---data was truncated (10240/21103) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a28fb78eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a28fb75e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a28fb7962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb2ce21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb2ce2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb2ce21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb2ce203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a28fb0ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a28fb0ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a28faf38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a28f7a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a28f7a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb2ce204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb2ce2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb2ce2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a28f7a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c (2255 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_x_f_qf_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %1, <vscale x 1 x float> %2, float %3, <vscale x 1 x i1> %0, i64 2, i64 %4, i64 2)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %1, <vscale x 2 x float> %2, float %3, <vscale x 2 x i1> %0, i64 2, i64 %4, i64 2)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale 
# | ...
# `---data was truncated (10240/26702) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564eb13dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564eb13dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564eb13e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f071d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f071d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f071d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f071d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564eb1375bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564eb1375a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564eb135a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564eb1009e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564eb1009b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f071d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f071d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f071d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564eb1009a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c (2256 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsle_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsle_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsle_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsle_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsle_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsle_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsle_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i
# | ...
# `---data was truncated (10240/63579) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aca7988eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aca7985e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aca798962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3639933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f363998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3639933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f363991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aca791ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aca791ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aca79038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aca75b2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aca75b2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f363991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f363991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f363991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aca75b2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c (2257 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4(<vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_f_f_w_f16mf2(<vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfncvt_f_f_w_f16m1(<vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfncvt_f_f_w_f16m2(<vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfncvt_f_f_w_f16m4(<vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfncvt_f_f_w_f32mf2(<vscale x 1 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> poison, <vscale x 1 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfncvt_f_f_w_f32m1(<vscale x 2 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> poison, <vscale x 2 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float>, <vscale x 2 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfncvt_f_f_w_f32m2(<vscale x 4 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> poison, <vscale x 4 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float>, <vscale x 4 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfncvt_f_f_w_f32m4(<vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> poison, <vscale x 8 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float>, <vscale x 8 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_f_f_w_f16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, <vscale x 2 x i1>, i64 immarg, i64, i64
# | ...
# `---data was truncated (10240/32186) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557a7f9e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557a7f9e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557a7f9e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c5bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c5bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c5bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c5bd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557a7f97abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557a7f97aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557a7f95f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557a7f60ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557a7f60eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7c5bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c5bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c5bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557a7f60ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c (2258 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei8_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %m
# | ...
# `---data was truncated (10240/160133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558310919eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558310916e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055831091a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f03b0f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03b0f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f03b0f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f03b0eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005583108afbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005583108afa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005583108948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558310543e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558310543b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f03b0eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03b0eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03b0eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558310543a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c (2259 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562777e17eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562777e14e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562777e1862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f38cd049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f38cd0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f38cd049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f38cd031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562777dadbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562777dada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562777d928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562777a41e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562777a41b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f38cd032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f38cd0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f38cd0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562777a41a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c (2260 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vror_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vror_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vror_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vror_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vror_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vror_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vror_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vror_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vror_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 
# | ...
# `---data was truncated (10240/222315) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558ef8bd4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558ef8bd1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558ef8bd562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f51cf449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f51cf4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f51cf449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f51cf431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558ef8b6abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558ef8b6aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558ef8b4f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558ef87fee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558ef87feb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f51cf432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51cf4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51cf4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558ef87fea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c (2261 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh    -target-feature +xsfvfexpa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexpa_v_f16mf4(<vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexpa_v_f16mf2(<vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexpa_v_f16m1(<vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexpa_v_f16m2(<vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexpa_v_f16m4(<vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vfexpa_v_f16m8(<vscale x 32 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexpa_v_f32mf2(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexpa_v_f32m1(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexpa_v_f32m2(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexpa_v_f32m4(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfexpa_v_f32m8(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.sf.vfexpa.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfexpa.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexpa_v_f16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.sf.vfexpa.mask.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexpa.mask.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 
# | ...
# `---data was truncated (10240/21465) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005639aaecceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005639aaec9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005639aaecd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4185333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f418538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4185333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f418531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005639aae62bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005639aae62a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005639aae478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005639aaaf6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005639aaaf6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f418531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f418531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f418531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639aaaf6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c (2262 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmerge_vfm_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmerge_vfm_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmerge_vfm_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmerge_vfm_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmerge_vfm_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, bfloat noundef %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, <vscale x 16 x i1> %3, i64 %4)
# |   ret <vscale x 16 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfmerge_vfm_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, bfloat noundef %op2, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, <vscale x 32 x i1> %3, i64 %4)
# |   ret <vscale x 32 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, <vscale x 32 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fbe24aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fbe24a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fbe24ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa186a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa186aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa186a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa186a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fbe2442bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fbe2442a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fbe24278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fbe20d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fbe20d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa186a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa186a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa186a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fbe20d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c (2263 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +xandesvbfhcvt -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_nds_vfwcvt_s_bf16_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_nds_vfwcvt_s_bf16_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_nds_vfwcvt_s_bf16_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_nds_vfwcvt_s_bf16_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_nds_vfwcvt_s_bf16_f32m8_tu(<vscale x 16 x float> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055feb4bd4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055feb4bd1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055feb4bd562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f966b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f966b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f966b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f966b31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055feb4b6abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055feb4b6aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055feb4b4f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055feb47fee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055feb47feb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f966b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f966b31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f966b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055feb47fea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c (2264 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f16m1x6(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f32m1x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f64m1x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei32_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558055d9feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558055d9ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558055da062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f50f3049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f50f30a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f50f3049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f50f3031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558055d35bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558055d35a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558055d1a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005580559c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005580559c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f50f3032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f50f30330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f50f30330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005580559c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c (2265 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556ff5d9aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556ff5d97e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556ff5d9b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f034e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f034e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f034e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f034e431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ff5d30bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556ff5d30a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556ff5d158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556ff59c4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556ff59c4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f034e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f034e4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f034e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556ff59c4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c (2266 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvtbf16_f_f_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvtbf16_f_f_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvtbf16_f_f_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvtbf16_f_f_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvtbf16_f_f_v_f32m8_tu(<vscale x 16 x float> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvtbf16_f_f_v_f32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvtbf16_f_f_v_f32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvtbf16_f_f_v_f32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvtbf16_f_f_v_f32m4_tum(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 8 x bfloat>, ptr %v
# | ...
# `---data was truncated (10240/23064) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564de130aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564de1307e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564de130b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f37eec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f37eeca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f37eec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f37eec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564de12a0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564de12a0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564de12858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564de0f34e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564de0f34b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f37eec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f37eec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f37eec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564de0f34a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c (2267 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjx_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjx_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjx_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjx_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjx_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjx_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjx_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjx_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjx_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <v
# | ...
# `---data was truncated (10240/157769) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056457a227eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056457a224e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056457a22862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1ff9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1ff998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1ff9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1ff991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056457a1bdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056457a1bda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056457a1a28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564579e51e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564579e51b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1ff991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1ff991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1ff991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564579e51a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c (2268 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsrl_wv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsrl_wx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsrl_wv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsrl_wx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsrl_wv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsrl_wx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsrl_wv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsrl_wx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsrl_wv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vsca
# | ...
# `---data was truncated (10240/154601) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005587db904eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005587db901e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005587db90562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d50c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d50ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d50c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d50c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005587db89abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005587db89aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005587db87f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005587db52ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005587db52eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4d50c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d50c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d50c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005587db52ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c (2269 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmin_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmin_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmin_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmin_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmin_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmin_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmin_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmin_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmin_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmin_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmin_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/97647) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562524e3ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562524e39e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562524e3d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa534f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa534f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa534f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa534f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562524dd2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562524dd2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562524db78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562524a66e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562524a66b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa534f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa534f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa534f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562524a66a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcaddq.c (2270 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcaddq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 0, <16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32, i32, <16 x i8>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot90_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 0, <8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32, i32, <8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot90_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 0, <4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32, i32, <4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 0, <16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot90_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 0, <8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot90_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 0, <4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcaddq_rot90_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32 1, i32 0, <8 x half> %0, <8 x half> %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32, i32, <8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcaddq_rot90_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = call <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32 1, i32 0, <4 x float> %0, <4 x float> %1)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32, i32, <4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot270_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 1, <16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot270_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 1, <8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot270_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 1, <4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot270_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 1, <16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot270_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 1, <8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot270_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 1, <4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcaddq_rot270_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32 1, i32 1, <8 x half> %0, <8 x half> %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcaddq_rot270_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = call <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32 1, i32 1, <4 x float> %0, <4 x float> %1)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_m_u8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align
# | ...
# `---data was truncated (10240/39627) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055af062e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055af062e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055af062e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe816105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe81615c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe816105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe8160ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055af06279bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055af06279a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055af0625e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055af05f0de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055af05f0db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe8160eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe8160ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe8160ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055af05f0da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c (2271 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561bdbd42eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561bdbd3fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561bdbd4362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa284333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa28438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa284333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa28431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561bdbcd8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561bdbcd8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561bdbcbd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561bdb96ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561bdb96cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa28431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa28431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa28431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561bdb96ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/neon/getset.c (2272 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/getset.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm  /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i8 @test_vget_lane_u8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vget_lane = extractelement <8 x i8> %1, i32 7
# |   store i8 %vget_lane, ptr %ref.tmp, align 1
# |   %2 = load i8, ptr %ref.tmp, align 1
# |   store i8 %2, ptr %__ret, align 1
# |   %3 = load i8, ptr %__ret, align 1
# |   store i8 %3, ptr %tmp, align 1
# |   %4 = load i8, ptr %tmp, align 1
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vget_lane_u16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i16>, align 8
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__s0, align 8
# |   %1 = load <4 x i16>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i16> %1, i32 3
# |   store i16 %vget_lane, ptr %ref.tmp, align 2
# |   %2 = load i16, ptr %ref.tmp, align 2
# |   store i16 %2, ptr %__ret, align 2
# |   %3 = load i16, ptr %__ret, align 2
# |   store i16 %3, ptr %tmp, align 2
# |   %4 = load i16, ptr %tmp, align 2
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_vget_lane_u32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0, align 8
# |   %1 = load <2 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x i32> %1, i32 1
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i8 @test_vget_lane_s8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vget_lane = extractelement <8 x i8> %1, i32 7
# |   store i8 %vget_lane, ptr %ref.tmp, align 1
# |   %2 = load i8, ptr %ref.tmp, align 1
# |   store i8 %2, ptr %__ret, align 1
# |   %3 = load i8, ptr %__ret, align 1
# |   store i8 %3, ptr %tmp, align 1
# |   %4 = load i8, ptr %tmp, align 1
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vget_lane_s16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i16>, align 8
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__s0, align 8
# |   %1 = load <4 x i16>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i16> %1, i32 3
# |   store i16 %vget_lane, ptr %ref.tmp, align 2
# |   %2 = load i16, ptr %ref.tmp, align 2
# |   store i16 %2, ptr %__ret, align 2
# |   %3 = load i16, ptr %__ret, align 2
# |   store i16 %3, ptr %tmp, align 2
# |   %4 = load i16, ptr %tmp, align 2
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_vget_lane_s32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0, align 8
# |   %1 = load <2 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x i32> %1, i32 1
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i8 @test_vget_lane_p8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vget_lane = extractelement <8 x i8> %1, i32 7
# |   store i8 %vget_lane, ptr %ref.tmp, align 1
# |   %2 = load i8, ptr %ref.tmp, align 1
# |   store i8 %2, ptr %__ret, align 1
# |   %3 = load i8, ptr %__ret, align 1
# |   store i8 %3, ptr %tmp, align 1
# |   %4 = load i8, ptr %tmp, align 1
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vget_lane_p16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i16>, align 8
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__s0, align 8
# |   %1 = load <4 x i16>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i16> %1, i32 3
# |   store i16 %vget_lane, ptr %ref.tmp, align 2
# |   %2 = load i16, ptr %ref.tmp, align 2
# |   store i16 %2, ptr %__ret, align 2
# |   %3 = load i16, ptr %__ret, align 2
# |   store i16 %3, ptr %tmp, align 2
# |   %4 = load i16, ptr %tmp, align 2
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i8> @test_vget_lane_mf8(<8 x i8> %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <1 x i8>, align 1
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <1 x i8>, align 1
# |   %tmp = alloca <1 x i8>, align 1
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vget_lane = extractelement <8 x i8> %1, i32 7
# |   store i8 %vget_lane, ptr %ref.tmp, align 1
# |   %2 = load <1 x i8>, ptr %ref.tmp, align 1
# |   store <1 x i8> %2, ptr %__ret, align 1
# |   %3 = load <1 x i8>, ptr %__ret, align 1
# |   store <1 x i8> %3, ptr %tmp, align 1
# |   %4 = load <1 x i8>, ptr %tmp, align 1
# |   ret <1 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vget_lane_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x half>, align 8
# |   %__ret_847 = alloca half, align 2
# |   %__s0_847 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca i16, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp1 = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   %tmp2 = alloca half, align 2
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__s0_847, align 8
# |   %1 = load <4 x i16>, ptr %__s0_847, align 8
# |   store <4 x i16> %1, ptr %__s0, align 8
# |   %2 = load <4 x i16>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i16> %2, i32 1
# |   store i16 %vget_lane, ptr %ref.tmp1, align 2
# |   %3 = load i16, ptr %ref.tmp1, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   store i16 %5, ptr %ref.tmp, align 2
# |   %6 = load half, ptr %ref.tmp, align 2
# |   store half %6, ptr %__ret_847, align 2
# |   %7 = load half, ptr %__ret_847, align 2
# |   store half %7, ptr %tmp2, align 2
# |   %8 = load half, ptr %tmp2, align 2
# |   %conv = fpext half %8 to float
# |   ret float %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vget_lane_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x float>, align 8
# |   %__ret = alloca float, align 4
# |   %__s0 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca float, align 4
# |   %tmp = alloca float, align 4
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__s0, align 8
# |   %1 = load <2 x float>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x float> %1, i32 1
# |   store float %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load float, ptr %ref.tmp, align 4
# |   store float %2, ptr %__ret, align 4
# |   %3 = load float, ptr %__ret, align 4
# |   store float %3, ptr %tmp, align 4
# |   %4 = load float, ptr %tmp, align 4
# |   ret float %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_vget_lane_f64(<1 x double> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <1 x double>, align 8
# |   %__ret = alloca double, align 8
# |   %__s0 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca double, align 8
# |   %tmp = alloca double, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__s0, align 8
# |   %1 = load <1 x double>, ptr %__s0, align 8
# |   %vget_lane = extractelement <1 x double> %1, i32 0
# |   store double %vget_lane, ptr %ref.tmp, align 8
# |   %2 = load double, ptr %ref.tmp, align 8
# |   store double %2, ptr %__ret, align 8
# |   %3 = load double, ptr %__ret, align 8
# |   store double %3, ptr %tmp, align 8
# |   %4 = load double, ptr %tmp, align 8
# |   ret double %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i8 @test_vgetq_lane_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 16
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca <16 x i8>, align 16
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__s0, align
# | ...
# `---data was truncated (10240/76998) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005574b13c3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005574b13c0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005574b13c462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f041be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f041bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f041be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f041be31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005574b1359bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005574b1359a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005574b133e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005574b0fede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005574b0fedb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f041be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f041be330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f041be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005574b0feda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c (2273 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_i8mf8x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_i8mf4x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_i8mf2x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8_v_i8m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_u8mf8x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_u8mf4x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_u8mf2x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8_v_u8m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_i8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_i8mf2x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = c
# | ...
# `---data was truncated (10240/16451) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560f8e7caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560f8e7c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560f8e7cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbbf1533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbbf158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbbf1533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbbf151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f8e760bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560f8e760a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560f8e7458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560f8e3f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560f8e3f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbbf151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbbf151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbbf151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f8e3f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c (2274 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cdf68dceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cdf68d9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cdf68dd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff693849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff6938a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff693849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff693831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cdf6872bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cdf6872a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cdf68578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cdf6506e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cdf6506b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff693832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff6938330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff6938330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cdf6506a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c (2275 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_i32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_i32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_u32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_u32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005592753c5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005592753c2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005592753c662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbad5933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbad598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbad5933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbad591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055927535bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055927535ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005592753408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559274fefe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559274fefb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbad591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbad591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbad591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559274fefa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c (2276 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccu_vv_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccu_vx_u16mf4(<vscale x 1 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccu_vv_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccu_vx_u16mf2(<vscale x 2 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccu_vv_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccu_vx_u16m1(<vscale x 4 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccu_vv_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccu_vx_u16m2(<vscale x 8 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccu_vv_u16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.ad
# | ...
# `---data was truncated (10240/79671) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005557e2f41eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005557e2f3ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005557e2f4262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd77c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd77c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd77c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd77c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005557e2ed7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005557e2ed7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005557e2ebc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005557e2b6be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005557e2b6bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd77c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd77c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd77c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005557e2b6ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c (2277 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563140c86eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563140c83e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563140c8762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff2c1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff2c1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff2c1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff2c1d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563140c1cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563140c1ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563140c018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005631408b0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005631408b0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff2c1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff2c1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff2c1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005631408b0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c (2278 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmax_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmax_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmax_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmax_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmax_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmax_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmax_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmax_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmax_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmax_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmax.
# | ...
# `---data was truncated (10240/69313) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005638fc06feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005638fc06ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005638fc07062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4883049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f48830a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4883049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4883031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005638fc005bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005638fc005a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005638fbfea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005638fbc99e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005638fbc99b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4883032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f48830330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f48830330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005638fbc99a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c (2279 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulh_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulh_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulh_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulh_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulh_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulh_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulh_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulh_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulh_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op
# | ...
# `---data was truncated (10240/222917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c8e3aebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c8e3ae8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c8e3aec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d4ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d4ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d4ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d4ad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c8e3a81bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c8e3a81a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c8e3a668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c8e3715e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c8e3715b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1d4ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d4ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d4ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c8e3715a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmullbq.c (2280 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmullbq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmullbq_int_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8>, <16 x i8>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0, i32 0)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1, i32 0)
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmullbq_poly_p16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmullbq_int_m_s8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 0, i32 0, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_m_u16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_m_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <2 x i64>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <2 x i64> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3)
# |   %5 = load <2 x i64>, ptr %inactive.addr, align 8
# |   %6 = call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %1, i32 0, i32 0, <2 x i1> %4, <2 x i64> %5)
# |   ret <2 x i64> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32>, <4 x i32>, i32, i32, <2 x i1>, <2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmullbq_poly_m_p8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 0, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmullbq_int_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 1, i32 0, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 0, i32 0, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |  
# | ...
# `---data was truncated (10240/12050) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564a7d922eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564a7d91fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564a7d92362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbf73849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbf738a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbf73849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbf73831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564a7d8b8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564a7d8b8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564a7d89d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564a7d54ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564a7d54cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbf73832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbf738330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbf738330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564a7d54ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c (2281 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", 
# | ...
# `---data was truncated (10240/16800) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559980a2aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559980a27e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559980a2b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa46da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa46daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa46da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa46da31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005599809c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005599809c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005599809a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559980654e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559980654b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa46da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa46da330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa46da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559980654a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c (2282 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bdd3be5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bdd3be2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bdd3be662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e09449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e094a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e09449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e09431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bdd3b7bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bdd3b7ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bdd3b608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bdd380fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bdd380fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1e09432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e094330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e094330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bdd380fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c (2283 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfne_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfne_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfne_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 32 x bflo
# | ...
# `---data was truncated (10240/27786) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f4b2a9beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f4b2a98e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f4b2a9c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f57c7849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57c78a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f57c7849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f57c7831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f4b2a31bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f4b2a31a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f4b2a168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f4b26c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f4b26c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f57c7832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57c78330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57c78330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f4b26c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c (2284 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eb4a7caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eb4a7c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eb4a7cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f044a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f044a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f044a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f044a31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb4a760bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eb4a760a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eb4a7458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eb4a3f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eb4a3f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f044a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f044a31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f044a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb4a3f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c (2285 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b0e920deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b0e920ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b0e920e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc61b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc61b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc61b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc61b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b0e91a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b0e91a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b0e91888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b0e8e37e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b0e8e37b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc61b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc61b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc61b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b0e8e37a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c (2286 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf8_i64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf8_i64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf8_i64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf8_i64m2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i64> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf8_i64m4_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i64> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf8_i64m8_tum(<vscale x 8 x i1> %mask, <vscale x 8 x i64> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1_tumu(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 
# | ...
# `---data was truncated (10240/18225) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d1c868feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d1c868ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d1c869062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efd5a21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efd5a2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efd5a21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efd5a203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d1c8625bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d1c8625a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d1c860a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d1c82b9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d1c82b9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efd5a204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efd5a2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efd5a2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d1c82b9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c (2287 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c  -check-prefix=RV64ZKNH
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @sha512sig0(i64 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   %1 = load i64, ptr %__x.addr.i, align 8
# |   %2 = call i64 @llvm.riscv.sha512sig0(i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @sha512sig1(i64 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   %1 = load i64, ptr %__x.addr.i, align 8
# |   %2 = call i64 @llvm.riscv.sha512sig1(i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @sha512sum0(i64 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   %1 = load i64, ptr %__x.addr.i, align 8
# |   %2 = call i64 @llvm.riscv.sha512sum0(i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @sha512sum1(i64 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   %1 = load i64, ptr %__x.addr.i, align 8
# |   %2 = call i64 @llvm.riscv.sha512sum1(i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @sha256sig0(i32 noundef signext %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sha256sig0(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @sha256sig1(i32 noundef signext %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sha256sig1(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @sha256sum0(i32 noundef signext %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sha256sum0(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @sha256sum1(i32 noundef signext %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sha256sum1(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.sha512sig0(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.sha512sig1(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.sha512sum0(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.sha512sum1(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha256sig0(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha256sig1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha256sum0(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha256sum1(i32) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zknh" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zknh1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562d0810deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562d0810ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562d0810e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1bfd649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1bfd6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1bfd649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1bfd631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d080a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562d080a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562d080888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562d07d37e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562d07d37b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1bfd632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1bfd6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1bfd6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d07d37a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c -check-prefix=RV64ZKNH
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c -check-prefix=RV64ZKNH
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c (2288 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4a_vv_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4a_vv_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <
# | ...
# `---data was truncated (10240/14421) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005647395b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005647395b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005647395b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f99a4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f99a438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f99a4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f99a431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564739549bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564739549a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056473952e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005647391dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005647391ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f99a431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f99a431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f99a431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005647391dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c (2289 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrec7_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrec7_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrec7_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrec7_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrec7_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrec7_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrec7_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrec7_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrec7_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrec7_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfrec7.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfrec7.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfrec7_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfrec7.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfrec7.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfrec7_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfrec7.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfrec7.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local
# | ...
# `---data was truncated (10240/51412) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bec93d3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bec93d0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bec93d462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbb1ba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbb1baa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbb1ba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbb1ba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bec9369bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bec9369a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bec934e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bec8ffde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bec8ffdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbb1ba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbb1ba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbb1ba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bec8ffda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c (2290 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrec7_v_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrec7_v_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrec7_v_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrec7_v_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrec7_v_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrec7_v_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrec7_v_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrec7_v_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrec7_v_bf16m1_tum(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |  
# | ...
# `---data was truncated (10240/28350) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564b62b3feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564b62b3ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564b62b4062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff44b905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff44b95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff44b905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff44b8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564b62ad5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564b62ad5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564b62aba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564b62769e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564b62769b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff44b8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff44b8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff44b8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564b62769a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c (2291 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64_v_f64m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vle.nxv1f64.p0.i64(<vscale x 1 x double> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x double> @llvm.riscv.vle.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64_v_f64m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.vle.nxv2f64.p0.i64(<vscale x 2 x double> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.riscv.vle.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vle64_v_f64m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.vle.nxv4f64.p0.i64(<vscale x 4 x double> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x double> @llvm.riscv.vle.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vle64_v_f64m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x double> @llvm.riscv.vle.nxv8f64.p0.i64(<vscale x 8 x double> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x double> @llvm.riscv.vle.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64_v_i64m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64_v_i64m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64_v_i64m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64_v_i64m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.p0.i64(<vscale x 8 x i64> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64_v_u64m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64_v_u64m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64_v_u64m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64_v_u64m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.p0.i64(<vscale x 8 x i64> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64_v_f64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vle.mask.nxv1f64.p0.i64(<vscale x 1 x double> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x double> @llvm.riscv.vle.mask.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64_v_f64m2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vle.mask.nxv2f64.p0.i64(<vscale x 2 x double> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.riscv.vle.mask.nxv2f64.p0.i64(<vscale x 2 x d
# | ...
# `---data was truncated (10240/19901) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005568f5f76eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005568f5f73e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005568f5f7762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f02d6f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f02d6f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f02d6f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f02d6f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005568f5f0cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005568f5f0ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005568f5ef18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005568f5ba0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005568f5ba0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f02d6f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f02d6f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f02d6f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005568f5ba0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c (2292 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f16m1x6(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f32m1x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f64m1x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei8_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vsca
# | ...
# `---data was truncated (10240/61665) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005577bee61eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005577bee5ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005577bee6262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff77a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff77a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff77a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff77a231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005577bedf7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005577bedf7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005577beddc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005577bea8be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005577bea8bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff77a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff77a2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff77a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005577bea8ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c (2293 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4(<vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2(<vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslidedown_vx_bf16m1(<vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslidedown_vx_bf16m2(<vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vslidedown_vx_bf16m4(<vscale x 16 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vslidedown_vx_bf16m8(<vscale x 32 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslidedown.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslidedown_vx_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vslidedown.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslidedown.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslidedown_vx_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i
# | ...
# `---data was truncated (10240/14325) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561b331eceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561b331e9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561b331ed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f36e4133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f36e418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f36e4133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f36e411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561b33182bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561b33182a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561b331678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561b32e16e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561b32e16b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f36e411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f36e411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f36e411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561b32e16a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c (2294 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vreinterpret_v_i16mf4_bf16mf4(<vscale x 1 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x i16> %0 to <vscale x 1 x bfloat>
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vreinterpret_v_i16mf2_bf16mf2(<vscale x 2 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x i16> %0 to <vscale x 2 x bfloat>
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vreinterpret_v_i16m1_bf16m1(<vscale x 4 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x i16> %0 to <vscale x 4 x bfloat>
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vreinterpret_v_i16m2_bf16m2(<vscale x 8 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 8 x bfloat>
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vreinterpret_v_i16m4_bf16m4(<vscale x 16 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x i16> %0 to <vscale x 16 x bfloat>
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vreinterpret_v_i16m8_bf16m8(<vscale x 32 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 32 x i16> %0 to <vscale x 32 x bfloat>
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vreinterpret_v_u16mf4_bf16mf4(<vscale x 1 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x i16> %0 to <vscale x 1 x bfloat>
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vreinterpret_v_u16mf2_bf16mf2(<vscale x 2 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x i16> %0 to <vscale x 2 x bfloat>
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vreinterpret_v_u16m1_bf16m1(<vscale x 4 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x i16> %0 to <vscale x 4 x bfloat>
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vreinterpret_v_u16m2_bf16m2(<vscale x 8 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 8 x bfloat>
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vreinterpret_v_u16m4_bf16m4(<vscale x 16 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x i16> %0 to <vscale x 16 x bfloat>
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vreinterpret_v_u16m8_bf16m8(<vscale x 32 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 32 x i16> %0 to <vscale x 32 x bfloat>
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i16> @test_vreinterpret_v_bf16mf4_i16mf4(<vscale x 1 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x bfloat> %0 to <vscale x 1 x i16>
# |   ret <vscale x 1 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i16> @test_vreinterpret_v_bf16mf2_i16mf2(<vscale x 2 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x bfloat> %0 to <vscale x 2 x i16>
# |   ret <vscale x 2 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i16> @test_vreinterpret_v_bf16m1_i16m1(<vscale x 4 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x bfloat> %0 to <vscale x 4 x i16>
# |   ret <vscale x 4 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i16> @test_vreinterpret_v_bf16m2_i16m2(<vscale x 8 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x bfloat> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i16> @test_vreinterpret_v_bf16m4_i16m4(<vscale x 16 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x bfloat> %0 to <vscale x 16 x i16>
# |   ret <vscale x 16 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i16> @test_vreinterpret_v_bf16m8_i16m8(<vscale x 32 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 32 x bfloat> %0 to <vscale x 32 x i16>
# |   ret <vscale x 32 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i16> @test_vreinterpret_v_bf16mf4_u16mf4(<vscale x 1 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x bfloat> %0 to <vscale x 1 x i16>
# |   ret <vscale x 1 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i16> @test_vreinterpret_v_bf16mf2_u16mf2(<vscale x 2 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x bfloat> %0 to <vscale x 2 x i16>
# |   ret <vscale x 2 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i16> @test_vreinterpret_v_bf16m1_u16m1(<vscale x 4 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x bfloat> %0 to <vscale x 4 x i16>
# |   ret <vscale x 4 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i16> @test_vreinterpret_v_bf16m2_u16m2(<vscale x 8 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x bfloat> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i16> @test_vreinterpret_v_bf16m4_u16m4(<vscale x 16 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x bfloat> %0 to <vsca
# | ...
# `---data was truncated (10240/11229) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557dbfbb8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557dbfbb5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557dbfbb962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb595c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb595ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb595c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb595c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557dbfb4ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557dbfb4ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557dbfb338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557dbf7e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557dbf7e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb595c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb595c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb595c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557dbf7e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c (2295 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f16m1x7(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f32m1x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f64m1x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei32_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d4af06aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d4af067e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d4af06b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe197933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe19798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe197933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe19791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d4af000bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d4af000a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d4aefe58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d4aec94e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d4aec94b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe19791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe19791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe19791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d4aec94a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c (2296 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei8_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, p
# | ...
# `---data was truncated (10240/14521) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556e4b58ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556e4b589e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556e4b58d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc150333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc15038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc150333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc15031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e4b522bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556e4b522a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556e4b5078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556e4b1b6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556e4b1b6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc15031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc15031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc15031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e4b1b6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c (2297 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjx_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjx_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjx_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjx_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjx_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjx_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjx_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjx_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjx_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjx_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory
# | ...
# `---data was truncated (10240/69669) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005600fa97ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005600fa979e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005600fa97d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffaa0733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffaa078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffaa0733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffaa071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005600fa912bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005600fa912a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005600fa8f78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005600fa5a6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005600fa5a6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffaa071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffaa071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffaa071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005600fa5a6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c (2298 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vcpop_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vcpop_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vcpopv.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vcpopv.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vcpop_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vcpopv.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vcpopv.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vcpop_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vcpopv.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vcpopv.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vcpop_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vcpopv.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vcpopv.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vcpop_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vcpopv.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vcpopv.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vcpop_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vcpopv.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vcpopv.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vcpop_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vcpopv.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vcpopv.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vcpop_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vcpopv.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vcpopv.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vcpop_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vcpopv.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vcpopv.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vs
# | ...
# `---data was truncated (10240/95355) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056281e012eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056281e00fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056281e01362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbb9761bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbb976725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbb9761ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbb97603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056281dfa8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056281dfa8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056281df8d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056281dc3ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056281dc3cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbb97604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbb976050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbb976050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056281dc3ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c (2299 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4a_vx_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4a_vx_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_l
# | ...
# `---data was truncated (10240/13585) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056370ccc6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056370ccc3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056370ccc762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f49cc533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f49cc58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f49cc533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f49cc51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056370cc5cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056370cc5ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056370cc418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056370c8f0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056370c8f0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f49cc51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f49cc51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f49cc51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056370c8f0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c (2300 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulh_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulh_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulh_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulh_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulh_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulh_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulh_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulh_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulh_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulh_vx_i8m4(<vscale x 32 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 64 x i8> @test_vmulh_vv_i8m8(<vscale x 64 x i8> %op1, <vscale x 64 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %op1.addr, al
# | ...
# `---data was truncated (10240/65723) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005584a6f07eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005584a6f04e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005584a6f0862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc667133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc66718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc667133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc66711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005584a6e9dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005584a6e9da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005584a6e828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005584a6b31e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005584a6b31b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc66711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc66711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc66711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005584a6b31a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c (2301 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f16m1x5(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f32m1x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f64m1x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei64_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a348ae1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a348adee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a348ae262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f742c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f742c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f742c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f742c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a348a77bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a348a77a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a348a5c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a34870be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a34870bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f742c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f742c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f742c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a34870ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c (2302 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredsum_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretu
# | ...
# `---data was truncated (10240/113047) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005592f4048eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005592f4045e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005592f404962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5c5c21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5c5c2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5c5c21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5c5c203507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005592f3fdebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005592f3fdea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005592f3fc38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005592f3c72e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005592f3c72b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5c5c204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5c5c2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5c5c2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005592f3c72a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c (2303 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwcvt_x_x_v_i16mf4(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwcvt_x_x_v_i16mf2(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwcvt_x_x_v_i16m1(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwcvt_x_x_v_i16m2(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwcvt_x_x_v_i16m4(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwcvt_x_x_v_i16m8(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwcvt_x_x_v_i32mf2(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwcvt_x_x_v_i32m1(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwcvt_x_x_v_i32m2(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vwcvt_x_x_v_i32m4(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vwcvt_x_x_v_i32m8(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vwadd.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vwadd.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vwcvt_x_x_v_i64m1(<vscale x 1 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> %0, i32 0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i32, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vwcvt_x_x_v_i64m2(<vscale x 2 x i32> %src, i64 noundef
# | ...
# `---data was truncated (10240/29167) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d6e5fd8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d6e5fd5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d6e5fd962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7125333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f712538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7125333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f712531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d6e5f6ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d6e5f6ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d6e5f538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d6e5c02e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d6e5c02b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f712531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f712531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f712531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d6e5c02a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c (2304 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005594808b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005594808b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005594808b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f74ee333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f74ee38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f74ee333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f74ee31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055948084bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055948084ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005594808308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005594804dfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005594804dfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f74ee31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f74ee31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f74ee31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005594804dfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c (2305 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4(<vscale x 16 x half> %vd, <vscale x 16 x half> %v
# | ...
# `---data was truncated (10240/148843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055da49afaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055da49af7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055da49afb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc05933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc0598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc05933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc0591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da49a90bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055da49a90a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055da49a758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055da49724e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055da49724b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efc0591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc0591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc0591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da49724a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c (2306 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vlm_v_b1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vlm.nxv64i1.p0.i64(ptr %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i1> @llvm.riscv.vlm.nxv64i1.p0.i64(ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vlm_v_b2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vlm.nxv32i1.p0.i64(ptr %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i1> @llvm.riscv.vlm.nxv32i1.p0.i64(ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vlm_v_b4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vlm.nxv16i1.p0.i64(ptr %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i1> @llvm.riscv.vlm.nxv16i1.p0.i64(ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vlm_v_b8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vlm.nxv8i1.p0.i64(ptr %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i1> @llvm.riscv.vlm.nxv8i1.p0.i64(ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vlm_v_b16(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vlm.nxv4i1.p0.i64(ptr %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i1> @llvm.riscv.vlm.nxv4i1.p0.i64(ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vlm_v_b32(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vlm.nxv2i1.p0.i64(ptr %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i1> @llvm.riscv.vlm.nxv2i1.p0.i64(ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vlm_v_b64(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vlm.nxv1i1.p0.i64(ptr %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i1> @llvm.riscv.vlm.nxv1i1.p0.i64(ptr captures(none), i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a6f41f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a6f41eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a6f41f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e6bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e6bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e6bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e6bf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a6f4187bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a6f4187a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a6f416c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a6f3e1be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a6f3e1bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6e6bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e6bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e6bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a6f3e1ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c (2307 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_f64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_i64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_u64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055be8f29beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055be8f298e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055be8f29c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0520049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f05200a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0520049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0520031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055be8f231bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055be8f231a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055be8f2168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055be8eec5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055be8eec5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0520032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f05200330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f05200330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055be8eec5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c (2308 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056419129feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056419129ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005641912a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b36e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b36ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b36e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b36e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564191235bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564191235a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056419121a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564190ec9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564190ec9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4b36e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b36e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b36e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564190ec9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c (2309 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_q_f8e4m3mf8(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf8(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_q_f8e4m3mf4(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf4(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_q_f8e4m3mf2(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf2(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_f_f_q_f8e4m3m1(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_sat_f_f_q_f8e4m3m1(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_f_f_q_f8e4m3m2(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_sat_f_f_q_f8e4m3m2(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_q_f8e4m3mf8_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf8_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   s
# | ...
# `---data was truncated (10240/69534) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564632639eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564632636e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056463263a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa2d2d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa2d2d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa2d2d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa2d2d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005646325cfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005646325cfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005646325b48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564632263e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564632263b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa2d2d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa2d2d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa2d2d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564632263a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c (2310 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f    -target-feature +xsfvfexp32e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexp_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexp_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexp_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexp_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32.i64(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfexp_v_f32m8_tu(<vscale x 16 x float> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32.i64(<vscale x 16 x float> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexp_v_f32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(<vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexp_v_f32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(<vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexp_v_f32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(<vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexp_v_f32m4_tum(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(<vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(<vscale x 8 x fl
# | ...
# `---data was truncated (10240/22298) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dcb935beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dcb9358e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dcb935c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7fb201bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7fb20725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7fb201ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7fb2003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dcb92f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dcb92f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dcb92d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dcb8f85e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dcb8f85b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7fb2004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7fb20050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7fb20050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dcb8f85a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c (2311 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vunzipo_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 2 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vunzipo_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 4 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vunzipo_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 8 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vunzipo_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 16 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vunzipo_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 32 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005643a6512eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005643a650fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005643a651362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb82f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb82f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb82f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb82f631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005643a64a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005643a64a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005643a648d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005643a613ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005643a613cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb82f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb82f6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb82f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005643a613ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c (2312 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055689d144eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055689d141e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055689d14562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f02d9049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f02d90a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f02d9049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f02d9031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055689d0dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055689d0daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055689d0bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055689cd6ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055689cd6eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f02d9032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f02d90330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f02d90330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055689cd6ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c (2313 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f16m1x6(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f32m1x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f64m1x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i64> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557bcaf18eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557bcaf15e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557bcaf1962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbb6b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbb6b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbb6b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbb6b31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557bcaeaebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557bcaeaea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557bcae938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557bcab42e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557bcab42b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbb6b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbb6b31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbb6b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557bcab42a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vrhaddq.c (2314 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vrhaddq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrhaddq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vrhadd.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vrhadd.v16i8(<16 x i8>, <16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrhaddq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vrhadd.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vrhadd.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrhaddq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vrhadd.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vrhadd.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrhaddq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.rhadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.rhadd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrhaddq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.rhadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.rhadd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrhaddq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.rhadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.rhadd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrhaddq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.rhadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrhaddq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.rhadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrhaddq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.rhadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d3e2cf0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d3e2cede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d3e2cf162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5755933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f575598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5755933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f575591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d3e2c86bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d3e2c86a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d3e2c6b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d3e291ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d3e291ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f575591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f575591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f575591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d3e291aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c (2315 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562619cb7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562619cb4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562619cb862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff8b1133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff8b118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff8b1133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff8b111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562619c4dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562619c4da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562619c328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005626198e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005626198e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff8b111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff8b111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff8b111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005626198e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c (2316 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willr
# | ...
# `---data was truncated (10240/44361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a311705eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a311702e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a31170662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa4ced33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa4ced8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa4ced33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa4ced1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a31169bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a31169ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a3116808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a31132fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a31132fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa4ced1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4ced1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4ced1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a31132fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/distributed-thin-lto/supports-hot-cold-new.ll (2317 of 27911)
******************** TEST 'Clang :: CodeGen/distributed-thin-lto/supports-hot-cold-new.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 8
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/supports-hot-cold-new.ll >/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/supports-hot-cold-new.ll.tmp.o
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/supports-hot-cold-new.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/supports-hot-cold-new.ll
# |  #0 0x000055ffcc78beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ffcc788e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ffcc78c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9c34849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9c348a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9c34849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9c34831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ffcc721bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ffcc721a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ffcc7068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ffcc3b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ffcc3b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9c34832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9c348330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9c348330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ffcc3b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c (2318 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgeu_vv_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgeu_vx_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgeu_vv_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgeu_vx_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgeu_vv_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgeu_vx_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgeu_vv_u8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8
# | ...
# `---data was truncated (10240/63713) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b822750eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b82274de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b82275162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd61d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd61d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd61d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd61d11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b8226e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b8226e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b8226cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b82237ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b82237ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd61d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd61d11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd61d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b82237aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp (2319 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme    -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | %class.anon = type { i8 }
# | 
# | $_Z15template_functyIiET_S0_ = comdat any
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local i32 @streaming_caller() #0 {
# | entry:
# |   %call = call i32 @normal_callee()
# |   ret i32 %call
# | }
# | 
# | declare i32 @normal_callee() #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local i32 @streaming_callee() #0 {
# | entry:
# |   %call = call i32 @streaming_decl() #15
# |   ret i32 %call
# | }
# | 
# | declare i32 @streaming_decl() #2
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @streaming_compatible_caller() #3 {
# | entry:
# |   %call = call i32 @normal_callee()
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @streaming_compatible_callee() #3 {
# | entry:
# |   %call = call i32 @streaming_compatible_decl() #16
# |   ret i32 %call
# | }
# | 
# | declare i32 @streaming_compatible_decl() #4
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local i32 @locally_streaming_caller() #5 {
# | entry:
# |   %call = call i32 @normal_callee()
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local i32 @locally_streaming_callee() #5 {
# | entry:
# |   %call = call i32 @locally_streaming_caller() #17
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @shared_za_caller() #6 {
# | entry:
# |   %call = call i32 @normal_callee()
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @shared_za_callee() #6 {
# | entry:
# |   %call = call i32 @shared_za_decl() #18
# |   ret i32 %call
# | }
# | 
# | declare i32 @shared_za_decl() #7
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @preserves_za_caller() #8 {
# | entry:
# |   %call = call i32 @normal_callee()
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @preserves_za_callee() #8 {
# | entry:
# |   %call = call i32 @preserves_za_decl() #19
# |   ret i32 %call
# | }
# | 
# | declare i32 @preserves_za_decl() #9
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @new_za_caller() #10 {
# | entry:
# |   %call = call i32 @normal_callee()
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @new_za_callee() #10 {
# | entry:
# |   %call = call i32 @private_za_decl()
# |   ret i32 %call
# | }
# | 
# | declare i32 @private_za_decl() #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @agnostic_za_caller() #11 {
# | entry:
# |   %call = call i32 @normal_callee()
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @agnostic_za_callee() #12 {
# | entry:
# |   %call = call i32 @agnostic_za_decl() #20
# |   ret i32 %call
# | }
# | 
# | declare i32 @agnostic_za_decl() #13
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @agnostic_za_callee_live_za() #6 {
# | entry:
# |   %call = call i32 @agnostic_za_decl() #20
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @test_streaming_ptrty(ptr noundef %f, i32 noundef %x, i32 noundef %y) #12 {
# | entry:
# |   %f.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   %y.addr = alloca i32, align 4
# |   store ptr %f, ptr %f.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   store i32 %y, ptr %y.addr, align 4
# |   %0 = load ptr, ptr %f.addr, align 8
# |   %1 = load i32, ptr %x.addr, align 4
# |   %2 = load i32, ptr %y.addr, align 4
# |   call void %0(i32 noundef %1, i32 noundef %2) #15
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @test_streaming_compatible_ptrty(ptr noundef %f, i32 noundef %x, i32 noundef %y) #12 {
# | entry:
# |   %f.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   %y.addr = alloca i32, align 4
# |   store ptr %f, ptr %f.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   store i32 %y, ptr %y.addr, align 4
# |   %0 = load ptr, ptr %f.addr, align 8
# |   %1 = load i32, ptr %x.addr, align 4
# |   %2 = load i32, ptr %y.addr, align 4
# |   call void %0(i32 noundef %1, i32 noundef %2) #16
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @test_shared_za(ptr noundef %f, i32 noundef %x, i32 noundef %y) #6 {
# | entry:
# |   %f.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   %y.addr = alloca i32, align 4
# |   store ptr %f, ptr %f.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   store i32 %y, ptr %y.addr, align 4
# |   %0 = load ptr, ptr %f.addr, align 8
# |   %1 = load i32, ptr %x.addr, align 4
# |   %2 = load i32, ptr %y.addr, align 4
# |   call void %0(i32 noundef %1, i32 noundef %2) #18
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @test_preserved_za(ptr noundef %f, i32 noundef %x, i32 noundef %y) #6 {
# | entry:
# |   %f.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   %y.addr = alloca i32, align 4
# |   store ptr %f, ptr %f.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   store i32 %y, ptr %y.addr, align 4
# |   %0 = load ptr, ptr %f.addr, align 8
# |   %1 = load i32, ptr %x.addr, align 4
# |   %2 = load i32, ptr %y.addr, align 4
# |   call void %0(i32 noundef %1, i32 noundef %2) #19
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @test_indirect_streaming_ptrty(ptr noundef %fptr, i32 noundef %x, i32 noundef %y) #12 {
# | entry:
# |   %fptr.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   %y.addr = alloca i32, align 4
# |   store ptr %fptr, ptr %fptr.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   store i32 %y, ptr %y.addr, align 4
# |   %0 = load ptr, ptr %fptr.addr, align 8
# |   %1 = load ptr, ptr %0, align 8
# |   %2 = load ptr, ptr %1, align 8
# |   %3 = load i32, ptr %x.addr, align 4
# |   %4 = load i32, ptr %y.addr, align 4
# |   call void %2(i32 noundef %3, i32 noundef %4) #15
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @_Z24test_same_type_streamingv() #12 {
# | entry:
# |   call void @_Z10streaming1v() #15
# |   call void @_Z10streaming2v() #15
# |   call void @_Z20same_type_streaming1v() #15
# |   call void @_Z20same_type_streaming2v() #15
# |   ret void
# | }
# | 
# | declare void @_Z10streaming1v() #2
# | 
# | declare void @_Z10streaming2v() #2
# | 
# | declare void @_Z20same_type_streaming1v() #2
# | 
# | declare void @_Z20same_type_streaming2v() #2
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local noundef i32 @_Z12overloadedfni(i32 noundef %x) #0 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local noundef float @_Z12overloadedfnf(float noundef %x) #12 {
# | entry:
# |   %x.addr = alloca float, align 4
# |   store float %x, ptr %x.addr, align 4
# |   %0 = load float, ptr %x.addr, align 4
# |   ret float %0
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local noundef i32 @_Z13test_overloadi(i32 noundef %x) #12 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = call noundef i32 @_Z12overloadedfni(i32 noundef %0) #15
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local noundef float @_Z13test_overloadf(float noundef %x) #12 {
# | entry:
# |   %x.addr = alloca float, align 4
# |   store float %x, ptr %x.addr, align 4
# |   %0 = load float, ptr %x.addr, align 4
# |   %call = call noundef float @_Z12overloadedfnf(float noundef %0)
# |   ret float %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local noundef i32 @_Z11test_lambdai(i32 noundef %x) #12 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   %F = alloca %class.anon, align 1
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = call noundef i32 @"_ZZ11test_lambdaiENK3$_0clEi"(ptr noundef nonnull align 1 dereferenceable(1) %F, i32 noundef %0) #15
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define internal noundef i32 @"_ZZ11test_lambdaiENK3$_0clEi"(ptr noundef nonnull align 1 dereferenceable(1) %this, i32 noundef %x) #0 {
# | entry:
# |   %this.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   store ptr %this, ptr %this.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   %this1 = load ptr, ptr %this.addr, align 8
# |   %0 = load i32, ptr %x.addr, align 4
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local noundef i32 @_Z27test_template_instantiationv() #12 {
# | entry:
# |   %call = call noundef i32 @_Z15template_functyIiET_S0_(i32 noundef 12) #15
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define linkonce_odr noundef i32 @_Z15template_functyIiET_S0_(i32 noundef %x) #0 comdat {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local void @_Z25locally_streaming_inheritv() #5 {
# | entry:
# |   %call = call i32 @streaming_decl() #15
# |   ret void
# | }
# | 
# | ; Function Attrs: alwaysinline mustprogress nounwind
# | define dso_local noundef i32 @_Z4callv() #14 {
# | entry:
# |   ret i32 0
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local noundef i32 @_Z22test_variadic_templatev() #6 {
# | entry:
# |   %f.addr.i16 = alloca ptr, align 8
# |   %f.addr.i12 = alloca ptr, align 8
# |   %other.addr.i13 = alloca ptr, align 8
# |   %f.addr.i7 = alloca ptr, align 8
# |   %other.addr.i8 = alloca ptr, align 8
# |   %other.addr2.i9 = alloca ptr, align 8
# |   %f.addr.i1 = alloca ptr, align 8
# |   %other.addr.i2 = alloca ptr, align 8
# |   %other.addr2.i3 = alloca ptr, align 8
# |   %other.addr4.i4 = alloca ptr, align 8
# |   %f.addr.i = alloca ptr, align 8
# |   %other.addr.i = alloca ptr, align 8
# |   %other.addr2.i = alloca ptr, align 8
# |   %other.addr4.i = alloca ptr, align 8
# |   %other.addr6.i = alloca ptr, align 8
# |   store ptr @normal_callee, ptr %f.addr.i, align 8
# |   store ptr @streaming_decl, ptr %other.addr.i, align 8
# |   store ptr @streaming_compatible_decl
# | ...
# `---data was truncated (10240/15241) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564b3c9bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564b3c9b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564b3c9bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6c92449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6c924a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6c92449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6c92431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564b3c952bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564b3c952a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564b3c9378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564b3c5e6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564b3c5e6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6c92432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6c924330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6c924330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564b3c5e6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline
# |  #0 0x00005605e69a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005605e69a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005605e69a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fae9a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fae9a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fae9a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fae9a11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005605e693dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005605e693da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005605e69228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005605e65d1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005605e65d1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fae9a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fae9a11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fae9a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005605e65d1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c (2320 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f16m1x7(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f32m1x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f64m1x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef
# | ...
# `---data was truncated (10240/69988) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f1ddd0beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f1ddd08e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f1ddd0c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f564ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f564caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f564ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f564ca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f1ddca1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f1ddca1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f1ddc868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f1dd935e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f1dd935b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f564ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f564ca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f564ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f1dd935a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c (2321 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_f16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_f16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_f16m1x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_i16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_i16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_i16m1x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_u16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_u16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_u16m1x7_m(<vs
# | ...
# `---data was truncated (10240/11851) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562abe6f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562abe6eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562abe6f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f67cad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f67cad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f67cad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f67cad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562abe687bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562abe687a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562abe66c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562abe31be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562abe31bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f67cad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67cad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67cad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562abe31ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c (2322 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f16m1x8(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f32m1x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f64m1x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i32> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f78eb72eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f78eb6fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f78eb7362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc929a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc929aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc929a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc929a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f78eb08bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f78eb08a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f78eaed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f78e79ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f78e79cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc929a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc929a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc929a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f78e79ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c (2323 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f16m1x7(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f32m1x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f64m1x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei16_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b3a2c51eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b3a2c4ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b3a2c5262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c0f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c0f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c0f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c0f431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b3a2be7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b3a2be7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b3a2bcc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b3a287be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b3a287bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1c0f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c0f4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c0f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b3a287ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c (2324 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vpaire_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vpaire.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vpaire.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vpaire_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vpaire.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vpaire.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vpaire_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vpaire.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vpaire.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vpaire_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vpaire.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vpaire.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vpaire_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vpaire.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vpaire.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vpaire_vv_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vpaire.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vpaire.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vpaire_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vpaire.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vpaire.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vpaire_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vpaire.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vpaire.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vpaire_vv_f32m2_tu
# | ...
# `---data was truncated (10240/288275) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a9ee28deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a9ee28ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a9ee28e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2971849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f29718a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2971849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2971831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a9ee223bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a9ee223a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a9ee2088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a9edeb7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a9edeb7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2971832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f29718330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f29718330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a9edeb7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c (2325 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjn_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjn_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjn_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjn_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjn_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjn_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjn_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjn_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnjn_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnjn_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr 
# | ...
# `---data was truncated (10240/29202) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560663b2ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560663b29e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560663b2d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f503cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f503cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f503cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f503cf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560663ac2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560663ac2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560663aa78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560663756e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560663756b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f503cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f503cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f503cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560663756a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c (2326 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f    -target-feature +xsfvfexp32e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexp_v_f32mf2(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexp_v_f32m1(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexp_v_f32m2(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexp_v_f32m4(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfexp_v_f32m8(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexp_v_f32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexp_v_f32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexp_v_f32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexp_v_f32m4_m(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfexp_v_f32m8_m(<vscale x 16 x i1> %vm, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.sf.vfexp.mask.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfexp.mask.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfvfexp32e,+zicsr,+zve32f,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfvfexp32e0p5"}
# | !3 = !{i32 8, !"Sma
# | ...
# `---data was truncated (10240/10293) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557492342eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055749233fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055749234362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2258133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f225818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2258133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f225811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005574922d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005574922d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005574922bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557491f6ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557491f6cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f225811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f225811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f225811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557491f6ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c (2327 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_u64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_u64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <v
# | ...
# `---data was truncated (10240/16552) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa8b54deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fa8b54ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fa8b54e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7811e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7811ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7811e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7811e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa8b4e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fa8b4e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fa8b4c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fa8b177e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fa8b177b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7811e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7811e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7811e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa8b177a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c (2328 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste8_i8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste8.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.sf.vste8.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste8_u8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste8.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557765ebceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557765eb9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557765ebd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f48a5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f48a52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f48a5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f48a5231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557765e52bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557765e52a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557765e378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557765ae6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557765ae6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f48a5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f48a52330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f48a52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557765ae6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c (2329 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vneg_v_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vneg_v_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vneg_v_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vneg_v_i8m1(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vneg_v_i8m2(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vneg_v_i8m4(<vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vneg_v_i8m8(<vscale x 64 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vneg_v_i16mf4(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vneg_v_i16mf2(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vneg_v_i16m1(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vneg_v_i16m2(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vrsub.nxv8i16.i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vrsub.nxv8i16.i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vneg_v_i16m4(<vscale x 16 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vrsub.nxv16i16.i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vrsub.nxv16i16.i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vneg_v_i16m8(<vscale x 32 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = c
# | ...
# `---data was truncated (10240/41433) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005615c9ea9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005615c9ea6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005615c9eaa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f997541bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f99754725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f997541ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9975403507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005615c9e3fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005615c9e3fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005615c9e248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005615c9ad3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005615c9ad3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9975404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f99754050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f99754050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615c9ad3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c (2330 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsqrt_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsqrt_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsqrt_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsqrt_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsqrt_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfsqrt_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfsqrt_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfsqrt_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfsqrt_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfsqrt_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfsqrt.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfsqrt.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfsqrt_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfsqrt.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfsqrt.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfsqrt_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfsqrt.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfsqrt.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define d
# | ...
# `---data was truncated (10240/51420) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055af08898eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055af08895e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055af0889962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe42a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe42a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe42a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe42a31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055af0882ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055af0882ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055af088138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055af084c2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055af084c2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe42a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe42a31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe42a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055af084c2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c (2331 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredsum_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredsum_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredsum_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   stor
# | ...
# `---data was truncated (10240/94371) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005556c11c6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005556c11c3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005556c11c762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b51b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b51b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b51b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b51b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005556c115cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005556c115ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005556c11418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005556c0df0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005556c0df0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3b51b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b51b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b51b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005556c0df0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c (2332 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055afcd0d0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055afcd0cde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055afcd0d162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcbeb849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcbeb8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcbeb849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcbeb831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055afcd066bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055afcd066a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055afcd04b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055afcccfae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055afcccfab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcbeb832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcbeb8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcbeb8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055afcccfaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c (2333 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_f32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_i32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_i32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_i32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_u32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_u32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vsc
# | ...
# `---data was truncated (10240/53446) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559ef1486eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559ef1483e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559ef148762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f30e5a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f30e5a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f30e5a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f30e5a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559ef141cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559ef141ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559ef14018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559ef10b0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559ef10b0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f30e5a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f30e5a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f30e5a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559ef10b0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c (2334 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c12d209eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c12d206e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c12d20a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e8e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e8e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e8e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e8e431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c12d19fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c12d19fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c12d1848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c12ce33e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c12ce33b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4e8e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e8e4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e8e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c12ce33a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c (2335 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560810863eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560810860e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056081086462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbe9b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbe9b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbe9b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbe9b11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005608107f9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005608107f9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005608107de8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056081048de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056081048db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbe9b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbe9b11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbe9b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056081048da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c (2336 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1(<vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x double> @test_sf_vfexpa_v_f64m2(<vscale x 2 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64.i64(<vscale x 2 x double> poison, <vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64.i64(<vscale x 2 x double>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x double> @test_sf_vfexpa_v_f64m4(<vscale x 4 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64.i64(<vscale x 4 x double> poison, <vscale x 4 x double> %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64.i64(<vscale x 4 x double>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vfexpa_v_f64m8(<vscale x 8 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64.i64(<vscale x 8 x double> poison, <vscale x 8 x double> %0, i64 %1)
# |   ret <vscale x 8 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64.i64(<vscale x 8 x double>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1_m(<vscale x 1 x i1> %vm, <vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x double> @test_sf_vfexpa_v_f64m2_m(<vscale x 2 x i1> %vm, <vscale x 2 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(<vscale x 2 x double> poison, <vscale x 2 x double> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x double> @test_sf_vfexpa_v_f64m4_m(<vscale x 4 x i1> %vm, <vscale x 4 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(<vscale x 4 x double> poison, <vscale x 4 x double> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(<vscale x 4 x double>, <vscale x 4 x double>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vfexpa_v_f64m8_m(<vscale x 8 x i1> %vm, <vscale x 8 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(<vscale x 8 x double> poison, <vscale x 8 x double> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(<vscale x 8 x double>, <vscale x 8 x double>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+xsfvfexpa,+xsfvfexpa64e,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfvfexpa0p2_xsfvfexpa64e0p2"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055791ae07eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055791ae04e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055791ae0862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4981b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4981b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4981b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4981b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055791ad9dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055791ad9da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055791ad828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055791aa31e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055791aa31b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4981b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4981b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4981b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055791aa31a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c (2337 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpairo_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vpairo.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpairo.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpairo_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vpairo.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpairo.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpairo_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vpairo.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vpairo.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vpairo_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vpairo.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vpairo.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vpairo_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vpairo.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vpairo.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vpairo_vv_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, <vscale x 32 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vpairo.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vpairo.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpairo_vv_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vpairo.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpairo.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpairo_vv_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, 
# | ...
# `---data was truncated (10240/32646) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056097e576eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056097e573e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056097e57762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f20fc449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f20fc4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f20fc449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f20fc431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056097e50cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056097e50ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056097e4f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056097e1a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056097e1a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f20fc432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f20fc4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f20fc4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056097e1a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c (2338 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesbfhcvt -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c -o -    -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesbfhcvt -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_fcvt_s_bf16(bfloat noundef %bf) #0 {
# | entry:
# |   %bf.addr.i = alloca bfloat, align 2
# |   %bf.addr = alloca bfloat, align 2
# |   store bfloat %bf, ptr %bf.addr, align 2
# |   %0 = load bfloat, ptr %bf.addr, align 2
# |   store bfloat %0, ptr %bf.addr.i, align 2
# |   %1 = load bfloat, ptr %bf.addr.i, align 2
# |   %2 = fpext bfloat %1 to float
# |   ret float %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local bfloat @test_fcvt_bf16_s(float noundef %sf) #0 {
# | entry:
# |   %sf.addr.i = alloca float, align 4
# |   %sf.addr = alloca float, align 4
# |   store float %sf, ptr %sf.addr, align 4
# |   %0 = load float, ptr %sf.addr, align 4
# |   store float %0, ptr %sf.addr.i, align 4
# |   %1 = load float, ptr %sf.addr.i, align 4
# |   %2 = fptrunc float %1 to bfloat
# |   ret bfloat %2
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+f,+i,+xandesbfhcvt,+zicsr" }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_f2p2_zicsr2p0_xandesbfhcvt5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f7a5fcceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f7a5fc9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f7a5fcd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4a4c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4a4c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4a4c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4a4c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f7a5f62bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f7a5f62a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f7a5f478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f7a5bf6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f7a5bf6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4a4c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4a4c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4a4c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f7a5bf6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c (2339 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f16m1x3(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_f16m2x3(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f32m1x3(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_f32m2x3(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f64m1x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/82983) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557de1914eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557de1911e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557de191562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd3841bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd384725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd3841ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd38403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557de18aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557de18aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557de188f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557de153ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557de153eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdd38404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd384050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd384050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557de153ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c (2340 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfwcvt_f_x_v_f16mf4(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfwcvt_f_x_v_f16mf2(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfwcvt_f_x_v_f16m1(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfwcvt_f_x_v_f16m2(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfwcvt_f_x_v_f16m4(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfwcvt_f_x_v_f16m8(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfwcvt_f_xu_v_f16mf4(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfwcvt_f_xu_v_f16mf2(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfwcvt_f_xu_v_f16m1(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfwcvt_f_xu_v_f16m2(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfwcvt_f_xu_v_f16m4(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfwcvt_f_xu_v_f16m8(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_x_f_v_i32mf2(<
# | ...
# `---data was truncated (10240/119297) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005643c3319eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005643c3316e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005643c331a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f44f4449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f44f44a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f44f4449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f44f4431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005643c32afbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005643c32afa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005643c32948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005643c2f43e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005643c2f43b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f44f4432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44f44330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44f44330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005643c2f43a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c (2341 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei8_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei8_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei8_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei8_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei8_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i8> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vloxei8_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, <vscale x 32 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i8> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei8_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei8_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function A
# | ...
# `---data was truncated (10240/30415) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005601ed62deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005601ed62ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005601ed62e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc30a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc30aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc30a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc30a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005601ed5c3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005601ed5c3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005601ed5a88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005601ed257e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005601ed257b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcc30a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc30a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc30a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005601ed257a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c (2342 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsle_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsle_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsle_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsle_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsle_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsle_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsle_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsle_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsle_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsle_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsle_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsle.nxv32i8.nxv32i8.i64(<vscale x 32 x 
# | ...
# `---data was truncated (10240/95089) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560d3de24eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560d3de21e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560d3de2562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffbd7f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffbd7f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffbd7f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffbd7eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560d3ddbabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560d3ddbaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560d3dd9f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560d3da4ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560d3da4eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffbd7eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffbd7eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffbd7eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560d3da4ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c (2343 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsge_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsge_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsge_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsge_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsge_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsge_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsge_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | 
# | ...
# `---data was truncated (10240/63571) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559cbbd02eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559cbbcffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559cbbd0362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f199e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f199e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f199e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f199e631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559cbbc98bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559cbbc98a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559cbbc7d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559cbb92ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559cbb92cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f199e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f199e6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f199e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559cbb92ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c (2344 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c8f10abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c8f10a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c8f10ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9f9ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9f9eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9f9ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9f9ea31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c8f1041bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c8f1041a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c8f10268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c8f0cd5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c8f0cd5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9f9ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9f9ea330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9f9ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c8f0cd5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c (2345 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwcvtu_x_x_v_u16mf4(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwcvtu_x_x_v_u16mf2(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwcvtu_x_x_v_u16m1(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwcvtu_x_x_v_u16m2(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwcvtu_x_x_v_u16m4(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwcvtu_x_x_v_u16m8(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwcvtu_x_x_v_u32mf2(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwcvtu_x_x_v_u32m1(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwcvtu_x_x_v_u32m2(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vwcvtu_x_x_v_u32m4(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vwcvtu_x_x_v_u32m8(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vwcvtu_x_x_v_u64m1(<vscale x 1 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> %0, i32 0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i32, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vwcvtu_x
# | ...
# `---data was truncated (10240/29267) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559720e21eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559720e1ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559720e2262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f150d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f150d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f150d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f150d631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559720db7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559720db7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559720d9c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559720a4be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559720a4bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f150d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f150d6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f150d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559720a4ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c (2346 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei32_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 
# | ...
# `---data was truncated (10240/284344) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c8032b6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c8032b3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c8032b762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb7b001bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb7b00725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb7b001ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb7b0003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c80324cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c80324ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c8032318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c802ee0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c802ee0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb7b0004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb7b00050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb7b00050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c802ee0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c (2347 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f13fe5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559f13fe2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559f13fe662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffa60849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffa608a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffa60849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffa60831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f13f7bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559f13f7ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559f13f608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559f13c0fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559f13c0fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffa60832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffa608330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffa608330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f13c0fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c (2348 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2cl_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2cl_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2cl_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2cl_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2cl_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2cl_vv_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2cl_vv_u64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2cl_vv_u64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define d
# | ...
# `---data was truncated (10240/12208) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556fb1442eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556fb143fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556fb144362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe220533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe22058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe220533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe22051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556fb13d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556fb13d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556fb13bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556fb106ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556fb106cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe22051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe22051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe22051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556fb106ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c (2349 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrec7_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrec7_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrec7_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrec7_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrec7_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrec7_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrec7_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrec7_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrec7_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrec7_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfrec7.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfrec7.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfrec7_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfrec7.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfrec7.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfrec7_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfrec7.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfrec7.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define d
# | ...
# `---data was truncated (10240/51420) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005557fec44eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005557fec41e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005557fec4562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa730d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa730d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa730d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa730ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005557febdabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005557febdaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005557febbf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005557fe86ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005557fe86eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa730ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa730cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa730cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005557fe86ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c (2350 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dotu_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dotu_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dotu_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dotu_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dotu_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dotu_vv_u64m1(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dotu_vv_u64m2(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dotu_vv_u64m4(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i6
# | ...
# `---data was truncated (10240/25511) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005565ab9feeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005565ab9fbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005565ab9ff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd81df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd81df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd81df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd81df1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005565ab994bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005565ab994a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005565ab9798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005565ab628e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005565ab628b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd81df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd81df1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd81df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005565ab628a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmaxnmq.c (2351 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmaxnmq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.maxnum.v8f16(<8 x half> %0, <8 x half> %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.maxnum.v8f16(<8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %0, <4 x float> %1)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x half>, ptr %inactive.addr, align 8
# |   %6 = call <8 x half> @llvm.arm.mve.max.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> %5)
# |   ret <8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.max.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>, <8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x float>, ptr %inactive.addr, align 8
# |   %6 = call <4 x float> @llvm.arm.mve.max.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.max.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>, <4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x half> @llvm.arm.mve.max.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> undef)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmq_x_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x float> @llvm.arm.mve.max.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> undef)
# |   ret <4 x float> %5
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055df7ddfceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055df7ddf9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055df7ddfd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0c4d505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0c4d55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0c4d505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0c4d4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055df7dd92bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055df7dd92a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055df7dd778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055df7da26e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055df7da26b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0c4d4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0c4d4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0c4d4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055df7da26a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c (2352 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasub_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasub_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasub_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasub_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasub_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasub_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasub_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasub_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasub_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasub_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vas
# | ...
# `---data was truncated (10240/99585) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de60a0deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055de60a0ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055de60a0e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff46a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff46a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff46a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff46a431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de609a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055de609a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055de609888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055de60637e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055de60637b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff46a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff46a4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff46a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de60637a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c (2353 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b9acb7aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b9acb77e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b9acb7b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7a04d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7a04d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7a04d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7a04d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b9acb10bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b9acb10a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b9acaf58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b9ac7a4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b9ac7a4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7a04d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7a04d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7a04d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b9ac7a4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c (2354 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e2c328aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e2c3287e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e2c328b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7486e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7486ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7486e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7486e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e2c3220bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e2c3220a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e2c32058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e2c2eb4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e2c2eb4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7486e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7486e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7486e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2c2eb4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c (2355 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562f7abe6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562f7abe3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562f7abe762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f215aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f215aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f215aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f215aa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562f7ab7cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562f7ab7ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562f7ab618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562f7a810e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562f7a810b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f215aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f215aa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f215aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562f7a810a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c (2356 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmin_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor
# | ...
# `---data was truncated (10240/61929) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563986ceeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563986cebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563986cef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba2aa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba2aa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba2aa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba2aa03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563986c84bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563986c84a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563986c698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563986918e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563986918b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fba2aa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba2aa050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba2aa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563986918a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c (2357 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei16_v_f16mf4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei16_v_f16mf2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei16_v_f16m1(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei16_v_f16m2(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei16_v_f16m4(ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vluxei16_v_f16m8(ptr noundef %base, <vscale x 32 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> poison, ptr %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei16_v_f32mf2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei16_v_f32m1(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei16_v_f32m2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei16_v_f32m4(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i16.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i16.i64(<vscale x 
# | ...
# `---data was truncated (10240/118164) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056154e591eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056154e58ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056154e59262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b59333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b5938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b59333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b5931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056154e527bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056154e527a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056154e50c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056154e1bbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056154e1bbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5b5931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b5931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b5931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056154e1bba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/admin.c (2358 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/admin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c --check-prefixes=CHECK,CHECK-LE
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcreateq_f16(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   %4 = bitcast <2 x i64> %3 to <8 x half>
# |   ret <8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcreateq_f32(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   %4 = bitcast <2 x i64> %3 to <4 x float>
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcreateq_s16(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   %4 = bitcast <2 x i64> %3 to <8 x i16>
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcreateq_s32(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   %4 = bitcast <2 x i64> %3 to <4 x i32>
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vcreateq_s64(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   ret <2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcreateq_s8(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   %4 = bitcast <2 x i64> %3 to <16 x i8>
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcreateq_u16(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   %4 = bitcast <2 x i64> %3 to <8 x i16>
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcreateq_u32(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   %4 = bitcast <2 x i64> %3 to <4 x i32>
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vcreateq_u64(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   ret <2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcreateq_u8(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   %4 = bitcast <2 x i64> %3 to <16 x i8>
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vuninitializedq_polymorphic_f16(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <8 x half> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vuninitializedq_polymorphic_f32(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <4 x float> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vuninitializedq_polymorphic_s8(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <16 x i8> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vuninitializedq_polymorphic_s16(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <8 x i16> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vuninitializedq_polymorphic_s32(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <4 x i32> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vuninitializedq_polymorphic_s64(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <2 x i64> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vuninitializedq_polymorphic_u8(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <16 x i8> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vuninitializedq_polymorphic_u16(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <8 x i16> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vuninitializedq_polymorphic_u32(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <4 x i32> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vuninitializedq_polymorphic_u64(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <2 x i64> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vuninitializedq_f16() #0 {
# | entry:
# |   ret <8 x half> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vuninitializedq_f32() #0 {
# | entry:
# |   ret <4 x float> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vuninitializedq_s16() #0 {
# | entry:
# |   ret <8 x i16> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vuninitializedq_s32() #0 {
# | entry:
# |   ret <4 x i32> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vuninitializedq_s64() #0 {
# | entry:
# |   ret <2 x i64> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vuninitializedq_s8() #0 {
# | entry:
# |   ret <16 x i8> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vuninitializedq_u16() #0 {
# | entry:
# |   ret <8 x i16> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vuninitializedq_u32() #0 {
# | entry:
# |   ret <4 x i32> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vuninitializedq_u64() #0 {
# | entry:
# |   ret <2 x i64> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vuninitializedq_u8() #0 {
# | entry:
# |   ret <16 x i8> undef
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>'
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<>
# |  #0 0x0000558ec6f19eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558ec6f16e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558ec6f1a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f65a9249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f65a92a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f65a9249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f65a9231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558ec6eafbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558ec6eafa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558ec6e948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558ec6b43e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558ec6b43b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f65a9232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f65a92330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f65a92330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558ec6b43a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c --check-prefixes=CHECK,CHECK-LE
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c --check-prefixes=CHECK,CHECK-LE
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c (2359 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1down_vf_bf16mf4(<vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1down_vf_bf16mf2(<vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1down_vf_bf16m1(<vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfslide1down_vf_bf16m2(<vscale x 8 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfslide1down_vf_bf16m4(<vscale x 16 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfslide1down_vf_bf16m8(<vscale x 32 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1down_vf_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1down_vf_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1down_vf_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsli
# | ...
# `---data was truncated (10240/14908) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eafdaf1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eafdaeee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eafdaf262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f95c7449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f95c74a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f95c7449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f95c7431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eafda87bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eafda87a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eafda6c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eafd71be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eafd71bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f95c7432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f95c74330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f95c74330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eafd71ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c (2360 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f16m1x8(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f32m1x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f64m1x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a4b3ec5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a4b3ec2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a4b3ec662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f99c6705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f99c675c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f99c6705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f99c66ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a4b3e5bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a4b3e5ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a4b3e408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a4b3aefe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a4b3aefb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f99c66eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f99c66ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f99c66ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a4b3aefa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c (2361 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccsu_vv_i16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccsu_vx_i16mf4_tu(<vscale x 1 x i16> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccsu_vv_i16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccsu_vx_i16mf2_tu(<vscale x 2 x i16> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccsu_vv_i16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccsu_vx_i16m1_tu(<vscale x 4 x i16> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccsu_vv_i16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccsu_vx_i16m2_tu(<vscale x 8 x i16> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccsu_vv_i16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i6
# | ...
# `---data was truncated (10240/151253) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005643fe600eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005643fe5fde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005643fe60162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c16333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c1638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c16333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c1631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005643fe596bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005643fe596a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005643fe57b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005643fe22ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005643fe22ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8c1631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c1631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c1631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005643fe22aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c (2362 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredand_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredand_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredand_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 
# | ...
# `---data was truncated (10240/94379) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a4c8102eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a4c80ffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a4c810362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd2a21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd2a2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd2a21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd2a203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a4c8098bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a4c8098a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a4c807d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a4c7d2ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a4c7d2cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdd2a204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd2a2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd2a2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a4c7d2ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c (2363 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_i16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_i16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_i16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_u16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_u16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_u16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ta
# | ...
# `---data was truncated (10240/47488) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a541504eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a541501e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a54150562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f993ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f993caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f993ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f993ca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a54149abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a54149aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a54147f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a54112ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a54112eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f993ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f993ca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f993ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a54112ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c (2364 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_f64m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_i64m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_u64m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563a16d0deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563a16d0ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563a16d0e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f32a9449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f32a94a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f32a9449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f32a9431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a16ca3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563a16ca3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563a16c888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563a16937e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563a16937b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f32a9432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f32a94330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f32a94330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a16937a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c (2365 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsmul_vv_i64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsmul_vx_i64m1(<vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsmul_vv_i64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsmul_vx_i64m2(<vscale x 2 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsmul_vv_i64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 4 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsmul_vx_i64m4(<vscale x 4 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsmul_vv_i64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 8 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsmul_vx_i64m8(<vscale x 8 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsmul_vv_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsmul_vx_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/18873) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c58221eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563c5821ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563c5822262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa4f9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa4f9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa4f9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa4f9f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c581b7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563c581b7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563c5819c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563c57e4be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563c57e4bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa4f9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4f9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4f9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c57e4ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c (2366 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16mf4x6(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16mf2x6(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16m1x6(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005573085d3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005573085d0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005573085d462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fde17333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fde1738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fde17333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fde1731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557308569bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557308569a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055730854e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005573081fde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005573081fdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fde1731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fde1731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fde1731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005573081fda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c (2367 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4a_vv_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4a_vv_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# | 
# | ...
# `---data was truncated (10240/26460) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556b08df5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556b08df2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556b08df662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f72ad933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f72ad98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f72ad933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f72ad91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b08d8bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556b08d8ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556b08d708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556b08a1fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556b08a1fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f72ad91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f72ad91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f72ad91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b08a1fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c (2368 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsub_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsub_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsub_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsub_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsub_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsub_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsub_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsub_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <
# | ...
# `---data was truncated (10240/34430) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056171ce4beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056171ce48e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056171ce4c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd241905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd24195c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd241905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd2418ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056171cde1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056171cde1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056171cdc68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056171ca75e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056171ca75b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd2418eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd2418ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd2418ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056171ca75a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c (2369 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   st
# | ...
# `---data was truncated (10240/11797) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565096d57eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565096d54e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000565096d5862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f48aa533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f48aa58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f48aa533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f48aa51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565096cedbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565096ceda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000565096cd28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565096981e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565096981b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f48aa51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f48aa51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f48aa51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565096981a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c (2370 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4asu_vv_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4asu_vv_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load
# | ...
# `---data was truncated (10240/14493) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005594428e7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005594428e4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005594428e862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6df2049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6df20a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6df2049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6df2031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055944287dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055944287da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005594428628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559442511e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559442511b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6df2032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6df20330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6df20330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559442511a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c (2371 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclip_wv_i8mf8(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclip_wx_i8mf8(<vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclip_wv_i8mf4(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclip_wx_i8mf4(<vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclip_wv_i8mf2(<vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclip_wx_i8mf2(<vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclip_wv_i8m1(<vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclip_wx_i8m1(<vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclip_wv_i8m2(<vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclip_wx_i8m2(<vscale x 16 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 %1, i64 0, i64 %2)
# | ...
# `---data was truncated (10240/69831) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e72da49eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e72da46e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e72da4a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff5ee333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff5ee38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff5ee333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff5ee31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e72d9dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e72d9dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e72d9c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e72d673e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e72d673b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff5ee31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff5ee31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff5ee31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e72d673a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c (2372 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadc_vvm_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadc_vxm_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadc_vvm_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadc_vxm_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadc_vvm_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadc_vxm_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadc_vvm_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadc_vxm_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, <vscale x 8 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vadc_vvm_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, a
# | ...
# `---data was truncated (10240/98149) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005621ba8d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005621ba8d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005621ba8d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5e1c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5e1c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5e1c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5e1c31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005621ba86ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005621ba86ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005621ba8538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005621ba502e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005621ba502b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5e1c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5e1c31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5e1c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005621ba502a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c (2373 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vpairo_vv_f16mf4(<vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vpairo.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vpairo.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vpairo_vv_f16mf2(<vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vpairo.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vpairo.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vpairo_vv_f16m1(<vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vpairo.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vpairo.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vpairo_vv_f16m2(<vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vpairo.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vpairo.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vpairo_vv_f16m4(<vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vpairo.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vpairo.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vpairo_vv_f16m8(<vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vpairo.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vpairo.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vpairo_vv_f32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vpairo.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vpairo.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vpairo_vv_f32m1(<vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vpairo.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vpairo.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vpairo_vv_f32m2(<vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vpairo.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vpairo.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vpairo_vv_f32m4(<vscale x 8 x float> %vs2, <vscale x 8 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load <v
# | ...
# `---data was truncated (10240/125480) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb4681aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fb46817e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fb4681b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb1b561bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb1b56725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb1b561ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb1b5603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb467b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fb467b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fb467958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fb46444e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fb46444b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb1b5604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb1b56050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb1b56050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb46444a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c (2374 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpairo_vv_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vpairo.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpairo.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpairo_vv_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vpairo.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpairo.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpairo_vv_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vpairo.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vpairo.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vpairo_vv_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vpairo.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vpairo.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vpairo_vv_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vpairo.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vpairo.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vpairo_vv_bf16m8(<vscale x 32 x bfloat> %vs2, <vscale x 32 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vpairo.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vpairo.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpairo_vv_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vpairo.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpairo.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpairo_vv_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vpairo.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpairo.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpairo_vv_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.add
# | ...
# `---data was truncated (10240/15312) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d5be31feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d5be31ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d5be32062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5c64d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5c64d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5c64d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5c64d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d5be2b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d5be2b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d5be29a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d5bdf49e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d5bdf49b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5c64d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5c64d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5c64d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d5bdf49a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c (2375 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vremu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vremu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vremu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vremu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vremu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vremu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vremu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vremu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vremu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vremu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vremu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vremu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vremu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vremu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vremu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/97913) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ff7951deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ff7951ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ff7951e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9cbc533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9cbc58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9cbc533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9cbc51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ff794b3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ff794b3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ff794988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ff79147e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ff79147b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9cbc51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9cbc51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9cbc51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ff79147a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-neon-dot-product.c (2376 of 27911)
******************** TEST 'Clang :: CodeGen/arm-neon-dot-product.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-linux-gnueabihf -target-cpu cortex-a75 -target-feature +dotprod  -disable-O0-optnone  -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-linux-gnueabihf -target-cpu cortex-a75 -target-feature +dotprod -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8-unknown-linux-gnueabihf"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vdot_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <8 x i8> %3 to <2 x i32>
# |   %vdot1.i = call <2 x i32> @llvm.arm.neon.udot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %4, <8 x i8> %5)
# |   store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vdotq_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 8
# |   %__p1.addr.i = alloca <16 x i8>, align 8
# |   %__p2.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vdot1.i = call <4 x i32> @llvm.arm.neon.udot.v4i32.v16i8(<4 x i32> %vdot.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vdot1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vdot_s32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <8 x i8> %3 to <2 x i32>
# |   %vdot1.i = call <2 x i32> @llvm.arm.neon.sdot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %4, <8 x i8> %5)
# |   store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vdotq_s32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 8
# |   %__p1.addr.i = alloca <16 x i8>, align 8
# |   %__p2.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vdot1.i = call <4 x i32> @llvm.arm.neon.sdot.v4i32.v16i8(<4 x i32> %vdot.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vdot1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vdot_lane_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   %__ret_831 = alloca <2 x i32>, align 8
# |   %__s0_831 = alloca <2 x i32>, align 8
# |   %__s1_831 = alloca <8 x i8>, align 8
# |   %__s2_831 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <2 x i32>, align 8
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp1 = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   %tmp2 = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0_831, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1_831, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <8 x i8> %2, ptr %__s2_831, align 8
# |   %3 = load <2 x i32>, ptr %__s0_831, align 8
# |   %4 = load <8 x i8>, ptr %__s1_831, align 8
# |   %5 = load <2 x i32>, ptr %__s2_831, align 8
# |   store <2 x i32> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x i32>
# |   %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> <i32 1, i32 1>
# |   store <2 x i32> %lane, ptr %ref.tmp1, align 8
# |   %8 = load <2 x i32>, ptr %ref.tmp1, align 8
# |   store <2 x i32> %8, ptr %__ret, align 8
# |   %9 = load <2 x i32>, ptr %__ret, align 8
# |   store <2 x i32> %9, ptr %tmp, align 8
# |   %10 = load <2 x i32>, ptr %tmp, align 8
# |   store <2 x i32> %10, ptr %ref.tmp, align 8
# |   %11 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <2 x i32> %3, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %4, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %11, ptr %__p2.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %14 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <8 x i8> %12 to <2 x i32>
# |   %vdot1.i = call <2 x i32> @llvm.arm.neon.udot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %13, <8 x i8> %14)
# |   store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8
# |   %15 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %15, ptr %__ret.i, align 8
# |   %16 = load <2 x i32>, ptr %__ret.i, align 8
# |   store <2 x i32> %16, ptr %__ret_831, align 8
# |   %17 = load <2 x i32>, ptr %__ret_831, align 8
# |   store <2 x i32> %17, ptr %tmp2, align 8
# |   %18 = load <2 x i32>, ptr %tmp2, align 8
# |   ret <2 x i32> %18
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vdotq_lane_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 8
# |   %__p1.addr.i = alloca <16 x i8>, align 8
# |   %__p2.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   %__ret_827 = alloca <4 x i32>, align 8
# |   %__s0_827 = alloca <4 x i32>, align 8
# |   %__s1_827 = alloca <16 x i8>, align 8
# |   %__s2_827 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <4 x i32>, align 8
# |   %__ret = alloca <4 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp1 = alloca <16 x i8>, align 8
# |   %tmp = alloca <4 x i32>, align 8
# |   %tmp2 = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   store <4 x i32> %0, ptr %__s0_827, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   store <16 x i8> %1, ptr %__s1_827, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <8 x i8> %2, ptr %__s2_827, align 8
# |   %3 = load <4 x i32>, ptr %__s0_827, align 8
# |   %4 = load <16 x i8>, ptr %__s1_827, align 8
# |   %5 = load <2 x i32>, ptr %__s2_827, align 8
# |   store <2 x i32> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x i32>
# |   %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <4 x i32> <i32 1, i32 1,
# | ...
# `---data was truncated (10240/18322) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine
# |  #0 0x000055a8d31e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a8d31e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a8d31e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb845e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb845ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb845e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb845e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a8d317abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a8d317aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a8d315f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a8d2e0ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a8d2e0eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb845e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb845e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb845e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a8d2e0ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c (2377 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vlse8_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vlse8_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vlse8_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vlse8_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vlse8_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.p0.i64(<vscale x 16 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vlse8_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8.p0.i64(<vscale x 32 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vlse8_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8.p0.i64(<vscale x 64 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vlse8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vlse8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vlse8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, ali
# | ...
# `---data was truncated (10240/63510) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005643406d3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005643406d0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005643406d462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fad3e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fad3e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fad3e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fad3e431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564340669bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564340669a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056434064e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005643402fde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005643402fdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fad3e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fad3e4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fad3e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005643402fda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c (2378 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f16m1x6(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f32m1x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f64m1x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei16_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556480e8aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556480e87e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556480e8b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb53c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb53c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb53c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb53c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556480e20bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556480e20a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556480e058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556480ab4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556480ab4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb53c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb53c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb53c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556480ab4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c (2379 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4k_vi_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4k_vi_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4k_vi_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4k_vi_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm4k_vi_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560fd2398eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560fd2395e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560fd239962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6dd4249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6dd42a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6dd4249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6dd4231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560fd232ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560fd232ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560fd23138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560fd1fc2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560fd1fc2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6dd4232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6dd42330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6dd42330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560fd1fc2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c (2380 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_i8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_i8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8_v_i8m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_u8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_u8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_u8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8_v_u8m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_i8mf8x8_tum(<vscale x 1 x i1> %mas
# | ...
# `---data was truncated (10240/43111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005612bad59eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005612bad56e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005612bad5a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f999cf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f999cf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f999cf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f999ceed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005612bacefbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005612bacefa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005612bacd48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005612ba983e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005612ba983b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f999ceeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f999ceef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f999ceef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005612ba983a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c (2381 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsif_m_b1_mu(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %maskedoff, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %2, <vscale x 64 x i1> %0, i64 %3)
# |   ret <vscale x 64 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsif_m_b2_mu(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %maskedoff, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %2, <vscale x 32 x i1> %0, i64 %3)
# |   ret <vscale x 32 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsif_m_b4_mu(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %maskedoff, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %2, <vscale x 16 x i1> %0, i64 %3)
# |   ret <vscale x 16 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsif_m_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %2, <vscale x 8 x i1> %0, i64 %3)
# |   ret <vscale x 8 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsif_m_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %2, <vscale x 4 x i1> %0, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsif_m_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %2, <vscale x 2 x i1> %0, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsif_m_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1.i64(<vscale x 1 x i1> %1, <vscale x 1 x i1> %2, <vscale x 1 x i1> %0, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005641fecaaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005641feca7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005641fecab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe652333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe65238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe652333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe65231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005641fec40bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005641fec40a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005641fec258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005641fe8d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005641fe8d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe65231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe65231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe65231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005641fe8d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c (2382 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssub_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssub_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssub_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssub_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssub_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssub_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssub_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssub_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssub_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssub_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vssub_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/97913) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055568f131eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055568f12ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055568f13262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbe0a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbe0a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbe0a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbe0a31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055568f0c7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055568f0c7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055568f0ac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055568ed5be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055568ed5bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbe0a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbe0a31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbe0a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055568ed5ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c (2383 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vunzipo_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 2 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vunzipo_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 4 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vunzipo_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 8 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vunzipo_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 16 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vunzipo_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 32 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056505ec2feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056505ec2ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056505ec3062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8736733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f873678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8736733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f873671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056505ebc5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056505ebc5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056505ebaa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056505e859e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056505e859b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f873671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f873671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f873671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056505e859a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c (2384 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f16m1x7(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f32m1x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f64m1x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/69980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005555f2b95eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005555f2b92e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005555f2b9662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e25933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e2598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e25933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e2591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005555f2b2bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005555f2b2ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005555f2b108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005555f27bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005555f27bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1e2591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e2591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e2591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005555f27bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c (2385 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vget_v_i8m2_i8m1(<vscale x 16 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> %0, i64 0)
# |   ret <vscale x 8 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vget_v_i8m4_i8m1(<vscale x 32 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> %0, i64 0)
# |   ret <vscale x 8 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vget_v_i8m8_i8m1(<vscale x 64 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv64i8(<vscale x 64 x i8> %0, i64 0)
# |   ret <vscale x 8 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv64i8(<vscale x 64 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vget_v_i8m4_i8m2(<vscale x 32 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> %0, i64 0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vget_v_i8m8_i8m2(<vscale x 64 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8> %0, i64 0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vget_v_i8m8_i8m4(<vscale x 64 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 32 x i8> @llvm.vector.extract.nxv32i8.nxv64i8(<vscale x 64 x i8> %0, i64 0)
# |   ret <vscale x 32 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.vector.extract.nxv32i8.nxv64i8(<vscale x 64 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vget_v_u8m2_u8m1(<vscale x 16 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> %0, i64 0)
# |   ret <vscale x 8 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vget_v_u8m4_u8m1(<vscale x 32 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> %0, i64 0)
# |   ret <vscale x 8 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vget_v_u8m8_u8m1(<vscale x 64 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv64i8(<vscale x 64 x i8> %0, i64 0)
# |   ret <vscale x 8 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vget_v_u8m4_u8m2(<vscale x 32 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> %0, i64 0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vget_v_u8m8_u8m2(<vscale x 64 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8> %0, i64 0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vget_v_u8m8_u8m4(<vscale x 64 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 32 x i8> @llvm.vector.extract.nxv32i8.nxv64i8(<vscale x 64 x i8> %0, i64 0)
# |   ret <vscale x 32 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vget_v_i16m2_i16m1(<vscale x 8 x i16> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv8i16(<vscale x 8 x i16> %0, i64 0)
# |   ret <vscale x 4 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv8i16(<vscale x 8 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vget_v_i16m4_i16m1(<vscale x 16 x i16> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv16i16(<vscale x 16 x i16> %0, i64 0)
# |   ret <vscale x 4 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv16i16(<vscale x 16 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vget_v_i16m8_i16m1(<vscale x 32 x i16> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv32i16(<vscale x 32 x i16> %0, i64 0)
# |   ret <vscale x 4 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv32i16(<vscale x 32 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale
# | ...
# `---data was truncated (10240/40902) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec242c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ec242bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ec242c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007facd7333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007facd738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007facd7333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007facd731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec24257bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ec24257a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ec2423c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ec23eebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ec23eebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007facd731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007facd731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007facd731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec23eeba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c (2386 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvtbf16_f_f_w_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvtbf16_f_f_w_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvtbf16_f_f_w_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvtbf16_f_f_w_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvtbf16_f_f_w_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |  
# | ...
# `---data was truncated (10240/43478) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055697be6eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055697be6be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055697be6f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb78ee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb78eea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb78ee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb78ee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055697be04bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055697be04a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055697bde98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055697ba98e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055697ba98b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb78ee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb78ee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb78ee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055697ba98a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c (2387 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_f16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_f16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_f16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_i16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_i16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_i16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_u16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_u16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_u16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale 
# | ...
# `---data was truncated (10240/23357) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005624392d9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005624392d6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005624392da62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc7b8b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc7b8b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc7b8b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc7b8b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056243926fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056243926fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005624392548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562438f03e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562438f03b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc7b8b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc7b8b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc7b8b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562438f03a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c (2388 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f16m1x8(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f32m1x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f64m1x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei16_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055654b1dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055654b1dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055654b1e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f13ac733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13ac78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f13ac733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f13ac71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055654b175bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055654b175a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055654b15a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055654ae09e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055654ae09b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f13ac71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13ac71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13ac71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055654ae09a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/zksh.c (2389 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/zksh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zksh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c  -check-prefix=RV32ZKSH
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zksh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sm3p0(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sm3p0(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sm3p1(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sm3p1(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sm3p0(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sm3p1(i32) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zksh" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zksh1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005646e39f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005646e39eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005646e39f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e6e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e6e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e6e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e6e631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005646e3987bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005646e3987a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005646e396c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005646e361be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005646e361bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0e6e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e6e6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e6e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005646e361ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c -check-prefix=RV32ZKSH
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c -check-prefix=RV32ZKSH
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c (2390 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmerge_vfm_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmerge_vfm_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmerge_vfm_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmerge_vfm_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmerge_vfm_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, bfloat noundef %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, <vscale x 16 x i1> %3, i64 %4)
# |   ret <vscale x 16 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfmerge_vfm_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, bfloat noundef %op2, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, <vscale x 32 x i1> %3, i64 %4)
# |   ret <vscale x 32 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, <vscale x 32 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005591eed07eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005591eed04e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005591eed0862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4934649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f49346a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4934649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4934631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005591eec9dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005591eec9da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005591eec828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005591ee931e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005591ee931b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4934632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f49346330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f49346330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005591ee931a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c (2391 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f16m1x8(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f32m1x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f64m1x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i16> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559e82d4feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559e82d4ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559e82d5062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f94fd049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f94fd0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f94fd049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f94fd031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e82ce5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559e82ce5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559e82cca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559e82979e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559e82979b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f94fd032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f94fd0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f94fd0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e82979a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c (2392 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_e5m2_e4m3_w4_f8e5m2m8_f8e4m3m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005614aa96ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005614aa969e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005614aa96d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8325933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f832598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8325933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f832591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005614aa902bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005614aa902a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005614aa8e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005614aa596e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005614aa596b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f832591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f832591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f832591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005614aa596a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c (2393 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmin_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretu
# | ...
# `---data was truncated (10240/61937) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ca8d264eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ca8d261e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ca8d26562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f67ee649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f67ee6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f67ee649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f67ee631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ca8d1fabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ca8d1faa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ca8d1df8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ca8ce8ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ca8ce8eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f67ee632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67ee6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67ee6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ca8ce8ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c (2394 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfabs_v_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfabs_v_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfabs_v_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1_tum(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store
# | ...
# `---data was truncated (10240/29296) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fc15091eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fc1508ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fc1509262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1838905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f183895c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1838905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f18388ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fc15027bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fc15027a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fc1500c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fc14cbbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fc14cbbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f18388eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f18388ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f18388ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fc14cbba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/predicates.c (2395 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/predicates.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp16q(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %0)
# |   %2 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %1)
# |   %3 = trunc i32 %2 to i16
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.vctp16(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp16q_m(i32 noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load i32, ptr %a.addr, align 4
# |   %4 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %3)
# |   %5 = and <8 x i1> %2, %4
# |   %6 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %5)
# |   %7 = trunc i32 %6 to i16
# |   ret i16 %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp32q(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %0)
# |   %2 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %1)
# |   %3 = trunc i32 %2 to i16
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.vctp32(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp32q_m(i32 noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load i32, ptr %a.addr, align 4
# |   %4 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %3)
# |   %5 = and <4 x i1> %2, %4
# |   %6 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %5)
# |   %7 = trunc i32 %6 to i16
# |   ret i16 %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp64q(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call <2 x i1> @llvm.arm.mve.vctp64(i32 %0)
# |   %2 = call i32 @llvm.arm.mve.pred.v2i.v2i1(<2 x i1> %1)
# |   %3 = trunc i32 %2 to i16
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i1> @llvm.arm.mve.vctp64(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.pred.v2i.v2i1(<2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp64q_m(i32 noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %1)
# |   %3 = load i32, ptr %a.addr, align 4
# |   %4 = call <2 x i1> @llvm.arm.mve.vctp64(i32 %3)
# |   %5 = and <2 x i1> %2, %4
# |   %6 = call i32 @llvm.arm.mve.pred.v2i.v2i1(<2 x i1> %5)
# |   %7 = trunc i32 %6 to i16
# |   ret i16 %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp8q(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %0)
# |   %2 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %1)
# |   %3 = trunc i32 %2 to i16
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.vctp8(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp8q_m(i32 noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)
# |   %3 = load i32, ptr %a.addr, align 4
# |   %4 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %3)
# |   %5 = and <16 x i1> %2, %4
# |   %6 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %5)
# |   %7 = trunc i32 %6 to i16
# |   ret i16 %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vpnot(i16 noundef zeroext %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   %1 = xor i16 %0, -1
# |   ret i16 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vpselq_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load <8 x half>, ptr %a.addr, align 8
# |   %4 = load <8 x half>, ptr %b.addr, align 8
# |   %5 = select <8 x i1> %2, <8 x half> %3, <8 x half> %4
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vpselq_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load <4 x float>, ptr %a.addr, align 8
# |   %4 = load <4 x float>, ptr %b.addr, align 8
# |   %5 = select <4 x i1> %2, <4 x float> %3, <4 x float> %4
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vpselq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load <8 x i16>, ptr %a.addr, align 8
# |   %4 = load <8 x i16>, ptr %b.addr, align 8
# |   %5 = select <8 x i1> %2, <8 x i16> %3, <8 x i16> %4
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vpselq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load <4 x i32>, ptr %a.addr, align 8
# |   %4 = load <4 x i32>, ptr %b.addr, align 8
# |   %5 = select <4 x i1> %2, <4 x i32> %3, <4 x i32> %4
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vpselq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   %b.addr = alloca <2 x i64>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load <2 x i64>, ptr %a.addr, align 8
# |   %4 = bitcast <2 x i64> %3 to <4 x i32>
# |   %5 = load <2 x i64>, ptr %b.addr, align 8
# |   %6 = bitcast <2 x i64> %5 to <4 x i32>
# |   %7 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %6
# |   %8 = bitcast <4 x i32> %7 to <2 x i64>
# |   ret <2 x i64> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vpselq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, ali
# | ...
# `---data was truncated (10240/13928) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>'
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<>
# |  #0 0x0000559a64013eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559a64010e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559a6401462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e05105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e0515c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e05105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e050ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a63fa9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559a63fa9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559a63f8e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559a63c3de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559a63c3db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0e050eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e050ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e050ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a63c3da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c (2396 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vcpop_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vcpop_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vcpopv.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vcpopv.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vcpop_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vcpopv.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vcpopv.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vcpop_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vcpopv.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vcpopv.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vcpop_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vcpopv.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vcpopv.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vcpop_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vcpopv.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vcpopv.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vcpop_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vcpopv.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vcpopv.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vcpop_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vcpopv.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vcpopv.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vcpop_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vcpopv.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vcpopv.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vcpop_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vcpopv.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vcpopv.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vcpop_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vcpopv.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vcpopv.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vcpop_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vcpopv.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vcpopv.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vcpop_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vcpopv.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | 
# | ...
# `---data was truncated (10240/40891) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055978fff4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055978fff1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055978fff562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbc30333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbc3038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbc30333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbc3031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055978ff8abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055978ff8aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055978ff6f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055978fc1ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055978fc1eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbc3031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbc3031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbc3031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055978fc1ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c (2397 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei8_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei8_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei8_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei8_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei8_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vloxei8_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> poison, ptr %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei8_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei8_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei8_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei8_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vs
# | ...
# `---data was truncated (10240/14201) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005556af09eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005556af09be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005556af09f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff8fdf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff8fdf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff8fdf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff8fdf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005556af034bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005556af034a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005556af0198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005556aecc8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005556aecc8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff8fdf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff8fdf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff8fdf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005556aecc8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c (2398 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwi
# | ...
# `---data was truncated (10240/44369) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557f14af9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557f14af6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557f14afa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbbbca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbbbcaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbbbca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbbbca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f14a8fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557f14a8fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557f14a748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557f14723e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557f14723b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbbbca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbbbca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbbbca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f14723a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c (2399 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_bf16mf4_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1bf16.i64(<vscale x 1 x i16> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1bf16.i64(<vscale x 1 x i16>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_bf16mf2_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2bf16.i64(<vscale x 2 x i16> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2bf16.i64(<vscale x 2 x i16>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_bf16m1_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4bf16.i64(<vscale x 4 x i16> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4bf16.i64(<vscale x 4 x i16>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_bf16m2_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8bf16.i64(<vscale x 8 x i16> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8bf16.i64(<vscale x 8 x i16>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_bf16m4_u16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16bf16.i64(<vscale x 16 x i16> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16bf16.i64(<vscale x 16 x i16>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfclass_v_bf16m8_u16m8_tu(<vscale x 32 x i16> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32bf16.i64(<vscale x 32 x i16> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32bf16.i64(<vscale x 32 x i16>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_bf16mf4_u16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i16> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1bf16.i64(<vscale x 1 x i16> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1bf16.i64(<vscale x 1 x i16>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_bf16mf2_u16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i16> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2bf16.i64(<vscale x 2 x i16> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2bf16.i64(<vscale x 2 x i16>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_bf16m1_u16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i16> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4bf16.i64(<vscale x 4 x i16> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4bf16.i64(<vscale x 4 x i16>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_bf16m2_u16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x i16> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #
# | ...
# `---data was truncated (10240/26584) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005566677c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005566677bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005566677c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f298a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f298a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f298a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f298a631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556667758bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556667758a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055666773d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005566673ece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005566673ecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f298a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f298a6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f298a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005566673eca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c (2400 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fba9f32eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fba9f2fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fba9f3362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f828f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f828f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f828f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f828f631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fba9ec8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fba9ec8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fba9ead8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fba9b5ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fba9b5cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f828f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f828f6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f828f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fba9b5ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c (2401 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16ff_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(<vscale x 1 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(<vscale x 1 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16ff_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(<vscale x 2 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(<vscale x 2 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16ff_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(<vscale x 4 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(<vscale x 4 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16ff_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(<vscale x 8 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(<vscale x 8 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16ff_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(<vscale x 16 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 16 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 16 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(<vscale x 16 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16ff_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(<vscale x 32 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 32 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 32 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(<vscale x 32 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16ff_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   %6 = extractvalue { <vscale x 1 x bfloat>, i64 } %5, 0
# |   %7 = extractvalue { <vscale x 1 x bfloat>, i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret <vscale x 1 x bfloat> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16ff_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(<vs
# | ...
# `---data was truncated (10240/32206) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558ea933eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558ea933be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558ea933f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f62bd905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f62bd95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f62bd905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f62bd8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558ea92d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558ea92d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558ea92b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558ea8f68e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558ea8f68b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f62bd8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f62bd8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f62bd8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558ea8f68a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c (2402 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_x_f_w_i8mf8(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_x_f_w_i8mf4(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_x_f_w_i8mf2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_x_f_w_i8m1(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_x_f_w_i8m2(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_x_f_w_i8m4(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_xu_f_w_u8mf8(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_xu_f_w_u8mf4(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_xu_f_w_u8mf2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_xu_f_w_u8m1(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_xu_f_w_u8m2(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_xu_f_w_u8m4(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x
# | ...
# `---data was truncated (10240/58661) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b03f2c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b03f2c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b03f2c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7cf9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7cf9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7cf9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7cf9f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b03f25abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b03f25aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b03f23f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b03eeeee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b03eeeeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7cf9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7cf9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7cf9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b03eeeea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c (2403 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsqrt7_v_bf16mf4(<vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsqrt7_v_bf16mf2(<vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsqrt7_v_bf16m1(<vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsqrt7_v_bf16m2(<vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsqrt7_v_bf16m4(<vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrsqrt7_v_bf16m8(<vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsqrt7_v_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsqrt7_v_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsqrt7_v_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsqrt7_v_bf16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsqrt7_v_bf16m4_m(<vscale x 16 x i1> %mask, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16
# | ...
# `---data was truncated (10240/12536) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555dcec4ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555dcec49e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555dcec4d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe65ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe65ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe65ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe65ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555dcebe2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555dcebe2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555dcebc78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555dce876e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555dce876b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe65ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe65ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe65ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555dce876a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c (2404 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64V /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local signext i32 @test() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvli.i64(i64 1, i64 0, i64 0)
# |   %conv = trunc i64 %0 to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e1a7396eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e1a7393e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e1a739762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbcb4849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbcb48a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbcb4849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbcb4831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e1a732cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e1a732ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e1a73118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e1a6fc0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e1a6fc0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbcb4832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbcb48330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbcb48330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e1a6fc0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64V /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64V /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/cx-complex-range.c (2405 of 27911)
******************** TEST 'Clang :: CodeGen/cx-complex-range.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c -O0 -disable-O0-optnone -emit-llvm -triple x86_64-unknown-unknown  -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c --check-prefix=FULL
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c -O0 -disable-O0-optnone -emit-llvm -triple x86_64-unknown-unknown -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-unknown"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @divf(<2 x float> noundef %a.coerce, <2 x float> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca { float, float }, align 4
# |   %a = alloca { float, float }, align 4
# |   %b = alloca { float, float }, align 4
# |   %coerce = alloca { float, float }, align 4
# |   store <2 x float> %a.coerce, ptr %a, align 4
# |   store <2 x float> %b.coerce, ptr %b, align 4
# |   %a.realp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 0
# |   %a.real = load float, ptr %a.realp, align 4
# |   %a.imagp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 1
# |   %a.imag = load float, ptr %a.imagp, align 4
# |   %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0
# |   %b.real = load float, ptr %b.realp, align 4
# |   %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1
# |   %b.imag = load float, ptr %b.imagp, align 4
# |   %call = call <2 x float> @__divsc3(float noundef %a.real, float noundef %a.imag, float noundef %b.real, float noundef %b.imag) #2
# |   store <2 x float> %call, ptr %coerce, align 4
# |   %coerce.realp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 0
# |   %coerce.real = load float, ptr %coerce.realp, align 4
# |   %coerce.imagp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 1
# |   %coerce.imag = load float, ptr %coerce.imagp, align 4
# |   %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0
# |   %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1
# |   store float %coerce.real, ptr %retval.realp, align 4
# |   store float %coerce.imag, ptr %retval.imagp, align 4
# |   %0 = load <2 x float>, ptr %retval, align 4
# |   ret <2 x float> %0
# | }
# | 
# | declare <2 x float> @__divsc3(float, float, float, float)
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @divassignf(ptr noundef %a, <2 x float> noundef %b.coerce) #0 {
# | entry:
# |   %b = alloca { float, float }, align 4
# |   %a.addr = alloca ptr, align 8
# |   %coerce = alloca { float, float }, align 4
# |   store <2 x float> %b.coerce, ptr %b, align 4
# |   store ptr %a, ptr %a.addr, align 8
# |   %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0
# |   %b.real = load float, ptr %b.realp, align 4
# |   %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1
# |   %b.imag = load float, ptr %b.imagp, align 4
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %.realp = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 0
# |   %.real = load float, ptr %.realp, align 4
# |   %.imagp = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 1
# |   %.imag = load float, ptr %.imagp, align 4
# |   %call = call <2 x float> @__divsc3(float noundef %.real, float noundef %.imag, float noundef %b.real, float noundef %b.imag) #2
# |   store <2 x float> %call, ptr %coerce, align 4
# |   %coerce.realp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 0
# |   %coerce.real = load float, ptr %coerce.realp, align 4
# |   %coerce.imagp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 1
# |   %coerce.imag = load float, ptr %coerce.imagp, align 4
# |   %.realp1 = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 0
# |   %.imagp2 = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 1
# |   store float %coerce.real, ptr %.realp1, align 4
# |   store float %coerce.imag, ptr %.imagp2, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @mulf(<2 x float> noundef %a.coerce, <2 x float> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca { float, float }, align 4
# |   %a = alloca { float, float }, align 4
# |   %b = alloca { float, float }, align 4
# |   %coerce = alloca { float, float }, align 4
# |   store <2 x float> %a.coerce, ptr %a, align 4
# |   store <2 x float> %b.coerce, ptr %b, align 4
# |   %a.realp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 0
# |   %a.real = load float, ptr %a.realp, align 4
# |   %a.imagp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 1
# |   %a.imag = load float, ptr %a.imagp, align 4
# |   %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0
# |   %b.real = load float, ptr %b.realp, align 4
# |   %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1
# |   %b.imag = load float, ptr %b.imagp, align 4
# |   %mul_ac = fmul float %a.real, %b.real
# |   %mul_bd = fmul float %a.imag, %b.imag
# |   %mul_ad = fmul float %a.real, %b.imag
# |   %mul_bc = fmul float %a.imag, %b.real
# |   %mul_r = fsub float %mul_ac, %mul_bd
# |   %mul_i = fadd float %mul_ad, %mul_bc
# |   %isnan_cmp = fcmp uno float %mul_r, %mul_r
# |   br i1 %isnan_cmp, label %complex_mul_imag_nan, label %complex_mul_cont, !prof !2
# | 
# | complex_mul_imag_nan:                             ; preds = %entry
# |   %isnan_cmp1 = fcmp uno float %mul_i, %mul_i
# |   br i1 %isnan_cmp1, label %complex_mul_libcall, label %complex_mul_cont, !prof !2
# | 
# | complex_mul_libcall:                              ; preds = %complex_mul_imag_nan
# |   %call = call <2 x float> @__mulsc3(float noundef %a.real, float noundef %a.imag, float noundef %b.real, float noundef %b.imag) #2
# |   store <2 x float> %call, ptr %coerce, align 4
# |   %coerce.realp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 0
# |   %coerce.real = load float, ptr %coerce.realp, align 4
# |   %coerce.imagp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 1
# |   %coerce.imag = load float, ptr %coerce.imagp, align 4
# |   br label %complex_mul_cont
# | 
# | complex_mul_cont:                                 ; preds = %complex_mul_libcall, %complex_mul_imag_nan, %entry
# |   %real_mul_phi = phi float [ %mul_r, %entry ], [ %mul_r, %complex_mul_imag_nan ], [ %coerce.real, %complex_mul_libcall ]
# |   %imag_mul_phi = phi float [ %mul_i, %entry ], [ %mul_i, %complex_mul_imag_nan ], [ %coerce.imag, %complex_mul_libcall ]
# |   %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0
# |   %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1
# |   store float %real_mul_phi, ptr %retval.realp, align 4
# |   store float %imag_mul_phi, ptr %retval.imagp, align 4
# |   %0 = load <2 x float>, ptr %retval, align 4
# |   ret <2 x float> %0
# | }
# | 
# | declare <2 x float> @__mulsc3(float, float, float, float)
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @mulassignf(ptr noundef %a, <2 x float> noundef %b.coerce) #0 {
# | entry:
# |   %b = alloca { float, float }, align 4
# |   %a.addr = alloca ptr, align 8
# |   %coerce = alloca { float, float }, align 4
# |   store <2 x float> %b.coerce, ptr %b, align 4
# |   store ptr %a, ptr %a.addr, align 8
# |   %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0
# |   %b.real = load float, ptr %b.realp, align 4
# |   %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1
# |   %b.imag = load float, ptr %b.imagp, align 4
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %.realp = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 0
# |   %.real = load float, ptr %.realp, align 4
# |   %.imagp = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 1
# |   %.imag = load float, ptr %.imagp, align 4
# |   %mul_ac = fmul float %.real, %b.real
# |   %mul_bd = fmul float %.imag, %b.imag
# |   %mul_ad = fmul float %.real, %b.imag
# |   %mul_bc = fmul float %.imag, %b.real
# |   %mul_r = fsub float %mul_ac, %mul_bd
# |   %mul_i = fadd float %mul_ad, %mul_bc
# |   %isnan_cmp = fcmp uno float %mul_r, %mul_r
# |   br i1 %isnan_cmp, label %complex_mul_imag_nan, label %complex_mul_cont, !prof !2
# | 
# | complex_mul_imag_nan:                             ; preds = %entry
# |   %isnan_cmp1 = fcmp uno float %mul_i, %mul_i
# |   br i1 %isnan_cmp1, label %complex_mul_libcall, label %complex_mul_cont, !prof !2
# | 
# | complex_mul_libcall:                              ; preds = %complex_mul_imag_nan
# |   %call = call <2 x float> @__mulsc3(float noundef %.real, float noundef %.imag, float noundef %b.real, float noundef %b.imag) #2
# |   store <2 x float> %call, ptr %coerce, align 4
# |   %coerce.realp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 0
# |   %coerce.real = load float, ptr %coerce.realp, align 4
# |   %coerce.imagp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 1
# |   %coerce.imag = load float, ptr %coerce.imagp, align 4
# |   br label %complex_mul_cont
# | 
# | complex_mul_cont:                                 ; preds = %complex_mul_libcall, %complex_mul_imag_nan, %entry
# |   %real_mul_phi = phi float [ %mul_r, %entry ], [ %mul_r, %complex_mul_imag_nan ], [ %coerce.real, %complex_mul_libcall ]
# |   %imag_mul_phi = phi float [ %mul_i, %entry ], [ %mul_i, %complex_mul_imag_nan ], [ %coerce.imag, %complex_mul_libcall ]
# |   %.realp2 = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 0
# |   %.imagp3 = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 1
# |   store float %real_mul_phi, ptr %.realp2, align 4
# |   store float %imag_mul_phi, ptr %.imagp3, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local { double, double } @divd(double noundef %a.coerce0, double noundef %a.coerce1, double noundef %b.coerce0, double noundef %b.coerce1) #1 {
# | entry:
# |   %retval = alloca { double, double }, align 8
# |   %a = alloca { double, double }, align 8
# |   %b = alloca { double, double }, align 8
# |   %0 = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 0
# |   store double %a.coerce0, ptr %0, align 8
# |   %1 = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 1
# |   store double %a.coerce1, ptr %1, align 8
# |   %2 = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 0
# |   store double %b.coerce0, ptr %2, align 8
# |   %3 = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 1
# |   store double %b.coerce1, ptr %3, align 8
# |   %a.realp = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 0
# |   %a.real = load double, ptr %a.realp, align 8
# |   %a.imagp = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 1
# |   %a.imag = load doub
# | ...
# `---data was truncated (10240/29171) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055a0462f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a0462efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a0462f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5275649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f52756a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5275649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5275631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a046288bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a046288a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a04626d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a045f1ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a045f1cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5275632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f52756330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f52756330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a045f1ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c --check-prefix=FULL
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c --check-prefix=FULL
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c (2406 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +xandesvbfhcvt -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_nds_vfwcvt_s_bf16_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_nds_vfwcvt_s_bf16_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_nds_vfwcvt_s_bf16_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_nds_vfwcvt_s_bf16_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_nds_vfwcvt_s_bf16_f32m8_tu(<vscale x 16 x float> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005596fc785eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005596fc782e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005596fc78662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1509e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1509e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1509e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1509e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005596fc71bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005596fc71ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005596fc7008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005596fc3afe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005596fc3afb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1509e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1509e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1509e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005596fc3afa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/thinlto_backend.ll (2407 of 27911)
******************** TEST 'Clang :: CodeGen/thinlto_backend.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend.ll
# |  #0 0x0000563a4dae6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563a4dae3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563a4dae762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb8dd105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb8dd15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb8dd105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb8dd0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a4da7cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563a4da7ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563a4da618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563a4d710e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563a4d710b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb8dd0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb8dd0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb8dd0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a4d710a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c (2408 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmul_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmul_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmul_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmul_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmul_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmul_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmul_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmul_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmul_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfmul.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmul.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmul_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   stor
# | ...
# `---data was truncated (10240/29518) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e3ee6f0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e3ee6ede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e3ee6f162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e85649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e856a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e85649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e85631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e3ee686bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e3ee686a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e3ee66b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e3ee31ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e3ee31ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8e85632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e856330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e856330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e3ee31aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c (2409 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_i32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_i32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_u32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_u32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_f32mf2x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple,
# | ...
# `---data was truncated (10240/40726) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b841b05eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b841b02e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b841b0662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fae51b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fae51b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fae51b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fae51b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b841a9bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b841a9ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b841a808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b84172fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b84172fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fae51b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fae51b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fae51b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b84172fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c (2410 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vclz_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vclz_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vclz.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vclz.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vclz_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vclz.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vclz.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vclz_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vclz.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vclz.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vclz_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vclz.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vclz.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vclz_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vclz.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vclz.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vclz_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vclz.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vclz.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vclz_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vclz.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vclz.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vclz_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vclz.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vclz.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vclz_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vclz.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vclz.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vclz_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vclz.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vclz.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vclz_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vclz.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vclz.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vclz_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vclz.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | ...
# `---data was truncated (10240/40669) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a1a9c78eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a1a9c75e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a1a9c7962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f37e361bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f37e36725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f37e361ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f37e3603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a1a9c0ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a1a9c0ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a1a9bf38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a1a98a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a1a98a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f37e3604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f37e36050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f37e36050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a1a98a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c (2411 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlsseg4e8_v_i8mf8x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e8_v_i8mf4x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e8_v_i8mf2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e8_v_i8m1x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e8_v_i8m2x4_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlsseg4e8_v_u8mf8x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e8_v_u8mf4x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e8_v_u8mf2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.
# | ...
# `---data was truncated (10240/13557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562f677f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562f677eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562f677f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f988ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f988ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f988ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f988ab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562f67787bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562f67787a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562f6776c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562f6741be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562f6741bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f988ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f988ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f988ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562f6741ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c (2412 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_i64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_u64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_f64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_i64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_u64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple
# | ...
# `---data was truncated (10240/20903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005566403f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005566403f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005566403fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe972c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe972ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe972c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe972c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055664038fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055664038fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005566403748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556640023e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556640023b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe972c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe972c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe972c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556640023a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c (2413 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaadd_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaadd_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaadd_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaadd_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaadd_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaadd_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaadd_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaadd_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaadd_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaadd_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vaa
# | ...
# `---data was truncated (10240/99585) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005647b09d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005647b09d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005647b09d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff2fa249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff2fa2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff2fa249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff2fa231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005647b096cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005647b096ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005647b09518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005647b0600e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005647b0600b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff2fa232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff2fa2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff2fa2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005647b0600a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c (2414 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei32_v_i8mf8x7
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558a912a0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558a9129de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558a912a162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f52cac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f52caca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f52cac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f52cac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a91236bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558a91236a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558a9121b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558a90ecae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558a90ecab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f52cac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f52cac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f52cac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a90ecaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c (2415 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f16m1x5(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f32m1x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f64m1x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i16> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556f38708eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556f38705e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556f3870962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd74449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd744a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd74449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd74431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556f3869ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556f3869ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556f386838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556f38332e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556f38332b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbd74432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd744330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd744330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556f38332a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c (2416 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_f32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_i32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_i32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_i32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_u32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_u32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tupl
# | ...
# `---data was truncated (10240/53454) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ff0aba4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ff0aba1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ff0aba562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd4c7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd4c778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd4c7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd4c771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ff0ab3abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ff0ab3aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ff0ab1f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ff0a7cee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ff0a7ceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd4c771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd4c771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd4c771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ff0a7cea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c (2417 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cf38f15eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cf38f12e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cf38f1662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0a85e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0a85ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0a85e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0a85e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf38eabbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cf38eaba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cf38e908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cf38b3fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cf38b3fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0a85e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0a85e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0a85e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf38b3fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c (2418 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_f64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_f64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_i64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_i64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_u64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_u64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_f64m1x3_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple",
# | ...
# `---data was truncated (10240/40860) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b207309eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b207306e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b20730a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd79d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd79d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd79d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd79d031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b20729fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b20729fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b2072848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b206f33e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b206f33b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd79d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd79d0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd79d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b206f33a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c (2419 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei32_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560f996e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560f996e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560f996e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f410f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f410f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f410f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f410f31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f9967bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560f9967ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560f996608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560f9930fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560f9930fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f410f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f410f31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f410f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f9930fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c (2420 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f    -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_sf_vfexp_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_sf_vfexp_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_sf_vfexp_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_sf_vfexp_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_sf_vfexp_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_sf_vfexp_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_sf_vfexp_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_sf_vfexp_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_sf_vfexp_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(<vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) 
# | ...
# `---data was truncated (10240/27055) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556c14aebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556c14ae8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556c14aec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4430d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4430d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4430d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4430d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556c14a81bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556c14a81a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556c14a668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556c14715e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556c14715b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4430d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4430d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4430d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556c14715a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c (2421 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_i8mf8_u8mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_i8mf4_u8mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_i8mf2_u8mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_i8m1_u8m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_i8m2_u8m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_i8m4_u8m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_i8m8_u8m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_u8mf8_i8mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_u8mf4_i8mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u8mf2_i8mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_i8m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_i8m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_i8m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_i8m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vreinterpret_v_i16mf4_f16mf4(<vscale x 1 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x i16> %0 to <vscale x 1 x half>
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vreinterpret_v_i16mf2_f16mf2(<vscale x 2 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x i16> %0 to <vscale x 2 x half>
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vreinterpret_v_i16m1_f16m1(<vscale x 4 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x i16> %0 to <vscale x 4 x half>
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vreinterpret_v_i16m2_f16m2(<vscale x 8 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 8 x half>
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vreinterpret_v_i16m4_f16m4(<vscale x 16 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x i16> %0 to <vscale x 16 x half>
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vreinterpret_v_i16m8_f16m8(<vscale x 32 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 32 x i16> %0 to <vscale x 32 x half>
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vreinterpret_v_u16mf4_f16mf4(<vscale x 1 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x i16> %0 to <vscale x 1 x half>
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vreinterpret_v_u16mf2_f16mf2(<vscale x 2 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x i16> %0 to <vscale x 2 x half>
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vreinterpret_v_u16m1_f16m1(<vscale x 4 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x i16> %0 to <vscale x 4 x half>
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vreinterpret_v_u16m2_f16m2(<vscale x 8 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 8 x half>
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vreinterpret_v_u16m4_f16m4(<vscale x 16 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x i16> %0 to <vscale x 16 x half>
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vreinterpret_v_u16m8_f16m8(<vscale x 32 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = bi
# | ...
# `---data was truncated (10240/136481) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed37163eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ed37160e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ed3716462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbb5d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbb5d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbb5d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbb5d631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed370f9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ed370f9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ed370de8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ed36d8de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ed36d8db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbb5d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbb5d6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbb5d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed36d8da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c (2422 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a349a30eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a349a2de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a349a3162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f416fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f416fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f416fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f416fd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a3499c6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a3499c6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a3499ab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a34965ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a34965ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f416fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f416fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f416fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a34965aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c (2423 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_v
# | ...
# `---data was truncated (10240/228865) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055732e381eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055732e37ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055732e38262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f502b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f502b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f502b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f502b631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055732e317bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055732e317a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055732e2fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055732dfabe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055732dfabb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f502b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f502b6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f502b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055732dfaba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c (2424 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_bf16mf4_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_bf16mf2_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_bf16m1_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_bf16m2_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_bf16m4_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_bf16m8_i8m4_tu(<vscale x 32 x i8> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> %0, <vscale x 32 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_bf16mf4_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_bf16mf2_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_bf16m1_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_bf16m2_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, 
# | ...
# `---data was truncated (10240/142319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ff56d00eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ff56cfde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ff56d0162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc06d21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc06d2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc06d21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc06d203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ff56c96bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ff56c96a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ff56c7b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ff5692ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ff5692ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc06d204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc06d2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc06d2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ff5692aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminq.c (2425 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = icmp ule <16 x i8> %0, %1
# |   %3 = select <16 x i1> %2, <16 x i8> %0, <16 x i8> %1
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = icmp sle <8 x i16> %0, %1
# |   %3 = select <8 x i1> %2, <8 x i16> %0, <8 x i16> %1
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = icmp ule <4 x i32> %0, %1
# |   %3 = select <4 x i1> %2, <4 x i32> %0, <4 x i32> %1
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.min.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.min.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.min.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminq_x_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563ee40eceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563ee40e9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563ee40ed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4555449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f45554a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4555449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4555431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ee4082bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563ee4082a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563ee40678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563ee3d16e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563ee3d16b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4555432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f45554330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f45554330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ee3d16a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c (2426 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f7725cfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f7725cce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f7725d062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f56f6649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56f66a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f56f6649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f56f6631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f772565bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f772565a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f77254a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f7721f9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f7721f9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f56f6632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56f66330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56f66330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f7721f9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/riscv-xcvalu-c-api.c (2427 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/riscv-xcvalu-c-api.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xcvalu -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xcvalu -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_sle(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %4 = icmp sle i32 %2, %3
# |   %sle.i = zext i1 %4 to i32
# |   ret i32 %sle.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_sleu(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %4 = icmp ule i32 %2, %3
# |   %sleu.i = zext i1 %4 to i32
# |   ret i32 %sleu.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_min(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %elt.min.i = call i32 @llvm.smin.i32(i32 %2, i32 %3)
# |   ret i32 %elt.min.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_minu(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %elt.min.i = call i32 @llvm.umin.i32(i32 %2, i32 %3)
# |   ret i32 %elt.min.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_max(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %elt.max.i = call i32 @llvm.smax.i32(i32 %2, i32 %3)
# |   ret i32 %elt.max.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_maxu(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %elt.max.i = call i32 @llvm.umax.i32(i32 %2, i32 %3)
# |   ret i32 %elt.max.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_exths(i16 noundef signext %a) #0 {
# | entry:
# |   %a.addr.i = alloca i16, align 2
# |   %a.addr = alloca i16, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %a.addr.i, align 2
# |   %1 = load i16, ptr %a.addr.i, align 2
# |   %conv.i = sext i16 %1 to i32
# |   %exths.i = sext i16 %1 to i32
# |   ret i32 %exths.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_exthz(i16 noundef zeroext %a) #0 {
# | entry:
# |   %a.addr.i = alloca i16, align 2
# |   %a.addr = alloca i16, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %a.addr.i, align 2
# |   %1 = load i16, ptr %a.addr.i, align 2
# |   %conv.i = zext i16 %1 to i32
# |   %exthz.i = zext i16 %1 to i32
# |   ret i32 %exthz.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_extbs(i8 noundef signext %a) #0 {
# | entry:
# |   %a.addr.i = alloca i8, align 1
# |   %a.addr = alloca i8, align 1
# |   store i8 %a, ptr %a.addr, align 1
# |   %0 = load i8, ptr %a.addr, align 1
# |   store i8 %0, ptr %a.addr.i, align 1
# |   %1 = load i8, ptr %a.addr.i, align 1
# |   %conv.i = sext i8 %1 to i32
# |   %extbs.i = sext i8 %1 to i32
# |   ret i32 %extbs.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_extbz(i8 noundef zeroext %a) #0 {
# | entry:
# |   %a.addr.i = alloca i8, align 1
# |   %a.addr = alloca i8, align 1
# |   store i8 %a, ptr %a.addr, align 1
# |   %0 = load i8, ptr %a.addr, align 1
# |   store i8 %0, ptr %a.addr.i, align 1
# |   %1 = load i8, ptr %a.addr.i, align 1
# |   %conv.i = zext i8 %1 to i32
# |   %extbz.i = zext i8 %1 to i32
# |   ret i32 %extbz.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_clip(i32 noundef %a) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 0, ptr %b.addr.i, align 4
# |   %1 = load i32, ptr %a.addr.i, align 4
# |   %2 = load i32, ptr %b.addr.i, align 4
# |   %3 = call i32 @llvm.riscv.cv.alu.clip(i32 %1, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_clipu(i32 noundef %a) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 0, ptr %b.addr.i, align 4
# |   %1 = load i32, ptr %a.addr.i, align 4
# |   %2 = load i32, ptr %b.addr.i, align 4
# |   %3 = call i32 @llvm.riscv.cv.alu.clipu(i32 %1, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_addN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %shft.addr.i = alloca i8, align 1
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   store i8 0, ptr %shft.addr.i, align 1
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %4 = load i8, ptr %shft.addr.i, align 1
# |   %conv.i = zext i8 %4 to i32
# |   %5 = call i32 @llvm.riscv.cv.alu.addN(i32 %2, i32 %3, i32 %conv.i)
# |   ret i32 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_adduN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %shft.addr.i = alloca i8, align 1
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   store i8 0, ptr %shft.addr.i, align 1
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %4 = load i8, ptr %shft.addr.i, align 1
# |   %conv.i = zext i8 %4 to i32
# |   %5 = call i32 @llvm.riscv.cv.alu.adduN(i32 %2, i32 %3, i32 %conv.i)
# |   ret i32 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_addRN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %shft.addr.i = alloca i8, align 1
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   store i8 0, ptr %shft.addr.i, align 1
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %4 = load i8, ptr %shft.addr.i, align 1
# |   %conv.i = zext i8 %4 to i32
# |   %5 = call i32 @llvm.riscv.cv.alu.addRN(i32 %2, i32 %3, i32 %conv.i)
# |   ret i32 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_adduRN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %shft.addr.i = alloca i8, align 1
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   store i8 0, ptr %shft.addr.i, align 1
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %4 = load i8, ptr %shft.addr.i, align 1
# |   %conv.i = zext i8 %4 to i32
# |   %5 = call i32 @llvm.riscv.cv.alu.adduRN(i32 %2, i32 %3, i32 %conv.i)
# |   ret i32 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_subN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %shft.addr.i = alloca i8, align 1
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   st
# | ...
# `---data was truncated (10240/15696) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e4d0f3beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e4d0f38e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e4d0f3c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0a1da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0a1daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0a1da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0a1da31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e4d0ed1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e4d0ed1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e4d0eb68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e4d0b65e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e4d0b65b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0a1da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0a1da330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0a1da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e4d0b65a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c (2428 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562320dabeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562320da8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562320dac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1a0f61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1a0f6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1a0f61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1a0f603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562320d41bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562320d41a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562320d268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005623209d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005623209d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1a0f604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1a0f6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1a0f6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005623209d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c (2429 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willr
# | ...
# `---data was truncated (10240/44361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d2382eceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d2382e9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d2382ed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd999049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd9990a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd999049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd999031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d238282bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d238282a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d2382678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d237f16e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d237f16b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd999032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd9990330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd9990330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d237f16a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c (2430 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_4x8x4_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_4x8x4_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_4x8x4_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_4x8x4_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f3cc1f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f3cc1f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f3cc1f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5eb0c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5eb0ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5eb0c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5eb0c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f3cc189bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f3cc189a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f3cc16e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f3cbe1de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f3cbe1db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5eb0c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5eb0c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5eb0c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f3cbe1da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c (2431 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m1_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m8_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   
# | ...
# `---data was truncated (10240/81304) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c9bece6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c9bece3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c9bece762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0ad1533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0ad158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0ad1533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0ad151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9bec7cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c9bec7ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c9bec618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c9be910e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c9be910b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0ad151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0ad151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0ad151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c9be910a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c (2432 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vand_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vand_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vand_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vand_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vand_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vand_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vand_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vand_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vand_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vand_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vand_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/175163) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056208f174eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056208f171e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056208f17562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ce1849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ce18a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ce1849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ce1831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056208f10abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056208f10aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056208f0ef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056208ed9ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056208ed9eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4ce1832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ce18330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ce18330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056208ed9ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c (2433 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dotsu_vv_i32mf2(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dotsu_vv_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dotsu_vv_i32m2(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dotsu_vv_i32m4(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dotsu_vv_i32m8(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dotsu_vv_i64m1(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dotsu_vv_i64m2(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dotsu_vv_i64m4(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotsu.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dotsu.nx
# | ...
# `---data was truncated (10240/25567) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005570c2700eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005570c26fde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005570c270162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd58f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd58f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd58f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd58f31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005570c2696bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005570c2696a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005570c267b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005570c232ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005570c232ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd58f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd58f31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd58f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005570c232aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c (2434 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b03845eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b03845be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b03845f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f76ed333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f76ed38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f76ed333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f76ed31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b0383f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b0383f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b0383d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b038088e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b038088b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f76ed31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f76ed31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f76ed31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b038088a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c (2435 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2cl_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2cl_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2cl_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2cl_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2cl_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2cl_vv_u64m1_tu(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2cl_vv_u64m2_tu(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2cl_vv_u64m4_tu(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(
# | ...
# `---data was truncated (10240/12227) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005650ebf25eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005650ebf22e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005650ebf2662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3d6f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3d6f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3d6f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3d6f51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005650ebebbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005650ebebba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005650ebea08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005650ebb4fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005650ebb4fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3d6f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3d6f51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3d6f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005650ebb4fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c (2436 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557d0bcd7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557d0bcd4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557d0bcd862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f35faa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f35faaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f35faa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f35faa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557d0bc6dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557d0bc6da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557d0bc528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557d0b901e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557d0b901b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f35faa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f35faa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f35faa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557d0b901a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/AArch64/neon/fullfp16.c (2437 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/fullfp16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16           -emit-llvm  /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg             | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vaddh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %3 = load half, ptr %__s1, align 2
# |   %vaddh = fadd half %2, %3
# |   store half %vaddh, ptr %ref.tmp, align 2
# |   %4 = load half, ptr %ref.tmp, align 2
# |   store half %4, ptr %__ret, align 2
# |   %5 = load half, ptr %__ret, align 2
# |   store half %5, ptr %tmp, align 2
# |   %6 = load half, ptr %tmp, align 2
# |   ret half %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vsubh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %3 = load half, ptr %__s1, align 2
# |   %vsubh = fsub half %2, %3
# |   store half %vsubh, ptr %ref.tmp, align 2
# |   %4 = load half, ptr %ref.tmp, align 2
# |   store half %4, ptr %__ret, align 2
# |   %5 = load half, ptr %__ret, align 2
# |   store half %5, ptr %tmp, align 2
# |   %6 = load half, ptr %tmp, align 2
# |   ret half %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vmulh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %3 = load half, ptr %__s1, align 2
# |   %vmulh = fmul half %2, %3
# |   store half %vmulh, ptr %ref.tmp, align 2
# |   %4 = load half, ptr %ref.tmp, align 2
# |   store half %4, ptr %__ret, align 2
# |   %5 = load half, ptr %__ret, align 2
# |   store half %5, ptr %tmp, align 2
# |   %6 = load half, ptr %tmp, align 2
# |   ret half %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vdivh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %3 = load half, ptr %__s1, align 2
# |   %vdivh = fdiv half %2, %3
# |   store half %vdivh, ptr %ref.tmp, align 2
# |   %4 = load half, ptr %ref.tmp, align 2
# |   store half %4, ptr %__ret, align 2
# |   %5 = load half, ptr %__ret, align 2
# |   store half %5, ptr %tmp, align 2
# |   %6 = load half, ptr %tmp, align 2
# |   ret half %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vmaxh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %3 = load half, ptr %__s1, align 2
# |   %vmax = call half @llvm.aarch64.neon.fmax.f16(half %2, half %3)
# |   store half %vmax, ptr %ref.tmp, align 2
# |   %4 = load half, ptr %ref.tmp, align 2
# |   store half %4, ptr %__ret, align 2
# |   %5 = load half, ptr %__ret, align 2
# |   store half %5, ptr %tmp, align 2
# |   %6 = load half, ptr %tmp, align 2
# |   ret half %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.neon.fmax.f16(half, half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vmaxnmh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %3 = load half, ptr %__s1, align 2
# |   %vmaxnm = call half @llvm.aarch64.neon.fmaxnm.f16(half %2, half %3)
# |   store half %vmaxnm, ptr %ref.tmp, align 2
# |   %4 = load half, ptr %ref.tmp, align 2
# |   store half %4, ptr %__ret, align 2
# |   %5 = load half, ptr %__ret, align 2
# |   store half %5, ptr %tmp, align 2
# |   %6 = load half, ptr %tmp, align 2
# |   ret half %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.neon.fmaxnm.f16(half, half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vminh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %3 = load half, ptr %__s1, align 2
# |   %vmin = call half @llvm.aarch64.neon.fmin.f16(half %2, half %3)
# |   store half %vmin, ptr %ref.tmp, align 2
# |   %4 = load half, ptr %ref.tmp, align 2
# |   store half %4, ptr %__ret, align 2
# |   %5 = load half, ptr %__ret, align 2
# |   store half %5, ptr %tmp, align 2
# |   %6 = load half, ptr %tmp, align 2
# |   ret half %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.neon.fmin.f16(half, half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vminnmh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %3 = load half, ptr %__s1, align 2
# |   %vminnm = call half @llvm.aarch64.neon.fminnm.f16(half %2, half %3)
# |   store half %vminnm, ptr %ref.tmp, align 2
# |   %4 = load half, ptr %ref.tmp, align 2
# |   store half %4, ptr %__ret, align 2
# |   %5 = load half, ptr %__ret, align 2
# |   store half %5, ptr %tmp, align 2
# |   %6 = load half, ptr %tmp, align 2
# |   ret half %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.neon.fminnm.f16(half, half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vceqzh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp oeq half %1, 0.000000e+00
# |   %vceqz = sext i1 %2 to i16
# |   store i16 %vceqz, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vabsh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vabs = call half @llvm.fabs.f16(half %1)
# |   store half %vabs, ptr %ref.tmp, align 2
# |   %2 = load half, ptr %ref.tmp, align 2
# |   store half %2, ptr %__ret, align 2
# |   %3 = load half, ptr %__ret, align 2
# |   store half %3, ptr %tmp, align 2
# |   %4 = load half, ptr %tmp, align 2
# |   ret half %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare half @llvm.fabs.f16(half) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vabdh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = all
# | ...
# `---data was truncated (10240/27802) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a5e9976eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a5e9973e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a5e997762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f79b7505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f79b755c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f79b7505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f79b74ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a5e990cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a5e990ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a5e98f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a5e95a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a5e95a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f79b74eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f79b74ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f79b74ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a5e95a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c (2438 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005568615b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005568615b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005568615b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa320e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa320ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa320e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa320e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055686154dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055686154da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005568615328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005568611e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005568611e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa320e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa320e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa320e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005568611e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c (2439 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfgt_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfgt_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfgt_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 3
# | ...
# `---data was truncated (10240/27794) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563249ed1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563249ecee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563249ed262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb0d1f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb0d1f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb0d1f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb0d1f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563249e67bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563249e67a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563249e4c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563249afbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563249afbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb0d1f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb0d1f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb0d1f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563249afba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c (2440 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056137f5aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056137f5a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056137f5ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa07b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa07b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa07b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa07b231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056137f542bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056137f542a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056137f5278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056137f1d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056137f1d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa07b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa07b2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa07b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056137f1d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c (2441 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_viota_m_u8mf8(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_viota_m_u8mf4(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_viota_m_u8mf2(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_viota_m_u8m1(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_viota_m_u8m2(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_viota_m_u8m4(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_viota_m_u8m8(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_viota_m_u16mf4(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_viota_m_u16mf2(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_viota_m_u16m1(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_viota_m_u16m2(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.viota.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.viota.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_viota_m_u16m4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.viota.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.viota.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_viota_m_u16m8(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.viota.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <
# | ...
# `---data was truncated (10240/40411) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005595516d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005595516d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005595516d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec33e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec33e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec33e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec33e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055955166bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055955166ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005595516508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005595512ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005595512ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fec33e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec33e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec33e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005595512ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcvt.c (2442 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c --check-prefixes=CHECK,CHECK-NOSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcvtq_f16_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = sitofp <8 x i16> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcvtq_f16_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = uitofp <8 x i16> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcvtq_f32_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = sitofp <4 x i32> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcvtq_f32_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = uitofp <4 x i32> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtq_s16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = fptosi <8 x half> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = fptosi <4 x float> %0 to <4 x i32>
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtq_u16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = fptoui <8 x half> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtq_u32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = fptoui <4 x float> %0 to <4 x i32>
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcvtq_m_f16_s16(<8 x half> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x half>, ptr %inactive.addr, align 8
# |   %5 = call <8 x half> @llvm.arm.mve.vcvt.fp.int.predicated.v8f16.v8i16.v8i1(<8 x i16> %0, i32 0, <8 x i1> %3, <8 x half> %4)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vcvt.fp.int.predicated.v8f16.v8i16.v8i1(<8 x i16>, i32, <8 x i1>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcvtq_m_f16_u16(<8 x half> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x half>, ptr %inactive.addr, align 8
# |   %5 = call <8 x half> @llvm.arm.mve.vcvt.fp.int.predicated.v8f16.v8i16.v8i1(<8 x i16> %0, i32 1, <8 x i1> %3, <8 x half> %4)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcvtq_m_f32_s32(<4 x float> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x float>, ptr %inactive.addr, align 8
# |   %5 = call <4 x float> @llvm.arm.mve.vcvt.fp.int.predicated.v4f32.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %3, <4 x float> %4)
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vcvt.fp.int.predicated.v4f32.v4i32.v4i1(<4 x i32>, i32, <4 x i1>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcvtq_m_f32_u32(<4 x float> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x float>, ptr %inactive.addr, align 8
# |   %5 = call <4 x float> @llvm.arm.mve.vcvt.fp.int.predicated.v4f32.v4i32.v4i1(<4 x i32> %0, i32 1, <4 x i1> %3, <4 x float> %4)
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtq_m_s16_f16(<8 x i16> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.vcvt.fp.int.predicated.v8i16.v8f16.v8i1(<8 x half> %0, i32 0, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcvt.fp.int.predicated.v8i16.v8f16.v8i1(<8 x half>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtq_m_s32_f32(<4 x i32> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = call <4 x i32> @llvm.arm.mve.vcvt.fp.int.predicated.v4i32.v4f32.v4i1(<4 x float> %0, i32 0, <4 x i1> %3, <4 x i32> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcvt.fp.int.predicated.v4i32.v4f32.v4i1(<4 x float>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtq_m_u16_f16(<8 x i16> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.vcvt.fp.int.predicated.v8i16.v8f16.v8i1(<8 x half> %0, i32 1, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtq_m_u32_f32(<4 x i32> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm
# | ...
# `---data was truncated (10240/37578) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563d9f03deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563d9f03ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563d9f03e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f39b0133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f39b018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f39b0133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f39b011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d9efd3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563d9efd3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563d9efb88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563d9ec67e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563d9ec67b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f39b011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f39b011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f39b011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d9ec67a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c --check-prefixes=CHECK,CHECK-NOSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c --check-prefixes=CHECK,CHECK-NOSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c (2443 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_f16mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_f16mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_f16m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_f16m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_i16mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_i16mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_i16m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_i16m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_u16mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_u16mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local vo
# | ...
# `---data was truncated (10240/26928) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ae0205eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557ae0202e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557ae020662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f574341bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57434725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f574341ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5743403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ae019bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557ae019ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557ae01808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557adfe2fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557adfe2fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5743404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57434050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57434050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557adfe2fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c (2444 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmacc_4x8x4_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmacc_4x8x4_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmacc_4x8x4_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmacc_4x8x4_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f7b6a27eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f7b6a24e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f7b6a2862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f92e2e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f92e2e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f92e2e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f92e2e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f7b69bdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f7b69bda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f7b69a28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f7b6651e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f7b6651b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f92e2e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f92e2e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f92e2e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f7b6651a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c (2445 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8mf8x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_u8mf8x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_u8mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_u8mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_u8m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, al
# | ...
# `---data was truncated (10240/21566) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bca0cf8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bca0cf5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bca0cf962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc6c5733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc6c578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc6c5733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc6c571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bca0c8ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bca0c8ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bca0c738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bca0922e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bca0922b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc6c571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc6c571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc6c571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bca0922a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c (2446 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vlse32_v_f32mf2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vlse.mask.nxv1f32.p0.i64(<vscale x 1 x float> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vlse.mask.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vlse32_v_f32m1_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vlse.mask.nxv2f32.p0.i64(<vscale x 2 x float> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vlse.mask.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vlse32_v_f32m2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vlse.mask.nxv4f32.p0.i64(<vscale x 4 x float> poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vlse.mask.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vlse32_v_f32m4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vlse.mask.nxv8f32.p0.i64(<vscale x 8 x float> poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vlse.mask.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vlse32_v_f32m8_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x float> @llvm.riscv.vlse.mask.nxv16f32.p0.i64(<vscale x 16 x float> poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 16 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x float> @llvm.riscv.vlse.mask.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vlse32_v_i32mf2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32.p0.i64(<vscale x 1 x i32> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vlse32_v_i32m1_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vlse.mask.nxv2i32.p0.i64(<vscale x 2 x i32> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i32> @llvm.riscv.vlse.mask.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vlse32_v_i32m2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vlse.mask.nxv4i32.p0.i64(<vscale x 4 x i32> poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i32> @llvm.riscv.vlse.mask.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vlse32_v_i32m4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstrid
# | ...
# `---data was truncated (10240/17118) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005609743aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005609743a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005609743ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f83be333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83be38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f83be333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f83be31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560974342bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560974342a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005609743278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560973fd6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560973fd6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f83be31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83be31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83be31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560973fd6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c (2447 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563ac84a0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563ac849de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563ac84a162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a3b41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a3b4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a3b41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a3b403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ac8436bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563ac8436a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563ac841b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563ac80cae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563ac80cab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2a3b404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a3b4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a3b4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ac80caa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c (2448 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_bf16m1x3_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: n
# | ...
# `---data was truncated (10240/22107) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eb71f97eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eb71f94e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eb71f9862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd63c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd63c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd63c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd63c031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb71f2dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eb71f2da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eb71f128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eb71bc1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eb71bc1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd63c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd63c0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd63c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb71bc1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c (2449 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdf_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdf.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdf.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdf_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdf_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdf_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesdf_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdf_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdf_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | ...
# `---data was truncated (10240/20149) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055687af2feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055687af2ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055687af3062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff9cf533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff9cf58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff9cf533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff9cf51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055687aec5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055687aec5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055687aeaa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055687ab59e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055687ab59b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff9cf51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff9cf51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff9cf51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055687ab59a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c (2450 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsbf_m_b1_mu(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %maskedoff, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %2, <vscale x 64 x i1> %0, i64 %3)
# |   ret <vscale x 64 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsbf_m_b2_mu(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %maskedoff, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %2, <vscale x 32 x i1> %0, i64 %3)
# |   ret <vscale x 32 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsbf_m_b4_mu(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %maskedoff, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %2, <vscale x 16 x i1> %0, i64 %3)
# |   ret <vscale x 16 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsbf_m_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %2, <vscale x 8 x i1> %0, i64 %3)
# |   ret <vscale x 8 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbf_m_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %2, <vscale x 4 x i1> %0, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbf_m_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %2, <vscale x 2 x i1> %0, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbf_m_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1.i64(<vscale x 1 x i1> %1, <vscale x 1 x i1> %2, <vscale x 1 x i1> %0, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005568f3da5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005568f3da2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005568f3da662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3c40049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3c400a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3c40049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3c40031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005568f3d3bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005568f3d3ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005568f3d208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005568f39cfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005568f39cfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3c40032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3c400330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3c400330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005568f39cfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c (2451 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i16> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i16> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i16> %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> %2, ptr %0, <vscale x 32 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x
# | ...
# `---data was truncated (10240/15614) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e5db2d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e5db2d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e5db2d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007facd0933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007facd098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007facd0933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007facd091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e5db26bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e5db26ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e5db2508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e5daeffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e5daeffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007facd091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007facd091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007facd091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e5daeffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c (2452 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesef_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesef_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesef_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | ...
# `---data was truncated (10240/20149) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056071a66aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056071a667e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056071a66b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f14d9c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f14d9ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f14d9c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f14d9c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056071a600bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056071a600a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056071a5e58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056071a294e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056071a294b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f14d9c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f14d9c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f14d9c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056071a294a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c (2453 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16mf4x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16mf2x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m1x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m2x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m4x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   
# | ...
# `---data was truncated (10240/13255) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f116d4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559f116d1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559f116d562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efff4d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efff4d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efff4d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efff4d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f1166abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559f1166aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559f1164f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559f112fee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559f112feb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efff4d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efff4d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efff4d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f112fea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c (2454 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmax_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmax_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmax_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmax_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmax_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmax_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmax_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmax_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmax_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfmax.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmax.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmax_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>
# | ...
# `---data was truncated (10240/29062) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005628b51f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005628b51f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005628b51fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0509533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f050958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0509533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f050951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005628b518fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005628b518fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005628b51748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005628b4e23e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005628b4e23b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f050951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f050951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f050951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005628b4e23a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c (2455 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrdiv_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrdiv_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfrdiv.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrdiv.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrdiv_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfrdiv.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrdiv.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrdiv_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfrdiv.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrdiv.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrdiv_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfrdiv.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrdiv.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrdiv_vf_f16m8(<vscale x 32 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfrdiv.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrdiv.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrdiv_vf_f32mf2(<vscale x 1 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrdiv_vf_f32m1(<vscale x 2 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfrdiv.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrdiv.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrdiv_vf_f32m2(<vscale x 4 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfrdiv.nxv4f32.f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrdiv.nxv4f32.f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrdiv_vf_f32m4(<vscale x 8 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfrdiv.nxv8f32.f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfrdiv.nxv8f32.f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x 
# | ...
# `---data was truncated (10240/61066) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562440cc1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562440cbee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562440cc262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f062b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f062b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f062b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f062b11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562440c57bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562440c57a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562440c3c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005624408ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005624408ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f062b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f062b11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f062b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005624408eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmulq.c (2456 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmulq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = mul <16 x i8> %0, %1
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = mul <8 x i16> %0, %1
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = mul <4 x i32> %0, %1
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmulq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = fmul <4 x float> %0, %1
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.mul.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.mul.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.mul.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.mul.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmulq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x half>, ptr %inactive.addr, align 8
# |   %6 = call <8 x half> @llvm.arm.mve.mul.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4, <8 x half> %5)
# |   ret <8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.mul.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.mul.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.mul.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmulq_x_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x float> @llvm.arm.mve.mul.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4, <4 x float> undef)
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.m
# | ...
# `---data was truncated (10240/21288) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055e6ac152eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e6ac14fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e6ac15362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f93a0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f93a08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f93a0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f93a0831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e6ac0e8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e6ac0e8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e6ac0cd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e6abd7ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e6abd7cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f93a0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f93a08330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f93a08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e6abd7ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c (2457 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f16m1x8(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f32m1x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f64m1x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f0e7509eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f0e7506e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f0e750a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9a77333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9a7738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9a77333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9a7731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f0e749fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f0e749fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f0e74848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f0e7133e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f0e7133b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9a7731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9a7731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9a7731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f0e7133a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c (2458 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561335ca2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561335c9fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561335ca362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce69f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce69f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce69f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce69f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561335c38bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561335c38a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561335c1d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005613358cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005613358ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fce69f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce69f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce69f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005613358cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c (2459 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f3ef1b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f3ef1b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f3ef1b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f805ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f805ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f805ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f805ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f3ef14dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f3ef14da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f3ef1328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f3eede1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f3eede1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f805ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f805ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f805ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f3eede1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c (2460 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsac_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsac_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsac_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsac_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsac_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsac_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsac_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsac_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# | ...
# `---data was truncated (10240/34438) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556d2f19eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556d2f19be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556d2f19f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7fef905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7fef95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7fef905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7fef8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556d2f134bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556d2f134a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556d2f1198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556d2edc8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556d2edc8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7fef8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7fef8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7fef8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556d2edc8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c (2461 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_f16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_f16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_f16m1x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_i16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_i16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_i16m1x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_u16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_u16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_u16m1x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_
# | ...
# `---data was truncated (10240/10396) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cd10ab9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cd10ab6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cd10aba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe329c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe329ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe329c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe329c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cd10a4fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cd10a4fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cd10a348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cd106e3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cd106e3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe329c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe329c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe329c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cd106e3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c (2462 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste32_f32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.sf.vste32.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste32_i32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste32_u32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558720124eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558720121e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055872012562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fed64533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fed6458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fed64533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fed6451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005587200babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005587200baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055872009f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055871fd4ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055871fd4eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fed6451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fed6451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fed6451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055871fd4ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/builtins-arm64.c (2463 of 27911)
******************** TEST 'Clang :: CodeGen/builtins-arm64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-unknown-linux -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c --check-prefix=CHECK --check-prefix=CHECK-LINUX
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-unknown-linux -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-unknown-linux"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @f0(ptr noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load ptr, ptr %b.addr, align 8
# |   call void @llvm.clear_cache.p0(ptr %0, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.clear_cache.p0(ptr, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local ptr @tp() #0 {
# | entry:
# |   %0 = call ptr @llvm.thread.pointer.p0()
# |   ret ptr %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare ptr @llvm.thread.pointer.p0() #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @rbit(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %rbit = call i32 @llvm.bitreverse.i32(i32 %0)
# |   ret i32 %rbit
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.bitreverse.i32(i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @rbitl(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %rbit = call i64 @llvm.bitreverse.i64(i64 %0)
# |   ret i64 %rbit
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.bitreverse.i64(i64) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @rbit64(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %rbit = call i64 @llvm.bitreverse.i64(i64 %0)
# |   ret i64 %rbit
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @hints() #0 {
# | entry:
# |   call void @llvm.aarch64.hint(i32 0)
# |   call void @llvm.aarch64.hint(i32 1)
# |   call void @llvm.aarch64.hint(i32 2)
# |   call void @llvm.aarch64.hint(i32 3)
# |   call void @llvm.aarch64.hint(i32 4)
# |   call void @llvm.aarch64.hint(i32 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.aarch64.hint(i32) #4
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @barriers() #0 {
# | entry:
# |   call void @llvm.aarch64.dmb(i32 1)
# |   call void @llvm.aarch64.dsb(i32 2)
# |   call void @llvm.aarch64.isb(i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nofree nounwind willreturn
# | declare void @llvm.aarch64.dmb(i32) #5
# | 
# | ; Function Attrs: nofree nounwind willreturn
# | declare void @llvm.aarch64.dsb(i32) #5
# | 
# | ; Function Attrs: nofree nounwind willreturn
# | declare void @llvm.aarch64.isb(i32) #5
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @prefetch() #0 {
# | entry:
# |   call void @llvm.aarch64.prefetch(ptr null, i32 1, i32 2, i32 0, i32 1)
# |   call void @llvm.aarch64.prefetch(ptr null, i32 0, i32 0, i32 1, i32 1)
# |   call void @llvm.aarch64.prefetch(ptr null, i32 0, i32 0, i32 1, i32 1)
# |   call void @llvm.aarch64.prefetch(ptr null, i32 0, i32 0, i32 0, i32 0)
# |   call void @llvm.aarch64.prefetch(ptr null, i32 0, i32 3, i32 0, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.aarch64.prefetch(ptr readonly, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #6
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @range_prefetch() #0 {
# | entry:
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 0)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 1, i64 0)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 1, i32 0, i64 0)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 1, i32 1, i64 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.aarch64.range.prefetch(ptr readonly, i32 immarg, i32 immarg, i64) #6
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @range_prefetch_x() #0 {
# | entry:
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 0)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 1, i64 0)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 1, i32 0, i64 0)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 1, i32 1, i64 0)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 576460752305520640)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 576460752301326335)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 -1152921504606846976)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 -2305843009213693952)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 -6917529027641081856)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @read_intent_prefetch() #0 {
# | entry:
# |   call void @llvm.aarch64.prefetch.ir(ptr null)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.aarch64.prefetch.ir(ptr readonly) #6
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @jcvt(double noundef %v) #7 {
# | entry:
# |   %v.addr = alloca double, align 8
# |   store double %v, ptr %v.addr, align 8
# |   %0 = load double, ptr %v.addr, align 8
# |   %1 = call i32 @llvm.aarch64.fjcvtzs(double %0)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.fjcvtzs(double) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @rsr() #0 {
# | entry:
# |   %0 = call i64 @llvm.read_volatile_register.i64(metadata !7)
# |   %1 = trunc i64 %0 to i32
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nounwind
# | declare i64 @llvm.read_volatile_register.i64(metadata) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @rsr64() #0 {
# | entry:
# |   %0 = call i64 @llvm.read_volatile_register.i64(metadata !7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local ptr @rsrp() #0 {
# | entry:
# |   %0 = call i64 @llvm.read_volatile_register.i64(metadata !7)
# |   %1 = inttoptr i64 %0 to ptr
# |   ret ptr %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @wsr(i32 noundef %v) #0 {
# | entry:
# |   %v.addr = alloca i32, align 4
# |   store i32 %v, ptr %v.addr, align 4
# |   %0 = load i32, ptr %v.addr, align 4
# |   %1 = zext i32 %0 to i64
# |   call void @llvm.write_register.i64(metadata !7, i64 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nounwind
# | declare void @llvm.write_register.i64(metadata, i64) #8
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @wsr64(i64 noundef %v) #0 {
# | entry:
# |   %v.addr = alloca i64, align 8
# |   store i64 %v, ptr %v.addr, align 8
# |   %0 = load i64, ptr %v.addr, align 8
# |   call void @llvm.write_register.i64(metadata !7, i64 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @wsrp(ptr noundef %v) #0 {
# | entry:
# |   %v.addr = alloca ptr, align 8
# |   store ptr %v, ptr %v.addr, align 8
# |   %0 = load ptr, ptr %v.addr, align 8
# |   %1 = ptrtoint ptr %0 to i64
# |   call void @llvm.write_register.i64(metadata !7, i64 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @cls(i32 noundef %v) #0 {
# | entry:
# |   %v.addr = alloca i32, align 4
# |   store i32 %v, ptr %v.addr, align 4
# |   %0 = load i32, ptr %v.addr, align 4
# |   %cls = call i32 @llvm.aarch64.cls(i32 %0)
# |   ret i32 %cls
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.cls(i32) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clsl(i64 noundef %v) #0 {
# | entry:
# |   %v.addr = alloca i64, align 8
# |   store i64 %v, ptr %v.addr, align 8
# |   %0 = load i64, ptr %v.addr, align 8
# |   %cls = call i32 @llvm.aarch64.cls64(i64 %0)
# |   ret i32 %cls
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.cls64(i64) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clsll(i64 noundef %v) #0 {
# | entry:
# |   %v.addr = alloca i64, align 8
# |   store i64 %v, ptr %v.addr, align 8
# |   %0 = load i64, ptr %v.addr, align 8
# |   %cls = call i32 @llvm.aarch64.cls64(i64 %0)
# |   ret i32 %cls
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @rndr(ptr noundef %__addr) #9 {
# | entry:
# |   %__addr.addr = alloca ptr, align 8
# |   store ptr %__addr, ptr %__addr.addr, align 8
# |   %0 = call { i64, i1 } @llvm.aarch64.rndr()
# |   %1 = extractvalue { i64, i1 } %0, 0
# |   %2 = extractvalue { i64, i1 } %0, 1
# |   %3 = load ptr, ptr %__addr.addr, align 8
# |   store i64 %1, ptr %3, align 8
# |   %4 = zext i1 %2 to i32
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { i64, i1 } @llvm.aarch64.rndr() #4
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @rndrrs(ptr noundef %__addr) #9 {
# | entry:
# |   %__addr.addr = alloca ptr, align 8
# |   store ptr %__addr, ptr %__addr.addr, align 8
# |   %0 = call { i64, i1 } @llvm.aarch64.rndrrs()
# |   %1 = extractvalue { i64, i1 } %0, 0
# |   %2 = extractvalue { i64, i1 } %0, 1
# |   %3 = load ptr, ptr %__addr.addr, align 8
# |   store i64 %1, ptr %3, align 8
# |   %4 = zext i1 %2 to i32
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { i64, i1 } @llvm.aarch64.rndrrs() #4
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @trap() #0 {
# | entry:
# |   call void @llvm.aarch64.break(i32 42)
# |   ret void
# | }
# | 
# | ; Function Attrs: cold noreturn nounwind
# | declare void @llvm.aarch64.break(i32 immarg) #10
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @atomic_store_with_hint(ptr noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca i64, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   store atomic i64 %1, ptr %0 monotonic, align 8, !mem.cache_hint !8
# |   %2 = load ptr, ptr %a.addr, align 8
# |   %3 = load i64, ptr %b.addr, a
# | ...
# `---data was truncated (10240/16808) (change limit with -D output_limit=N)
# .---command stderr------------
# | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:243:3: warning: unrecognised hint type argument to atomic hint operation (5) [-Watomic-hint-type]
# |   243 |   __builtin_arm_atomic_store_with_hint(a, b, __ATOMIC_RELAXED, 5); // Invalid Hint
# |       |   ^                                                            ~
# | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:305:3: warning: unrecognised hint type argument to atomic hint operation (0) [-Watomic-hint-type]
# |   305 |   __builtin_arm_atomic_fetch_add_with_hint(a, b, __ATOMIC_RELAXED, HINT_STSHH_KEEP);
# |       |   ^                                                                ~~~~~~~~~~~~~~~
# | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:306:3: warning: unrecognised hint type argument to atomic hint operation (1) [-Watomic-hint-type]
# |   306 |   __builtin_arm_atomic_fetch_sub_with_hint(a, b, __ATOMIC_RELAXED, HINT_STSHH_STRM);
# |       |   ^                                                                ~~~~~~~~~~~~~~~
# | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:307:3: warning: unrecognised hint type argument to atomic hint operation (2) [-Watomic-hint-type]
# |   307 |   __builtin_arm_atomic_fetch_and_with_hint(a, b, __ATOMIC_RELAXED, HINT_STCPH);
# |       |   ^                                                                ~~~~~~~~~~
# | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:308:10: warning: unrecognised hint type argument to atomic hint operation (5) [-Watomic-hint-type]
# |   308 |   return __builtin_arm_atomic_fetch_add_with_hint(a, b, __ATOMIC_RELAXED, 5);
# |       |          ^                                                                ~
# | 5 warnings generated.
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056383d22feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056383d22ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056383d23062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa311049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa3110a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa311049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa311031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056383d1c5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056383d1c5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056383d1aa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056383ce59e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056383ce59b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa311032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa3110330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa3110330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056383ce59a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c --check-prefix=CHECK --check-prefix=CHECK-LINUX
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c --check-prefix=CHECK --check-prefix=CHECK-LINUX
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c (2464 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dotu_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dotu_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dotu_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dotu_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dotu_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dotu_vv_u64m1_tu(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dotu_vv_u64m2_tu(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dotu_vv_u64m4_tu(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dotu.nxv4i64.nxv1
# | ...
# `---data was truncated (10240/47628) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558717d5eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558717d5be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558717d5f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2509733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f250978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2509733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f250971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558717cf4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558717cf4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558717cd98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558717988e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558717988b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f250971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f250971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f250971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558717988a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c (2465 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_i16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_i16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_i16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_u16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca 
# | ...
# `---data was truncated (10240/60551) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005572bb41beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005572bb418e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005572bb41c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fde6e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fde6e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fde6e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fde6e71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005572bb3b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005572bb3b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005572bb3968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005572bb045e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005572bb045b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fde6e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fde6e71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fde6e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005572bb045a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c (2466 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_vv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_vx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_wv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_wx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_vv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_vx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_wv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_wx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwaddu_vv_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |  
# | ...
# `---data was truncated (10240/306627) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556b7ff57eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556b7ff54e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556b7ff5862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7871f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7871f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7871f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7871f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b7feedbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556b7feeda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556b7fed28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556b7fb81e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556b7fb81b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7871f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7871f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7871f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b7fb81a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c (2467 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_f64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_f64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_i64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_i64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_u64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_u64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_f64m1x4_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local t
# | ...
# `---data was truncated (10240/36031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559d0e8f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559d0e8efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559d0e8f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9d9a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9d9a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9d9a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9d9a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559d0e888bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559d0e888a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559d0e86d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559d0e51ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559d0e51cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9d9a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9d9a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9d9a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559d0e51ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c (2468 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_f64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_i64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_u64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560a52a63eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560a52a60e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560a52a6462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f04f9a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f04f9aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f04f9a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f04f9a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a529f9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560a529f9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560a529de8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560a5268de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560a5268db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f04f9a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f04f9a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f04f9a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a5268da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c (2469 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfeq_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfeq_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfeq_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 32 x bflo
# | ...
# `---data was truncated (10240/27786) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555ec5459eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555ec5456e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555ec545a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f88f2d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f88f2d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f88f2d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f88f2ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555ec53efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555ec53efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555ec53d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555ec5083e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555ec5083b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f88f2ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f88f2cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f88f2cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555ec5083a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c (2470 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f19cae8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f19cae5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f19cae962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6b6301bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6b630725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6b6301ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6b63003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f19ca7ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f19ca7ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f19ca638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f19c712e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f19c712b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6b63004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6b630050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6b630050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f19c712a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c (2471 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_x_f_qf_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %1, <vscale x 1 x float> %2, float %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %1, <vscale x 2 x float> %2, float %3, <vscale x 2 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x 
# | ...
# `---data was truncated (10240/26696) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558552c1eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558552c1be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558552c1f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd5b7533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd5b758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd5b7533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd5b751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558552bb4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558552bb4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558552b998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558552848e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558552848b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd5b751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd5b751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd5b751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558552848a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c (2472 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f16m1x4(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_f16m2x4(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f32m1x4(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_f32m2x4(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f64m1x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/87892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561d45547eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561d45544e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561d4554862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd4f6533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd4f658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd4f6533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd4f651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561d454ddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561d454dda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561d454c28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561d45171e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561d45171b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd4f651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd4f651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd4f651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561d45171a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c (2473 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfslide1up_vf_f16mf4(<vscale x 1 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfslide1up_vf_f16mf2(<vscale x 2 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfslide1up_vf_f16m1(<vscale x 4 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfslide1up_vf_f16m2(<vscale x 8 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfslide1up_vf_f16m4(<vscale x 16 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfslide1up_vf_f16m8(<vscale x 32 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfslide1up_vf_f32mf2(<vscale x 1 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfslide1up_vf_f32m1(<vscale x 2 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfslide1up_vf_f32m2(<vscale x 4 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfslide1up.nxv4f32.f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, float %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfslide1up.nxv4f32.f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfslide1up_vf_f32m4(<vscale x 8 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfslide1up.nxv8f32.f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, float %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfslide1up.nxv8f32.f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | de
# | ...
# `---data was truncated (10240/34581) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560f0a325eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560f0a322e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560f0a32662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efd96d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efd96d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efd96d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efd96d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f0a2bbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560f0a2bba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560f0a2a08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560f09f4fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560f09f4fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efd96d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efd96d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efd96d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f09f4fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c (2474 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vcompress_vm_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %src, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vcompress_vm_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %src, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vcompress_vm_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %src, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vcompress_vm_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %src, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vcompress_vm_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %src, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vcompress_vm_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %src, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i1> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vcompress_vm_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %src, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vcompress_vm_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %src, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vcompress.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretu
# | ...
# `---data was truncated (10240/77054) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056223a3dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056223a3dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056223a3e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe53e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe53e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe53e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe53e71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056223a375bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056223a375a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056223a35a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056223a009e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056223a009b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe53e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe53e71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe53e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056223a009a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c (2475 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfeq_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfeq_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfeq_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 3
# | ...
# `---data was truncated (10240/27794) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055712e390eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055712e38de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055712e39162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc09c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc09ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc09c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc09c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055712e326bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055712e326a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055712e30b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055712dfbae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055712dfbab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcc09c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc09c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc09c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055712dfbaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c (2476 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_i32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_i32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_u32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_u32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_f32mf2x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscal
# | ...
# `---data was truncated (10240/35921) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dc8aa10eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dc8aa0de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dc8aa1162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe254849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe2548a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe254849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe254831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc8a9a6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dc8a9a6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dc8a98b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dc8a63ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dc8a63ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe254832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe2548330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe2548330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc8a63aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c (2477 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f16m1x6(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f32m1x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f64m1x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei8_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none
# | ...
# `---data was truncated (10240/61673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055680837aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556808377e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055680837b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffbebc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffbebc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffbebc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffbebc03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556808310bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556808310a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005568082f58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556807fa4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556807fa4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffbebc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffbebc050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffbebc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556807fa4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c (2478 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f16m1x5(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f32m1x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f64m1x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005626f03c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005626f03c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005626f03c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6372d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6372d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6372d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6372d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005626f035abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005626f035aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005626f033f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005626effeee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005626effeeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6372d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6372d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6372d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005626effeea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c (2479 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8.p0.i64(<vscale x 16 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.p0.i64(<vscale x 32 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.p0.i64(<vscale x 64 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = l
# | ...
# `---data was truncated (10240/54480) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056262ee7eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056262ee7be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056262ee7f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcdc401bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcdc40725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcdc401ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcdc4003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056262ee14bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056262ee14a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056262edf98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056262eaa8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056262eaa8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcdc4004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcdc40050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcdc40050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056262eaa8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c (2480 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmv_v_f_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmv.v.f.nxv1bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmv.v.f.nxv1bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmv_v_f_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmv.v.f.nxv2bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmv.v.f.nxv2bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmv_v_f_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmv.v.f.nxv4bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmv.v.f.nxv4bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmv_v_f_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmv.v.f.nxv8bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmv.v.f.nxv8bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmv_v_f_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfmv.v.f.nxv16bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmv.v.f.nxv16bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfmv_v_f_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfmv.v.f.nxv32bf16.i64(<vscale x 32 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfmv.v.f.nxv32bf16.i64(<vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmv_s_f_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmv.s.f.nxv1bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmv.s.f.nxv1bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmv_s_f_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmv.s.f.nxv2bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmv.s.f.nxv2bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmv_s_f_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmv.s.f.nxv4bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmv.s.f.nxv4bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmv_s_f_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmv.s.f.nxv8bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmv.s.f.nxv8bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmv_s_f_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.
# | ...
# `---data was truncated (10240/12648) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b34f42eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b34f42be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b34f42f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff33f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff33f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff33f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff33f831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b34f3c4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b34f3c4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b34f3a98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b34f058e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b34f058b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff33f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff33f8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff33f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b34f058a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c (2481 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f29561eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559f2955ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559f2956262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc51c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc51c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc51c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc51c31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f294f7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559f294f7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559f294dc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559f2918be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559f2918bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc51c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc51c31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc51c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f2918ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c (2482 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_rtz_x_f_v_i16mf4(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_rtz_x_f_v_i16mf2(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_rtz_x_f_v_i16m1(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_rtz_x_f_v_i16m2(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_rtz_x_f_v_i16m4(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_rtz_x_f_v_i16m8(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_rtz_xu_f_v_u16mf4(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_rtz_xu_f_v_u16mf2(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_rtz_xu_f_v_u16m1(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_rtz_xu_f_v_u16m2(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_rtz_xu_f_v_u16m4(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_rtz_xu_f_v_u16m8(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz
# | ...
# `---data was truncated (10240/58675) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e31e0e6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e31e0e3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e31e0e762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efe70d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efe70d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efe70d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efe70d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e31e07cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e31e07ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e31e0618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e31dd10e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e31dd10b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efe70d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efe70d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efe70d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e31dd10a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c (2483 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei8_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei8_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei8_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei8_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei8_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vloxei8_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> poison, ptr %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei8_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei8_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei8_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei8_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = al
# | ...
# `---data was truncated (10240/14209) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055be7f179eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055be7f176e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055be7f17a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f72fc449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f72fc4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f72fc449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f72fc431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055be7f10fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055be7f10fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055be7f0f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055be7eda3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055be7eda3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f72fc432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f72fc4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f72fc4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055be7eda3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c (2484 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclipu_wv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclipu_wx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclipu_wv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclipu_wx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclipu_wv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclipu_wx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclipu_wv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclipu_wx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclipu
# | ...
# `---data was truncated (10240/156765) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055673d9efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055673d9ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055673d9f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe6ff01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe6ff0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe6ff01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe6ff003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055673d985bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055673d985a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055673d96a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055673d619e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055673d619b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe6ff004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe6ff0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe6ff0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055673d619a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c (2485 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>
# | ...
# `---data was truncated (10240/19492) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dd10cbceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dd10cb9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dd10cbd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0558d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0558d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0558d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0558d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd10c52bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dd10c52a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dd10c378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dd108e6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dd108e6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0558d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0558d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0558d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd108e6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c (2486 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_ffb(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca i64, align 8
# |   %__b.addr.i = alloca i64, align 8
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   store i64 %0, ptr %__a.addr.i, align 8
# |   store i64 %1, ptr %__b.addr.i, align 8
# |   %2 = load i64, ptr %__a.addr.i, align 8
# |   %3 = load i64, ptr %__b.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.nds.ffb.i64(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_ffzmism(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca i64, align 8
# |   %__b.addr.i = alloca i64, align 8
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   store i64 %0, ptr %__a.addr.i, align 8
# |   store i64 %1, ptr %__b.addr.i, align 8
# |   %2 = load i64, ptr %__a.addr.i, align 8
# |   %3 = load i64, ptr %__b.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.nds.ffzmism.i64(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_ffmism(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca i64, align 8
# |   %__b.addr.i = alloca i64, align 8
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   store i64 %0, ptr %__a.addr.i, align 8
# |   store i64 %1, ptr %__b.addr.i, align 8
# |   %2 = load i64, ptr %__a.addr.i, align 8
# |   %3 = load i64, ptr %__b.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.nds.ffmism.i64(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_flmism(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca i64, align 8
# |   %__b.addr.i = alloca i64, align 8
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   store i64 %0, ptr %__a.addr.i, align 8
# |   store i64 %1, ptr %__b.addr.i, align 8
# |   %2 = load i64, ptr %__a.addr.i, align 8
# |   %3 = load i64, ptr %__b.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.nds.flmism.i64(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i64 @llvm.riscv.nds.ffb.i64(i64, i64) #1
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i64 @llvm.riscv.nds.ffzmism.i64(i64, i64) #1
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i64 @llvm.riscv.nds.ffmism.i64(i64, i64) #1
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i64 @llvm.riscv.nds.flmism.i64(i64, i64) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xandesperf" }
# | attributes #1 = { nounwind speculatable memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_xandesperf5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560571e1beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560571e18e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560571e1c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb35c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb35c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb35c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb35c231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560571db1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560571db1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560571d968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560571a45e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560571a45b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb35c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb35c2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb35c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560571a45a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c (2487 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_f64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_f64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_f64m4x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_i64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_i64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_i64m4x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_u64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %
# | ...
# `---data was truncated (10240/13690) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056340dd41eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056340dd3ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056340dd4262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f503bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f503bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f503bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f503bb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056340dcd7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056340dcd7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056340dcbc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056340d96be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056340d96bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f503bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f503bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f503bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056340d96ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c (2488 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f16m1x6(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f32m1x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f64m1x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei64_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e6cc7b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e6cc7b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e6cc7b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8564849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f85648a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8564849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8564831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e6cc74dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e6cc74da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e6cc7328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e6cc3e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e6cc3e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8564832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f85648330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f85648330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e6cc3e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqaddq.c (2489 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqaddq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqaddq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqaddq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqaddq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqaddq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.qadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.qadd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqaddq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.qadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.qadd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqaddq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.qadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.qadd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqaddq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %0, <16 x i8> %.splat)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqaddq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %0, <8 x i16> %.splat)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqaddq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %0, <4 x i32> %.splat)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqaddq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.qadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqaddq_m_n_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.qadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, i32 1, <8 x i1> %4, <8 
# | ...
# `---data was truncated (10240/12015) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e95ac30eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e95ac2de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e95ac3162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9a21a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9a21aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9a21a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9a21a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e95abc6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e95abc6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e95abab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e95a85ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e95a85ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9a21a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9a21a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9a21a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e95a85aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c (2490 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsub_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsub_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsub_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsub_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsub_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsub_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsub_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsub_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsub_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsub.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsub.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsub_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscal
# | ...
# `---data was truncated (10240/29510) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b9ed5a4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b9ed5a1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b9ed5a562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6685249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f66852a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6685249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6685231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b9ed53abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b9ed53aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b9ed51f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b9ed1cee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b9ed1ceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6685232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f66852330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f66852330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b9ed1cea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c (2491 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16mf4_bf16(<vscale x 1 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv1bf16(<vscale x 1 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv1bf16(<vscale x 1 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16mf2_bf16(<vscale x 2 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv2bf16(<vscale x 2 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv2bf16(<vscale x 2 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16m1_bf16(<vscale x 4 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv4bf16(<vscale x 4 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv4bf16(<vscale x 4 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16m2_bf16(<vscale x 8 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv8bf16(<vscale x 8 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv8bf16(<vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16m4_bf16(<vscale x 16 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv16bf16(<vscale x 16 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv16bf16(<vscale x 16 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16m8_bf16(<vscale x 32 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv32bf16(<vscale x 32 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv32bf16(<vscale x 32 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557e4db2deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557e4db2ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557e4db2e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb0c8449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb0c84a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb0c8449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb0c8431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e4dac3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557e4dac3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557e4daa88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557e4d757e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557e4d757b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb0c8432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb0c84330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb0c84330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e4d757a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c (2492 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsleu_vv_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsleu_vx_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsleu_vv_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsleu_vx_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsleu_vv_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsleu_vx_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsleu_vv_u8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8
# | ...
# `---data was truncated (10240/63713) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bb2e2fbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bb2e2f8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bb2e2fc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3c82649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3c826a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3c82649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3c82631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bb2e291bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bb2e291a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bb2e2768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bb2df25e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bb2df25b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3c82632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3c826330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3c826330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bb2df25a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c (2493 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16mf4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16mf2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m1_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m8_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, a
# | ...
# `---data was truncated (10240/44177) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b4ad5b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b4ad5b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b4ad5b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc73cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc73cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc73cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc73cb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b4ad54dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b4ad54da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b4ad5328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b4ad1e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b4ad1e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc73cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc73cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc73cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b4ad1e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c (2494 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4a_vx_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4a_vx_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range
# | ...
# `---data was truncated (10240/24990) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565038a43eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565038a40e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000565038a4462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd885105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd88515c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd885105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd8850ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005650389d9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005650389d9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005650389be8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056503866de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056503866db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd8850eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd8850ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd8850ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056503866da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c (2495 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a16f  -target-feature +xsfmm32a32f -target-feature +xsfmm64a64f  -target-feature +zvfhmin -target-feature +zve64d -disable-O0-optnone  -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a16f -target-feature +xsfmm32a32f -target-feature +xsfmm64a64f -target-feature +zvfhmin -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_mm_f_f_w2_f16m8(<vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 0, <vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2, i64 %3, i64 %4, i64 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 immarg, <vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_mm_f_f_w1_f32m8(<vscale x 16 x float> %vs2, <vscale x 16 x float> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vs1.addr = alloca <vscale x 16 x float>, align 4
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 16 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 0, <vscale x 16 x float> %0, <vscale x 16 x float> %1, i64 %2, i64 %3, i64 %4, i64 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 immarg, <vscale x 16 x float>, <vscale x 16 x float>, i64, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_mm_f_f_w1_f64m8(<vscale x 8 x double> %vs2, <vscale x 8 x double> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vs1.addr = alloca <vscale x 8 x double>, align 8
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x double> %vs1, ptr %vs1.addr, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 8 x double>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.f.f.i64.nxv8f64(i64 0, <vscale x 8 x double> %0, <vscale x 8 x double> %1, i64 %2, i64 %3, i64 %4, i64 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.f.f.i64.nxv8f64(i64 immarg, <vscale x 8 x double>, <vscale x 8 x double>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+xsfmm32a16f,+xsfmm32a32f,+xsfmm64a64f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvl32b1p0_zvl64b1p0_xsfmm32a16f0p6_xsfmm32a32f0p6_xsfmm64a64f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c2f36b1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c2f36aee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c2f36b262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3edf849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3edf8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3edf849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3edf831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c2f3647bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c2f3647a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c2f362c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c2f32dbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c2f32dbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3edf832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3edf8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3edf8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c2f32dba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c (2496 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4asu_vx_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4asu_vx_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) 
# | ...
# `---data was truncated (10240/25094) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba38605eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ba38602e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ba3860662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6994533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f699458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6994533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f699451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba3859bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ba3859ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ba385808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ba3822fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ba3822fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f699451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f699451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f699451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba3822fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c (2497 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei16_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei16_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei16_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei16_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei16_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vluxei16_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, <vscale x 32 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei16_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei16_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei16_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <v
# | ...
# `---data was truncated (10240/280163) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564692f2ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564692f29e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564692f2d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b94b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b94b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b94b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b94b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564692ec2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564692ec2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564692ea78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564692b56e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564692b56b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8b94b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b94b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b94b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564692b56a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c (2498 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_i64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_u64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_i64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_u64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.ve
# | ...
# `---data was truncated (10240/18498) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561ff4b7eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561ff4b7be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561ff4b7f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f343da1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f343da725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f343da1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f343da03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561ff4b14bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561ff4b14a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561ff4af98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561ff47a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561ff47a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f343da04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f343da050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f343da050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561ff47a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c (2499 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vle16_v_f16mf4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vle.mask.nxv1f16.p0.i64(<vscale x 1 x half> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x half> @llvm.riscv.vle.mask.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vle16_v_f16mf2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vle.mask.nxv2f16.p0.i64(<vscale x 2 x half> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x half> @llvm.riscv.vle.mask.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vle16_v_f16m1_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vle.mask.nxv4f16.p0.i64(<vscale x 4 x half> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x half> @llvm.riscv.vle.mask.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vle16_v_f16m2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vle.mask.nxv8f16.p0.i64(<vscale x 8 x half> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x half> @llvm.riscv.vle.mask.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vle16_v_f16m4_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vle.mask.nxv16f16.p0.i64(<vscale x 16 x half> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x half> @llvm.riscv.vle.mask.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vle16_v_f16m8_m(<vscale x 32 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vle.mask.nxv32f16.p0.i64(<vscale x 32 x half> poison, ptr %1, <vscale x 32 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x half> @llvm.riscv.vle.mask.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16_v_i16mf4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vle.mask.nxv1i16.p0.i64(<vscale x 1 x i16> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i16> @llvm.riscv.vle.mask.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16_v_i16mf2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vle.mask.nxv2i16.p0.i64(<vscale x 2 x i16> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i16> @llvm.riscv.vle.mask.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vle16_v_i16m1_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vle.mask.nxv4i16.p0.i64(<vscale x 4 x i16> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i16> @llvm.riscv.vle.mask.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vle16_v_i16m2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vle.mask.nxv8i16.p0.i64(<vscale x 8 x i16> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i16> @llvm.riscv.vle.mask.nxv8i16.p0.i64(<vscale x 8 x i16>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinli
# | ...
# `---data was truncated (10240/17403) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a2a8102eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a2a80ffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a2a810362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b2ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b2ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b2ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b2ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a2a8098bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a2a8098a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a2a807d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a2a7d2ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a2a7d2cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8b2ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b2ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b2ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a2a7d2ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vrmulhq.c (2500 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vrmulhq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrmulhq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vrmulh.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vrmulh.v16i8(<16 x i8>, <16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrmulhq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vrmulh.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vrmulh.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrmulhq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vrmulh.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vrmulh.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrmulhq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.rmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.rmulh.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrmulhq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.rmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.rmulh.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrmulhq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.rmulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.rmulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrmulhq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.rmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrmulhq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.rmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrmulhq_m_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.rmulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a87c6e7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a87c6e4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a87c6e862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f90a8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f90a878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f90a8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f90a871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a87c67dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a87c67da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a87c6628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a87c311e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a87c311b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f90a871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f90a871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f90a871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a87c311a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c (2501 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmxnor_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmxnor.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmxnor.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmxnor_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmxnor.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmxnor.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmxnor_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmxnor.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmxnor.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmxnor_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmxnor.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmxnor.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmxnor_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmxnor.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmxnor.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmxnor_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmxnor.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmxnor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmxnor_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmxnor.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmxnor.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005650aa53beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005650aa538e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005650aa53c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f12a4c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f12a4ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f12a4c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f12a4c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005650aa4d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005650aa4d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005650aa4b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005650aa165e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005650aa165b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f12a4c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f12a4c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f12a4c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005650aa165a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c (2502 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16mf4x7(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16mf2x7(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16m1x7(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056012e861eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056012e85ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056012e86262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f142ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f142ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f142ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f142ff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056012e7f7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056012e7f7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056012e7dc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056012e48be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056012e48bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f142ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f142ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f142ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056012e48ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c (2503 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f16m1x5(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f32m1x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f64m1x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei16_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f20e1edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f20e1eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f20e1ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f41bbf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f41bbf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f41bbf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f41bbf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f20e183bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f20e183a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f20e1688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f20de17e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f20de17b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f41bbf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f41bbf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f41bbf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f20de17a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c (2504 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f16m1x5(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f32m1x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f64m1x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei16_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b16fd6beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b16fd68e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b16fd6c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f711a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f711a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f711a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f711a31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b16fd01bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b16fd01a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b16fce68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b16f995e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b16f995b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f711a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f711a31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f711a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b16f995a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c (2505 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ea2c628eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ea2c625e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ea2c62962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb6dad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb6dad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb6dad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb6dad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ea2c5bebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ea2c5bea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ea2c5a38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ea2c252e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ea2c252b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb6dad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb6dad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb6dad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ea2c252a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c (2506 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei32_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 
# | ...
# `---data was truncated (10240/284344) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b3a143aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b3a1437e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b3a143b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7473c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7473ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7473c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7473c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b3a13d0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b3a13d0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b3a13b58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b3a1064e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b3a1064b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7473c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7473c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7473c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b3a1064a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c (2507 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfne
# | ...
# `---data was truncated (10240/18668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056141d750eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056141d74de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056141d75162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff82e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff82e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff82e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff82e51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056141d6e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056141d6e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056141d6cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056141d37ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056141d37ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff82e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff82e51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff82e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056141d37aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c (2508 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvtbf16_f_f_w_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvtbf16_f_f_w_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvtbf16_f_f_w_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvtbf16_f_f_w_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvtbf16_f_f_w_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, a
# | ...
# `---data was truncated (10240/43486) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561b23f12eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561b23f0fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561b23f1362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd7cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd7cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd7cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd7cf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561b23ea8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561b23ea8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561b23e8d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561b23b3ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561b23b3cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdd7cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd7cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd7cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561b23b3ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c (2509 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ec7c24eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564ec7c21e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564ec7c2562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f91ff505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f91ff55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f91ff505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f91ff4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ec7bbabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564ec7bbaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564ec7b9f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564ec784ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564ec784eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f91ff4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f91ff4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f91ff4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ec784ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c (2510 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>,
# | ...
# `---data was truncated (10240/296943) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005646f43d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005646f43d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005646f43d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa11fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa11fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa11fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa11fc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005646f436bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005646f436ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005646f43508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005646f3fffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005646f3fffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa11fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa11fc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa11fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005646f3fffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c (2511 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16mf4x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16mf2x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16m1x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16m2x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca targ
# | ...
# `---data was truncated (10240/11920) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b922331eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b92232ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b92233262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee86249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee862a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee86249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee86231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b9222c7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b9222c7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b9222ac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b921f5be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b921f5bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fee86232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee862330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee862330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b921f5ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c (2512 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.
# | ...
# `---data was truncated (10240/16808) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005580cdd0aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005580cdd07e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005580cdd0b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f76b8d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f76b8d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f76b8d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f76b8d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005580cdca0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005580cdca0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005580cdc858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005580cd934e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005580cd934b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f76b8d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f76b8d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f76b8d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005580cd934a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c (2513 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_i16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_i16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_i16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nx
# | ...
# `---data was truncated (10240/78682) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b644e4beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b644e48e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b644e4c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f270241bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f27024725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f270241ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2702403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b644de1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b644de1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b644dc68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b644a75e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b644a75b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2702404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f27024050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f27024050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b644a75a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c (2514 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsadd_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsadd_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsadd_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsadd_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsadd_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsadd_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsadd_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsadd_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsadd_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsadd_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsadd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsadd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsadd_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr
# | ...
# `---data was truncated (10240/97905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d0b0a6beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d0b0a68e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d0b0a6c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9538849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f95388a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9538849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9538831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0b0a01bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d0b0a01a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d0b09e68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d0b0695e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d0b0695b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9538832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f95388330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f95388330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d0b0695a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c (2515 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabd_vv_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabd_vx_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabd_vv_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabd_vx_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabd_vv_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabd_vx_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabd_vv_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabd_vx_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabd_vv_u8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8
# | ...
# `---data was truncated (10240/215036) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055932a993eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055932a990e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055932a99462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb90a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb90aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb90a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb90a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055932a929bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055932a929a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055932a90e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055932a5bde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055932a5bdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feb90a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb90a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb90a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055932a5bda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c (2516 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16mf4(ptr noundef %base, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1f16.p0.i64(<vscale x 1 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16mf2(ptr noundef %base, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2f16.p0.i64(<vscale x 2 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16m1(ptr noundef %base, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4f16.p0.i64(<vscale x 4 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16m2(ptr noundef %base, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8f16.p0.i64(<vscale x 8 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16m4(ptr noundef %base, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16f16.p0.i64(<vscale x 16 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16m8(ptr noundef %base, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv32f16.p0.i64(<vscale x 32 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16mf4(ptr noundef %base, <vscale x 1 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i16.p0.i64(<vscale x 1 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16mf2(ptr noundef %base, <vscale x 2 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i16.p0.i64(<vscale x 2 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16m1(ptr noundef %base, <vscale x 4 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i16.p0.i64(<vscale x 4 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16m2(ptr noundef %base, <vscale x 8 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i16.p0.i64(<vscale x 8 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8i16.p0.i64(<vscale x 8 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16m4(ptr noundef %base, <vscale x 16 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16i16.p0.i64(<vscale x 16 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16i16.p0.i64(<vscale x 16 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16m8(ptr noundef %base, <vscale x 32 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/33764) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e141844eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e141841e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e14184562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8710933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f871098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8710933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f871091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e1417dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e1417daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e1417bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e14146ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e14146eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f871091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f871091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f871091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e14146ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c (2517 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_u64m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005631a8526eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005631a8523e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005631a852762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f359fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f359fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f359fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f359fd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005631a84bcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005631a84bca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005631a84a18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005631a8150e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005631a8150b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f359fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f359fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f359fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005631a8150a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c (2518 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrsqrt7_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrsqrt7_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrsqrt7_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrsqrt7_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrsqrt7_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrsqrt7_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrsqrt7_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrsqrt7_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrsqrt7_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrsqrt7_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfrsqrt7.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfrsqrt7.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfrsqrt7_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfrsqrt7.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfrsqrt7.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfrsqrt7_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfrsqrt7.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfrsqrt7.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vfrsqrt7_v_f64m2(<vscale x 2 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align
# | ...
# `---data was truncated (10240/29111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055983591aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559835917e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055983591b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1fa5b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1fa5b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1fa5b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1fa5aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005598358b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005598358b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005598358958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559835544e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559835544b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1fa5aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1fa5aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1fa5aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559835544a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c (2519 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vle32_v_f32mf2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vle.mask.nxv1f32.p0.i64(<vscale x 1 x float> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x float> @llvm.riscv.vle.mask.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vle32_v_f32m1_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vle.mask.nxv2f32.p0.i64(<vscale x 2 x float> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x float> @llvm.riscv.vle.mask.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vle32_v_f32m2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vle.mask.nxv4f32.p0.i64(<vscale x 4 x float> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.riscv.vle.mask.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vle32_v_f32m4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vle.mask.nxv8f32.p0.i64(<vscale x 8 x float> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x float> @llvm.riscv.vle.mask.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vle32_v_f32m8_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vle.mask.nxv16f32.p0.i64(<vscale x 16 x float> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x float> @llvm.riscv.vle.mask.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32_v_i32mf2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vle.mask.nxv1i32.p0.i64(<vscale x 1 x i32> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i32> @llvm.riscv.vle.mask.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32_v_i32m1_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vle.mask.nxv2i32.p0.i64(<vscale x 2 x i32> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i32> @llvm.riscv.vle.mask.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32_v_i32m2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vle.mask.nxv4i32.p0.i64(<vscale x 4 x i32> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.riscv.vle.mask.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vle32_v_i32m4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vle.mask.nxv8i32.p0.i64(<vscale x 8 x i32> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i32> @llvm.riscv.vle.mask.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vle32_v_i32m8_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vle.mask.nxv16i32.p0.i64(<vscale x 16 x i32> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i32> @llvm.riscv.vle.mask.nxv16i32.p0.i64(<vscale x 16 x i32>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; 
# | ...
# `---data was truncated (10240/14699) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005556199a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055561999fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005556199a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f279bc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f279bca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f279bc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f279bc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555619938bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555619938a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055561991d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005556195cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005556195ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f279bc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f279bc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f279bc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005556195cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c (2520 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_i8mf8x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_i8mf4x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8_v_i8mf2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8_v_i8m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8_v_i8m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_u8mf8x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_u8mf4x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8_v_u8mf2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8_v_u8m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8_v_u8m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_i8mf8x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_i8mf4x4_m(<vscale x 2 x i1> %mask, ptr noundef %bas
# | ...
# `---data was truncated (10240/20340) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c134309eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c134306e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c13430a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa4c5a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa4c5a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa4c5a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa4c5a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c13429fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c13429fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c1342848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c133f33e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c133f33b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa4c5a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4c5a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4c5a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c133f33a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c (2521 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei64_v_f16mf4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei64_v_f16mf2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei64_v_f16m1(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei64_v_f16m2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei64_v_f32mf2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei64_v_f32m1(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei64_v_f32m2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei64_v_f32m4(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vluxei64_v_f64m1(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vluxei64_v_f64m2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.p0.nxv2i64.i64(<vscale x 2 x double> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.p0.nxv2i64.i64(<vscale x 2 x doubl
# | ...
# `---data was truncated (10240/91275) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a742366eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a742363e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a74236762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ffe305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ffe35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ffe305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ffe2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a7422fcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a7422fca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a7422e18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a741f90e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a741f90b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8ffe2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ffe2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ffe2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a741f90a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c (2522 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_f16m1x2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_f16m2x2(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei16_v_f16m4x2(ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_f32m1x2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_f32m2x2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple
# | ...
# `---data was truncated (10240/113757) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558a7122aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558a71227e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558a7122b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f23ae049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f23ae0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f23ae049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f23ae031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a711c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558a711c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558a711a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558a70e54e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558a70e54b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f23ae032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f23ae0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f23ae0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a70e54a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/AArch64/atomic-hint-template.cpp (2523 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/atomic-hint-template.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple aarch64-none-elf -target-feature +v9.4a -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple aarch64-none-elf -target-feature +v9.4a -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-unknown-none-elf"
# | 
# | $_Z37test_atomic_store_hint_template_orderILj3EEvPii = comdat any
# | 
# | $_Z36test_atomic_store_hint_template_hintILj1EEvPii = comdat any
# | 
# | $_Z37test_atomic_fetch_hint_template_orderILj2EEiPii = comdat any
# | 
# | $_Z36test_atomic_fetch_hint_template_hintILj4EEiPii = comdat any
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define weak_odr void @_Z37test_atomic_store_hint_template_orderILj3EEvPii(ptr noundef %ptr, i32 noundef %val) #0 comdat {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %val.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %val, ptr %val.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %val.addr, align 4
# |   store atomic i32 %1, ptr %0 release, align 4, !mem.cache_hint !4
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define weak_odr void @_Z36test_atomic_store_hint_template_hintILj1EEvPii(ptr noundef %ptr, i32 noundef %val) #0 comdat {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %val.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %val, ptr %val.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %val.addr, align 4
# |   store atomic i32 %1, ptr %0 seq_cst, align 4, !mem.cache_hint !6
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local void @_Z43test_atomic_store_hint_array_consexpr_orderPii(ptr noundef %ptr, i32 noundef %value) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %value.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %value, ptr %value.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %value.addr, align 4
# |   store atomic i32 %1, ptr %0 monotonic, align 4, !mem.cache_hint !4
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local void @_Z42test_atomic_store_hint_array_consexpr_hintPii(ptr noundef %ptr, i32 noundef %value) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %value.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %value, ptr %value.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %value.addr, align 4
# |   store atomic i32 %1, ptr %0 monotonic, align 4, !mem.cache_hint !6
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define weak_odr noundef i32 @_Z37test_atomic_fetch_hint_template_orderILj2EEiPii(ptr noundef %ptr, i32 noundef %val) #0 comdat {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %val.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %val, ptr %val.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %val.addr, align 4
# |   %2 = atomicrmw add ptr %0, i32 %1 acquire, align 4, !mem.cache_hint !8
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define weak_odr noundef i32 @_Z36test_atomic_fetch_hint_template_hintILj4EEiPii(ptr noundef %ptr, i32 noundef %val) #0 comdat {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %val.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %val, ptr %val.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %val.addr, align 4
# |   %2 = atomicrmw xor ptr %0, i32 %1 seq_cst, align 4, !mem.cache_hint !10
# |   ret i32 %2
# | }
# | 
# | attributes #0 = { mustprogress noinline nounwind vscale_range(1,16) "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+complxnum,+crc,+cssc,+dit,+dotprod,+flagm,+fp-armv8,+fullfp16,+hbc,+i8mm,+jsconv,+lse,+mec,+mops,+neon,+pauth,+predres,+ras,+rasv2,+rcpc,+rdm,+rme,+sb,+spe-eef,+specres2,+ssbs,+sve,+sve2,+sve2p1,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v8.9a,+v8a,+v9.1a,+v9.2a,+v9.3a,+v9.4a,+v9a,+wfxt" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# | !4 = !{i32 1, !5}
# | !5 = !{!"aarch64.mem_hint", i32 0}
# | !6 = !{i32 1, !7}
# | !7 = !{!"aarch64.mem_hint", i32 1}
# | !8 = !{i32 0, !9}
# | !9 = !{!"aarch64.mem_hint", i32 3}
# | !10 = !{i32 0, !11}
# | !11 = !{!"aarch64.mem_hint", i32 4}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a2ade5feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a2ade5ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a2ade6062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f99ecb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f99ecb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f99ecb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f99ecb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a2addf5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a2addf5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a2addda8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a2ada89e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a2ada89b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f99ecb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f99ecb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f99ecb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a2ada89a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c (2524 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjx_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjx_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjx_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjx_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjx_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjx_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjx_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjx_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bf
# | ...
# `---data was truncated (10240/65202) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005584dde7ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005584dde79e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005584dde7d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6863533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f686358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6863533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f686351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005584dde12bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005584dde12a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005584dddf78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005584ddaa6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005584ddaa6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f686351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f686351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f686351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005584ddaa6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c (2525 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_f16mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_f16mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_f16m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_i16mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_i16mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_i16m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_u16mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_u16mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_u16m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_f16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.ri
# | ...
# `---data was truncated (10240/20449) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c9d4574eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c9d4571e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c9d457562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f307e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f307e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f307e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f307e631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9d450abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c9d450aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c9d44ef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c9d419ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c9d419eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f307e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f307e6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f307e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c9d419ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c (2526 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_i64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_u64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_f64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_i64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_u64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vsca
# | ...
# `---data was truncated (10240/20895) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ecb3e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557ecb3e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557ecb3e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ac2249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ac22a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ac2249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ac2231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ecb37abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557ecb37aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557ecb35f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557ecb00ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557ecb00eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8ac2232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ac22330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ac22330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ecb00ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c (2527 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_x_f_w_bf16mf4_i8mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_x_f_w_bf16mf2_i8mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_x_f_w_bf16m1_i8mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_x_f_w_bf16m2_i8m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_x_f_w_bf16m4_i8m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_x_f_w_bf16m8_i8m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_xu_f_w_bf16mf4_u8mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_xu_f_w_bf16mf2_u8mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_xu_f_w_bf16m1_u8mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_xu_f_w_bf16m2_u8m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_xu_f_w_bf16m4_u8m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_xu_f_w_bf16m8_u8m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32bf16.i64(<vscale x
# | ...
# `---data was truncated (10240/24328) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d4bb427eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d4bb424e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d4bb42862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc2cca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc2ccaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc2cca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc2cca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d4bb3bdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d4bb3bda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d4bb3a28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d4bb051e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d4bb051b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc2cca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc2cca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc2cca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d4bb051a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c (2528 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsub_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsub_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsub_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsub_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsub_vf_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrsub_vf_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsub_vf_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsub_vf_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, pt
# | ...
# `---data was truncated (10240/32402) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560931c90eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560931c8de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560931c9162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f525281bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f52528725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f525281ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5252803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560931c26bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560931c26a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560931c0b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005609318bae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005609318bab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5252804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f52528050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f52528050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005609318baa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/builtin-align.c (2529 of 27911)
******************** TEST 'Clang :: CodeGen/builtin-align.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple=x86_64-unknown-unknown -DTEST_VOID_PTR    -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -check-prefixes CHECK,CHECK-VOID_PTR    -enable-var-scope '-D$PTRTYPE=i8'
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple=x86_64-unknown-unknown -DTEST_VOID_PTR -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-unknown"
# | 
# | @aligned_true = global i8 1, align 1
# | @aligned_false = global i8 0, align 1
# | @down_1 = global i32 992, align 4
# | @down_2 = global i32 256, align 4
# | @up_1 = global i32 1024, align 4
# | @up_2 = global i32 256, align 4
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local ptr @get_type() #0 {
# | entry:
# |   ret ptr null
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local zeroext i1 @is_aligned(ptr noundef %ptr, i32 noundef %align) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %align.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %align, ptr %align.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %align.addr, align 4
# |   %alignment = zext i32 %1 to i64
# |   %mask = sub i64 %alignment, 1
# |   %src_addr = ptrtoint ptr %0 to i64
# |   %set_bits = and i64 %src_addr, %mask
# |   %is_aligned = icmp eq i64 %set_bits, 0
# |   ret i1 %is_aligned
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local ptr @align_up(ptr noundef %ptr, i32 noundef %align) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %align.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %align, ptr %align.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %align.addr, align 4
# |   %alignment = zext i32 %1 to i64
# |   %mask = sub i64 %alignment, 1
# |   %over_boundary = getelementptr inbounds i8, ptr %0, i64 %mask
# |   %inverted_mask = xor i64 %mask, -1
# |   %aligned_result = call ptr @llvm.ptrmask.p0.i64(ptr %over_boundary, i64 %inverted_mask)
# |   ret ptr %aligned_result
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare ptr @llvm.ptrmask.p0.i64(ptr, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local ptr @align_down(ptr noundef %ptr, i32 noundef %align) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %align.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %align, ptr %align.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %align.addr, align 4
# |   %alignment = zext i32 %1 to i64
# |   %mask = sub i64 %alignment, 1
# |   %inverted_mask = xor i64 %mask, -1
# |   %aligned_result = call ptr @llvm.ptrmask.p0.i64(ptr %0, i64 %inverted_mask)
# |   ret ptr %aligned_result
# | }
# | 
# | attributes #0 = { noinline nounwind "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x00005574552adeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005574552aae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005574552ae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f64ee649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f64ee6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f64ee649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f64ee631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557455243bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557455243a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005574552288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557454ed7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557454ed7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f64ee632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f64ee6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f64ee6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557454ed7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -check-prefixes CHECK,CHECK-VOID_PTR -enable-var-scope '-D$PTRTYPE=i8'
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -check-prefixes CHECK,CHECK-VOID_PTR -enable-var-scope -D$PTRTYPE=i8
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c (2530 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557db80b8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557db80b5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557db80b962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c8e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c8e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c8e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c8e231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557db804ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557db804ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557db80338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557db7ce2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557db7ce2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1c8e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c8e2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c8e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557db7ce2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c (2531 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_i64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_u64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_i64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_u64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("
# | ...
# `---data was truncated (10240/18506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cbeda0deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cbeda0ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cbeda0e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca8db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca8db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca8db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca8db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cbed9a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cbed9a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cbed9888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cbed637e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cbed637b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fca8db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca8db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca8db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cbed637a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c (2532 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmflt_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmflt_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmflt_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 32 x bflo
# | ...
# `---data was truncated (10240/27786) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056084ae2beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056084ae28e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056084ae2c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec80849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec808a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec80849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec80831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056084adc1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056084adc1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056084ada68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056084aa55e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056084aa55b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fec80832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec808330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec808330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056084aa55a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c (2533 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_f64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_f64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_f64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_i64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_i64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_i64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_u64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8
# | ...
# `---data was truncated (10240/60809) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561eabcc2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561eabcbfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561eabcc362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f924d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f924d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f924d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f924d831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561eabc58bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561eabc58a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561eabc3d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561eab8ece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561eab8ecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f924d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f924d8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f924d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561eab8eca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c (2534 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16mf4(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1f16.p0.i64(<vscale x 1 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2f16.p0.i64(<vscale x 2 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16m1(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4f16.p0.i64(<vscale x 4 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16m2(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8f16.p0.i64(<vscale x 8 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16m4(ptr noundef %base, i64 noundef %bstride, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv16f16.p0.i64(<vscale x 16 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16m8(ptr noundef %base, i64 noundef %bstride, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv32f16.p0.i64(<vscale x 32 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_i16mf4(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i16.p0.i64(<vscale x 1 x i16> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_i16mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i16.p0.i64(<vscale x 2 x i16> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_i16m1(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i16.p0.i64(<vscale x 4 x i16> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_i16m2(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align
# | ...
# `---data was truncated (10240/39586) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556eefe92eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556eefe8fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556eefe9362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f95f4049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f95f40a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f95f4049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f95f4031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556eefe28bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556eefe28a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556eefe0d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556eefabce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556eefabcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f95f4032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f95f40330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f95f40330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556eefabca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c (2535 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ea11d5aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ea11d57e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ea11d5b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8547a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8547aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8547a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8547a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ea11cf0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ea11cf0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ea11cd58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ea11984e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ea11984b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8547a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8547a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8547a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ea11984a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-cde-gpr.c (2536 of 27911)
******************** TEST 'Clang :: CodeGen/arm-cde-gpr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi    -target-feature +cdecp0 -target-feature +cdecp1    -mfloat-abi hard -O0 -disable-O0-optnone    -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +cdecp1 -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_cx1() #0 {
# | entry:
# |   %0 = call i32 @llvm.arm.cde.cx1(i32 0, i32 123)
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.cde.cx1(i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_cx1a(i32 noundef %acc) #0 {
# | entry:
# |   %acc.addr = alloca i32, align 4
# |   store i32 %acc, ptr %acc.addr, align 4
# |   %0 = load i32, ptr %acc.addr, align 4
# |   %1 = call i32 @llvm.arm.cde.cx1a(i32 0, i32 %0, i32 345)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.cde.cx1a(i32 immarg, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_cx1d() #0 {
# | entry:
# |   %0 = call { i32, i32 } @llvm.arm.cde.cx1d(i32 1, i32 567)
# |   %1 = extractvalue { i32, i32 } %0, 1
# |   %2 = zext i32 %1 to i64
# |   %3 = shl i64 %2, 32
# |   %4 = extractvalue { i32, i32 } %0, 0
# |   %5 = zext i32 %4 to i64
# |   %6 = or i64 %3, %5
# |   ret i64 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.cde.cx1d(i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_cx1da(i64 noundef %acc) #0 {
# | entry:
# |   %acc.addr = alloca i64, align 8
# |   store i64 %acc, ptr %acc.addr, align 8
# |   %0 = load i64, ptr %acc.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = call { i32, i32 } @llvm.arm.cde.cx1da(i32 0, i32 %3, i32 %2, i32 789)
# |   %5 = extractvalue { i32, i32 } %4, 1
# |   %6 = zext i32 %5 to i64
# |   %7 = shl i64 %6, 32
# |   %8 = extractvalue { i32, i32 } %4, 0
# |   %9 = zext i32 %8 to i64
# |   %10 = or i64 %7, %9
# |   ret i64 %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.cde.cx1da(i32 immarg, i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_cx2(i32 noundef %n) #0 {
# | entry:
# |   %n.addr = alloca i32, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   %0 = load i32, ptr %n.addr, align 4
# |   %1 = call i32 @llvm.arm.cde.cx2(i32 0, i32 %0, i32 11)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.cde.cx2(i32 immarg, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_cx2a(i32 noundef %acc, i32 noundef %n) #0 {
# | entry:
# |   %acc.addr = alloca i32, align 4
# |   %n.addr = alloca i32, align 4
# |   store i32 %acc, ptr %acc.addr, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   %0 = load i32, ptr %acc.addr, align 4
# |   %1 = load i32, ptr %n.addr, align 4
# |   %2 = call i32 @llvm.arm.cde.cx2a(i32 1, i32 %0, i32 %1, i32 22)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.cde.cx2a(i32 immarg, i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_cx2d(i32 noundef %n) #0 {
# | entry:
# |   %n.addr = alloca i32, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   %0 = load i32, ptr %n.addr, align 4
# |   %1 = call { i32, i32 } @llvm.arm.cde.cx2d(i32 1, i32 %0, i32 33)
# |   %2 = extractvalue { i32, i32 } %1, 1
# |   %3 = zext i32 %2 to i64
# |   %4 = shl i64 %3, 32
# |   %5 = extractvalue { i32, i32 } %1, 0
# |   %6 = zext i32 %5 to i64
# |   %7 = or i64 %4, %6
# |   ret i64 %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.cde.cx2d(i32 immarg, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_cx2da(i64 noundef %acc, i32 noundef %n) #0 {
# | entry:
# |   %acc.addr = alloca i64, align 8
# |   %n.addr = alloca i32, align 4
# |   store i64 %acc, ptr %acc.addr, align 8
# |   store i32 %n, ptr %n.addr, align 4
# |   %0 = load i64, ptr %acc.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load i32, ptr %n.addr, align 4
# |   %5 = call { i32, i32 } @llvm.arm.cde.cx2da(i32 0, i32 %3, i32 %2, i32 %4, i32 44)
# |   %6 = extractvalue { i32, i32 } %5, 1
# |   %7 = zext i32 %6 to i64
# |   %8 = shl i64 %7, 32
# |   %9 = extractvalue { i32, i32 } %5, 0
# |   %10 = zext i32 %9 to i64
# |   %11 = or i64 %8, %10
# |   ret i64 %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.cde.cx2da(i32 immarg, i32, i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_cx3(i32 noundef %n, i32 noundef %m) #0 {
# | entry:
# |   %n.addr = alloca i32, align 4
# |   %m.addr = alloca i32, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   store i32 %m, ptr %m.addr, align 4
# |   %0 = load i32, ptr %n.addr, align 4
# |   %1 = load i32, ptr %m.addr, align 4
# |   %2 = call i32 @llvm.arm.cde.cx3(i32 0, i32 %0, i32 %1, i32 1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.cde.cx3(i32 immarg, i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_cx3a(i32 noundef %acc, i32 noundef %n, i32 noundef %m) #0 {
# | entry:
# |   %acc.addr = alloca i32, align 4
# |   %n.addr = alloca i32, align 4
# |   %m.addr = alloca i32, align 4
# |   store i32 %acc, ptr %acc.addr, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   store i32 %m, ptr %m.addr, align 4
# |   %0 = load i32, ptr %acc.addr, align 4
# |   %1 = load i32, ptr %n.addr, align 4
# |   %2 = load i32, ptr %m.addr, align 4
# |   %3 = call i32 @llvm.arm.cde.cx3a(i32 1, i32 %0, i32 %1, i32 %2, i32 2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.cde.cx3a(i32 immarg, i32, i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_cx3d(i32 noundef %n, i32 noundef %m) #0 {
# | entry:
# |   %n.addr = alloca i32, align 4
# |   %m.addr = alloca i32, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   store i32 %m, ptr %m.addr, align 4
# |   %0 = load i32, ptr %n.addr, align 4
# |   %1 = load i32, ptr %m.addr, align 4
# |   %2 = call { i32, i32 } @llvm.arm.cde.cx3d(i32 1, i32 %0, i32 %1, i32 3)
# |   %3 = extractvalue { i32, i32 } %2, 1
# |   %4 = zext i32 %3 to i64
# |   %5 = shl i64 %4, 32
# |   %6 = extractvalue { i32, i32 } %2, 0
# |   %7 = zext i32 %6 to i64
# |   %8 = or i64 %5, %7
# |   ret i64 %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.cde.cx3d(i32 immarg, i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_cx3da(i64 noundef %acc, i32 noundef %n, i32 noundef %m) #0 {
# | entry:
# |   %acc.addr = alloca i64, align 8
# |   %n.addr = alloca i32, align 4
# |   %m.addr = alloca i32, align 4
# |   store i64 %acc, ptr %acc.addr, align 8
# |   store i32 %n, ptr %n.addr, align 4
# |   store i32 %m, ptr %m.addr, align 4
# |   %0 = load i64, ptr %acc.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load i32, ptr %n.addr, align 4
# |   %5 = load i32, ptr %m.addr, align 4
# |   %6 = call { i32, i32 } @llvm.arm.cde.cx3da(i32 0, i32 %3, i32 %2, i32 %4, i32 %5, i32 4)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.cde.cx3da(i32 immarg, i32, i32, i32, i32, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+cdecp0,+cdecp1,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560958b59eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560958b56e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560958b5a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4188533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f418858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4188533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f418851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560958aefbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560958aefa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560958ad48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560958783e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560958783b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f418851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f418851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f418851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560958783a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c (2537 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005596325abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005596325a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005596325ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f46ed049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f46ed0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f46ed049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f46ed031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559632541bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559632541a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005596325268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005596321d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005596321d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f46ed032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f46ed0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f46ed0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005596321d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c (2538 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclipu_wv_u8mf8(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclipu_wx_u8mf8(<vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclipu_wv_u8mf4(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclipu_wx_u8mf4(<vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclipu_wv_u8mf2(<vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclipu_wx_u8mf2(<vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclipu_wv_u8m1(<vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclipu_wx_u8m1(<vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclipu_wv_u8m2(<vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclipu_wx_u8m2(<vscale x 16 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x 
# | ...
# `---data was truncated (10240/70013) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c16257beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c162578e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c16257c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f583eb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f583eb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f583eb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f583eaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c162511bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c162511a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c1624f68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c1621a5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c1621a5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f583eaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f583eaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f583eaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c1621a5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c (2539 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4(<vscale x 16 x half> %
# | ...
# `---data was truncated (10240/149145) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005650ed6d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005650ed6d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005650ed6d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0787449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f07874a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0787449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0787431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005650ed66bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005650ed66ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005650ed6508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005650ed2ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005650ed2ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0787432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f07874330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f07874330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005650ed2ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c (2540 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste32_f32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.sf.vste32.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste32_i32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste32_u32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564d93744eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564d93741e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564d9374562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb1ed533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb1ed58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb1ed533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb1ed51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d936dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564d936daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564d936bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564d9336ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564d9336eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb1ed51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb1ed51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb1ed51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d9336ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/dup.c (2541 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/dup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vdupq_n_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   %.splatinsert = insertelement <8 x half> poison, half %0, i64 0
# |   %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
# |   ret <8 x half> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vdupq_n_f32(float noundef %a) #0 {
# | entry:
# |   %a.addr = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   %0 = load float, ptr %a.addr, align 4
# |   %.splatinsert = insertelement <4 x float> poison, float %0, i64 0
# |   %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer
# |   ret <4 x float> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdupq_n_s8(i8 noundef signext %a) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   store i8 %a, ptr %a.addr, align 1
# |   %0 = load i8, ptr %a.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %0, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   ret <16 x i8> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdupq_n_s16(i16 noundef signext %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %0, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   ret <8 x i16> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vdupq_n_s32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %0, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   ret <4 x i32> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdupq_n_u8(i8 noundef zeroext %a) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   store i8 %a, ptr %a.addr, align 1
# |   %0 = load i8, ptr %a.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %0, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   ret <16 x i8> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdupq_n_u16(i16 noundef zeroext %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %0, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   ret <8 x i16> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vdupq_n_u32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %0, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   ret <4 x i32> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vdupq_m_n_f16(<8 x half> noundef %inactive, half noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca half, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store half %a, ptr %a.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load half, ptr %a.addr, align 2
# |   %.splatinsert = insertelement <8 x half> poison, half %3, i64 0
# |   %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
# |   %4 = load <8 x half>, ptr %inactive.addr, align 8
# |   %5 = select <8 x i1> %2, <8 x half> %.splat, <8 x half> %4
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vdupq_m_n_f32(<4 x float> noundef %inactive, float noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca float, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store float %a, ptr %a.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load float, ptr %a.addr, align 4
# |   %.splatinsert = insertelement <4 x float> poison, float %3, i64 0
# |   %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer
# |   %4 = load <4 x float>, ptr %inactive.addr, align 8
# |   %5 = select <4 x i1> %2, <4 x float> %.splat, <4 x float> %4
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdupq_m_n_s8(<16 x i8> noundef %inactive, i8 noundef signext %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)
# |   %3 = load i8, ptr %a.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %3, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = select <16 x i1> %2, <16 x i8> %.splat, <16 x i8> %4
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdupq_m_n_s16(<8 x i16> noundef %inactive, i16 noundef signext %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load i16, ptr %a.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %3, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = select <8 x i1> %2, <8 x i16> %.splat, <8 x i16> %4
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vdupq_m_n_s32(<4 x i32> noundef %inactive, i32 noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load i32, ptr %a.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %3, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = select <4 x i1> %2, <4 x i32> %.splat, <4 x i32> %4
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdupq_m_n_u8(<16 x i8> noundef %inactive, i8 noundef zeroext %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)
# |   %3 = load i8, ptr %a.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %3, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = select <16 x i1> %2, <16 x i8> %.splat, <16 x i8> %4
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdupq_m_n_u16(<8 x i16> noundef %inactive, i16 noundef zeroext %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load i16, ptr %a.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %3, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = select <8 x i1> %2,
# | ...
# `---data was truncated (10240/17297) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>'
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<>
# |  #0 0x0000556d6bf8beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556d6bf88e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556d6bf8c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f003ac1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f003ac725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f003ac1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f003ac03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556d6bf21bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556d6bf21a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556d6bf068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556d6bbb5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556d6bbb5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f003ac04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f003ac050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f003ac050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556d6bbb5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c (2542 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055700da85eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055700da82e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055700da8662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c35733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c3578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c35733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c3571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055700da1bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055700da1ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055700da008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055700d6afe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055700d6afb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7c3571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c3571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c3571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055700d6afa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c (2543 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8_v_i8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8_v_i8mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8_v_i8mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8_v_i8m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8_v_i8m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8_v_i8m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8_v_u8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8_v_u8mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# | 
# | ...
# `---data was truncated (10240/64349) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005642b47b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005642b47b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005642b47b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd721a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd721aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd721a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd721a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005642b4749bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005642b4749a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005642b472e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005642b43dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005642b43ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd721a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd721a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd721a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005642b43dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c (2544 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8ff_v_i8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8ff_v_i8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8ff_v_i8m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_u8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8ff_v_u8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8ff_v_u8mf2
# | ...
# `---data was truncated (10240/54694) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b62790aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b627907e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b62790b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f31c5733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f31c578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f31c5733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f31c571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b6278a0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b6278a0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b6278858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b627534e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b627534b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f31c571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31c571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31c571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b627534a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c (2545 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zve64x    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e8w1(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 3, i64 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtzero.t.i64(i64 immarg, i64, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e8w2(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 3, i64 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e8w4(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e16w1(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 4, i64 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e16w2(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 4, i64 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e16w4(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e32w1(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 5, i64 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e32w2(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 5, i64 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e64w1(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 6, i64 1)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056285d4c5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056285d4c2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056285d4c662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7da5f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7da5f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7da5f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7da5f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056285d45bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056285d45ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056285d4408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056285d0efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056285d0efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7da5f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7da5f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7da5f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056285d0efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c (2546 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f16m1x6(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f32m1x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f64m1x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei16_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055882b59eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055882b59be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055882b59f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8cd0b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8cd0b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8cd0b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8cd0b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055882b534bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055882b534a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055882b5198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055882b1c8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055882b1c8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8cd0b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8cd0b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8cd0b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055882b1c8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c (2547 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055887b897eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055887b894e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055887b89862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8cb6933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8cb698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8cb6933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8cb691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055887b82dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055887b82da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055887b8128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055887b4c1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055887b4c1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8cb691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8cb691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8cb691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055887b4c1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c (2548 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zve64x    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e8w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.sf.vsettnt.i64(i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e8w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e8w4(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e16w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e16w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e16w4(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e32w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 2, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e32w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 2, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e64w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 3, i64 1)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d73490deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d73490ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d73490e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7aa6a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7aa6aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7aa6a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7aa6a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d7348a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d7348a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d7348888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d734537e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d734537b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7aa6a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7aa6a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7aa6a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d734537a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c (2549 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsll_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsll_vx_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsll_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsll_vx_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsll_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsll_vx_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsll_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsll_vx_i8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsll_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsll_vx_i8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsll_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/176543) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005571a1804eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005571a1801e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005571a180562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f63c2e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f63c2e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f63c2e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f63c2e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005571a179abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005571a179aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005571a177f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005571a142ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005571a142eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f63c2e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f63c2e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f63c2e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005571a142ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c (2550 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_i32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_i32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_u32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_u32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_f32mf2x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedof
# | ...
# `---data was truncated (10240/40734) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560b904baeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560b904b7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560b904bb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc55849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc558a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc55849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc55831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b90450bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560b90450a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560b904358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560b900e4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560b900e4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efc55832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc558330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc558330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b900e4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGenCXX/attr-musttail.cpp (2551 of 27911)
******************** TEST 'Clang :: CodeGenCXX/attr-musttail.cpp' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fno-elide-constructors -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp -triple x86_64-unknown-linux-gnu -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fno-elide-constructors -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp -triple x86_64-unknown-linux-gnu -o -
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fno-elide-constructors -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp -triple x86_64-unknown-linux-gnu -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=verify
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fno-elide-constructors -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp -triple x86_64-unknown-linux-gnu -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | %class.Foo = type { i8 }
# | %class.HasTrivialDestructor = type { i8 }
# | %struct.Data = type { ptr }
# | %struct.HasNonTrivialCopyConstructor = type { i8 }
# | %struct.HasNonTrivialCopyConstructor2 = type { i8 }
# | %struct.LargeWithCopyConstructor = type { [32 x i8] }
# | %class.anon = type { i8 }
# | 
# | $_Z12TemplateFuncIiET_S0_ = comdat any
# | 
# | $_Z6Func10IiEii = comdat any
# | 
# | $_Z6Func12IiET_S0_ = comdat any
# | 
# | @pmf = global { i64, i64 } zeroinitializer, align 8
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z5Func1i(i32 noundef %x) #0 {
# | entry:
# |   %retval = alloca i32, align 4
# |   %x.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %tobool = icmp ne i32 %0, 0
# |   br i1 %tobool, label %if.then, label %if.else
# | 
# | if.then:                                          ; preds = %entry
# |   %1 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 @_Z3Bari(i32 noundef %1)
# |   ret i32 %call
# | 
# | 2:                                                ; No predecessors!
# |   store i32 undef, ptr %retval, align 4
# |   br label %return
# | 
# | if.else:                                          ; preds = %entry
# |   %3 = load i32, ptr %x.addr, align 4
# |   %call1 = musttail call noundef i32 @_Z3Bazi(i32 noundef %3)
# |   ret i32 %call1
# | 
# | 4:                                                ; No predecessors!
# |   store i32 undef, ptr %retval, align 4
# |   br label %return
# | 
# | return:                                           ; preds = %4, %2
# |   %5 = load i32, ptr %retval, align 4
# |   ret i32 %5
# | }
# | 
# | declare noundef i32 @_Z3Bari(i32 noundef) #1
# | 
# | declare noundef i32 @_Z3Bazi(i32 noundef) #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z5Func2i(i32 noundef %x) #0 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = call noundef i32 @_Z3Bari(i32 noundef %0)
# |   %call1 = musttail call noundef i32 @_Z3Bari(i32 noundef %call)
# |   ret i32 %call1
# | 
# | 1:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_ZN3Foo8TailFromEi(ptr noundef nonnull align 1 dereferenceable(1) %this, i32 noundef %x) #0 align 2 {
# | entry:
# |   %this.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   store ptr %this, ptr %this.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   %this1 = load ptr, ptr %this.addr, align 8
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 @_ZN3Foo14MemberFunctionEi(ptr noundef nonnull align 1 dereferenceable(1) %this1, i32 noundef %0)
# |   ret i32 %call
# | 
# | 1:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | declare noundef i32 @_ZN3Foo14MemberFunctionEi(ptr noundef nonnull align 1 dereferenceable(1), i32 noundef) #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z5Func3i(i32 noundef %x) #0 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 @_ZN3Foo12StaticMethodEi(i32 noundef %0)
# |   ret i32 %call
# | 
# | 1:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | declare noundef i32 @_ZN3Foo12StaticMethodEi(i32 noundef) #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z5Func4i(i32 noundef %x) #0 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   %foo = alloca %class.Foo, align 1
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 @_ZN3Foo12StaticMethodEi(i32 noundef %0)
# |   ret i32 %call
# | 
# | 1:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_ZN3Foo9TailFrom2Ei(ptr noundef nonnull align 1 dereferenceable(1) %this, i32 noundef %x) #0 align 2 {
# | entry:
# |   %this.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   store ptr %this, ptr %this.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   %this1 = load ptr, ptr %this.addr, align 8
# |   %0 = load { i64, i64 }, ptr @pmf, align 8
# |   %memptr.adj = extractvalue { i64, i64 } %0, 1
# |   %1 = getelementptr inbounds i8, ptr %this1, i64 %memptr.adj
# |   %memptr.ptr = extractvalue { i64, i64 } %0, 0
# |   %2 = and i64 %memptr.ptr, 1
# |   %memptr.isvirtual = icmp ne i64 %2, 0
# |   br i1 %memptr.isvirtual, label %memptr.virtual, label %memptr.nonvirtual
# | 
# | memptr.virtual:                                   ; preds = %entry
# |   %vtable = load ptr, ptr %1, align 8
# |   %3 = sub i64 %memptr.ptr, 1
# |   %4 = getelementptr i8, ptr %vtable, i64 %3, !nosanitize !1
# |   %memptr.virtualfn = load ptr, ptr %4, align 8, !nosanitize !1
# |   br label %memptr.end
# | 
# | memptr.nonvirtual:                                ; preds = %entry
# |   %memptr.nonvirtualfn = inttoptr i64 %memptr.ptr to ptr
# |   br label %memptr.end
# | 
# | memptr.end:                                       ; preds = %memptr.nonvirtual, %memptr.virtual
# |   %5 = phi ptr [ %memptr.virtualfn, %memptr.virtual ], [ %memptr.nonvirtualfn, %memptr.nonvirtual ]
# |   %6 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 %5(ptr noundef nonnull align 1 dereferenceable(1) %1, i32 noundef %6)
# |   ret i32 %call
# | 
# | 7:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_ZN3Foo9TailFrom3Ei(ptr noundef nonnull align 1 dereferenceable(1) %this, i32 noundef %x) #0 align 2 {
# | entry:
# |   %this.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   store ptr %this, ptr %this.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   %this1 = load ptr, ptr %this.addr, align 8
# |   %0 = load { i64, i64 }, ptr @pmf, align 8
# |   %memptr.adj = extractvalue { i64, i64 } %0, 1
# |   %1 = getelementptr inbounds i8, ptr %this1, i64 %memptr.adj
# |   %memptr.ptr = extractvalue { i64, i64 } %0, 0
# |   %2 = and i64 %memptr.ptr, 1
# |   %memptr.isvirtual = icmp ne i64 %2, 0
# |   br i1 %memptr.isvirtual, label %memptr.virtual, label %memptr.nonvirtual
# | 
# | memptr.virtual:                                   ; preds = %entry
# |   %vtable = load ptr, ptr %1, align 8
# |   %3 = sub i64 %memptr.ptr, 1
# |   %4 = getelementptr i8, ptr %vtable, i64 %3, !nosanitize !1
# |   %memptr.virtualfn = load ptr, ptr %4, align 8, !nosanitize !1
# |   br label %memptr.end
# | 
# | memptr.nonvirtual:                                ; preds = %entry
# |   %memptr.nonvirtualfn = inttoptr i64 %memptr.ptr to ptr
# |   br label %memptr.end
# | 
# | memptr.end:                                       ; preds = %memptr.nonvirtual, %memptr.virtual
# |   %5 = phi ptr [ %memptr.virtualfn, %memptr.virtual ], [ %memptr.nonvirtualfn, %memptr.nonvirtual ]
# |   %6 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 %5(ptr noundef nonnull align 1 dereferenceable(1) %1, i32 noundef %6)
# |   ret i32 %call
# | 
# | 7:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local void @_Z5Func5v() #0 {
# | entry:
# |   musttail call void @_Z11ReturnsVoidv()
# |   ret void
# | 
# | 0:                                                ; No predecessors!
# |   ret void
# | }
# | 
# | declare void @_Z11ReturnsVoidv() #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z5Func6i(i32 noundef %x) #0 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   %foo = alloca %class.HasTrivialDestructor, align 1
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 @_Z10ReturnsInti(i32 noundef %0)
# |   ret i32 %call
# | 
# | 1:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | declare noundef i32 @_Z10ReturnsInti(i32 noundef) #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z5Func7P4Data(ptr noundef %data) #0 {
# | entry:
# |   %data.addr = alloca ptr, align 8
# |   store ptr %data, ptr %data.addr, align 8
# |   %0 = load ptr, ptr %data.addr, align 8
# |   %fptr = getelementptr inbounds nuw %struct.Data, ptr %0, i32 0, i32 0
# |   %1 = load ptr, ptr %fptr, align 8
# |   %2 = load ptr, ptr %data.addr, align 8
# |   %call = musttail call noundef i32 %1(ptr noundef %2)
# |   ret i32 %call
# | 
# | 3:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z5Func9i(i32 noundef %x) #0 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 @_Z12TemplateFuncIiET_S0_(i32 noundef %0)
# |   ret i32 %call
# | 
# | 1:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define linkonce_odr noundef i32 @_Z12TemplateFuncIiET_S0_(i32 noundef %0) #0 comdat {
# | entry:
# |   %.addr = alloca i32, align 4
# |   store i32 %0, ptr %.addr, align 4
# |   ret i32 5
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z6Func11i(i32 noundef %x) #0 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = call noundef i32 @_Z6Func10IiEii(i32 noundef %0)
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define linkonce_odr noundef i32 @_Z6Func10IiEii(i32 noundef %x) #0 comdat {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   %t = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 @_Z3Bari(i32 noundef %0)
# |   ret i32 %call
# | 
# | 1:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z6Func13i(i32 noundef %x) #0 {
# | entry:
# |   %x.ad
# | ...
# `---data was truncated (10240/18685) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=verify
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=verify
# |  #0 0x0000560b7ea1deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560b7ea1ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560b7ea1e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc286b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc286b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc286b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc286b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b7e9b3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560b7e9b3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560b7e9988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560b7e647e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560b7e647b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc286b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc286b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc286b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b7e647a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqdmulltq.c (2552 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqdmulltq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1)
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_m_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_m_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <2 x i64>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <2 x i64> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3)
# |   %5 = load <2 x i64>, ptr %inactive.addr, align 8
# |   %6 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %1, i32 1, <2 x i1> %4, <2 x i64> %5)
# |   ret <2 x i64> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32>, <4 x i32>, i32, <2 x i1>, <2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %.splat, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %.splat, i32 1)
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_m_n_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %.splat, i32 1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_m_n_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <2 x i64>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store <2 x i64> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3)
# |   %5 = load <2 x i64>, ptr %inactive.addr, align 8
# |   %6 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %.splat, i32 1, <2 x i1> %4, <2 x i64> %5)
# |   ret <2 x i64> %6
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005556786fbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005556786f8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005556786fc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe69ce1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe69ce725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe69ce1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe69ce03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555678691bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555678691a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005556786768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555678325e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555678325b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe69ce04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe69ce050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe69ce050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555678325a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c (2553 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f16m1x6(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f32m1x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f64m1x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005606ca733eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005606ca730e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005606ca73462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe8cf649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe8cf6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe8cf649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe8cf631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005606ca6c9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005606ca6c9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005606ca6ae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005606ca35de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005606ca35db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe8cf632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe8cf6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe8cf6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005606ca35da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c (2554 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558e718ddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558e718dae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558e718de62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7406d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7406d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7406d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7406d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558e71873bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558e71873a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558e718588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558e71507e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558e71507b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7406d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7406d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7406d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558e71507a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c (2555 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_x_f_v_i16mf4(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_x_f_v_i16mf2(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_x_f_v_i16m1(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_x_f_v_i16m2(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_x_f_v_i16m4(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_x_f_v_i16m8(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_xu_f_v_u16mf4(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_xu_f_v_u16mf2(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_xu_f_v_u16m1(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_xu_f_v_u16m2(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_xu_f_v_u16m4(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_xu_f_v_u16m8(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwi
# | ...
# `---data was truncated (10240/205813) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555bd2f46eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555bd2f43e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555bd2f4762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e51a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e51aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e51a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e51a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555bd2edcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555bd2edca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555bd2ec18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555bd2b70e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555bd2b70b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0e51a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e51a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e51a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555bd2b70a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c (2556 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_u64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_u64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <v
# | ...
# `---data was truncated (10240/16552) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005584500a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055845009fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005584500a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f045d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f045d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f045d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f045d831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558450038bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558450038a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055845001d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055844fccce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055844fcccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f045d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f045d8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f045d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055844fccca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c (2557 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a16f  -target-feature +xsfmm32a32f -target-feature +xsfmm64a64f  -target-feature +zvfhmin -target-feature +zve64d -disable-O0-optnone  -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a16f -target-feature +xsfmm32a32f -target-feature +xsfmm64a64f -target-feature +zvfhmin -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_mm_f_f_w2_f16m8(<vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 0, <vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2, i64 %3, i64 %4, i64 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 immarg, <vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_mm_f_f_w1_f32m8(<vscale x 16 x float> %vs2, <vscale x 16 x float> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vs1.addr = alloca <vscale x 16 x float>, align 4
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 16 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 0, <vscale x 16 x float> %0, <vscale x 16 x float> %1, i64 %2, i64 %3, i64 %4, i64 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 immarg, <vscale x 16 x float>, <vscale x 16 x float>, i64, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_mm_f_f_w1_f64m8(<vscale x 8 x double> %vs2, <vscale x 8 x double> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vs1.addr = alloca <vscale x 8 x double>, align 8
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x double> %vs1, ptr %vs1.addr, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 8 x double>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.f.f.i64.nxv8f64(i64 0, <vscale x 8 x double> %0, <vscale x 8 x double> %1, i64 %2, i64 %3, i64 %4, i64 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.f.f.i64.nxv8f64(i64 immarg, <vscale x 8 x double>, <vscale x 8 x double>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+xsfmm32a16f,+xsfmm32a32f,+xsfmm64a64f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvl32b1p0_zvl64b1p0_xsfmm32a16f0p6_xsfmm32a32f0p6_xsfmm64a64f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cc44cd5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cc44cd2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cc44cd662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efebcf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efebcf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efebcf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efebcf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc44c6bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cc44c6ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cc44c508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cc448ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cc448ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efebcf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efebcf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efebcf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc448ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c (2558 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_f64m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_i64m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_u64m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564c3e7b6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564c3e7b3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564c3e7b762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f07aeb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f07aeb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f07aeb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f07aeb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c3e74cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564c3e74ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564c3e7318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564c3e3e0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564c3e3e0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f07aeb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f07aeb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f07aeb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c3e3e0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c (2559 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_bf16m1x
# | ...
# `---data was truncated (10240/25695) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d3703bfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d3703bce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d3703c062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f57d2449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57d24a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f57d2449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f57d2431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d370355bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d370355a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d37033a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d36ffe9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d36ffe9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f57d2432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57d24330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57d24330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d36ffe9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c (2560 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16mf4(ptr noundef %base, <vscale x 1 x i16> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16mf2(ptr noundef %base, <vscale x 2 x i16> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16m1(ptr noundef %base, <vscale x 4 x i16> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16m2(ptr noundef %base, <vscale x 8 x i16> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16m4(ptr noundef %base, <vscale x 16 x i16> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16m8(ptr noundef %base, <vscale x 32 x i16> %bindex, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> %2, ptr %0, <vscale x 32 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f32mf2(ptr noundef %base, <vscale x 1 x i16> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f32m1(ptr noundef %base, <vscale x 2 x i16> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f32m2(ptr noundef %base, <vscale x 4 x i16> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   
# | ...
# `---data was truncated (10240/132462) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de140b4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055de140b1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055de140b562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc36849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc368a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc36849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc36831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de1404abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055de1404aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055de1402f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055de13cdee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055de13cdeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcc36832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc368330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc368330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de13cdea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c (2561 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_2x8x2_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_2x8x2_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_2x8x2_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_2x8x2_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555584ee6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555584ee3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555584ee762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca07f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca07f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca07f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca07f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555584e7cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555584e7ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555584e618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555584b10e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555584b10b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fca07f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca07f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca07f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555584b10a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcvt_anpm.c (2562 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcvt_anpm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_s16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcvta.v8i16.v8f16(i32 0, <8 x half> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcvta.v8i16.v8f16(i32, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtaq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcvta.v4i32.v4f32(i32 0, <4 x float> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcvta.v4i32.v4f32(i32, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_u16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcvta.v8i16.v8f16(i32 1, <8 x half> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtaq_u32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcvta.v4i32.v4f32(i32 1, <4 x float> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtmq_s16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcvtm.v8i16.v8f16(i32 0, <8 x half> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcvtm.v8i16.v8f16(i32, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtmq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcvtm.v4i32.v4f32(i32 0, <4 x float> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcvtm.v4i32.v4f32(i32, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtmq_u16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcvtm.v8i16.v8f16(i32 1, <8 x half> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtmq_u32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcvtm.v4i32.v4f32(i32 1, <4 x float> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtnq_s16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcvtn.v8i16.v8f16(i32 0, <8 x half> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcvtn.v8i16.v8f16(i32, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtnq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcvtn.v4i32.v4f32(i32 0, <4 x float> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcvtn.v4i32.v4f32(i32, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtnq_u16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcvtn.v8i16.v8f16(i32 1, <8 x half> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtnq_u32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcvtn.v4i32.v4f32(i32 1, <4 x float> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtpq_s16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcvtp.v8i16.v8f16(i32 0, <8 x half> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcvtp.v8i16.v8f16(i32, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtpq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcvtp.v4i32.v4f32(i32 0, <4 x float> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcvtp.v4i32.v4f32(i32, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtpq_u16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcvtp.v8i16.v8f16(i32 1, <8 x half> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtpq_u32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcvtp.v4i32.v4f32(i32 1, <4 x float> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_m_s16_f16(<8 x i16> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %1 = load <8 x half>, ptr %a.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vcvta.predicated.v8i16.v8f16.v8i1(i32 0, <8 x i16> %0, <8 x half> %1, <8 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcvta.predicated.v8i16.v8f16.v8i1(i32, <8 x i16>, <8 x half>, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtaq_m_s32_f32(<4 x i32> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x float>, ptr %a.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.vcvta.predicated.v4i32.v4f32.v4i1(i32 0, <4 x i32> %0, <4 x float> %1, <4 x i1> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcvta.predicated.v4i32.v4f32.v4i1(i32, <4 x i32>, <4 x float>, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_m_u16_f16(<8 x i16> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %1 = load <8 x half>, ptr %a.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(
# | ...
# `---data was truncated (10240/32505) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed1f346eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ed1f343e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ed1f34762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc4e5933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc4e598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc4e5933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc4e591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed1f2dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ed1f2dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ed1f2c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ed1ef70e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ed1ef70b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc4e591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc4e591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc4e591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed1ef70a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c (2563 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlsseg3e8_v_i8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e8_v_i8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e8_v_i8mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e8_v_i8m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e8_v_i8m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlsseg3e8_v_u8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e8_v_u8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.ris
# | ...
# `---data was truncated (10240/60220) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563ee4acfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563ee4acce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563ee4ad062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d95a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d95aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d95a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d95a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ee4a65bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563ee4a65a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563ee4a4a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563ee46f9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563ee46f9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1d95a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d95a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d95a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ee46f9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c (2564 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_f64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_f64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_i64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_i64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_u64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_u64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Functi
# | ...
# `---data was truncated (10240/15986) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bbc39e7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bbc39e4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bbc39e862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa81e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa81e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa81e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa81e91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bbc397dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bbc397da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bbc39628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bbc3611e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bbc3611b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa81e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa81e91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa81e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bbc3611a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c (2565 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_bf16mf4x4(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_bf16mf2x4(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_bf16m1x4(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_bf16m2x4(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ff979feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557ff979ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557ff97a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f81af61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f81af6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f81af61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f81af603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ff9735bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557ff9735a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557ff971a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557ff93c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557ff93c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f81af604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f81af6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f81af6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ff93c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c (2566 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555ad6fc6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555ad6fc3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555ad6fc762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0b0f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0b0f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0b0f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0b0f031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555ad6f5cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555ad6f5ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555ad6f418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555ad6bf0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555ad6bf0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0b0f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0b0f0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0b0f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555ad6bf0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c (2567 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_i64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_u64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_f64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_i64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_u64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple
# | ...
# `---data was truncated (10240/20903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f72aa9ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f72aa99e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f72aa9d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac0ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac0caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac0ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac0ca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f72aa32bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f72aa32a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f72aa178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f72a6c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f72a6c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fac0ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac0ca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac0ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f72a6c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c (2568 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfge
# | ...
# `---data was truncated (10240/18668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ae39ff2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ae39fefe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ae39ff362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff559333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff55938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff559333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff55931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ae39f88bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ae39f88a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ae39f6d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ae39c1ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ae39c1cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff55931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff55931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff55931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ae39c1ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c (2569 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei32_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b48da4ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b48da49e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b48da4d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f119af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f119af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f119af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f119af1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b48d9e2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b48d9e2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b48d9c78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b48d676e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b48d676b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f119af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f119af1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f119af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b48d676a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c (2570 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrsub_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrsub_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrsub_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrsub_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrsub_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrsub_vf_f16m8(<vscale x 32 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrsub_vf_f32mf2(<vscale x 1 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrsub_vf_f32m1(<vscale x 2 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrsub_vf_f32m2(<vscale x 4 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfrsub.nxv4f32.f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrsub.nxv4f32.f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrsub_vf_f32m4(<vscale x 8 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfrsub.nxv8f32.f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfrsub.nxv8f32.f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x 
# | ...
# `---data was truncated (10240/61066) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056359c097eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056359c094e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056359c09862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd292049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd2920a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd292049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd292031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056359c02dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056359c02da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056359c0128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056359bcc1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056359bcc1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd292032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd2920330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd2920330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056359bcc1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c (2571 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrev8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrev8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrev8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrev8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrev8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrev8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrev8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrev8_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrev8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrev8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrev8_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrev8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrev8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vrev8_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vrev8.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrev8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vrev8_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vrev8.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrev8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vrev8_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vrev8.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrev8.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vrev8_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vrev8.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrev8.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vrev8_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vrev8.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrev8.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define ds
# | ...
# `---data was truncated (10240/95215) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a7b8a52eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a7b8a4fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a7b8a5362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c49933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c4998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c49933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c4991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a7b89e8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a7b89e8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a7b89cd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a7b867ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a7b867cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1c4991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c4991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c4991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a7b867ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c (2572 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055afca765eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055afca762e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055afca76662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f72c0f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f72c0f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f72c0f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f72c0f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055afca6fbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055afca6fba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055afca6e08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055afca38fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055afca38fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f72c0f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f72c0f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f72c0f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055afca38fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c (2573 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmslt_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmslt_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmslt_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmslt_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmslt_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmslt_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmslt_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | 
# | ...
# `---data was truncated (10240/63571) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055655aaf3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055655aaf0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055655aaf462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2c18f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2c18f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2c18f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2c18f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055655aa89bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055655aa89a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055655aa6e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055655a71de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055655a71db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2c18f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2c18f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2c18f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055655a71da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c (2574 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpaire_vv_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vpaire.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpaire.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpaire_vv_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vpaire.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpaire.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpaire_vv_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vpaire.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vpaire.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vpaire_vv_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vpaire.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vpaire.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vpaire_vv_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vpaire.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vpaire.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vpaire_vv_bf16m8(<vscale x 32 x bfloat> %vs2, <vscale x 32 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vpaire.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vpaire.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpaire_vv_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vpaire.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpaire.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpaire_vv_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vpaire.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpaire.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpaire_vv_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.add
# | ...
# `---data was truncated (10240/15312) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563dda8baeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563dda8b7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563dda8bb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ede533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ede58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ede533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ede51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563dda850bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563dda850a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563dda8358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563dda4e4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563dda4e4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5ede51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ede51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ede51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563dda4e4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c (2575 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_f32mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_f32m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_f32m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_i32mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_i32m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_i32m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_u32mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_u32m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_u32m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_f32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | decl
# | ...
# `---data was truncated (10240/20497) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cf1e6a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cf1e6a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cf1e6a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5382f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5382f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5382f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5382f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf1e63dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cf1e63da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cf1e6228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cf1e2d1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cf1e2d1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5382f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5382f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5382f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf1e2d1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c (2576 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560b0ade1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560b0addee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560b0ade262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe22d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe22d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe22d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe22d11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b0ad77bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560b0ad77a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560b0ad5c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560b0aa0be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560b0aa0bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe22d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe22d11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe22d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b0aa0ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c (2577 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("risc
# | ...
# `---data was truncated (10240/21103) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ca1af9beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ca1af98e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ca1af9c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e4a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e4a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e4a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e4a231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ca1af31bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ca1af31a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ca1af168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ca1abc5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ca1abc5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0e4a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e4a2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e4a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ca1abc5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c (2578 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfwma -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vf_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vf_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vf_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vf_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x flo
# | ...
# `---data was truncated (10240/51759) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bff2ad4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bff2ad1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bff2ad562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6d8f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6d8f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6d8f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6d8f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bff2a6abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bff2a6aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bff2a4f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bff26fee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bff26feb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6d8f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6d8f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6d8f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bff26fea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c (2579 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjn_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjn_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjn_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjn_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjn_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjn_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjn_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjn_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bf
# | ...
# `---data was truncated (10240/65202) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556c9ee07eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556c9ee04e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556c9ee0862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f15933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f1598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f15933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f1591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556c9ed9dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556c9ed9da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556c9ed828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556c9ea31e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556c9ea31b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2f1591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f1591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f1591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556c9ea31a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c (2580 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4asu_vv_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4asu_vv_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 =
# | ...
# `---data was truncated (10240/26564) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555d24355eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555d24352e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555d2435662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd04333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd0438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd04333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd0431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555d242ebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555d242eba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555d242d08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555d23f7fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555d23f7fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbd0431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd0431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd0431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555d23f7fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c (2581 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdiv_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdiv_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdiv_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdiv_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdiv_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdiv_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdiv_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdiv_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdiv_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vdiv.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vdiv.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdiv_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vdiv.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vdiv.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vdiv_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/97647) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005578c9a53eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005578c9a50e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005578c9a5462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f202e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f202e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f202e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f202e231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005578c99e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005578c99e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005578c99ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005578c967de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005578c967db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f202e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f202e2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f202e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005578c967da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c (2582 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf4(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf2(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvt_rod_f_f_w_bf16m1(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvt_rod_f_f_w_bf16m2(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvt_rod_f_f_w_bf16m4(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvt_rod_f_f_w_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvt_rod_f_f_w_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvt_rod_f_f_w_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vs
# | ...
# `---data was truncated (10240/10886) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005575cb736eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005575cb733e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005575cb73762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f98b5049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f98b50a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f98b5049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f98b5031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005575cb6ccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005575cb6cca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005575cb6b18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005575cb360e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005575cb360b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f98b5032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f98b50330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f98b50330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005575cb360a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c (2583 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsqrt_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsqrt_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsqrt_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsqrt_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsqrt_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfsqrt_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfsqrt_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfsqrt_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfsqrt_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfsqrt_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfsqrt.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfsqrt.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfsqrt_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfsqrt.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfsqrt.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfsqrt_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfsqrt.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfsqrt.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local
# | ...
# `---data was truncated (10240/51412) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562565963eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562565960e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056256596462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdfbb905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdfbb95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdfbb905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdfbb8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005625658f9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005625658f9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005625658de8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056256558de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056256558db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdfbb8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdfbb8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdfbb8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056256558da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c (2584 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i8.nxv1i8.nxv1i8.i32(i32 3, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i8.nxv1i8.nxv1i8.i32(i32 immarg, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv2i8.nxv2i8.nxv2i8.i32(i32 3, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv2i8.nxv2i8.nxv2i8.i32(i32 immarg, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv4i8.nxv4i8.nxv4i8.i32(i32 3, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv4i8.nxv4i8.nxv4i8.i32(i32 immarg, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv8i8.nxv8i8.nxv8i8.i32(i32 3, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv8i8.nxv8i8.nxv8i8.i32(i32 immarg, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv16i8.nxv16i8.nxv16i8.i32(i32 3, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv16i8.nxv16i8.nxv16i8.i32(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u8m4(<vscale x 32 x i8> %vd, <vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 32 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 32 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv32i8.nxv32i8.nxv32i8.i32(i32 3, <vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv32i8.nxv32i8.nxv32i8.i32(i32 immarg, <vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u8m8(<vscale x 64 x i8> %vd, <vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 64 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 64 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv64i8.nxv64i8.nxv64i8.i32(i32 3, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv64i8.nxv64i8.nxv64i8.i32(i32 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, <vscale x 64 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i16.nxv1i16.nxv1i16.i32(i32 3, <vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i16.nxv1i16.nxv1i16.i32(i32 immarg, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv2i16.nxv2i16.nxv
# | ...
# `---data was truncated (10240/255166) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005591df4f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005591df4f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005591df4f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3a99b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3a99b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3a99b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3a99b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005591df48ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005591df48ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005591df4738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005591df122e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005591df122b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3a99b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3a99b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3a99b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005591df122a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c (2585 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1down_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1down_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1down_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfslide1down_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfslide1down_vf_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfslide1down_vf_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1down_vf_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %3 = load bfloat, ptr %value.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1down_vf_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale 
# | ...
# `---data was truncated (10240/32694) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de9d8d7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055de9d8d4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055de9d8d862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3a5b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3a5b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3a5b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3a5b431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de9d86dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055de9d86da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055de9d8528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055de9d501e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055de9d501b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3a5b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3a5b4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3a5b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de9d501a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-poly-add.c (2586 of 27911)
******************** TEST 'Clang :: CodeGen/arm-poly-add.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-arm-none-eabi    -target-feature +neon    -mfloat-abi hard  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa   | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-arm-none-eabi -target-feature +neon -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8.2a-arm-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i8> @test_vadd_p8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = xor <8 x i8> %2, %3
# |   store <8 x i8> %4, ptr %ref.tmp.i, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %5, ptr %__ret.i, align 8
# |   %6 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i16> @test_vadd_p16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = xor <8 x i8> %2, %3
# |   %5 = bitcast <8 x i8> %4 to <4 x i16>
# |   store <4 x i16> %5, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <1 x i64> @test_vadd_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = xor <8 x i8> %2, %3
# |   %5 = bitcast <8 x i8> %4 to <1 x i64>
# |   store <1 x i64> %5, ptr %ref.tmp.i, align 8
# |   %6 = load <1 x i64>, ptr %ref.tmp.i, align 8
# |   store <1 x i64> %6, ptr %__ret.i, align 8
# |   %7 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vaddq_p8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 8
# |   %__p1.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <16 x i8>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = xor <16 x i8> %2, %3
# |   store <16 x i8> %4, ptr %ref.tmp.i, align 8
# |   %5 = load <16 x i8>, ptr %ref.tmp.i, align 8
# |   store <16 x i8> %5, ptr %__ret.i, align 8
# |   %6 = load <16 x i8>, ptr %__ret.i, align 8
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vaddq_p16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 8
# |   %__p1.addr.i = alloca <8 x i16>, align 8
# |   %__ret.i = alloca <8 x i16>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = xor <16 x i8> %2, %3
# |   %5 = bitcast <16 x i8> %4 to <8 x i16>
# |   store <8 x i16> %5, ptr %ref.tmp.i, align 8
# |   %6 = load <8 x i16>, ptr %ref.tmp.i, align 8
# |   store <8 x i16> %6, ptr %__ret.i, align 8
# |   %7 = load <8 x i16>, ptr %__ret.i, align 8
# |   ret <8 x i16> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vaddq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 8
# |   %__p1.addr.i = alloca <2 x i64>, align 8
# |   %__ret.i = alloca <2 x i64>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <2 x i64>, align 8
# |   %b.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = load <2 x i64>, ptr %b.addr, align 8
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = xor <16 x i8> %2, %3
# |   %5 = bitcast <16 x i8> %4 to <2 x i64>
# |   store <2 x i64> %5, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x i64>, ptr %ref.tmp.i, align 8
# |   store <2 x i64> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x i64>, ptr %__ret.i, align 8
# |   ret <2 x i64> %7
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.2-a,+neon,+v8.1a,+v8.2a,-thumb-mode" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055b994913eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b994910e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b99491462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f64af133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f64af18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f64af133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f64af11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b9948a9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b9948a9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b99488e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b99453de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b99453db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f64af11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f64af11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f64af11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b99453da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c (2587 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cd94610eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cd9460de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cd9461162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7912d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7912d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7912d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7912d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cd945a6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cd945a6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cd9458b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cd9423ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cd9423ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7912d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7912d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7912d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cd9423aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c (2588 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f16m1x4(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_f16m2x4(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f32m1x4(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_f32m2x4(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f64m1x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captu
# | ...
# `---data was truncated (10240/87308) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005610bdbc9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005610bdbc6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005610bdbca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8803449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f88034a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8803449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8803431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005610bdb5fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005610bdb5fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005610bdb448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005610bd7f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005610bd7f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8803432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f88034330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f88034330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005610bd7f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c (2589 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf8_u8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf4_u8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf2_u8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m1_u8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m2_u8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m4_u8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m8_u8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmaxu_vs_u16mf4_u16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmaxu_vs_u16mf2_u16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmaxu_vs_u16m1_u16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %sc
# | ...
# `---data was truncated (10240/52741) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557940715eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557940712e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055794071662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9b00133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9b0018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9b00133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9b0011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005579406abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005579406aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005579406908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055794033fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055794033fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9b0011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9b0011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9b0011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055794033fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c (2590 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16mf2_f16mf4(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv2f16(<vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv2f16(<vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16m1_f16mf4(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv4f16(<vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv4f16(<vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_trunc_v_f16m1_f16mf2(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv4f16(<vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv4f16(<vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16m2_f16mf4(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv8f16(<vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_trunc_v_f16m2_f16mf2(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_trunc_v_f16m2_f16m1(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16m4_f16mf4(<vscale x 16 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_trunc_v_f16m4_f16mf2(<vscale x 16 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_trunc_v_f16m4_f16m1(<vscale x 16 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_trunc_v_f16m4_f16m2(<vscale x 16 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16m8_f16mf4(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_trunc_v_f16m8_f16mf2(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_trunc_v_f16m8_f16m1(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_trunc_v_f16m8_f16m2(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_trunc_v_f16m8_f16m4(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | ...
# `---data was truncated (10240/78234) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b5b8c31eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b5b8c2ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b5b8c3262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f821f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f821f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f821f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f821f831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b5b8bc7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b5b8bc7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b5b8bac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b5b885be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b5b885bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f821f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f821f8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f821f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b5b885ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c (2591 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_f32mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_f32m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_f32m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_i32mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_i32m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_i32m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_u32mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_u32m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_u32m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_f32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void
# | ...
# `---data was truncated (10240/20489) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556beb64aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556beb647e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556beb64b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3058249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f30582a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3058249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3058231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556beb5e0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556beb5e0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556beb5c58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556beb274e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556beb274b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3058232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f30582330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f30582330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556beb274a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c (2592 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f0ad672eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f0ad66fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f0ad67362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3fc7b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3fc7b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3fc7b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3fc7b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f0ad608bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f0ad608a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f0ad5ed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f0ad29ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f0ad29cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3fc7b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3fc7b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3fc7b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f0ad29ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c (2593 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredor_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredor_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredor_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align
# | ...
# `---data was truncated (10240/94149) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b0516eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b0516ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b0516ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f80c5933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f80c598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f80c5933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f80c591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b051684bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b051684a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b0516698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b051318e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b051318b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f80c591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f80c591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f80c591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b051318a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c (2594 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055633008deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055633008ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055633008e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbabcd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbabcd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbabcd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbabcced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556330023bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556330023a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005563300088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055632fcb7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055632fcb7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbabcceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbabccef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbabccef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055632fcb7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c (2595 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccu_vv_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccu_vx_u16mf4_tu(<vscale x 1 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccu_vv_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccu_vx_u16mf2_tu(<vscale x 2 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccu_vv_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccu_vx_u16m1_tu(<vscale x 4 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccu_vv_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccu_vx_u16m2_tu(<vscale x 8 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccu_vv_u16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i
# | ...
# `---data was truncated (10240/150943) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557d638a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557d6389fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557d638a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa87d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa87d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa87d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa87d631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557d63838bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557d63838a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557d6381d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557d634cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557d634ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa87d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa87d6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa87d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557d634cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c (2596 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf8_u8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf4_u8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf2_u8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m1_u8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m2_u8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m4_u8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m8_u8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16mf4_u16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16mf2_u16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16m1_u16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, pt
# | ...
# `---data was truncated (10240/52733) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d90c8b8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d90c8b5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d90c8b962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f830cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f830cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f830cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f830cf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d90c84ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d90c84ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d90c8338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d90c4e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d90c4e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f830cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f830cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f830cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d90c4e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c (2597 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_i8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_i8mf2x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8_v_i8m1x6_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_u8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_u8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_u8mf2x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8_v_u8m1x6_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559cfd28feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559cfd28ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559cfd29062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f515b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f515b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f515b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f515b31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559cfd225bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559cfd225a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559cfd20a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559cfceb9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559cfceb9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f515b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f515b31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f515b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559cfceb9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c (2598 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgatherei16_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgatherei16_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgatherei16_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgatherei16_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgatherei16_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vrgatherei16_vv_f16m8(<vscale x 32 x half> %op1, <vscale x 32 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 32 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vrgatherei16_vv_f32mf2(<vscale x 1 x float> %op1, <vscale x 1 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vrgatherei16_vv_f32m1(<vscale x 2 x float> %op1, <vscale x 2 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vrgatherei16.vv.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vrgatherei16.vv.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vrgatherei16_vv_f32m2(<vscale x 4 x float> %op1, <vscale x 4 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %op2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 4 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vrgatherei16.vv.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vrgatherei16.vv.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vrgatherei16_vv_f32m4(<vscale x 8 x float> %op1, <vscale x 8 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %op2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 8 x 
# | ...
# `---data was truncated (10240/124028) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559179a3beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559179a38e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559179a3c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbb32b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbb32b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbb32b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbb32aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005591799d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005591799d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005591799b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559179665e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559179665b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbb32aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbb32aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbb32aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559179665a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c (2599 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei32_v_i8mf8x6
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558be945deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558be945ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558be945e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb60f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb60f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb60f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb60f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558be93f3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558be93f3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558be93d88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558be9087e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558be9087b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb60f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb60f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb60f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558be9087a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c (2600 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrol_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrol_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrol_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrol_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrol_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrol_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrol_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrol_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrol_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 
# | ...
# `---data was truncated (10240/222315) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e310cd4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e310cd1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e310cd562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee80c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee80ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee80c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee80c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e310c6abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e310c6aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e310c4f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e3108fee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e3108feb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fee80c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee80c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee80c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e3108fea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c (2601 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vslidedown_vx_f16mf4(<vscale x 1 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vslidedown_vx_f16mf2(<vscale x 2 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vslidedown_vx_f16m1(<vscale x 4 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vslidedown_vx_f16m2(<vscale x 8 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vslidedown_vx_f16m4(<vscale x 16 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vslidedown_vx_f16m8(<vscale x 32 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vslidedown_vx_f32mf2(<vscale x 1 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vslidedown_vx_f32m1(<vscale x 2 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vslidedown_vx_f32m2(<vscale x 4 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vslidedown_vx_f32m4(<vscale x 8 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i
# | ...
# `---data was truncated (10240/120468) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561132c17eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561132c14e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561132c1862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6fc2b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6fc2b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6fc2b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6fc2b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561132badbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561132bada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561132b928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561132841e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561132841b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6fc2b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6fc2b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6fc2b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561132841a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcmulq.c (2602 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcmulq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 0, <8 x half> %0, <8 x half> %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32, <8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 0, <4 x float> %0, <4 x float> %1)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32, <4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot90_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 1, <8 x half> %0, <8 x half> %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot90_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 1, <4 x float> %0, <4 x float> %1)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot180_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 2, <8 x half> %0, <8 x half> %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot180_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 2, <4 x float> %0, <4 x float> %1)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot270_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 3, <8 x half> %0, <8 x half> %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot270_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 3, <4 x float> %0, <4 x float> %1)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %inactive.addr, align 8
# |   %1 = load <8 x half>, ptr %a.addr, align 8
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
# |   %6 = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 0, <8 x half> %0, <8 x half> %1, <8 x half> %2, <8 x i1> %5)
# |   ret <8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32, <8 x half>, <8 x half>, <8 x half>, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %inactive.addr, align 8
# |   %1 = load <4 x float>, ptr %a.addr, align 8
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 0, <4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x i1> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32, <4 x float>, <4 x float>, <4 x float>, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot90_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %inactive.addr, align 8
# |   %1 = load <8 x half>, ptr %a.addr, align 8
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
# |   %6 = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 1, <8 x half> %0, <8 x half> %1, <8 x half> %2, <8 x i1> %5)
# |   ret <8 x half> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot90_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %inactive.addr, align 8
# |   %1 = load <4 x float>, ptr %a.addr, align 8
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 1, <4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x i1> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot180_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %inactive.addr, align 8
# |   %1 = load <8 x half>, ptr %a.addr, align 8
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %
# | ...
# `---data was truncated (10240/20326) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d8d679feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d8d679ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d8d67a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f773501bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f77350725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f773501ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7735003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d8d6735bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d8d6735a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d8d671a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d8d63c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d8d63c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7735004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f77350050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f77350050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d8d63c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/AArch64/neon/vpaddl.c (2603 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/vpaddl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -disable-O0-optnone           -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c --check-prefixes=LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vpaddl_s8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vpaddl.i = call <4 x i16> @llvm.aarch64.neon.saddlp.v4i16.v8i8(<8 x i8> %1)
# |   store <4 x i16> %vpaddl.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vpaddlq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vpaddl.i = call <8 x i16> @llvm.aarch64.neon.saddlp.v8i16.v16i8(<16 x i8> %1)
# |   store <8 x i16> %vpaddl.i, ptr %ref.tmp.i, align 16
# |   %2 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %2, ptr %__ret.i, align 16
# |   %3 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vpaddl_s16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vpaddl.i = bitcast <8 x i8> %1 to <4 x i16>
# |   %vpaddl1.i = call <2 x i32> @llvm.aarch64.neon.saddlp.v2i32.v4i16(<4 x i16> %vpaddl.i)
# |   store <2 x i32> %vpaddl1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vpaddlq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vpaddl.i = bitcast <16 x i8> %1 to <8 x i16>
# |   %vpaddl1.i = call <4 x i32> @llvm.aarch64.neon.saddlp.v4i32.v8i16(<8 x i16> %vpaddl.i)
# |   store <4 x i32> %vpaddl1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vpaddl_s32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vpaddl.i = bitcast <8 x i8> %1 to <2 x i32>
# |   %vpaddl1.i = call <1 x i64> @llvm.aarch64.neon.saddlp.v1i64.v2i32(<2 x i32> %vpaddl.i)
# |   store <1 x i64> %vpaddl1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <1 x i64>, ptr %ref.tmp.i, align 8
# |   store <1 x i64> %2, ptr %__ret.i, align 8
# |   %3 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vpaddlq_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vpaddl.i = bitcast <16 x i8> %1 to <4 x i32>
# |   %vpaddl1.i = call <2 x i64> @llvm.aarch64.neon.saddlp.v2i64.v4i32(<4 x i32> %vpaddl.i)
# |   store <2 x i64> %vpaddl1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <2 x i64>, ptr %ref.tmp.i, align 16
# |   store <2 x i64> %2, ptr %__ret.i, align 16
# |   %3 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vpaddl_u8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vpaddl.i = call <4 x i16> @llvm.aarch64.neon.uaddlp.v4i16.v8i8(<8 x i8> %1)
# |   store <4 x i16> %vpaddl.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vpaddlq_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vpaddl.i = call <8 x i16> @llvm.aarch64.neon.uaddlp.v8i16.v16i8(<16 x i8> %1)
# |   store <8 x i16> %vpaddl.i, ptr %ref.tmp.i, align 16
# |   %2 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %2, ptr %__ret.i, align 16
# |   %3 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vpaddl_u16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vpaddl.i = bitcast <8 x i8> %1 to <4 x i16>
# |   %vpaddl1.i = call <2 x i32> @llvm.aarch64.neon.uaddlp.v2i32.v4i16(<4 x i16> %vpaddl.i)
# |   store <2 x i32> %vpaddl1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vpaddlq_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vpaddl.i = bitcast <16 x i8> %1 to <8 x i16>
# |   %vpaddl1.i = call <4 x i32> @llvm.aarch64.neon.uaddlp.v4i32.v8i16(<8 x i16> %vpaddl.i)
# |   store <4 x i32> %vpaddl1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vpaddl_u32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vpaddl.i = bitcast <8 x i8> %1 to <2 x i32>
# |   %vpaddl1.i = call <1 x i64> @llvm.aarch64.neon.uaddlp.v1i64.v2i32(<2 x i32> %vpaddl.i)
# |   store <1 x i64> %vpaddl1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <1 x i64>, ptr %ref.tmp.i, align 8
# |   store <1 x i64> %2, ptr %__ret.i, align 8
# |   %3 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vpaddlq_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vpaddl.i = bitcast <16 x i8> %1 to <4 x i32>
# |   %vpaddl1.i = call <2 x i64> @llvm.aarch64.neon.uaddlp.v2i64.v4i32(<4 x i32> %vpaddl.i)
# |   store <2 x i64> %vpaddl1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <2 x i64>, ptr %ref.tmp.i, align 16
# |   store <2 x i64> %2, ptr %__ret.i, align 16
# |   %3 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vpadal_s8(<4 x i16> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <8 x i8>, al
# | ...
# `---data was truncated (10240/26059) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000555d50842eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555d5083fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555d5084362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f84b7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f84b778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f84b7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f84b771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555d507d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555d507d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555d507bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555d5046ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555d5046cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f84b771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f84b771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f84b771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555d5046ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c --check-prefixes=LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c --check-prefixes=LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/AArch64/builtin-shufflevector-fp8.c (2604 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/builtin-shufflevector-fp8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-linux -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-linux -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-unknown-linux"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_8x8(<8 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <8 x i8>, ptr %x.addr, align 8
# |   %1 = load <8 x i8>, ptr %x.addr, align 8
# |   %shuffle = shufflevector <8 x i8> %0, <8 x i8> %1, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 3, i32 2, i32 1, i32 0>
# |   ret <8 x i8> %shuffle
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_8x8_v(<8 x i8> %x, <8 x i8> noundef %p) #0 {
# | entry:
# |   %x.addr = alloca <8 x i8>, align 8
# |   %p.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %x, ptr %x.addr, align 8
# |   store <8 x i8> %p, ptr %p.addr, align 8
# |   %0 = load <8 x i8>, ptr %x.addr, align 8
# |   %1 = load <8 x i8>, ptr %p.addr, align 8
# |   %mask = and <8 x i8> %1, splat (i8 7)
# |   %shuf_idx = extractelement <8 x i8> %mask, i64 0
# |   %shuf_elt = extractelement <8 x i8> %0, i8 %shuf_idx
# |   %shuf_ins = insertelement <8 x i8> poison, i8 %shuf_elt, i64 0
# |   %shuf_idx1 = extractelement <8 x i8> %mask, i64 1
# |   %shuf_elt2 = extractelement <8 x i8> %0, i8 %shuf_idx1
# |   %shuf_ins3 = insertelement <8 x i8> %shuf_ins, i8 %shuf_elt2, i64 1
# |   %shuf_idx4 = extractelement <8 x i8> %mask, i64 2
# |   %shuf_elt5 = extractelement <8 x i8> %0, i8 %shuf_idx4
# |   %shuf_ins6 = insertelement <8 x i8> %shuf_ins3, i8 %shuf_elt5, i64 2
# |   %shuf_idx7 = extractelement <8 x i8> %mask, i64 3
# |   %shuf_elt8 = extractelement <8 x i8> %0, i8 %shuf_idx7
# |   %shuf_ins9 = insertelement <8 x i8> %shuf_ins6, i8 %shuf_elt8, i64 3
# |   %shuf_idx10 = extractelement <8 x i8> %mask, i64 4
# |   %shuf_elt11 = extractelement <8 x i8> %0, i8 %shuf_idx10
# |   %shuf_ins12 = insertelement <8 x i8> %shuf_ins9, i8 %shuf_elt11, i64 4
# |   %shuf_idx13 = extractelement <8 x i8> %mask, i64 5
# |   %shuf_elt14 = extractelement <8 x i8> %0, i8 %shuf_idx13
# |   %shuf_ins15 = insertelement <8 x i8> %shuf_ins12, i8 %shuf_elt14, i64 5
# |   %shuf_idx16 = extractelement <8 x i8> %mask, i64 6
# |   %shuf_elt17 = extractelement <8 x i8> %0, i8 %shuf_idx16
# |   %shuf_ins18 = insertelement <8 x i8> %shuf_ins15, i8 %shuf_elt17, i64 6
# |   %shuf_idx19 = extractelement <8 x i8> %mask, i64 7
# |   %shuf_elt20 = extractelement <8 x i8> %0, i8 %shuf_idx19
# |   %shuf_ins21 = insertelement <8 x i8> %shuf_ins18, i8 %shuf_elt20, i64 7
# |   ret <8 x i8> %shuf_ins21
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_8x16(<16 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   %0 = load <16 x i8>, ptr %x.addr, align 16
# |   %1 = load <16 x i8>, ptr %x.addr, align 16
# |   %shuffle = shufflevector <16 x i8> %0, <16 x i8> %1, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
# |   ret <16 x i8> %shuffle
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_8x16_v(<16 x i8> %x, <16 x i8> noundef %p) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   %p.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   store <16 x i8> %p, ptr %p.addr, align 16
# |   %0 = load <16 x i8>, ptr %x.addr, align 16
# |   %1 = load <16 x i8>, ptr %p.addr, align 16
# |   %mask = and <16 x i8> %1, splat (i8 15)
# |   %shuf_idx = extractelement <16 x i8> %mask, i64 0
# |   %shuf_elt = extractelement <16 x i8> %0, i8 %shuf_idx
# |   %shuf_ins = insertelement <16 x i8> poison, i8 %shuf_elt, i64 0
# |   %shuf_idx1 = extractelement <16 x i8> %mask, i64 1
# |   %shuf_elt2 = extractelement <16 x i8> %0, i8 %shuf_idx1
# |   %shuf_ins3 = insertelement <16 x i8> %shuf_ins, i8 %shuf_elt2, i64 1
# |   %shuf_idx4 = extractelement <16 x i8> %mask, i64 2
# |   %shuf_elt5 = extractelement <16 x i8> %0, i8 %shuf_idx4
# |   %shuf_ins6 = insertelement <16 x i8> %shuf_ins3, i8 %shuf_elt5, i64 2
# |   %shuf_idx7 = extractelement <16 x i8> %mask, i64 3
# |   %shuf_elt8 = extractelement <16 x i8> %0, i8 %shuf_idx7
# |   %shuf_ins9 = insertelement <16 x i8> %shuf_ins6, i8 %shuf_elt8, i64 3
# |   %shuf_idx10 = extractelement <16 x i8> %mask, i64 4
# |   %shuf_elt11 = extractelement <16 x i8> %0, i8 %shuf_idx10
# |   %shuf_ins12 = insertelement <16 x i8> %shuf_ins9, i8 %shuf_elt11, i64 4
# |   %shuf_idx13 = extractelement <16 x i8> %mask, i64 5
# |   %shuf_elt14 = extractelement <16 x i8> %0, i8 %shuf_idx13
# |   %shuf_ins15 = insertelement <16 x i8> %shuf_ins12, i8 %shuf_elt14, i64 5
# |   %shuf_idx16 = extractelement <16 x i8> %mask, i64 6
# |   %shuf_elt17 = extractelement <16 x i8> %0, i8 %shuf_idx16
# |   %shuf_ins18 = insertelement <16 x i8> %shuf_ins15, i8 %shuf_elt17, i64 6
# |   %shuf_idx19 = extractelement <16 x i8> %mask, i64 7
# |   %shuf_elt20 = extractelement <16 x i8> %0, i8 %shuf_idx19
# |   %shuf_ins21 = insertelement <16 x i8> %shuf_ins18, i8 %shuf_elt20, i64 7
# |   %shuf_idx22 = extractelement <16 x i8> %mask, i64 8
# |   %shuf_elt23 = extractelement <16 x i8> %0, i8 %shuf_idx22
# |   %shuf_ins24 = insertelement <16 x i8> %shuf_ins21, i8 %shuf_elt23, i64 8
# |   %shuf_idx25 = extractelement <16 x i8> %mask, i64 9
# |   %shuf_elt26 = extractelement <16 x i8> %0, i8 %shuf_idx25
# |   %shuf_ins27 = insertelement <16 x i8> %shuf_ins24, i8 %shuf_elt26, i64 9
# |   %shuf_idx28 = extractelement <16 x i8> %mask, i64 10
# |   %shuf_elt29 = extractelement <16 x i8> %0, i8 %shuf_idx28
# |   %shuf_ins30 = insertelement <16 x i8> %shuf_ins27, i8 %shuf_elt29, i64 10
# |   %shuf_idx31 = extractelement <16 x i8> %mask, i64 11
# |   %shuf_elt32 = extractelement <16 x i8> %0, i8 %shuf_idx31
# |   %shuf_ins33 = insertelement <16 x i8> %shuf_ins30, i8 %shuf_elt32, i64 11
# |   %shuf_idx34 = extractelement <16 x i8> %mask, i64 12
# |   %shuf_elt35 = extractelement <16 x i8> %0, i8 %shuf_idx34
# |   %shuf_ins36 = insertelement <16 x i8> %shuf_ins33, i8 %shuf_elt35, i64 12
# |   %shuf_idx37 = extractelement <16 x i8> %mask, i64 13
# |   %shuf_elt38 = extractelement <16 x i8> %0, i8 %shuf_idx37
# |   %shuf_ins39 = insertelement <16 x i8> %shuf_ins36, i8 %shuf_elt38, i64 13
# |   %shuf_idx40 = extractelement <16 x i8> %mask, i64 14
# |   %shuf_elt41 = extractelement <16 x i8> %0, i8 %shuf_idx40
# |   %shuf_ins42 = insertelement <16 x i8> %shuf_ins39, i8 %shuf_elt41, i64 14
# |   %shuf_idx43 = extractelement <16 x i8> %mask, i64 15
# |   %shuf_elt44 = extractelement <16 x i8> %0, i8 %shuf_idx43
# |   %shuf_ins45 = insertelement <16 x i8> %shuf_ins42, i8 %shuf_elt44, i64 15
# |   ret <16 x i8> %shuf_ins45
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f084b0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564f084ade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564f084b162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f83d3a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83d3aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f83d3a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f83d3a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f08446bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564f08446a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564f0842b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564f080dae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564f080dab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f83d3a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83d3a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83d3a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f080daa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c (2605 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_f32mf2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_f32m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_f32m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_f32m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_i32mf2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_i32m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_i32m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_i32m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_u32mf2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_u32m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_u32m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_u32m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_f32mf2x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   
# | ...
# `---data was truncated (10240/23061) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c86af0beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c86af08e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c86af0c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6fed333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6fed38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6fed333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6fed31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c86aea1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c86aea1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c86ae868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c86ab35e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c86ab35b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6fed31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6fed31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6fed31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c86ab35a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqrdmulhq.c (2606 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqrdmulhq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmulhq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vqrdmulh.v16i8(<16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vqrdmulh.v16i8(<16 x i8>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqrdmulhq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vqrdmulh.v8i16(<8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vqrdmulh.v8i16(<8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqrdmulhq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmulhq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.qrdmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.qrdmulh.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqrdmulhq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.qrdmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.qrdmulh.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqrdmulhq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.qrdmulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.qrdmulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmulhq_n_s8(<16 x i8> noundef %a, i8 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = call <16 x i8> @llvm.arm.mve.vqrdmulh.v16i8(<16 x i8> %0, <16 x i8> %.splat)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqrdmulhq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = call <8 x i16> @llvm.arm.mve.vqrdmulh.v8i16(<8 x i16> %0, <8 x i16> %.splat)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqrdmulhq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %0, <4 x i32> %.splat)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmulhq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.qrdmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqrdmulhq_m_n_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.qrdmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 
# | ...
# `---data was truncated (10240/11881) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005590495e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005590495e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005590495ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe9c701bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe9c70725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe9c701ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe9c7003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055904957fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055904957fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005590495648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559049213e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559049213b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe9c7004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe9c70050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe9c70050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559049213a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c (2607 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_i16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_i16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_i16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_u16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_u16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5),
# | ...
# `---data was truncated (10240/53330) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056372e346eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056372e343e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056372e34762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb255449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb2554a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb255449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb255431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056372e2dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056372e2dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056372e2c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056372df70e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056372df70b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb255432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb2554330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb2554330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056372df70a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c (2608 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vv_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vf_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vv_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vf_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vv_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vf_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vv_bf16m2_f32m4(<vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vf_bf16m2_f32m4(<vscale x 8 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwmul_vv_bf16m4_f32m8(<vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwmul.nxv16f32.nxv16bf16.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwmul.nxv16f32.nxv16bf16.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwmul_vf_bf16m4_f32m8(<vscale x 16 x bfloat> %vs2, bflo
# | ...
# `---data was truncated (10240/43940) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e7bb69beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e7bb698e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e7bb69c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe0ee849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe0ee8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe0ee849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe0ee831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e7bb631bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e7bb631a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e7bb6168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e7bb2c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e7bb2c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe0ee832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe0ee8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe0ee8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e7bb2c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/SystemZ/zvector.c (2609 of 27911)
******************** TEST 'Clang :: CodeGen/SystemZ/zvector.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple s390x-linux-gnu -target-cpu z13 -fzvector  -emit-llvm -o - -W -Wall -Werror  /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple s390x-linux-gnu -target-cpu z13 -fzvector -emit-llvm -o - -W -Wall -Werror /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c"
# | target datalayout = "E-S64-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64"
# | target triple = "s390x-unknown-linux-gnu"
# | 
# | @sc2 = global <16 x i8> zeroinitializer, align 8
# | @sc = global <16 x i8> zeroinitializer, align 8
# | @uc2 = global <16 x i8> zeroinitializer, align 8
# | @uc = global <16 x i8> zeroinitializer, align 8
# | @ss2 = global <8 x i16> zeroinitializer, align 8
# | @ss = global <8 x i16> zeroinitializer, align 8
# | @us2 = global <8 x i16> zeroinitializer, align 8
# | @us = global <8 x i16> zeroinitializer, align 8
# | @si2 = global <4 x i32> zeroinitializer, align 8
# | @si = global <4 x i32> zeroinitializer, align 8
# | @ui2 = global <4 x i32> zeroinitializer, align 8
# | @ui = global <4 x i32> zeroinitializer, align 8
# | @sl2 = global <2 x i64> zeroinitializer, align 8
# | @sl = global <2 x i64> zeroinitializer, align 8
# | @ul2 = global <2 x i64> zeroinitializer, align 8
# | @ul = global <2 x i64> zeroinitializer, align 8
# | @slll2 = global <1 x i128> zeroinitializer, align 8
# | @slll = global <1 x i128> zeroinitializer, align 8
# | @ulll2 = global <1 x i128> zeroinitializer, align 8
# | @ulll = global <1 x i128> zeroinitializer, align 8
# | @fd2 = global <2 x double> zeroinitializer, align 8
# | @fd = global <2 x double> zeroinitializer, align 8
# | @bc2 = global <16 x i8> zeroinitializer, align 8
# | @bc = global <16 x i8> zeroinitializer, align 8
# | @bs2 = global <8 x i16> zeroinitializer, align 8
# | @bs = global <8 x i16> zeroinitializer, align 8
# | @bi2 = global <4 x i32> zeroinitializer, align 8
# | @bi = global <4 x i32> zeroinitializer, align 8
# | @bl2 = global <2 x i64> zeroinitializer, align 8
# | @bl = global <2 x i64> zeroinitializer, align 8
# | @blll2 = global <1 x i128> zeroinitializer, align 8
# | @blll = global <1 x i128> zeroinitializer, align 8
# | @cnt = global i32 0, align 4
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @test_assign() #0 {
# | entry:
# |   %0 = load volatile <16 x i8>, ptr @sc2, align 8
# |   store volatile <16 x i8> %0, ptr @sc, align 8
# |   %1 = load volatile <16 x i8>, ptr @uc2, align 8
# |   store volatile <16 x i8> %1, ptr @uc, align 8
# |   %2 = load volatile <8 x i16>, ptr @ss2, align 8
# |   store volatile <8 x i16> %2, ptr @ss, align 8
# |   %3 = load volatile <8 x i16>, ptr @us2, align 8
# |   store volatile <8 x i16> %3, ptr @us, align 8
# |   %4 = load volatile <4 x i32>, ptr @si2, align 8
# |   store volatile <4 x i32> %4, ptr @si, align 8
# |   %5 = load volatile <4 x i32>, ptr @ui2, align 8
# |   store volatile <4 x i32> %5, ptr @ui, align 8
# |   %6 = load volatile <2 x i64>, ptr @sl2, align 8
# |   store volatile <2 x i64> %6, ptr @sl, align 8
# |   %7 = load volatile <2 x i64>, ptr @ul2, align 8
# |   store volatile <2 x i64> %7, ptr @ul, align 8
# |   %8 = load volatile <1 x i128>, ptr @slll2, align 8
# |   store volatile <1 x i128> %8, ptr @slll, align 8
# |   %9 = load volatile <1 x i128>, ptr @ulll2, align 8
# |   store volatile <1 x i128> %9, ptr @ulll, align 8
# |   %10 = load volatile <2 x double>, ptr @fd2, align 8
# |   store volatile <2 x double> %10, ptr @fd, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @test_pos() #0 {
# | entry:
# |   %0 = load volatile <16 x i8>, ptr @sc2, align 8
# |   store volatile <16 x i8> %0, ptr @sc, align 8
# |   %1 = load volatile <16 x i8>, ptr @uc2, align 8
# |   store volatile <16 x i8> %1, ptr @uc, align 8
# |   %2 = load volatile <8 x i16>, ptr @ss2, align 8
# |   store volatile <8 x i16> %2, ptr @ss, align 8
# |   %3 = load volatile <8 x i16>, ptr @us2, align 8
# |   store volatile <8 x i16> %3, ptr @us, align 8
# |   %4 = load volatile <4 x i32>, ptr @si2, align 8
# |   store volatile <4 x i32> %4, ptr @si, align 8
# |   %5 = load volatile <4 x i32>, ptr @ui2, align 8
# |   store volatile <4 x i32> %5, ptr @ui, align 8
# |   %6 = load volatile <2 x i64>, ptr @sl2, align 8
# |   store volatile <2 x i64> %6, ptr @sl, align 8
# |   %7 = load volatile <2 x i64>, ptr @ul2, align 8
# |   store volatile <2 x i64> %7, ptr @ul, align 8
# |   %8 = load volatile <1 x i128>, ptr @slll2, align 8
# |   store volatile <1 x i128> %8, ptr @slll, align 8
# |   %9 = load volatile <1 x i128>, ptr @ulll2, align 8
# |   store volatile <1 x i128> %9, ptr @ulll, align 8
# |   %10 = load volatile <2 x double>, ptr @fd2, align 8
# |   store volatile <2 x double> %10, ptr @fd, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @test_neg() #0 {
# | entry:
# |   %0 = load volatile <16 x i8>, ptr @sc2, align 8
# |   %sub = sub <16 x i8> zeroinitializer, %0
# |   store volatile <16 x i8> %sub, ptr @sc, align 8
# |   %1 = load volatile <8 x i16>, ptr @ss2, align 8
# |   %sub1 = sub <8 x i16> zeroinitializer, %1
# |   store volatile <8 x i16> %sub1, ptr @ss, align 8
# |   %2 = load volatile <4 x i32>, ptr @si2, align 8
# |   %sub2 = sub <4 x i32> zeroinitializer, %2
# |   store volatile <4 x i32> %sub2, ptr @si, align 8
# |   %3 = load volatile <2 x i64>, ptr @sl2, align 8
# |   %sub3 = sub <2 x i64> zeroinitializer, %3
# |   store volatile <2 x i64> %sub3, ptr @sl, align 8
# |   %4 = load volatile <1 x i128>, ptr @slll2, align 8
# |   %sub4 = sub <1 x i128> zeroinitializer, %4
# |   store volatile <1 x i128> %sub4, ptr @slll, align 8
# |   %5 = load volatile <2 x double>, ptr @fd2, align 8
# |   %fneg = fneg <2 x double> %5
# |   store volatile <2 x double> %fneg, ptr @fd, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @test_preinc() #0 {
# | entry:
# |   %0 = load volatile <16 x i8>, ptr @sc2, align 8
# |   %inc = add <16 x i8> %0, splat (i8 1)
# |   store volatile <16 x i8> %inc, ptr @sc2, align 8
# |   %1 = load volatile <16 x i8>, ptr @uc2, align 8
# |   %inc1 = add <16 x i8> %1, splat (i8 1)
# |   store volatile <16 x i8> %inc1, ptr @uc2, align 8
# |   %2 = load volatile <8 x i16>, ptr @ss2, align 8
# |   %inc2 = add <8 x i16> %2, splat (i16 1)
# |   store volatile <8 x i16> %inc2, ptr @ss2, align 8
# |   %3 = load volatile <8 x i16>, ptr @us2, align 8
# |   %inc3 = add <8 x i16> %3, splat (i16 1)
# |   store volatile <8 x i16> %inc3, ptr @us2, align 8
# |   %4 = load volatile <4 x i32>, ptr @si2, align 8
# |   %inc4 = add <4 x i32> %4, splat (i32 1)
# |   store volatile <4 x i32> %inc4, ptr @si2, align 8
# |   %5 = load volatile <4 x i32>, ptr @ui2, align 8
# |   %inc5 = add <4 x i32> %5, splat (i32 1)
# |   store volatile <4 x i32> %inc5, ptr @ui2, align 8
# |   %6 = load volatile <2 x i64>, ptr @sl2, align 8
# |   %inc6 = add <2 x i64> %6, splat (i64 1)
# |   store volatile <2 x i64> %inc6, ptr @sl2, align 8
# |   %7 = load volatile <2 x i64>, ptr @ul2, align 8
# |   %inc7 = add <2 x i64> %7, splat (i64 1)
# |   store volatile <2 x i64> %inc7, ptr @ul2, align 8
# |   %8 = load volatile <1 x i128>, ptr @slll2, align 8
# |   %inc8 = add <1 x i128> %8, splat (i128 1)
# |   store volatile <1 x i128> %inc8, ptr @slll2, align 8
# |   %9 = load volatile <1 x i128>, ptr @ulll2, align 8
# |   %inc9 = add <1 x i128> %9, splat (i128 1)
# |   store volatile <1 x i128> %inc9, ptr @ulll2, align 8
# |   %10 = load volatile <2 x double>, ptr @fd2, align 8
# |   %inc10 = fadd <2 x double> %10, splat (double 1.000000e+00)
# |   store volatile <2 x double> %inc10, ptr @fd2, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @test_postinc() #0 {
# | entry:
# |   %0 = load volatile <16 x i8>, ptr @sc2, align 8
# |   %inc = add <16 x i8> %0, splat (i8 1)
# |   store volatile <16 x i8> %inc, ptr @sc2, align 8
# |   %1 = load volatile <16 x i8>, ptr @uc2, align 8
# |   %inc1 = add <16 x i8> %1, splat (i8 1)
# |   store volatile <16 x i8> %inc1, ptr @uc2, align 8
# |   %2 = load volatile <8 x i16>, ptr @ss2, align 8
# |   %inc2 = add <8 x i16> %2, splat (i16 1)
# |   store volatile <8 x i16> %inc2, ptr @ss2, align 8
# |   %3 = load volatile <8 x i16>, ptr @us2, align 8
# |   %inc3 = add <8 x i16> %3, splat (i16 1)
# |   store volatile <8 x i16> %inc3, ptr @us2, align 8
# |   %4 = load volatile <4 x i32>, ptr @si2, align 8
# |   %inc4 = add <4 x i32> %4, splat (i32 1)
# |   store volatile <4 x i32> %inc4, ptr @si2, align 8
# |   %5 = load volatile <4 x i32>, ptr @ui2, align 8
# |   %inc5 = add <4 x i32> %5, splat (i32 1)
# |   store volatile <4 x i32> %inc5, ptr @ui2, align 8
# |   %6 = load volatile <2 x i64>, ptr @sl2, align 8
# |   %inc6 = add <2 x i64> %6, splat (i64 1)
# |   store volatile <2 x i64> %inc6, ptr @sl2, align 8
# |   %7 = load volatile <2 x i64>, ptr @ul2, align 8
# |   %inc7 = add <2 x i64> %7, splat (i64 1)
# |   store volatile <2 x i64> %inc7, ptr @ul2, align 8
# |   %8 = load volatile <1 x i128>, ptr @slll2, align 8
# |   %inc8 = add <1 x i128> %8, splat (i128 1)
# |   store volatile <1 x i128> %inc8, ptr @slll2, align 8
# |   %9 = load volatile <1 x i128>, ptr @ulll2, align 8
# |   %inc9 = add <1 x i128> %9, splat (i128 1)
# |   store volatile <1 x i128> %inc9, ptr @ulll2, align 8
# |   %10 = load volatile <2 x double>, ptr @fd2, align 8
# |   %inc10 = fadd <2 x double> %10, splat (double 1.000000e+00)
# |   store volatile <2 x double> %inc10, ptr @fd2, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @test_predec() #0 {
# | entry:
# |   %0 = load volatile <16 x i8>, ptr @sc2, align 8
# |   %dec = add <16 x i8> %0, splat (i8 -1)
# |   store volatile <16 x i8> %dec, ptr @sc2, align 8
# |   %1 = load volatile <16 x i8>, ptr @uc2, align 8
# |   %dec1 = add <16 x i8> %1, splat (i8 -1)
# |   store volatile <16 x i8> %dec1, ptr @uc2, align 8
# |   %2 = load volatile <8 x i16>, ptr @ss2, align 8
# |   %dec2 = add <8 x i16> %2, splat (i16 -1)
# |   store volatile <8 x i16> %dec2, ptr @ss2, align 8
# |   %3 = load volatile <8 x i16>, ptr @us2, align 8
# |   %dec3 = add <8 x i16> %3, splat (i16 -1)
# |   store volatile <8 x i16> %dec3, ptr @us2, align 8
# |   %4 = load volatile <4 x i32>, ptr @si2, align 8
# |   %dec4 = add <4 x i32> %4, splat (i32 -1)
# |   store volatile <4 x i32> %dec4, ptr @si2, align 8
# |   %5 = load volatile <4 x i32>, ptr @ui2, align 8
# |   %dec5 = add <4 x i32> %5, splat (i32 -1)
# |   store volatile <4 x i32> %dec5, ptr @ui2, align 8
# |   %6 = load volatile <2 x i64>, ptr @sl2, align 8
# |   %dec6 = add <2 x i64> %6, splat (i64 -1)
# |   store volatile <2 x i64> %dec6, ptr @sl2, align 8
# |   %7 = load volatile <2 x i64>, ptr @ul2, align 8
# |   %dec7 = add <2 x i64> %7, splat (i64 -1)
# |   store volatile <2 x i64> %dec7, ptr @ul2, align 8
# |   %8 = load volatile <1 x i128>, ptr @slll2, align 8
# |   %dec8 = add <1 x i128> %8, splat (i128 -1)
# |   store volatile <1 x i128> %dec8, ptr @slll2, align 8
# |   %9 = load volatile <1 x i128>, ptr @ulll2, align 8
# |   %dec
# | ...
# `---data was truncated (10240/152876) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dd9113ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dd91139e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dd9113d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f660ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f660ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f660ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f660ad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd910d2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dd910d2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dd910b78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dd90d66e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dd90d66b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f660ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f660ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f660ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd90d66a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c (2610 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmv_v_f_bf16mf4(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfmv.v.f.nxv1bf16.i64(<vscale x 1 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmv.v.f.nxv1bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmv_v_f_bf16mf2(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfmv.v.f.nxv2bf16.i64(<vscale x 2 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmv.v.f.nxv2bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmv_v_f_bf16m1(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfmv.v.f.nxv4bf16.i64(<vscale x 4 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmv.v.f.nxv4bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmv_v_f_bf16m2(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfmv.v.f.nxv8bf16.i64(<vscale x 8 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmv.v.f.nxv8bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmv_v_f_bf16m4(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfmv.v.f.nxv16bf16.i64(<vscale x 16 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmv.v.f.nxv16bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfmv_v_f_bf16m8(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfmv.v.f.nxv32bf16.i64(<vscale x 32 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfmv.v.f.nxv32bf16.i64(<vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16mf4_bf16(<vscale x 1 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv1bf16(<vscale x 1 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv1bf16(<vscale x 1 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmv_s_f_bf16mf4(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfmv.s.f.nxv1bf16.i64(<vscale x 1 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmv.s.f.nxv1bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16mf2_bf16(<vscale x 2 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv2bf16(<vscale x 2 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv2bf16(<vscale x 2 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmv_s_f_bf16mf2(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfmv.s.f.nxv2bf16.i64(<vscale x 2 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmv.s.f.nxv2bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16m1_bf16(<vscale x 4 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv4bf16(<vscale x 4 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv4bf16(<vscale x 4 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmv_s_f_bf16m1(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfmv.s.f.nxv4bf16.i64(<vscale x 4 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmv.s.f.nxv4bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16m2_bf16(<vscale x 8 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv8bf16(<vscale x 8 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv8bf16(<vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmv_s_f_bf16m2(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfmv.s.f.nxv8bf16.i64(<vscale x 8 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmv.s.f.nxv8bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16m4_bf16(<vscale x 16 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %
# | ...
# `---data was truncated (10240/13308) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560b02dfeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560b02dfbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560b02dff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f325b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f325b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f325b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f325b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b02d94bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560b02d94a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560b02d798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560b02a28e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560b02a28b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f325b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f325b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f325b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b02a28a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c (2611 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmslt_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmslt_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmslt_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmslt_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmslt_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmslt_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmslt_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i
# | ...
# `---data was truncated (10240/63579) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e1ec64eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e1ec64be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e1ec64f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc6c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc6c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc6c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc6c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e1ec5e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e1ec5e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e1ec5c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e1ec278e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e1ec278b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdc6c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc6c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc6c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e1ec278a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c (2612 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zvfhmin -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -target-feature +zve64d    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_sf_vtmv_v_t_bf16m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.sf.vtmv.v.t.nxv32bf16.i64(i64 %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare <vscale x 32 x bfloat> @llvm.riscv.sf.vtmv.v.t.nxv32bf16.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vtmv_v_t_f16m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.sf.vtmv.v.t.nxv32f16.i64(i64 %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare <vscale x 32 x half> @llvm.riscv.sf.vtmv.v.t.nxv32f16.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vtmv_v_t_f32m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.sf.vtmv.v.t.nxv16f32.i64(i64 %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare <vscale x 16 x float> @llvm.riscv.sf.vtmv.v.t.nxv16f32.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vtmv_v_t_f64m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x double> @llvm.riscv.sf.vtmv.v.t.nxv8f64.i64(i64 %0, i64 %1)
# |   ret <vscale x 8 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare <vscale x 8 x double> @llvm.riscv.sf.vtmv.v.t.nxv8f64.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_sf_vtmv_v_t_i8m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare <vscale x 64 x i8> @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i16> @test_sf_vtmv_v_t_i16m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.sf.vtmv.v.t.nxv32i16.i64(i64 %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare <vscale x 32 x i16> @llvm.riscv.sf.vtmv.v.t.nxv32i16.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vtmv_v_t_i32m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.sf.vtmv.v.t.nxv16i32.i64(i64 %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vtmv.v.t.nxv16i32.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i64> @test_sf_vtmv_v_t_i64m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.sf.vtmv.v.t.nxv8i64.i64(i64 %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare <vscale x 8 x i64> @llvm.riscv.sf.vtmv.v.t.nxv8i64.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_sf_vtmv_v_t_u8m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i16> @test_sf_vtmv_v_t_u16m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.sf.vtmv.v.t.nxv32i16.i64(i64 %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vtmv_v_t_u32m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.sf.vtmv.v.t.nxv16i32.i64(i64 %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i64> @test_sf_vtmv_v_t_u64m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.sf.vtmv.v.t.nxv8i64.i64(i64 %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_sf_vtmv_v_t_f8e4m3m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_sf_vtmv_v_t_f8e5m2m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfofp8min,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvfhmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvfhmin1p0_zvfofp8min0p9_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560487926eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560487923e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056048792762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f82ad449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f82ad4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f82ad449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f82ad431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005604878bcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005604878bca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005604878a18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560487550e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560487550b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f82ad432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f82ad4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f82ad4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560487550a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c (2613 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16mf2(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.insert.nxv2bf16.nxv1bf16(<vscale x 2 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.insert.nxv2bf16.nxv1bf16(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m1(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv1bf16(<vscale x 4 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv1bf16(<vscale x 4 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m2(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv1bf16(<vscale x 8 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv1bf16(<vscale x 8 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m4(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv1bf16(<vscale x 16 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv1bf16(<vscale x 16 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m8(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv1bf16(<vscale x 32 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv1bf16(<vscale x 32 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m1(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv2bf16(<vscale x 4 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv2bf16(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m2(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv2bf16(<vscale x 8 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv2bf16(<vscale x 8 x bfloat>, <vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m4(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv2bf16(<vscale x 16 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv2bf16(<vscale x 16 x bfloat>, <vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m8(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv2bf16(<vscale x 32 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv2bf16(<vscale x 32 x bfloat>, <vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_ext_v_bf16m1_bf16m2(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16m1_bf16m4(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16m1_bf16m8(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16m2_bf16m4(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16m2_bf16m8(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale
# | ...
# `---data was truncated (10240/12129) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557b0c7b8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557b0c7b5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557b0c7b962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff98b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff98b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff98b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff98b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b0c74ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557b0c74ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557b0c7338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557b0c3e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557b0c3e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff98b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff98b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff98b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b0c3e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c (2614 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_u64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_u64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tu
# | ...
# `---data was truncated (10240/16560) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005623ecb8ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005623ecb89e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005623ecb8d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0d2ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0d2ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0d2ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0d2ff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005623ecb22bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005623ecb22a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005623ecb078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005623ec7b6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005623ec7b6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0d2ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0d2ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0d2ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005623ec7b6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c (2615 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei32_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005607ce82aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005607ce827e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005607ce82b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe35dd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe35dd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe35dd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe35dced507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607ce7c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005607ce7c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005607ce7a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005607ce454e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005607ce454b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe35dceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe35dcef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe35dcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607ce454a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c (2616 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vloxei16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> poison, ptr %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr =
# | ...
# `---data was truncated (10240/14319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b009b1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563b009aee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563b009b262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3a69c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3a69ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3a69c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3a69c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b00947bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563b00947a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563b0092c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563b005dbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563b005dbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3a69c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3a69c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3a69c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b005dba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c (2617 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8mf8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 5)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vsetvlimax.i64(i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8mf4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 6)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8mf2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8m1() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8m2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8m4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8m8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16mf4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 6)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16mf2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16m1() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16m2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16m4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16m8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32mf2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32m1() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32m2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32m4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32m8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e64m1() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e64m2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e64m4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e64m8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 3)
# |   ret i64 %0
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055986ebf0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055986ebede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055986ebf162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5e13d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5e13d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5e13d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5e13d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055986eb86bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055986eb86a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055986eb6b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055986e81ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055986e81ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5e13d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5e13d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5e13d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055986e81aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c (2618 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei16_v_i8mf8x7
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005584364e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005584364e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005584364e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbdc2533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbdc258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbdc2533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbdc251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558436479bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558436479a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055843645e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055843610de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055843610db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbdc251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbdc251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbdc251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055843610da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c (2619 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557c2e792eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557c2e78fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557c2e79362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7353f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7353f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7353f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7353f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557c2e728bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557c2e728a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557c2e70d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557c2e3bce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557c2e3bcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7353f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7353f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7353f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557c2e3bca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c (2620 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgeu_vv_u8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgeu_vx_u8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgeu_vv_u8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgeu_vx_u8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgeu_vv_u8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgeu_vx_u8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgeu_vv_u8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgeu_vx_u8m1_b8(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgeu_vv_u8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgeu_vx_u8m2_b4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsgeu_vv_u8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.nxv32i8.n
# | ...
# `---data was truncated (10240/95347) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558c9c34beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558c9c348e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558c9c34c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fae70f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fae70f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fae70f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fae70f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c9c2e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558c9c2e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558c9c2c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558c9bf75e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558c9bf75b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fae70f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fae70f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fae70f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c9bf75a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c (2621 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_f16mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_f16mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_f16m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_f16m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_i16mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_i16mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_i16m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_i16m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_u16mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_u16mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_
# | ...
# `---data was truncated (10240/26936) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005648a5151eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005648a514ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005648a515262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc3a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc3a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc3a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc3a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005648a50e7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005648a50e7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005648a50cc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005648a4d7be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005648a4d7bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcc3a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc3a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc3a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005648a4d7ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c (2622 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed73b1feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ed73b1ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ed73b2062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb72cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb72cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb72cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb72cc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed73ab5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ed73ab5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ed73a9a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ed73749e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ed73749b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb72cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb72cc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb72cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed73749a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c (2623 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_i32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_i32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_u32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_u32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_f32mf2x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscal
# | ...
# `---data was truncated (10240/35921) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055be11a8feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055be11a8ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055be11a9062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3526733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f352678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3526733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f352671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055be11a25bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055be11a25a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055be11a0a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055be116b9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055be116b9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f352671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f352671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f352671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055be116b9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c (2624 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1up_vf_bf16mf4(<vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1up_vf_bf16mf2(<vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1up_vf_bf16m1(<vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfslide1up_vf_bf16m2(<vscale x 8 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfslide1up_vf_bf16m4(<vscale x 16 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfslide1up_vf_bf16m8(<vscale x 32 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1up_vf_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1up_vf_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1up_vf_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 
# | ...
# `---data was truncated (10240/14824) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fae8070eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fae806de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fae807162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa767249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa7672a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa767249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa767231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fae8006bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fae8006a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fae7feb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fae7c9ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fae7c9ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa767232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa7672330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa7672330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fae7c9aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c (2625 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfslide1up_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfslide1up_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfslide1up_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfslide1up_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfslide1up_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfslide1up_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfslide1up_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load float, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfslide1up_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load float, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfslide1up_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x flo
# | ...
# `---data was truncated (10240/78024) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dbf1729eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dbf1726e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dbf172a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2535933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f253598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2535933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f253591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dbf16bfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dbf16bfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dbf16a48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dbf1353e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dbf1353b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f253591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f253591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f253591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dbf1353a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/AArch64/neon/fused-multiply-constrained.c (2626 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/fused-multiply-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -ffp-exception-behavior=strict -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -ffp-exception-behavior=strict -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <1 x double> @test_vfma_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__p1.addr.i = alloca <1 x double>, align 8
# |   %__p2.addr.i = alloca <1 x double>, align 8
# |   %__ret.i = alloca <1 x double>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %c.addr = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   store <1 x double> %c, ptr %c.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   %1 = load <1 x double>, ptr %b.addr, align 8
# |   %2 = load <1 x double>, ptr %c.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   store <1 x double> %1, ptr %__p1.addr.i, align 8
# |   store <1 x double> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %6 = bitcast <8 x i8> %3 to <1 x double>
# |   %7 = bitcast <8 x i8> %4 to <1 x double>
# |   %8 = bitcast <8 x i8> %5 to <1 x double>
# |   %9 = call <1 x double> @llvm.experimental.constrained.fma.v1f64(<1 x double> %7, <1 x double> %8, <1 x double> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <1 x double> %9, ptr %ref.tmp.i, align 8
# |   %10 = load <1 x double>, ptr %ref.tmp.i, align 8
# |   store <1 x double> %10, ptr %__ret.i, align 8
# |   %11 = load <1 x double>, ptr %__ret.i, align 8
# |   ret <1 x double> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <1 x double> @test_vfma_laneq_f64(<1 x double> noundef %a, <1 x double> noundef %b, <2 x double> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <1 x double>, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %v.addr = alloca <2 x double>, align 16
# |   %__ret = alloca <1 x double>, align 8
# |   %__s0 = alloca <1 x double>, align 8
# |   %__s1 = alloca <1 x double>, align 8
# |   %__s2 = alloca <2 x double>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   store <2 x double> %v, ptr %v.addr, align 16
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__s0, align 8
# |   %1 = load <1 x double>, ptr %b.addr, align 8
# |   store <1 x double> %1, ptr %__s1, align 8
# |   %2 = load <2 x double>, ptr %v.addr, align 16
# |   store <2 x double> %2, ptr %__s2, align 16
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <16 x i8>, ptr %__s2, align 16
# |   %6 = bitcast <8 x i8> %3 to double
# |   %7 = bitcast <8 x i8> %4 to double
# |   %8 = bitcast <16 x i8> %5 to <2 x double>
# |   %extract = extractelement <2 x double> %8, i32 0
# |   %9 = call double @llvm.experimental.constrained.fma.f64(double %7, double %extract, double %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   %10 = bitcast double %9 to <1 x double>
# |   store <1 x double> %10, ptr %ref.tmp, align 8
# |   %11 = load <1 x double>, ptr %ref.tmp, align 8
# |   store <1 x double> %11, ptr %__ret, align 8
# |   %12 = load <1 x double>, ptr %__ret, align 8
# |   store <1 x double> %12, ptr %tmp, align 8
# |   %13 = load <1 x double>, ptr %tmp, align 8
# |   ret <1 x double> %13
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare double @llvm.experimental.constrained.fma.f64(double, double, double, metadata, metadata) #1
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <2 x double> @test_vfmaq_laneq_f64(<2 x double> noundef %a, <2 x double> noundef %b, <2 x double> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <2 x double>, align 16
# |   %b.addr = alloca <2 x double>, align 16
# |   %v.addr = alloca <2 x double>, align 16
# |   %__ret = alloca <2 x double>, align 16
# |   %__s0 = alloca <2 x double>, align 16
# |   %__s1 = alloca <2 x double>, align 16
# |   %__s2 = alloca <2 x double>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   store <2 x double> %v, ptr %v.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__s0, align 16
# |   %1 = load <2 x double>, ptr %b.addr, align 16
# |   store <2 x double> %1, ptr %__s1, align 16
# |   %2 = load <2 x double>, ptr %v.addr, align 16
# |   store <2 x double> %2, ptr %__s2, align 16
# |   %3 = load <16 x i8>, ptr %__s0, align 16
# |   %4 = load <16 x i8>, ptr %__s1, align 16
# |   %5 = load <16 x i8>, ptr %__s2, align 16
# |   %6 = bitcast <16 x i8> %3 to <2 x double>
# |   %7 = bitcast <16 x i8> %4 to <2 x double>
# |   %8 = bitcast <16 x i8> %5 to <2 x double>
# |   %lane = shufflevector <2 x double> %8, <2 x double> %8, <2 x i32> <i32 1, i32 1>
# |   %9 = call <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double> %lane, <2 x double> %7, <2 x double> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <2 x double> %9, ptr %ref.tmp, align 16
# |   %10 = load <2 x double>, ptr %ref.tmp, align 16
# |   store <2 x double> %10, ptr %__ret, align 16
# |   %11 = load <2 x double>, ptr %__ret, align 16
# |   store <2 x double> %11, ptr %tmp, align 16
# |   %12 = load <2 x double>, ptr %tmp, align 16
# |   ret <2 x double> %12
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double>, <2 x double>, <2 x double>, metadata, metadata) #1
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local float @test_vfmas_lane_f32(float noundef %a, float noundef %b, <2 x float> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca float, align 4
# |   %b.addr = alloca float, align 4
# |   %c.addr = alloca <2 x float>, align 8
# |   %__ret = alloca float, align 4
# |   %__s0 = alloca float, align 4
# |   %__s1 = alloca float, align 4
# |   %__s2 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca float, align 4
# |   %tmp = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   store float %b, ptr %b.addr, align 4
# |   store <2 x float> %c, ptr %c.addr, align 8
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__s0, align 4
# |   %1 = load float, ptr %b.addr, align 4
# |   store float %1, ptr %__s1, align 4
# |   %2 = load <2 x float>, ptr %c.addr, align 8
# |   store <2 x float> %2, ptr %__s2, align 8
# |   %3 = load float, ptr %__s0, align 4
# |   %4 = load float, ptr %__s1, align 4
# |   %5 = load <2 x float>, ptr %__s2, align 8
# |   %extract = extractelement <2 x float> %5, i32 1
# |   %6 = call float @llvm.experimental.constrained.fma.f32(float %4, float %extract, float %3, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store float %6, ptr %ref.tmp, align 4
# |   %7 = load float, ptr %ref.tmp, align 4
# |   store float %7, ptr %__ret, align 4
# |   %8 = load float, ptr %__ret, align 4
# |   store float %8, ptr %tmp, align 4
# |   %9 = load float, ptr %tmp, align 4
# |   ret float %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare float @llvm.experimental.constrained.fma.f32(float, float, float, metadata, metadata) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare <1 x double> @llvm.experimental.constrained.fma.v1f64(<1 x double>, <1 x double>, <1 x double>, metadata, metadata) #1
# | 
# | attributes #0 = { noinline nounwind strictfp "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | attributes #1 = { nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) }
# | attributes #2 = { strictfp }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055c578129eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c578126e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c57812a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd412449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd4124a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd412449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd412431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c5780bfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c5780bfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c5780a48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c577d53e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c577d53b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd412432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd4124330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd4124330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c577d53a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c (2627 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmnand_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmnand_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmnand_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmnand_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmnand_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmnand_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmnand_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d0063aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558d00637e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558d0063b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f042e41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f042e4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f042e41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f042e403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d005d0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558d005d0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558d005b58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558d00264e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558d00264b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f042e404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f042e4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f042e4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d00264a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c (2628 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>
# | ...
# `---data was truncated (10240/19492) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f702e2beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f702e28e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f702e2c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f06d3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f06d338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f06d3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f06d331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f702dc1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f702dc1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f702da68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f702a55e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f702a55b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f06d331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f06d331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f06d331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f702a55a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c (2629 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_bf16m1x2_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, i64 nou
# | ...
# `---data was truncated (10240/27442) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005608caa32eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005608caa2fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005608caa3362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f605a049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f605a0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f605a049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f605a031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005608ca9c8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005608ca9c8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005608ca9ad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005608ca65ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005608ca65cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f605a032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f605a0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f605a0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005608ca65ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c (2630 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ffb(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca i32, align 4
# |   %__b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__a.addr.i, align 4
# |   store i32 %1, ptr %__b.addr.i, align 4
# |   %2 = load i32, ptr %__a.addr.i, align 4
# |   %3 = load i32, ptr %__b.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.nds.ffb.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ffzmism(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca i32, align 4
# |   %__b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__a.addr.i, align 4
# |   store i32 %1, ptr %__b.addr.i, align 4
# |   %2 = load i32, ptr %__a.addr.i, align 4
# |   %3 = load i32, ptr %__b.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.nds.ffzmism.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ffmism(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca i32, align 4
# |   %__b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__a.addr.i, align 4
# |   store i32 %1, ptr %__b.addr.i, align 4
# |   %2 = load i32, ptr %__a.addr.i, align 4
# |   %3 = load i32, ptr %__b.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.nds.ffmism.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_flmism(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca i32, align 4
# |   %__b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__a.addr.i, align 4
# |   store i32 %1, ptr %__b.addr.i, align 4
# |   %2 = load i32, ptr %__a.addr.i, align 4
# |   %3 = load i32, ptr %__b.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.nds.flmism.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i32 @llvm.riscv.nds.ffb.i32(i32, i32) #1
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i32 @llvm.riscv.nds.ffzmism.i32(i32, i32) #1
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i32 @llvm.riscv.nds.ffmism.i32(i32, i32) #1
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i32 @llvm.riscv.nds.flmism.i32(i32, i32) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+xandesperf" }
# | attributes #1 = { nounwind speculatable memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_xandesperf5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f9b69c9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f9b69c6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f9b69ca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe6baa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe6baaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe6baa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe6baa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f9b695fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f9b695fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f9b69448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f9b65f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f9b65f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe6baa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe6baa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe6baa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f9b65f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c (2631 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrdiv_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrdiv_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfrdiv.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrdiv.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrdiv_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfrdiv.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrdiv.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrdiv_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfrdiv.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrdiv.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrdiv_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfrdiv.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrdiv.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrdiv_vf_f16m8(<vscale x 32 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfrdiv.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrdiv.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrdiv_vf_f32mf2(<vscale x 1 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrdiv_vf_f32m1(<vscale x 2 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfrdiv.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrdiv.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrdiv_vf_f32m2(<vscale x 4 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfrdiv.nxv4f32.f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrdiv.nxv4f32.f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrdiv_vf_f32m4(<vscale x 8 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfrdiv.nxv8f32.f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfrdiv.nxv8f32.f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @
# | ...
# `---data was truncated (10240/61058) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056000a4b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056000a4b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056000a4b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fedb3e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fedb3ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fedb3e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fedb3e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056000a449bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056000a449a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056000a42e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056000a0dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056000a0ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fedb3e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fedb3e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fedb3e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056000a0dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c (2632 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_u64m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d620da6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d620da3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d620da762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff617c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff617ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff617c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff617c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d620d3cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d620d3ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d620d218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d6209d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d6209d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff617c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff617c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff617c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d6209d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c (2633 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmul_vv_i16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmul_vx_i16mf4(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmul_vv_i16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmul_vx_i16mf2(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmul_vv_i16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmul_vx_i16m1(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmul_vv_i16m2(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmul_vx_i16m2(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmul_vv_i16m4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmul_vx_i16m4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | def
# | ...
# `---data was truncated (10240/68073) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055599467eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055599467be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055599467f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f51b0105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f51b015c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f51b0105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f51b00ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555994614bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555994614a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005559945f98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005559942a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005559942a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f51b00eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51b00ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51b00ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005559942a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c (2634 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_v
# | ...
# `---data was truncated (10240/228865) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555ccb3c6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555ccb3c3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555ccb3c762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff72b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff72b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff72b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff72b831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555ccb35cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555ccb35ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555ccb3418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555ccaff0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555ccaff0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff72b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff72b8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff72b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555ccaff0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c (2635 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ca92514eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ca92511e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ca9251562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7479b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7479b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7479b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7479b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ca924aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ca924aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ca9248f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ca9213ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ca9213eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7479b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7479b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7479b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ca9213ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c (2636 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvt_f_f_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvt_f_f_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvt_f_f_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvt_f_f_v_f32m8_tu(<vscale x 16 x float> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwcvt_f_f_v_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vfwcvt_f_f_v_f64m2_tu(<vscale x 2 x double> %maskedoff, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x double>, align 8
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vfwcvt_f_f_v_f64m4_tu(<vscale x 4 x double> %maskedoff, <vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x double>, align 8
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vfwcvt_f_f_v_f64m8_tu(<vscale x 8 x double> %maskedoff, <vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x double>, align 8
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2_tum(<vscale x 1 x i1> %mask, <vscale x 1 x float> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = al
# | ...
# `---data was truncated (10240/41670) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fe109dceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fe109d9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fe109dd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f74649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f746a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f74649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f74631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fe10972bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fe10972a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fe109578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fe10606e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fe10606b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2f74632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f746330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f746330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fe10606a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c (2637 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_u64m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ff8c5aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ff8c5a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ff8c5ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f64acf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f64acf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f64acf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f64acf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ff8c542bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ff8c542a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ff8c5278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ff8c1d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ff8c1d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f64acf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f64acf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f64acf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ff8c1d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c (2638 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f0e92d7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f0e92d4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f0e92d862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fda25333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fda2538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fda25333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fda2531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f0e926dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f0e926da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f0e92528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f0e8f01e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f0e8f01b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fda2531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fda2531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fda2531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f0e8f01a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c (2639 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_i8mf8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_i8mf4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8_v_i8mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8_v_i8m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8_v_i8m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8_v_i8m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8_v_i8m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_u8mf8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_u8mf4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8_v_u8mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8_v_u8m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8_v_u8m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8_v_u8m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8_v_u8m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_i8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_i8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %
# | ...
# `---data was truncated (10240/21774) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c2baa9feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c2baa9ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c2baaa062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0090249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f00902a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0090249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0090231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c2baa35bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c2baa35a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c2baa1a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c2ba6c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c2ba6c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0090232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f00902330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f00902330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c2ba6c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c (2640 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_u_u_w4_u8m8_u8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.u.u.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.u.u.i64.nxv64i8.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559cdc73beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559cdc738e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559cdc73c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f440c105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f440c15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f440c105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f440c0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559cdc6d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559cdc6d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559cdc6b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559cdc365e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559cdc365b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f440c0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f440c0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f440c0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559cdc365a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c (2641 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_f32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_i32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_i32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_i32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_u32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base
# | ...
# `---data was truncated (10240/60683) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561d92ad3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561d92ad0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561d92ad462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ed9049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ed90a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ed9049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ed9031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561d92a69bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561d92a69a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561d92a4e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561d926fde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561d926fdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5ed9032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ed90330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ed90330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561d926fda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c (2642 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte8_i8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte8.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vlte8.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte8_u8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte8.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b27855deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b27855ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b27855e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b71133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b7118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b71133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b7111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b2784f3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b2784f3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b2784d88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b278187e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b278187b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5b7111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b7111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b7111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b278187a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c (2643 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvsintload -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vln8_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.nds.vln.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vln.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vln8_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.nds.vln.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vln.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vln8_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.nds.vln.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vln.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vln8_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.nds.vln.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vln.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vln8_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.nds.vln.nxv16i8.p0.i64(<vscale x 16 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.nds.vln.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i8> @test_nds_vln8_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.nds.vln.nxv32i8.p0.i64(<vscale x 32 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.nds.vln.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_nds_vln8_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.nds.vln.nxv64i8.p0.i64(<vscale x 64 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.nds.vln.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vln8_v_i8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8> %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vln8_v_i8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8> %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vln8_v_i8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64(<vscale x 4 x i8> %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x i8>
# | ...
# `---data was truncated (10240/29371) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005566b8c99eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005566b8c96e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005566b8c9a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ffc533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ffc58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ffc533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ffc51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005566b8c2fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005566b8c2fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005566b8c148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005566b88c3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005566b88c3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4ffc51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ffc51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ffc51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005566b88c3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c (2644 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_f32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_f32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_i32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_i32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_u32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_u32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounw
# | ...
# `---data was truncated (10240/15952) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555e241a4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555e241a1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555e241a562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2afd905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2afd95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2afd905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2afd8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555e2413abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555e2413aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555e2411f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555e23dcee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555e23dceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2afd8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2afd8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2afd8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555e23dcea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c (2645 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i32> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i32> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale
# | ...
# `---data was truncated (10240/13161) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed548d1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ed548cee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ed548d262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5067049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f50670a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5067049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5067031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed54867bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ed54867a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ed5484c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ed544fbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ed544fbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5067032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f50670330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f50670330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed544fba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c (2646 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmacc_4x8x4_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmacc_4x8x4_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmacc_4x8x4_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmacc_4x8x4_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cf2d485eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cf2d482e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cf2d48662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f220bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f220bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f220bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f220bb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf2d41bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cf2d41ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cf2d4008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cf2d0afe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cf2d0afb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f220bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f220bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f220bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf2d0afa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c (2647 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_f16mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_f16mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_f16m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_f16m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_i16mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_i16mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_i16m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_i16m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_u16mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_u16mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local vo
# | ...
# `---data was truncated (10240/26928) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005577df4fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005577df4f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005577df4fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5911933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f591198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5911933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f591191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005577df492bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005577df492a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005577df4778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005577df126e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005577df126b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f591191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f591191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f591191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005577df126a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c (2648 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfadd_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfadd_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfadd_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfadd_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfadd_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfadd_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfadd_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfadd_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfa
# | ...
# `---data was truncated (10240/65574) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558bf0ed8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558bf0ed5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558bf0ed962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc014c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc014ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc014c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc014c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558bf0e6ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558bf0e6ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558bf0e538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558bf0b02e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558bf0b02b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc014c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc014c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc014c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558bf0b02a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vld24.c (2649 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vld24.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | %struct.float16x8x2_t = type { [2 x <8 x half>] }
# | %struct.uint8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.uint32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.int8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.uint16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.int32x4x2_t = type { [2 x <4 x i32>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc %struct.float16x8x2_t @test_vld2q_f16(ptr noundef %addr) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = call { <8 x half>, <8 x half> } @llvm.arm.mve.vld2q.v8f16.p0(ptr %0)
# |   %2 = extractvalue { <8 x half>, <8 x half> } %1, 0
# |   %3 = insertvalue %struct.float16x8x2_t poison, <8 x half> %2, 0, 0
# |   %4 = extractvalue { <8 x half>, <8 x half> } %1, 1
# |   %5 = insertvalue %struct.float16x8x2_t %3, <8 x half> %4, 0, 1
# |   ret %struct.float16x8x2_t %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <8 x half>, <8 x half> } @llvm.arm.mve.vld2q.v8f16.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc %struct.uint8x16x4_t @test_vld4q_u8(ptr noundef %addr) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.mve.vld4q.v16i8.p0(ptr %0)
# |   %2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 0
# |   %3 = insertvalue %struct.uint8x16x4_t poison, <16 x i8> %2, 0, 0
# |   %4 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 1
# |   %5 = insertvalue %struct.uint8x16x4_t %3, <16 x i8> %4, 0, 1
# |   %6 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 2
# |   %7 = insertvalue %struct.uint8x16x4_t %5, <16 x i8> %6, 0, 2
# |   %8 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 3
# |   %9 = insertvalue %struct.uint8x16x4_t %7, <16 x i8> %8, 0, 3
# |   ret %struct.uint8x16x4_t %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.mve.vld4q.v16i8.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc void @test_vst2q_u32(ptr noundef %addr, %struct.uint32x4x2_t %value.coerce) #0 {
# | entry:
# |   %value = alloca %struct.uint32x4x2_t, align 8
# |   %addr.addr = alloca ptr, align 4
# |   %tmp = alloca %struct.uint32x4x2_t, align 8
# |   %0 = getelementptr inbounds nuw %struct.uint32x4x2_t, ptr %value, i32 0, i32 0
# |   %1 = extractvalue %struct.uint32x4x2_t %value.coerce, 0
# |   store [2 x <4 x i32>] %1, ptr %0, align 8
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %2 = load ptr, ptr %addr.addr, align 4
# |   call void @llvm.memcpy.p0.p0.i32(ptr align 8 %tmp, ptr align 8 %value, i32 32, i1 false)
# |   %3 = load %struct.uint32x4x2_t, ptr %tmp, align 8
# |   %4 = extractvalue %struct.uint32x4x2_t %3, 0, 0
# |   %5 = extractvalue %struct.uint32x4x2_t %3, 0, 1
# |   call void @llvm.arm.mve.vst2q.p0.v4i32(ptr %2, <4 x i32> %4, <4 x i32> %5, i32 0)
# |   call void @llvm.arm.mve.vst2q.p0.v4i32(ptr %2, <4 x i32> %4, <4 x i32> %5, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.memcpy.p0.p0.i32(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i32, i1 immarg) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.arm.mve.vst2q.p0.v4i32(ptr, <4 x i32>, <4 x i32>, i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc void @test_vst4q_s8(ptr noundef %addr, %struct.int8x16x4_t %value.coerce) #0 {
# | entry:
# |   %value = alloca %struct.int8x16x4_t, align 8
# |   %addr.addr = alloca ptr, align 4
# |   %tmp = alloca %struct.int8x16x4_t, align 8
# |   %0 = getelementptr inbounds nuw %struct.int8x16x4_t, ptr %value, i32 0, i32 0
# |   %1 = extractvalue %struct.int8x16x4_t %value.coerce, 0
# |   store [4 x <16 x i8>] %1, ptr %0, align 8
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %2 = load ptr, ptr %addr.addr, align 4
# |   call void @llvm.memcpy.p0.p0.i32(ptr align 8 %tmp, ptr align 8 %value, i32 64, i1 false)
# |   %3 = load %struct.int8x16x4_t, ptr %tmp, align 8
# |   %4 = extractvalue %struct.int8x16x4_t %3, 0, 0
# |   %5 = extractvalue %struct.int8x16x4_t %3, 0, 1
# |   %6 = extractvalue %struct.int8x16x4_t %3, 0, 2
# |   %7 = extractvalue %struct.int8x16x4_t %3, 0, 3
# |   call void @llvm.arm.mve.vst4q.p0.v16i8(ptr %2, <16 x i8> %4, <16 x i8> %5, <16 x i8> %6, <16 x i8> %7, i32 0)
# |   call void @llvm.arm.mve.vst4q.p0.v16i8(ptr %2, <16 x i8> %4, <16 x i8> %5, <16 x i8> %6, <16 x i8> %7, i32 1)
# |   call void @llvm.arm.mve.vst4q.p0.v16i8(ptr %2, <16 x i8> %4, <16 x i8> %5, <16 x i8> %6, <16 x i8> %7, i32 2)
# |   call void @llvm.arm.mve.vst4q.p0.v16i8(ptr %2, <16 x i8> %4, <16 x i8> %5, <16 x i8> %6, <16 x i8> %7, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.arm.mve.vst4q.p0.v16i8(ptr, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc void @test_vst2q_f16(ptr noundef %addr, %struct.float16x8x2_t %value.coerce) #0 {
# | entry:
# |   %value = alloca %struct.float16x8x2_t, align 8
# |   %addr.addr = alloca ptr, align 4
# |   %tmp = alloca %struct.float16x8x2_t, align 8
# |   %0 = getelementptr inbounds nuw %struct.float16x8x2_t, ptr %value, i32 0, i32 0
# |   %1 = extractvalue %struct.float16x8x2_t %value.coerce, 0
# |   store [2 x <8 x half>] %1, ptr %0, align 8
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %2 = load ptr, ptr %addr.addr, align 4
# |   call void @llvm.memcpy.p0.p0.i32(ptr align 8 %tmp, ptr align 8 %value, i32 32, i1 false)
# |   %3 = load %struct.float16x8x2_t, ptr %tmp, align 8
# |   %4 = extractvalue %struct.float16x8x2_t %3, 0, 0
# |   %5 = extractvalue %struct.float16x8x2_t %3, 0, 1
# |   call void @llvm.arm.mve.vst2q.p0.v8f16(ptr %2, <8 x half> %4, <8 x half> %5, i32 0)
# |   call void @llvm.arm.mve.vst2q.p0.v8f16(ptr %2, <8 x half> %4, <8 x half> %5, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.arm.mve.vst2q.p0.v8f16(ptr, <8 x half>, <8 x half>, i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc void @load_into_variable(ptr noundef %addr, ptr noundef %values) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   %values.addr = alloca ptr, align 4
# |   %v = alloca %struct.uint16x8x2_t, align 8
# |   %tmp = alloca %struct.uint16x8x2_t, align 8
# |   store ptr %addr, ptr %addr.addr, align 4
# |   store ptr %values, ptr %values.addr, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = call { <8 x i16>, <8 x i16> } @llvm.arm.mve.vld2q.v8i16.p0(ptr %0)
# |   %2 = extractvalue { <8 x i16>, <8 x i16> } %1, 0
# |   %3 = insertvalue %struct.uint16x8x2_t poison, <8 x i16> %2, 0, 0
# |   %4 = extractvalue { <8 x i16>, <8 x i16> } %1, 1
# |   %5 = insertvalue %struct.uint16x8x2_t %3, <8 x i16> %4, 0, 1
# |   store %struct.uint16x8x2_t %5, ptr %tmp, align 8
# |   call void @llvm.memcpy.p0.p0.i32(ptr align 8 %v, ptr align 8 %tmp, i32 32, i1 false)
# |   %val = getelementptr inbounds nuw %struct.uint16x8x2_t, ptr %v, i32 0, i32 0
# |   %arrayidx = getelementptr inbounds [2 x <8 x i16>], ptr %val, i32 0, i32 0
# |   %6 = load <8 x i16>, ptr %arrayidx, align 8
# |   %7 = load ptr, ptr %values.addr, align 4
# |   %arrayidx1 = getelementptr inbounds <8 x i16>, ptr %7, i32 0
# |   store <8 x i16> %6, ptr %arrayidx1, align 8
# |   %val2 = getelementptr inbounds nuw %struct.uint16x8x2_t, ptr %v, i32 0, i32 0
# |   %arrayidx3 = getelementptr inbounds [2 x <8 x i16>], ptr %val2, i32 0, i32 1
# |   %8 = load <8 x i16>, ptr %arrayidx3, align 8
# |   %9 = load ptr, ptr %values.addr, align 4
# |   %arrayidx4 = getelementptr inbounds <8 x i16>, ptr %9, i32 1
# |   store <8 x i16> %8, ptr %arrayidx4, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <8 x i16>, <8 x i16> } @llvm.arm.mve.vld2q.v8i16.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @extract_one_vector(ptr noundef %addr) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   %ref.tmp = alloca %struct.int32x4x2_t, align 8
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = call { <4 x i32>, <4 x i32> } @llvm.arm.mve.vld2q.v4i32.p0(ptr %0)
# |   %2 = extractvalue { <4 x i32>, <4 x i32> } %1, 0
# |   %3 = insertvalue %struct.int32x4x2_t poison, <4 x i32> %2, 0, 0
# |   %4 = extractvalue { <4 x i32>, <4 x i32> } %1, 1
# |   %5 = insertvalue %struct.int32x4x2_t %3, <4 x i32> %4, 0, 1
# |   store %struct.int32x4x2_t %5, ptr %ref.tmp, align 8
# |   %val = getelementptr inbounds nuw %struct.int32x4x2_t, ptr %ref.tmp, i32 0, i32 0
# |   %arrayidx = getelementptr inbounds [2 x <4 x i32>], ptr %val, i32 0, i32 0
# |   %6 = load <4 x i32>, ptr %arrayidx, align 8
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <4 x i32>, <4 x i32> } @llvm.arm.mve.vld2q.v4i32.p0(ptr) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
# | attributes #3 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>'
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<>
# |  #0 0x0000560432f95eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560432f92e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560432f9662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd162849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd1628a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd162849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd162831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560432f2bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560432f2ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560432f108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560432bbfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560432bbfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd162832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd1628330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd1628330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560432bbfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c (2650 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_f16mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_f16mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_f16m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_i16mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_i16mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_i16m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_u16mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_u16mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_u16m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_f16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsse
# | ...
# `---data was truncated (10240/20441) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562e4caedeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562e4caeae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562e4caee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2fd9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2fd9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2fd9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2fd9b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562e4ca83bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562e4ca83a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562e4ca688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562e4c717e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562e4c717b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2fd9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2fd9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2fd9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562e4c717a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c (2651 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055967c241eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055967c23ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055967c24262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6513649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f65136a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6513649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6513631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055967c1d7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055967c1d7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055967c1bc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055967be6be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055967be6bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6513632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f65136330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f65136330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055967be6ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c (2652 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vlse64_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64.p0.i64(<vscale x 1 x double> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vlse64_v_f64m2_tu(<vscale x 2 x double> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64.p0.i64(<vscale x 2 x double> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vlse64_v_f64m4_tu(<vscale x 4 x double> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64.p0.i64(<vscale x 4 x double> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vlse64_v_f64m8_tu(<vscale x 8 x double> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64.p0.i64(<vscale x 8 x double> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vlse64_v_i64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vlse64_v_i64m2_tu(<vscale x 2 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.p0.i64(<vscale x 2 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vlse64_v_i64m4_tu(<vscale x 4 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.p0.i64(<vscale x 4 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vlse64_v_i64m8_tu(<vscale x 8 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.p0.i64(<vscale x 8 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vlse64_v_u64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale 
# | ...
# `---data was truncated (10240/56179) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055661fca9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055661fca6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055661fcaa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb5cac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb5caca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb5cac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb5cac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055661fc3fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055661fc3fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055661fc248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055661f8d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055661f8d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb5cac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb5cac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb5cac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055661f8d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c (2653 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_xu_f_qf_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %1, <vscale x 1 x float> %2, float %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %1, <vscale x 2 x float> %2, float %3, <vscale x 2 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   
# | ...
# `---data was truncated (10240/26748) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560efc55beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560efc558e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560efc55c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3e3ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3e3ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3e3ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3e3ed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560efc4f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560efc4f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560efc4d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560efc185e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560efc185b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3e3ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3e3ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3e3ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560efc185a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/WebAssembly/builtins-table-funcref.c (2654 of 27911)
******************** TEST 'Clang :: CodeGen/WebAssembly/builtins-table-funcref.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple wasm32 -target-feature +reference-types -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple wasm32 -target-feature +reference-types -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c"
# | target datalayout = "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-i128:128-n32:64-S128-ni:1:10:20"
# | target triple = "wasm32"
# | 
# | @table = internal addrspace(1) global [0 x target("wasm.funcref")] zeroinitializer, align 4
# | @other_table = internal addrspace(1) global [0 x target("wasm.funcref")] zeroinitializer, align 4
# | 
# | ; Function Attrs: noinline nounwind
# | define target("wasm.funcref") @test_builtin_wasm_table_get(i32 noundef %index) #0 {
# | entry:
# |   %index.addr = alloca i32, align 4
# |   store i32 %index, ptr %index.addr, align 4
# |   %0 = load i32, ptr %index.addr, align 4
# |   %1 = call target("wasm.funcref") @llvm.wasm.table.get.funcref(ptr addrspace(1) @table, i32 %0)
# |   ret target("wasm.funcref") %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("wasm.funcref") @llvm.wasm.table.get.funcref(ptr addrspace(1), i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define void @test_builtin_wasm_table_set(i32 noundef %index, target("wasm.funcref") noundef %ref) #0 {
# | entry:
# |   %index.addr = alloca i32, align 4
# |   %ref.addr = alloca target("wasm.funcref"), align 4
# |   store i32 %index, ptr %index.addr, align 4
# |   store target("wasm.funcref") %ref, ptr %ref.addr, align 4
# |   %0 = load i32, ptr %index.addr, align 4
# |   %1 = load target("wasm.funcref"), ptr %ref.addr, align 4
# |   call void @llvm.wasm.table.set.funcref(ptr addrspace(1) @table, i32 %0, target("wasm.funcref") %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.wasm.table.set.funcref(ptr addrspace(1), i32, target("wasm.funcref")) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define i32 @test_builtin_wasm_table_size() #0 {
# | entry:
# |   %0 = call i32 @llvm.wasm.table.size(ptr addrspace(1) @table)
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare i32 @llvm.wasm.table.size(ptr addrspace(1)) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define i32 @test_builtin_wasm_table_grow(target("wasm.funcref") noundef %ref, i32 noundef %nelem) #0 {
# | entry:
# |   %ref.addr = alloca target("wasm.funcref"), align 4
# |   %nelem.addr = alloca i32, align 4
# |   store target("wasm.funcref") %ref, ptr %ref.addr, align 4
# |   store i32 %nelem, ptr %nelem.addr, align 4
# |   %0 = load target("wasm.funcref"), ptr %ref.addr, align 4
# |   %1 = load i32, ptr %nelem.addr, align 4
# |   %2 = call i32 @llvm.wasm.table.grow.funcref(ptr addrspace(1) @table, target("wasm.funcref") %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare i32 @llvm.wasm.table.grow.funcref(ptr addrspace(1), target("wasm.funcref"), i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define void @test_builtin_wasm_table_fill(i32 noundef %index, target("wasm.funcref") noundef %ref, i32 noundef %nelem) #0 {
# | entry:
# |   %index.addr = alloca i32, align 4
# |   %ref.addr = alloca target("wasm.funcref"), align 4
# |   %nelem.addr = alloca i32, align 4
# |   store i32 %index, ptr %index.addr, align 4
# |   store target("wasm.funcref") %ref, ptr %ref.addr, align 4
# |   store i32 %nelem, ptr %nelem.addr, align 4
# |   %0 = load i32, ptr %index.addr, align 4
# |   %1 = load target("wasm.funcref"), ptr %ref.addr, align 4
# |   %2 = load i32, ptr %nelem.addr, align 4
# |   call void @llvm.wasm.table.fill.funcref(ptr addrspace(1) @table, i32 %0, target("wasm.funcref") %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.wasm.table.fill.funcref(ptr addrspace(1), i32, target("wasm.funcref"), i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define void @test_table_copy(i32 noundef %dst_idx, i32 noundef %src_idx, i32 noundef %nelem) #0 {
# | entry:
# |   %dst_idx.addr = alloca i32, align 4
# |   %src_idx.addr = alloca i32, align 4
# |   %nelem.addr = alloca i32, align 4
# |   store i32 %dst_idx, ptr %dst_idx.addr, align 4
# |   store i32 %src_idx, ptr %src_idx.addr, align 4
# |   store i32 %nelem, ptr %nelem.addr, align 4
# |   %0 = load i32, ptr %dst_idx.addr, align 4
# |   %1 = load i32, ptr %src_idx.addr, align 4
# |   %2 = load i32, ptr %nelem.addr, align 4
# |   call void @llvm.wasm.table.copy(ptr addrspace(1) @table, ptr addrspace(1) @other_table, i32 %1, i32 %0, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.wasm.table.copy(ptr addrspace(1), ptr addrspace(1), i32, i32, i32) #3
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+reference-types" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | attributes #3 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564954b01eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564954afee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564954b0262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f36a8849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f36a88a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f36a8849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f36a8831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564954a97bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564954a97a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564954a7c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056495472be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056495472bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f36a8832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f36a88330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f36a88330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056495472ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c (2655 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmacc_vv_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmacc_vx_i8mf8_tu(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmacc_vv_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmacc_vx_i8mf4_tu(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmacc_vv_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmacc_vx_i8mf2_tu(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmacc_vv_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmacc_vx_i8m1_tu(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmacc_vv_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8
# | ...
# `---data was truncated (10240/414525) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005563b1d79eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005563b1d76e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005563b1d7a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f479cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f479cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f479cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f479cb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005563b1d0fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005563b1d0fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005563b1cf48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005563b19a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005563b19a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f479cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f479cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f479cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005563b19a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c (2656 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccus_vx_i16mf4_tu(<vscale x 1 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccus_vx_i16mf2_tu(<vscale x 2 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccus_vx_i16m1_tu(<vscale x 4 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccus_vx_i16m2_tu(<vscale x 8 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccus_vx_i16m4_tu(<vscale x 16 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16>, i8, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwmaccus_vx_i16m8_tu(<vscale x 32 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 32 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16>, i8, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwmaccus_vx_i32mf2_tu(<vscale x 1 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32>, i16, <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwmaccus_vx_i32m1_tu(<vscale x 2 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32>, i16, <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwmaccus_vx_i32m2_tu(<vscale x 4 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, pt
# | ...
# `---data was truncated (10240/73955) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563d15f88eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563d15f85e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563d15f8962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6282f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6282f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6282f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6282f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d15f1ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563d15f1ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563d15f038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563d15bb2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563d15bb2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6282f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6282f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6282f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d15bb2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c (2657 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564d2475eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564d2475be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564d2475f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd448849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd4488a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd448849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd448831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d246f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564d246f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564d246d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564d24388e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564d24388b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd448832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd4488330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd4488330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d24388a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c (2658 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmnand_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmnand_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmnand_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmnand_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmnand_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmnand_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmnand_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cfbd332eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cfbd32fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cfbd33362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0b93649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0b936a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0b93649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0b93631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cfbd2c8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cfbd2c8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cfbd2ad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cfbcf5ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cfbcf5cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0b93632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0b936330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0b936330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cfbcf5ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/zksed.c (2659 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/zksed.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zksed -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c  -check-prefix=RV32ZKSED
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zksed -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sm4ks(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   %2 = call i32 @llvm.riscv.sm4ks(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sm4ks(i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sm4ed(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   %2 = call i32 @llvm.riscv.sm4ed(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sm4ed(i32, i32, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zksed" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zksed1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562bfa906eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562bfa903e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562bfa90762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9ddfd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9ddfd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9ddfd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9ddfd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562bfa89cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562bfa89ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562bfa8818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562bfa530e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562bfa530b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9ddfd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9ddfd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9ddfd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562bfa530a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c -check-prefix=RV32ZKSED
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c -check-prefix=RV32ZKSED
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c (2660 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16m1x2(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16m2x2(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16m4x2(ptr noundef %base, <vscale x 16 x i8> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f32m1x2(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f32m2x2(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>,
# | ...
# `---data was truncated (10240/128444) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562caf65ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562caf659e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562caf65d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbeb0505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbeb055c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbeb0505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbeb04ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562caf5f2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562caf5f2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562caf5d78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562caf286e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562caf286b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbeb04eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbeb04ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbeb04ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562caf286a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c (2661 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16mf4x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16mf2x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16m1x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055febeba1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055febeb9ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055febeba262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd5a01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd5a0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd5a01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd5a003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055febeb37bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055febeb37a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055febeb1c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055febe7cbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055febe7cbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbd5a004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd5a0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd5a0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055febe7cba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c (2662 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvt_f_f_v_f32m1(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvt_f_f_v_f32m2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvt_f_f_v_f32m4(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvt_f_f_v_f32m8(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwcvt_f_f_v_f64m1(<vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vfwcvt_f_f_v_f64m2(<vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vfwcvt_f_f_v_f64m4(<vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vfwcvt_f_f_v_f64m8(<vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2_m(<vscale x 1 x i1> %mask, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvt_f_f_v_f32m1_m(<vscale x 2 x i1> %mask, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvt_f_f_v_f32m2_m(<vscale x 4 x i1> %mask, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entr
# | ...
# `---data was truncated (10240/18361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b2d5dc7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b2d5dc4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b2d5dc862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f30e261bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f30e26725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f30e261ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f30e2603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b2d5d5dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b2d5d5da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b2d5d428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b2d59f1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b2d59f1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f30e2604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f30e26050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f30e26050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b2d59f1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c (2663 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_i64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_u64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_i64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_u64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.ve
# | ...
# `---data was truncated (10240/18498) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055861b3fdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055861b3fae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055861b3fe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa243a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa243aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa243a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa243a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055861b393bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055861b393a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055861b3788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055861b027e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055861b027b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa243a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa243a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa243a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055861b027a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c (2664 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmacc_4x8x4_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmacc_4x8x4_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmacc_4x8x4_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmacc_4x8x4_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556fbedf1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556fbedeee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556fbedf262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1abd849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1abd8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1abd849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1abd831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556fbed87bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556fbed87a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556fbed6c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556fbea1be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556fbea1bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1abd832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1abd8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1abd8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556fbea1ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c (2665 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmax_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmax_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmax_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 
# | ...
# `---data was truncated (10240/52607) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec973d2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ec973cfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ec973d362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6093905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f609395c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6093905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f60938ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec97368bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ec97368a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ec9734d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ec96ffce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ec96ffcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f60938eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f60938ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f60938ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec96ffca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c (2666 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4a_vx_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4a_vx_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | defi
# | ...
# `---data was truncated (10240/13593) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055880c488eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055880c485e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055880c48962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9106933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f910698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9106933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f910691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055880c41ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055880c41ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055880c4038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055880c0b2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055880c0b2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f910691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f910691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f910691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055880c0b2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c (2667 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005606e50ceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005606e50cbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005606e50cf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0402d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0402d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0402d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0402d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005606e5064bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005606e5064a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005606e50498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005606e4cf8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005606e4cf8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0402d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0402d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0402d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005606e4cf8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c (2668 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsub_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsub_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsub_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsub_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsub_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrsub_vf_bf16m8(<vscale x 32 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsub_vf_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsub_vf_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsub.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsub.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsub_vf_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsub.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsub.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64 immar
# | ...
# `---data was truncated (10240/14780) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b53439feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b53439ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b5343a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f85d0249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f85d02a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f85d0249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f85d0231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b534335bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b534335a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b53431a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b533fc9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b533fc9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f85d0232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f85d02330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f85d02330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b533fc9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c (2669 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1f32.p0.i64(<vscale x 1 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32m1(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2f32.p0.i64(<vscale x 2 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32m2(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4f32.p0.i64(<vscale x 4 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32m4(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8f32.p0.i64(<vscale x 8 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32m8(ptr noundef %base, i64 noundef %bstride, <vscale x 16 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 16 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 16 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv16f32.p0.i64(<vscale x 16 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i32.p0.i64(<vscale x 1 x i32> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32m1(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i32.p0.i64(<vscale x 2 x i32> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32m2(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i32.p0.i64(<vscale x 4 x i32> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32m4(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8i32.p0.i64(<vscale x 8 x i32> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32m8(ptr noundef %base, i64 noundef %bstride, <vscale x 16 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 16 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, p
# | ...
# `---data was truncated (10240/33198) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d09fdb9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d09fdb6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d09fdba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f38a5133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f38a518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f38a5133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f38a511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d09fd4fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d09fd4fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d09fd348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d09f9e3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d09f9e3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f38a511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f38a511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f38a511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d09f9e3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c (2670 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_i16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_i16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vsc
# | ...
# `---data was truncated (10240/88436) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cf8dcf3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cf8dcf0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cf8dcf462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f353e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f353e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f353e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f353e91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf8dc89bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cf8dc89a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cf8dc6e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cf8d91de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cf8d91db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f353e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f353e91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f353e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf8d91da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c (2671 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrsqrt7_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrsqrt7_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrsqrt7_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrsqrt7_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrsqrt7_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrsqrt7_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrsqrt7_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrsqrt7_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrsqrt7_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrsqrt7_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfrsqrt7.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfrsqrt7.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfrsqrt7_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfrsqrt7.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfrsqrt7.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfrsqrt7_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfrsqrt7.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfrsqrt7.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vfrsqrt7_v_f64m2(<vscale x 2 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double
# | ...
# `---data was truncated (10240/29119) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565057158eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565057155e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056505715962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fae4e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fae4e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fae4e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fae4e231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005650570eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005650570eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005650570d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565056d82e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565056d82b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fae4e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fae4e2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fae4e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565056d82a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c (2672 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmin_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmin_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmin_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmin_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmin_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmin_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmin_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmin_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmin_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i6
# | ...
# `---data was truncated (10240/157165) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561495b8beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561495b88e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561495b8c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca38105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca3815c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca38105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca380ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561495b21bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561495b21a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561495b068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005614957b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005614957b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fca380eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca380ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca380ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005614957b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c (2673 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f16m1x8(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f32m1x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f64m1x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei16_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005585b63ceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005585b63cbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005585b63cf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f01e7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f01e778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f01e7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f01e771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005585b6364bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005585b6364a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005585b63498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005585b5ff8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005585b5ff8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f01e771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f01e771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f01e771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005585b5ff8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c (2674 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005582f293deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005582f293ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005582f293e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3121c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3121ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3121c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3121c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005582f28d3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005582f28d3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005582f28b88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005582f2567e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005582f2567b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3121c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3121c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3121c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005582f2567a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c (2675 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_f16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_f16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_f16m1x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_i16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_i16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_i16m1x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_u16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_u16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_u16m1x6_m(<vs
# | ...
# `---data was truncated (10240/11851) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005625672cceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005625672c9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005625672cd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9a0fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9a0fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9a0fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9a0fd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562567262bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562567262a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005625672478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562566ef6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562566ef6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9a0fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9a0fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9a0fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562566ef6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c (2676 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_i8mf8_u8mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_i8mf4_u8mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_i8mf2_u8mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_i8m1_u8m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_i8m2_u8m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_i8m4_u8m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_i8m8_u8m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_u8mf8_i8mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_u8mf4_i8mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u8mf2_i8mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_i8m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_i8m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_i8m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_i8m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vreinterpret_v_i16mf4_f16mf4(<vscale x 1 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x i16> %0 to <vscale x 1 x half>
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vreinterpret_v_i16mf2_f16mf2(<vscale x 2 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x i16> %0 to <vscale x 2 x half>
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vreinterpret_v_i16m1_f16m1(<vscale x 4 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x i16> %0 to <vscale x 4 x half>
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vreinterpret_v_i16m2_f16m2(<vscale x 8 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 8 x half>
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vreinterpret_v_i16m4_f16m4(<vscale x 16 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x i16> %0 to <vscale x 16 x half>
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vreinterpret_v_i16m8_f16m8(<vscale x 32 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 32 x i16> %0 to <vscale x 32 x half>
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vreinterpret_v_u16mf4_f16mf4(<vscale x 1 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x i16> %0 to <vscale x 1 x half>
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vreinterpret_v_u16mf2_f16mf2(<vscale x 2 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x i16> %0 to <vscale x 2 x half>
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vreinterpret_v_u16m1_f16m1(<vscale x 4 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x i16> %0 to <vscale x 4 x half>
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vreinterpret_v_u16m2_f16m2(<vscale x 8 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 8 x half>
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vreinterpret_v_u16m4_f16m4(<vscale x 16 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x i16> %0 to <vscale x 16 x half>
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vreinterpret_v_u16m8_f16m8(<vscale x 32 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |  
# | ...
# `---data was truncated (10240/136489) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560ca50a3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560ca50a0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560ca50a462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9974449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f99744a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9974449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9974431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ca5039bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560ca5039a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560ca501e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560ca4ccde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560ca4ccdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9974432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f99744330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f99744330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ca4ccda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c (2677 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_i8mf8x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8ff_v_i8mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8ff_v_i8mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8ff_v_i8m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_u8mf8x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8ff_v_u8mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8ff_v_u8mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8ff_v_u8m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %m
# | ...
# `---data was truncated (10240/22258) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056095fabdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056095fabae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056095fabe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f16b5b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f16b5b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f16b5b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f16b5b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056095fa53bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056095fa53a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056095fa388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056095f6e7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056095f6e7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f16b5b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f16b5b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f16b5b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056095f6e7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c (2678 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3e
# | ...
# `---data was truncated (10240/216250) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056430238feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056430238ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056430239062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc6c5333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc6c538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc6c5333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc6c531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564302325bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564302325a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056430230a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564301fb9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564301fb9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc6c531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc6c531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc6c531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564301fb9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c (2679 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvt_rod_f_f_w_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvt_rod_f_f_w_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvt_rod_f_f_w_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvt_rod_f_f_w_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvt_rod_f_f_w_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# | 
# | ...
# `---data was truncated (10240/23255) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056496457beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564964578e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056496457c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7ba2049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7ba20a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7ba2049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7ba2031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564964511bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564964511a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005649644f68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005649641a5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005649641a5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7ba2032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7ba20330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7ba20330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005649641a5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm64-crc32.c (2680 of 27911)
******************** TEST 'Clang :: CodeGen/arm64-crc32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +crc   -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +crc -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32b(i32 noundef %a, i8 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i8, align 1
# |   store i32 %a, ptr %a.addr, align 4
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i8, ptr %b.addr, align 1
# |   %2 = zext i8 %1 to i32
# |   %3 = call i32 @llvm.aarch64.crc32b(i32 %0, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.crc32b(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32cb(i32 noundef %a, i8 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i8, align 1
# |   store i32 %a, ptr %a.addr, align 4
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i8, ptr %b.addr, align 1
# |   %2 = zext i8 %1 to i32
# |   %3 = call i32 @llvm.aarch64.crc32cb(i32 %0, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.crc32cb(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32h(i32 noundef %a, i16 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i16, ptr %b.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call i32 @llvm.aarch64.crc32h(i32 %0, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.crc32h(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32ch(i32 noundef %a, i16 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i16, ptr %b.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call i32 @llvm.aarch64.crc32ch(i32 %0, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.crc32ch(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32w(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.aarch64.crc32w(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.crc32w(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32cw(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.aarch64.crc32cw(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.crc32cw(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32d(i32 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i64, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i64, ptr %b.addr, align 8
# |   %2 = call i32 @llvm.aarch64.crc32x(i32 %0, i64 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.crc32x(i32, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32cd(i32 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i64, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i64, ptr %b.addr, align 8
# |   %2 = call i32 @llvm.aarch64.crc32cx(i32 %0, i64 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.crc32cx(i32, i64) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d9ad03feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d9ad03ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d9ad04062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff4bf049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff4bf0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff4bf049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff4bf031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d9acfd5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d9acfd5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d9acfba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d9acc69e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d9acc69b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff4bf032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff4bf0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff4bf0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d9acc69a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c (2681 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vset_v_i8m1_i8m2(<vscale x 16 x i8> %dest, i64 noundef %index, <vscale x 8 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 16 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 0)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8>, <vscale x 8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vset_v_i8m1_i8m4(<vscale x 32 x i8> %dest, i64 noundef %index, <vscale x 8 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 32 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv8i8(<vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 0)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv8i8(<vscale x 32 x i8>, <vscale x 8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vset_v_i8m2_i8m4(<vscale x 32 x i8> %dest, i64 noundef %index, <vscale x 16 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 32 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 16 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv16i8(<vscale x 32 x i8> %0, <vscale x 16 x i8> %1, i64 0)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv16i8(<vscale x 32 x i8>, <vscale x 16 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vset_v_i8m1_i8m8(<vscale x 64 x i8> %dest, i64 noundef %index, <vscale x 8 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 64 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv8i8(<vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 0)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv8i8(<vscale x 64 x i8>, <vscale x 8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vset_v_i8m2_i8m8(<vscale x 64 x i8> %dest, i64 noundef %index, <vscale x 16 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 64 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 16 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8> %0, <vscale x 16 x i8> %1, i64 0)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8>, <vscale x 16 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vset_v_i8m4_i8m8(<vscale x 64 x i8> %dest, i64 noundef %index, <vscale x 32 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 64 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 32 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv32i8(<vscale x 64 x i8> %0, <vscale x 32 x i8> %1, i64 0)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv32i8(<vscale x 64 x i8>, <vscale x 32 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vset_v_u8m1_u8m2(<vscale x 16 x i8> %dest, i64 noundef %index, <vscale x 8 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 16 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 0)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vset_v_u8m1_u8m4(<vscale x 32 x i8> %dest, i64 noundef %index, <vscale x 8 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 32 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv8i8(<vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 0)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vset_v_u8m2_u8m4(<vscale x 32 x i8> %dest, i64 noundef %index, <vscale x 16 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 32 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 16 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv16i8(<vscale x 32 x i8> %0, <vscale x 16 x i8> %1, i64 0)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vset_v_u8m1_u8m8(<vscale x 64 x i8> %dest, i64 noundef %index, <vscale x 8 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 64 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv8i8(<vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 0)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vset_v_u8m2_u8m8(<vscale x 64 x i8> %dest, i64 noundef %index, <vscale x 16 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 64 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 16 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8> %0, <vscale x 16 x i8> %1, i64 0)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vset_v_u8m4_u8m8(<vscale x 64 x i8> %dest, i64 noundef %index, <vscale x 32 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 64 x i8> %dest, p
# | ...
# `---data was truncated (10240/54546) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee39722eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ee3971fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ee3972362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5131d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5131d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5131d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5131d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee396b8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ee396b8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ee3969d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ee3934ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ee3934cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5131d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5131d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5131d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee3934ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c (2682 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_f64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_i64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_u64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556500985eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556500982e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055650098662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f68fc933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f68fc98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f68fc933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f68fc91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055650091bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055650091ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005565009008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005565005afe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005565005afb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f68fc91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f68fc91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f68fc91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005565005afa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c (2683 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlse16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlse16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlse16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vlse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vlse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlse16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vlse.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat> poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vlse.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlse16_v_bf16m4_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vlse.mask.nxv16bf16.p0.i64(<vscale x 16 x bfloat> poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vlse.mask.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlse16_v_bf16m8_m(<vscale x 32 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 32 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vlse.mask.nxv32bf16.p0.i64(<vscale x 32 x bfloat> poison, ptr %1, i64 %2, <vscale x 32 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vlse.mask.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64, <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dafd9d7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dafd9d4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dafd9d862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f63b5049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f63b50a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f63b5049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f63b5031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dafd96dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dafd96da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dafd9528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dafd601e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dafd601b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f63b5032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f63b50330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f63b50330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dafd601a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c (2684 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055713d297eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055713d294e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055713d29862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2efa533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2efa58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2efa533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2efa51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055713d22dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055713d22da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055713d2128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055713cec1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055713cec1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2efa51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2efa51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2efa51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055713cec1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c (2685 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei32_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei32_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei32_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Fun
# | ...
# `---data was truncated (10240/12067) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b81cf74eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b81cf71e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b81cf7562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f294e505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f294e55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f294e505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f294e4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b81cf0abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b81cf0aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b81ceef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b81cb9ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b81cb9eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f294e4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f294e4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f294e4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b81cb9ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c (2686 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_f32m2x4_tu(target("riscv.vector.tuple", <vscale x 1
# | ...
# `---data was truncated (10240/227763) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bb20fbceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bb20fb9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bb20fbd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb23fa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb23fa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb23fa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb23fa03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bb20f52bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bb20f52a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bb20f378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bb20be6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bb20be6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb23fa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb23fa050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb23fa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bb20be6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c (2687 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_i16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_i16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_i16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_i16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_
# | ...
# `---data was truncated (10240/63061) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559c20fe9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559c20fe6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559c20fea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f90e381bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f90e38725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f90e381ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f90e3803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c20f7fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559c20f7fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559c20f648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559c20c13e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559c20c13b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f90e3804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f90e38050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f90e38050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c20c13a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c (2688 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16ff_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(<vscale x 1 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(<vscale x 1 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16ff_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(<vscale x 2 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(<vscale x 2 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16ff_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(<vscale x 4 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(<vscale x 4 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16ff_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(<vscale x 8 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(<vscale x 8 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16ff_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(<vscale x 16 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 16 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 16 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(<vscale x 16 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16ff_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(<vscale x 32 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 32 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 32 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(<vscale x 32 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16ff_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   %6 = extractvalue { <vscale x 1 x bfloat>, i64 } %5, 0
# |   %7 = extractvalue { <vscale x 1 x bfloat>, i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret <vscale x 1 x bfloat> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16ff_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(<vscale x 2
# | ...
# `---data was truncated (10240/32198) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558bbb8f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558bbb8f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558bbb8fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ede733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ede78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ede733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ede71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558bbb88fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558bbb88fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558bbb8748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558bbb523e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558bbb523b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5ede71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ede71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ede71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558bbb523a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c (2689 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf8_u16m1(<vscale x 1 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> poison, <vscale x 1 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16>, <vscale x 1 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf4_u16m1(<vscale x 2 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> poison, <vscale x 2 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16>, <vscale x 2 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf2_u16m1(<vscale x 4 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m1_u16m1(<vscale x 8 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> poison, <vscale x 8 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16>, <vscale x 8 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m2_u16m1(<vscale x 16 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> poison, <vscale x 16 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16>, <vscale x 16 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m4_u16m1(<vscale x 32 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> poison, <vscale x 32 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16>, <vscale x 32 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m8_u16m1(<vscale x 64 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> poison, <vscale x 64 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16>, <vscale x 64 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsumu_vs_u16mf4_u32m1(<vscale x 1 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv1i16.i64(<vscale x 2 x i32> poison, <vscale x 1 x i16> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv1i16.i64(<vscale x 2 x i32>, <vscale x 1 x i16>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsumu_vs_u16mf2_u32m1(<vscale x 2 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsumu_vs_u16m1_u32m1(<vscale x 4 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>
# | ...
# `---data was truncated (10240/43625) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556f99111eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556f9910ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556f9911262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f30fbc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f30fbca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f30fbc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f30fbc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556f990a7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556f990a7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556f9908c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556f98d3be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556f98d3bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f30fbc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f30fbc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f30fbc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556f98d3ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c (2690 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4(<vscale x 16 x half> %vd, <vsc
# | ...
# `---data was truncated (10240/149137) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556e62194eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556e62191e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556e6219562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f019b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f019b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f019b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f019b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e6212abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556e6212aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556e6210f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556e61dbee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556e61dbeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f019b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f019b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f019b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e61dbea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c (2691 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f16m1x6(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f32m1x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f64m1x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i64> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a4edaceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a4edacbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a4edacf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e6d61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e6d6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e6d61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e6d603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a4eda64bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a4eda64a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a4eda498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a4ed6f8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a4ed6f8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6e6d604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e6d6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e6d6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a4ed6f8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c (2692 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmandn_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmandn.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmandn.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmandn_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmandn.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmandn.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmandn_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmandn.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmandn.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmandn_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmandn.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmandn.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmandn_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmandn.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmandn.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmandn_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmandn.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmandn.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmandn_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmandn.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmandn.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ef7f3d0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ef7f3cde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ef7f3d162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ad5b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ad5b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ad5b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ad5aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ef7f366bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ef7f366a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ef7f34b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ef7effae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ef7effab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3ad5aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ad5aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ad5aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ef7effaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c (2693 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjn_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjn_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjn_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjn_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjn_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjn_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjn_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjn_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2,
# | ...
# `---data was truncated (10240/65194) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055615f496eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055615f493e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055615f49762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e94a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e94aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e94a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e94a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055615f42cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055615f42ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055615f4118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055615f0c0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055615f0c0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4e94a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e94a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e94a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055615f0c0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c (2694 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_f64m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_i64m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_u64m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dc5e9ddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dc5e9dae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dc5e9de62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fde7f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fde7f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fde7f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fde7f51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc5e973bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dc5e973a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dc5e9588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dc5e607e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dc5e607b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fde7f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fde7f51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fde7f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc5e607a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c (2695 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_4x8x4_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_4x8x4_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_4x8x4_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_4x8x4_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564e4cb7aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564e4cb77e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564e4cb7b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f492cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f492cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f492cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f492cb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564e4cb10bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564e4cb10a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564e4caf58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564e4c7a4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564e4c7a4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f492cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f492cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f492cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564e4c7a4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c (2696 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vle.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vle.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16_v_bf16m4_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vle.mask.nxv16bf16.p0.i64(<vscale x 16 x bfloat> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vle.mask.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16_v_bf16m8_m(<vscale x 32 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 32 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vle.mask.nxv32bf16.p0.i64(<vscale x 32 x bfloat> poison, ptr %1, <vscale x 32 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vle.mask.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005637e4c16eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005637e4c13e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005637e4c1762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f15ec049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f15ec0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f15ec049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f15ec031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005637e4bacbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005637e4baca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005637e4b918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005637e4840e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005637e4840b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f15ec032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15ec0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15ec0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005637e4840a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c (2697 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f16m1x7(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f32m1x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f64m1x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei16_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555cc9318eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555cc9315e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555cc931962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efda7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efda778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efda7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efda771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555cc92aebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555cc92aea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555cc92938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555cc8f42e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555cc8f42b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efda771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efda771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efda771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555cc8f42a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c (2698 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_2x8x2_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_2x8x2_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_2x8x2_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_2x8x2_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005572f30a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005572f30a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005572f30a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ef441bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ef44725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ef441ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ef4403507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005572f303cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005572f303ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005572f30218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005572f2cd0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005572f2cd0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8ef4404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ef44050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ef44050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005572f2cd0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c (2699 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zvfhmin -target-feature +zvfbfmin    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte16_bf16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vlte16.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte16_f16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte16_i16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte16_u16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvfbfmin,+zvfhmin,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfhmin1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564db5660eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564db565de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564db566162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff26b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff26b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff26b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff26b231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564db55f6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564db55f6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564db55db8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564db528ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564db528ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff26b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff26b2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff26b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564db528aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c (2700 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmin_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmin_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmin_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmin_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmin_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmin_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmin_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmin_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmin_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, <vscale x 16 x half> 
# | ...
# `---data was truncated (10240/157173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005650f2122eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005650f211fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005650f212362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa4f7f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa4f7f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa4f7f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa4f7f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005650f20b8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005650f20b8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005650f209d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005650f1d4ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005650f1d4cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa4f7f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4f7f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4f7f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005650f1d4ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c (2701 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_f16mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_f16mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_f16m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_i16mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_i16mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_i16m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_u16mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_u16mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_u16m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_f16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.v
# | ...
# `---data was truncated (10240/20439) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a6eefeaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a6eefe7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a6eefeb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007facec049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007facec0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007facec049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007facec031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a6eef80bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a6eef80a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a6eef658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a6eec14e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a6eec14b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007facec032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007facec0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007facec0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a6eec14a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c (2702 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_x_f_v_i32mf2(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_x_f_v_i32m1(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_x_f_v_i32m2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_x_f_v_i32m4(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_x_f_v_i32m8(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_xu_f_v_u32mf2(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_xu_f_v_u32m1(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_xu_f_v_u32m2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_xu_f_v_u32m4(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_xu_f_v_u32m8(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vfwcvt_rtz_x_f_v_i64m1(<vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x i64>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vfwcvt_rtz_x_f_v_i64m2(<vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i6
# | ...
# `---data was truncated (10240/35605) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d83a157eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d83a154e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d83a15862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2234849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f22348a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2234849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2234831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d83a0edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d83a0eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d83a0d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d839d81e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d839d81b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2234832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f22348330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f22348330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d839d81a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c (2703 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vv_bf16mf4_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vf_bf16mf4_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vv_bf16mf2_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vf_bf16mf2_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vv_bf16m1_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vf_bf16m1_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vv_bf16m2_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vf_bf16m2_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac
# | ...
# `---data was truncated (10240/51796) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bc16425eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bc16422e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bc1642662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6631733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f663178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6631733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f663171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bc163bbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bc163bba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bc163a08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bc1604fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bc1604fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f663171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f663171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f663171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bc1604fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c (2704 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1down_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1down_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1down_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfslide1down_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfslide1down_vf_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfslide1down_vf_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1down_vf_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %3 = load bfloat, ptr %value.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1down_vf_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load 
# | ...
# `---data was truncated (10240/32702) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562b24846eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562b24843e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562b2484762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ac0649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ac06a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ac0649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ac0631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b247dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562b247dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562b247c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562b24470e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562b24470b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4ac0632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ac06330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ac06330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b24470a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c (2705 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmacc_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmacc_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmacc_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmacc_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmacc_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmacc_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmacc_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmacc_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bflo
# | ...
# `---data was truncated (10240/34364) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555cefcb3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555cefcb0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555cefcb462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5511649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f55116a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5511649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5511631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555cefc49bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555cefc49a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555cefc2e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555cef8dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555cef8ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5511632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f55116330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f55116330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555cef8dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c (2706 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredor_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x
# | ...
# `---data was truncated (10240/112817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dd8cd2ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dd8cd29e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dd8cd2d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efd16b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efd16b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efd16b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efd16aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd8ccc2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dd8ccc2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dd8cca78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dd8c956e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dd8c956b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efd16aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efd16aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efd16aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd8c956a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c (2707 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |  
# | ...
# `---data was truncated (10240/30268) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005634c05c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005634c05bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005634c05c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb82e505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb82e55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb82e505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb82e4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005634c0557bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005634c0557a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005634c053c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005634c01ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005634c01ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb82e4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb82e4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb82e4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005634c01eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c (2708 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_i8mf8x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_i8mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e8_v_i8mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e8_v_i8m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_u8mf8x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_u8mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e8_v_u8mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e8_v_u8m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_i8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 
# | ...
# `---data was truncated (10240/19037) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dd718beeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dd718bbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dd718bf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6561105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f656115c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6561105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f65610ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd71854bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dd71854a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dd718398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dd714e8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dd714e8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f65610eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f65610ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f65610ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd714e8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c (2709 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmacc_2x8x2_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmacc_2x8x2_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmacc_2x8x2_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmacc_2x8x2_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f5b724eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559f5b721e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559f5b72562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ef2049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ef20a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ef2049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ef2031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f5b6babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559f5b6baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559f5b69f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559f5b34ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559f5b34eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3ef2032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ef20330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ef20330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f5b34ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c (2710 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_x_f_qf_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %1, <vscale x 1 x float> %2, float %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %1, <vscale x 2 x float> %2, float %3, <vscale x 2 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscal
# | ...
# `---data was truncated (10240/26704) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563fc5e23eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563fc5e20e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563fc5e2462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fabbb049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fabbb0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fabbb049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fabbb031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563fc5db9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563fc5db9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563fc5d9e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563fc5a4de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563fc5a4db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fabbb032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fabbb0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fabbb0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563fc5a4da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c (2711 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabd_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabd_vx_u8mf8(<vscale x 1 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabd_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabd_vx_u8mf4(<vscale x 2 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabd_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabd_vx_u8mf2(<vscale x 4 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabd_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabd_vx_u8m1(<vscale x 8 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabd_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabd_vx_u8m2(<vscale x 16 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vabd_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64
# | ...
# `---data was truncated (10240/97248) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d6605eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d6605ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d6605ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5689505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f568955c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5689505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f56894ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d660584bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d660584a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d6605698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d660218e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d660218b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f56894eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56894ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56894ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d660218a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c (2712 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsra_wv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsra_wx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsra_wv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsra_wx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsra_wv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsra_wx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsra_wv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsra_wx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsra_wv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = allo
# | ...
# `---data was truncated (10240/154609) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c987ee9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c987ee6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c987eea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ca8a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ca8aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ca8a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ca8a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c987e7fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c987e7fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c987e648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c987b13e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c987b13b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5ca8a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ca8a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ca8a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c987b13a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c (2713 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmadd_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmadd_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmadd_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmadd_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmadd_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmadd_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmadd_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmadd_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | ...
# `---data was truncated (10240/34356) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562db440deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562db440ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562db440e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2fccf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2fccf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2fccf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2fccf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562db43a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562db43a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562db43888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562db4037e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562db4037b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2fccf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2fccf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2fccf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562db4037a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c (2714 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { targ
# | ...
# `---data was truncated (10240/21111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd05e32eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fd05e2fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fd05e3362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2975849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f29758a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2975849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2975831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd05dc8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fd05dc8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fd05dad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fd05a5ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fd05a5cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2975832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f29758330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f29758330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd05a5ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c (2715 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabd_vv_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabd_vx_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabd_vv_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabd_vx_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabd_vv_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabd_vx_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabd_vv_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabd_vx_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabd_vv_u8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vabd
# | ...
# `---data was truncated (10240/215044) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564e66e87eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564e66e84e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564e66e8862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f22d9c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f22d9ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f22d9c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f22d9c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564e66e1dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564e66e1da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564e66e028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564e66ab1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564e66ab1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f22d9c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f22d9c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f22d9c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564e66ab1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c (2716 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf4_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf4_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vzext_vf4_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vzext_vf4_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf4_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf4_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf4_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf4_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i32> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/39922) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055944db70eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055944db6de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055944db7162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa87b21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa87b2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa87b21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa87b203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055944db06bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055944db06a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055944daeb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055944d79ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055944d79ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa87b204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa87b2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa87b2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055944d79aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c (2717 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvt_rod_f_f_w_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvt_rod_f_f_w_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvt_rod_f_f_w_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvt_rod_f_f_w_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvt_rod_f_f_w_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %2 = l
# | ...
# `---data was truncated (10240/23247) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f46348feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f46348ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f46349062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb9b661bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb9b66725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb9b661ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb9b6603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f463425bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f463425a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f46340a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f4630b9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f4630b9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb9b6604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb9b66050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb9b66050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f4630b9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c (2718 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i8> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>
# | ...
# `---data was truncated (10240/15607) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557d3d646eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557d3d643e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557d3d64762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd438e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd438ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd438e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd438e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557d3d5dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557d3d5dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557d3d5c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557d3d270e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557d3d270b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd438e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd438e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd438e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557d3d270a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c (2719 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16mf4x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16mf2x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16m1x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555720ca4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555720ca1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555720ca562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb585049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb5850a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb585049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb585031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555720c3abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555720c3aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555720c1f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005557208cee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005557208ceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb585032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb5850330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb5850330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005557208cea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c (2720 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m4_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat>
# | ...
# `---data was truncated (10240/53686) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558136bd0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558136bcde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558136bd162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce27f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce27f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce27f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce27f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558136b66bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558136b66a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558136b4b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005581367fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005581367fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fce27f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce27f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce27f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005581367faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c (2721 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f16m1x4(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_f16m2x4(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f32m1x4(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_f32m2x4(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f64m1x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.
# | ...
# `---data was truncated (10240/87884) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005577176c6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005577176c3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005577176c762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4a68249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4a682a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4a68249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4a68231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055771765cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055771765ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005577176418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005577172f0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005577172f0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4a68232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4a682330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4a682330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005577172f0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c (2722 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_x_v_bf16mf4(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_x_v_bf16mf2(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_x_v_bf16m1(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_x_v_bf16m2(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_x_v_bf16m4(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_x_v_bf16m8(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_xu_v_bf16mf4(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_xu_v_bf16mf2(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_xu_v_bf16m1(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_xu_v_bf16m2(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_xu_v_bf16m4(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_xu_v_bf16m8(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.n
# | ...
# `---data was truncated (10240/33624) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005579daea3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005579daea0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005579daea462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3824d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3824d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3824d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3824d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005579dae39bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005579dae39a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005579dae1e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005579daacde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005579daacdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3824d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3824d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3824d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005579daacda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c (2723 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_vv_u16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_vx_u16mf4(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_wv_u16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_wx_u16mf4(<vscale x 1 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_vv_u16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_vx_u16mf2(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_wv_u16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_wx_u16mf2(<vscale x 2 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsubu_vv_u16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsubu_vx_u16m1(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscal
# | ...
# `---data was truncated (10240/134927) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055671071aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556710717e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055671071b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f346a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f346a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f346a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f346a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005567106b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005567106b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005567106958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556710344e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556710344b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f346a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f346a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f346a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556710344a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c (2724 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_i32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_i32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_u32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_u32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_f32mf2x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple,
# | ...
# `---data was truncated (10240/40726) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005647a25a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005647a25a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005647a25a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd095733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd09578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd095733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd09571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005647a253bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005647a253ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005647a25208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005647a21cfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005647a21cfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd09571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd09571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd09571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005647a21cfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c (2725 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vx_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmul_vv_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmul_vx_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmul_vv_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmul_vx_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmul_vv_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmul_vx_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vsc
# | ...
# `---data was truncated (10240/41579) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564cf9ae9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564cf9ae6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564cf9aea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb9f3449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb9f34a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb9f3449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb9f3431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564cf9a7fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564cf9a7fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564cf9a648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564cf9713e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564cf9713b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb9f3432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb9f34330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb9f34330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564cf9713a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c (2726 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f16m1x8(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f32m1x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f64m1x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei32_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005651456fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005651456f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005651456fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f430a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f430a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f430a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f430a91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565145692bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565145692a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005651456778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565145326e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565145326b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f430a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f430a91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f430a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565145326a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c (2727 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf8x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_u8mf8x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_u8mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_u8mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_u8m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, pt
# | ...
# `---data was truncated (10240/18980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055da1860deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055da1860ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055da1860e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f67d8249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f67d82a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f67d8249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f67d8231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da185a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055da185a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055da185888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055da18237e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055da18237b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f67d8232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67d82330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67d82330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da18237a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c (2728 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_bf16mf2x7(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_bf16m1x7(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f9a7aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564f9a7a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564f9a7ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb733e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb733e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb733e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb733e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f9a740bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564f9a740a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564f9a7258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564f9a3d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564f9a3d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb733e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb733e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb733e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f9a3d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c (2729 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8ff_v_i8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8ff_v_i8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8ff_v_i8m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_u8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8ff_v_u8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8ff
# | ...
# `---data was truncated (10240/54702) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005639eb4b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005639eb4b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005639eb4b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4a3ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4a3aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4a3ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4a3ac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005639eb44bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005639eb44ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005639eb4308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005639eb0dfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005639eb0dfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4a3ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4a3ac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4a3ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639eb0dfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c (2730 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_f64m1(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1f64.p0.i64(<vscale x 1 x double> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_f64m2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2f64.p0.i64(<vscale x 2 x double> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_f64m4(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4f64.p0.i64(<vscale x 4 x double> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_f64m8(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8f64.p0.i64(<vscale x 8 x double> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_i64m1(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i64.p0.i64(<vscale x 1 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_i64m2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i64.p0.i64(<vscale x 2 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_i64m4(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i64.p0.i64(<vscale x 4 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_i64m8(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8i64.p0.i64(<vscale x 8 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_u64m1(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i64.p0.i64(<vscale x 1 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_u64m2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i64.p0.i64(<vscale x 2 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | def
# | ...
# `---data was truncated (10240/26764) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d1b4ecdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d1b4ecae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d1b4ece62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff32bc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff32bc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff32bc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff32bc03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d1b4e63bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d1b4e63a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d1b4e488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d1b4af7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d1b4af7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff32bc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff32bc050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff32bc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d1b4af7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c (2731 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractva
# | ...
# `---data was truncated (10240/27866) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556ef4e2aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556ef4e27e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556ef4e2b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc73f41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc73f4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc73f41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc73f403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ef4dc0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556ef4dc0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556ef4da58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556ef4a54e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556ef4a54b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc73f404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc73f4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc73f4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556ef4a54a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c (2732 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgatherei16_vv_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgatherei16_vv_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgatherei16_vv_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vrgatherei16_vv_bf16m8(<vscale x 32 x bfloat> %vs2, <vscale x 32 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgatherei16_vv_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x i16
# | ...
# `---data was truncated (10240/15367) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f3c164eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f3c164be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f3c164f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb414449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb4144a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb414449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb414431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f3c15e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f3c15e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f3c15c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f3c1278e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f3c1278b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb414432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb4144330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb4144330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f3c1278a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c (2733 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564972fd9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564972fd6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564972fda62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6fdfe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6fdfea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6fdfe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6fdfe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564972f6fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564972f6fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564972f548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564972c03e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564972c03b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6fdfe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6fdfe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6fdfe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564972c03a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c (2734 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vclz_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vclz_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vclz.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vclz.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vclz_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vclz.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vclz.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vclz_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vclz.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vclz.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vclz_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vclz.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vclz.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vclz_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vclz.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vclz.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vclz_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vclz.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vclz.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vclz_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vclz.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vclz.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vclz_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vclz.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vclz.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vclz_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vclz.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vclz.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vclz_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vclz.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vclz.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vclz_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vclz.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vclz.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vclz_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vclz.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(
# | ...
# `---data was truncated (10240/40661) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005644b8d11eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005644b8d0ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005644b8d1262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3520d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3520d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3520d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3520d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005644b8ca7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005644b8ca7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005644b8c8c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005644b893be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005644b893bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3520d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3520d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3520d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005644b893ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c (2735 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei32_v_f16mf4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei32_v_f16mf2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei32_v_f16m1(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei32_v_f16m2(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei32_v_f16m4(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei32_v_f32mf2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei32_v_f32m1(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei32_v_f32m2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei32_v_f32m4(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vluxei32_v_f32m8(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.p0.nxv16i32.i64(<vscale x 16 x float> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.p0.nxv16i32.i64(<vscal
# | ...
# `---data was truncated (10240/107872) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b65dcaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563b65dc7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563b65dcb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd6a4105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd6a415c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd6a4105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd6a40ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b65d60bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563b65d60a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563b65d458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563b659f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563b659f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd6a40eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd6a40ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd6a40ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b659f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c (2736 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_f64m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_i64m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_u64m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563da1b3beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563da1b38e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563da1b3c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fea1e01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fea1e0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fea1e01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fea1e003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563da1ad1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563da1ad1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563da1ab68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563da1765e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563da1765b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fea1e004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fea1e0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fea1e0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563da1765a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-neon-vcvtX.c (2737 of 27911)
******************** TEST 'Clang :: CodeGen/arm-neon-vcvtX.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8-unknown-linux-gnueabihf"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vcvta_s32_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvta_s32_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vcvta_s32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtas.v2i32.v2f32(<2 x float> %vcvta_s32_v.i)
# |   store <2 x i32> %vcvta_s32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vcvta_u32_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvta_u32_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vcvta_u32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtau.v2i32.v2f32(<2 x float> %vcvta_u32_v.i)
# |   store <2 x i32> %vcvta_u32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcvtaq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtaq_s32_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vcvtaq_s32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtas.v4i32.v4f32(<4 x float> %vcvtaq_s32_v.i)
# |   store <4 x i32> %vcvtaq_s32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcvtaq_u32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtaq_u32_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vcvtaq_u32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtau.v4i32.v4f32(<4 x float> %vcvtaq_u32_v.i)
# |   store <4 x i32> %vcvtaq_u32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vcvtn_s32_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtn_s32_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vcvtn_s32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtns.v2i32.v2f32(<2 x float> %vcvtn_s32_v.i)
# |   store <2 x i32> %vcvtn_s32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vcvtn_u32_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtn_u32_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vcvtn_u32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtnu.v2i32.v2f32(<2 x float> %vcvtn_u32_v.i)
# |   store <2 x i32> %vcvtn_u32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcvtnq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtnq_s32_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vcvtnq_s32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtns.v4i32.v4f32(<4 x float> %vcvtnq_s32_v.i)
# |   store <4 x i32> %vcvtnq_s32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcvtnq_u32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtnq_u32_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vcvtnq_u32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtnu.v4i32.v4f32(<4 x float> %vcvtnq_u32_v.i)
# |   store <4 x i32> %vcvtnq_u32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vcvtp_s32_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtp_s32_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vcvtp_s32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtps.v2i32.v2f32(<2 x float> %vcvtp_s32_v.i)
# |   store <2 x i32> %vcvtp_s32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vcvtp_u32_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtp_u32_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vcvtp_u32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtpu.v2i32.v2f32(<2 x float> %vcvtp_u32_v.i)
# |   store <2 x i32> %vcvtp_u32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcvtpq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtpq_s32_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vcvtpq_s32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtps.v4i32.v4f32(<4 x float> %vcvtpq_s32_v.i)
# |   store <4 x i32> %vcvtpq_s32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcvtpq_u32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtpq_u32_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vcvtpq_u32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtpu.v4i32.v4f32(<4 x float> %vcvtpq_u32_v.i)
# |   st
# | ...
# `---data was truncated (10240/16770) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005560baf60eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005560baf5de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005560baf6162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8997849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f89978a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8997849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8997831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005560baef6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005560baef6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005560baedb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005560bab8ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005560bab8ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8997832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f89978330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f89978330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005560bab8aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c (2738 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd25b4beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fd25b48e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fd25b4c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc68ab05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc68ab5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc68ab05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc68aaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd25ae1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fd25ae1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fd25ac68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fd25775e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fd25775b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc68aaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc68aaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc68aaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd25775a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c (2739 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_i32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_i32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_u32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_u32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_f32mf2x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscal
# | ...
# `---data was truncated (10240/35921) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d5b4088eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d5b4085e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d5b408962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc748449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc7484a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc748449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc748431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d5b401ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d5b401ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d5b40038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d5b3cb2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d5b3cb2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc748432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc7484330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc7484330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d5b3cb2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c (2740 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_i8mf8x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_i8mf4x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8_v_i8mf2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8_v_i8m1x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8_v_i8m2x4_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_u8mf8x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_u8mf4x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8_v_u8mf2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8_v_u8m1x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x 
# | ...
# `---data was truncated (10240/11943) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005610a039deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005610a039ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005610a039e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff895333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff89538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff895333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff89531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005610a0333bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005610a0333a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005610a03188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056109ffc7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056109ffc7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff89531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff89531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff89531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056109ffc7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c (2741 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlsseg2e8_v_i8mf8x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e8_v_i8mf4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e8_v_i8mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e8_v_i8m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e8_v_i8m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e8_v_i8m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlsseg2e8_v_u8mf8x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e8_v_u8mf4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e8_v_u8mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e8_v_u8m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstrid
# | ...
# `---data was truncated (10240/28111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a069599eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a069596e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a06959a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd5daa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd5daaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd5daa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd5daa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a06952fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a06952fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a0695148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a0691c3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a0691c3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd5daa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd5daa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd5daa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a0691c3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c (2742 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_i16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_i16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_i16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_u16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_u16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_u16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ta
# | ...
# `---data was truncated (10240/47488) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005640569d0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005640569cde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005640569d162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f289d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f289d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f289d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f289d631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564056966bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564056966a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056405694b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005640565fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005640565fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f289d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f289d6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f289d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005640565faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c (2743 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_x_f_w_bf16mf4_i8mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_x_f_w_bf16mf2_i8mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_x_f_w_bf16m1_i8mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_x_f_w_bf16m2_i8m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_x_f_w_bf16m4_i8m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_x_f_w_bf16m8_i8m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_xu_f_w_bf16mf4_u8mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_xu_f_w_bf16mf2_u8mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_xu_f_w_bf16m1_u8mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_xu_f_w_bf16m2_u8m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_xu_f_w_bf16m4_u8m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_xu_f_w_bf16m8_u8m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8
# | ...
# `---data was truncated (10240/24320) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a1f0e04eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a1f0e01e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a1f0e0562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb5cfb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb5cfb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb5cfb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb5cfaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a1f0d9abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a1f0d9aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a1f0d7f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a1f0a2ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a1f0a2eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb5cfaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb5cfaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb5cfaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a1f0a2ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c (2744 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vpaire_vv_f16mf4(<vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vpaire.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vpaire.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vpaire_vv_f16mf2(<vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vpaire.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vpaire.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vpaire_vv_f16m1(<vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vpaire.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vpaire.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vpaire_vv_f16m2(<vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vpaire.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vpaire.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vpaire_vv_f16m4(<vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vpaire.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vpaire.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vpaire_vv_f16m8(<vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vpaire.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vpaire.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vpaire_vv_f32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vpaire.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vpaire.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vpaire_vv_f32m1(<vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vpaire.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vpaire.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vpaire_vv_f32m2(<vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vpaire.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vpaire.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vpaire_vv_f32m4(<vscale x 8 x float> %vs2, <vscale x 8 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load <v
# | ...
# `---data was truncated (10240/125480) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556c8b8a0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556c8b89de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556c8b8a162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb25ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb25ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb25ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb25ff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556c8b836bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556c8b836a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556c8b81b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556c8b4cae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556c8b4cab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb25ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb25ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb25ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556c8b4caa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c (2745 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_f64m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_i64m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_u64m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005586e6843eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005586e6840e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005586e684462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbba6f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbba6f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbba6f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbba6f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005586e67d9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005586e67d9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005586e67be8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005586e646de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005586e646db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbba6f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbba6f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbba6f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005586e646da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c (2746 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i
# | ...
# `---data was truncated (10240/32100) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056335fb72eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056335fb6fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056335fb7362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f97ca649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f97ca6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f97ca649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f97ca631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056335fb08bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056335fb08a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056335faed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056335f79ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056335f79cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f97ca632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f97ca6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f97ca6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056335f79ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c (2747 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b32_m(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %0, i64 %2)
# |   ret i6
# | ...
# `---data was truncated (10240/11946) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558cf958beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558cf9588e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558cf958c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbc55b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbc55b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbc55b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbc55aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558cf9521bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558cf9521a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558cf95068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558cf91b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558cf91b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbc55aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbc55aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbc55aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558cf91b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-bf16-reinterpret-intrinsics.c (2748 of 27911)
******************** TEST 'Clang :: CodeGen/arm-bf16-reinterpret-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-arm-none-eabi -target-feature +neon -mfloat-abi hard  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-arm-none-eabi -target-feature +neon -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8.2a-arm-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_s8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_s16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_s32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_u8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_u16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_u32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_p8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_p16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_u64(<1 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_s64(<1 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <8 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 8
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <8 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 8
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <8 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 8
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <8 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 8
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <8 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 8
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <8 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 8
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_u32(<4 x i32> nou
# | ...
# `---data was truncated (10240/28396) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine
# |  #0 0x0000564adaa4aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564adaa47e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564adaa4b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f696de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f696dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f696de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f696de31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ada9e0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564ada9e0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564ada9c58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564ada674e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564ada674b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f696de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f696de330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f696de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ada674a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c (2749 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmorn_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmorn.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmorn.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmorn_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmorn.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmorn.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmorn_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmorn.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmorn.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmorn_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmorn.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmorn.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmorn_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmorn.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmorn.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmorn_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmorn.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmorn.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmorn_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmorn.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmorn.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055849931ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558499319e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055849931d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7013b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7013b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7013b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7013aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005584992b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005584992b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005584992978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558498f46e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558498f46b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7013aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7013aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7013aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558498f46a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c (2750 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cd74c2eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cd74c2be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cd74c2f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f57f6c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57f6ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f57f6c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f57f6c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cd74bc4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cd74bc4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cd74ba98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cd74858e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cd74858b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f57f6c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57f6c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57f6c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cd74858a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c (2751 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_u64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_u64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <v
# | ...
# `---data was truncated (10240/16552) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557d23b43eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557d23b40e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557d23b4462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca97f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca97f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca97f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca97f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557d23ad9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557d23ad9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557d23abe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557d2376de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557d2376db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fca97f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca97f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca97f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557d2376da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c (2752 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16mf4(ptr noundef %base, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1f16.p0.i64(<vscale x 1 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16mf2(ptr noundef %base, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2f16.p0.i64(<vscale x 2 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16m1(ptr noundef %base, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4f16.p0.i64(<vscale x 4 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16m2(ptr noundef %base, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8f16.p0.i64(<vscale x 8 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16m4(ptr noundef %base, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16f16.p0.i64(<vscale x 16 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16m8(ptr noundef %base, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv32f16.p0.i64(<vscale x 32 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16mf4(ptr noundef %base, <vscale x 1 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i16.p0.i64(<vscale x 1 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16mf2(ptr noundef %base, <vscale x 2 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i16.p0.i64(<vscale x 2 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16m1(ptr noundef %base, <vscale x 4 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i16.p0.i64(<vscale x 4 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16m2(ptr noundef %base, <vscale x 8 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i16.p0.i64(<vscale x 8 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8i16.p0.i64(<vscale x 8 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16m4(ptr noundef %base, <vscale x 16 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16i16.p0.i64(<vscale x 16 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16i16.p0.i64(<vscale x 16 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16m8(ptr noundef %base, <vscale x 32 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, ali
# | ...
# `---data was truncated (10240/33772) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559ee4287eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559ee4284e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559ee428862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdbc1f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdbc1f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdbc1f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdbc1f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559ee421dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559ee421da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559ee42028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559ee3eb1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559ee3eb1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdbc1f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdbc1f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdbc1f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559ee3eb1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c (2753 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vcpop_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vcpop_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vcpopv.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vcpopv.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vcpop_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vcpopv.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vcpopv.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vcpop_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vcpopv.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vcpopv.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vcpop_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vcpopv.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vcpopv.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vcpop_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vcpopv.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vcpopv.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vcpop_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vcpopv.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vcpopv.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vcpop_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vcpopv.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vcpopv.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vcpop_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vcpopv.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vcpopv.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vcpop_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vcpopv.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vcpopv.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vcpop_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vcpopv.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vcpopv.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vcpop_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vcpopv.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vcpopv.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vcpop_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vcpopv.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Fun
# | ...
# `---data was truncated (10240/40883) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f2fb2c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f2fb2c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f2fb2c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4c46849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4c468a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4c46849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4c46831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f2fb25ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f2fb25ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f2fb2438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f2faef2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f2faef2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4c46832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4c468330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4c468330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f2faef2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c (2754 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f16m1x5(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f32m1x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f64m1x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/69980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b71c935eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b71c932e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b71c93662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9dcb933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9dcb98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9dcb933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9dcb91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b71c8cbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b71c8cba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b71c8b08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b71c55fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b71c55fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9dcb91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9dcb91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9dcb91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b71c55fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c (2755 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16mf4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16mf2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m1_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m8_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff
# | ...
# `---data was truncated (10240/44185) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055985ecf9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055985ecf6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055985ecfa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3cd7533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3cd758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3cd7533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3cd751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055985ec8fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055985ec8fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055985ec748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055985e923e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055985e923b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3cd751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3cd751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3cd751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055985e923a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c (2756 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562fa1c3aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562fa1c37e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562fa1c3b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f45be249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f45be2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f45be249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f45be231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562fa1bd0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562fa1bd0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562fa1bb58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562fa1864e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562fa1864b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f45be232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f45be2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f45be2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562fa1864a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c (2757 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1(<vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vx_u64m1(<vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmul_vv_u64m2(<vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmul_vx_u64m2(<vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmul_vv_u64m4(<vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmul_vx_u64m4(<vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmul_vv_u64m8(<vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmul_vx_u64m8(<vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vx_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, a
# | ...
# `---data was truncated (10240/18875) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056196b003eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056196b000e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056196b00462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe68c41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe68c4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe68c41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe68c403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056196af99bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056196af99a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056196af7e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056196ac2de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056196ac2db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe68c404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe68c4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe68c4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056196ac2da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c (2758 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_i16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_i16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_i16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_i16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_
# | ...
# `---data was truncated (10240/63061) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055558efbceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055558efb9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055558efbd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb394c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb394ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb394c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb394c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055558ef52bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055558ef52a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055558ef378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055558ebe6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055558ebe6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb394c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb394c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb394c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055558ebe6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c (2759 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei8_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei8_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei8_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei8_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei8_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vluxei8_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> poison, ptr %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei8_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei8_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei8_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei8_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = al
# | ...
# `---data was truncated (10240/14209) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e9b656deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e9b656ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e9b656e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f259701bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f25970725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f259701ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2597003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e9b6503bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e9b6503a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e9b64e88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e9b6197e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e9b6197b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2597004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f25970050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f25970050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e9b6197a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c (2760 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_f32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_f32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_f32m2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_i32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_i32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_i32m2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_u32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractval
# | ...
# `---data was truncated (10240/13669) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562fbfd05eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562fbfd02e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562fbfd0662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b65d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b65d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b65d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b65d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562fbfc9bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562fbfc9ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562fbfc808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562fbf92fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562fbf92fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8b65d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b65d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b65d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562fbf92fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c (2761 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vghsh_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vghsh_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vghsh_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vghsh_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vghsh_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bded2ddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bded2dae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bded2de62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ec2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ec2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ec2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ec2f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bded273bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bded273a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bded2588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bdecf07e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bdecf07b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3ec2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ec2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ec2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bdecf07a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c (2762 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563689febeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563689fe8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563689fec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b0fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b0fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b0fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b0fd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563689f81bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563689f81a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563689f668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563689c15e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563689c15b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3b0fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b0fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b0fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563689c15a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c (2763 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558f5c983eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558f5c980e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558f5c98462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9509a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9509a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9509a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9509a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f5c919bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558f5c919a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558f5c8fe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558f5c5ade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558f5c5adb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9509a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9509a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9509a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f5c5ada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c (2764 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmin_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmin_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmin_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmin_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmin_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmin_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmin_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmin_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ...
# `---data was truncated (10240/64958) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005585253f6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005585253f3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005585253f762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c88a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c88aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c88a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c88a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055852538cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055852538ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005585253718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558525020e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558525020b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8c88a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c88a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c88a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558525020a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c (2765 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564098e4aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564098e47e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564098e4b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7866849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f78668a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7866849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7866831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564098de0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564098de0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564098dc58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564098a74e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564098a74b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7866832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f78668330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f78668330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564098a74a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/builtins-riscv.c (2766 of 27911)
******************** TEST 'Clang :: CodeGen/builtins-riscv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple riscv32 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple riscv32 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_eh_return_data_regno() #0 {
# | entry:
# |   %res = alloca i32, align 4
# |   store volatile i32 10, ptr %res, align 4
# |   store volatile i32 11, ptr %res, align 4
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i" }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e3bda03eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e3bda00e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e3bda0462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2574c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2574ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2574c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2574c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e3bd999bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e3bd999a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e3bd97e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e3bd62de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e3bd62db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2574c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2574c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2574c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e3bd62da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c (2767 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b1c6be4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b1c6be1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b1c6be562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f20c4533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f20c458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f20c4533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f20c451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b1c6b7abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b1c6b7aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b1c6b5f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b1c680ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b1c680eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f20c451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f20c451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f20c451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b1c680ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c (2768 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_f32mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_f32m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_i32mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_i32m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_u32mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_u32m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_i32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_i32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/14010) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c467c7aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c467c77e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c467c7b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f58e6533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f58e658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f58e6533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f58e651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c467c10bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c467c10a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c467bf58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c4678a4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c4678a4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f58e651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f58e651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f58e651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c4678a4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c (2769 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsqrt7_v_bf16mf4(<vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsqrt7_v_bf16mf2(<vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsqrt7_v_bf16m1(<vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsqrt7_v_bf16m2(<vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsqrt7_v_bf16m4(<vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrsqrt7_v_bf16m8(<vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsqrt7_v_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsqrt7_v_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsqrt7_v_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsqrt7_v_bf16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsqrt7_v_bf16m4_m(<vscale x 16 x i1> %mask, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x bfloa
# | ...
# `---data was truncated (10240/12528) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559933abaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559933ab7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559933abb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6578849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f65788a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6578849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6578831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559933a50bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559933a50a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559933a358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005599336e4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005599336e4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6578832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f65788330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f65788330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005599336e4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c (2770 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16ff_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16ff_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %6
# | 
# | ...
# `---data was truncated (10240/34641) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c10fb93eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c10fb90e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c10fb9462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f90e5733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f90e578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f90e5733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f90e571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c10fb29bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c10fb29a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c10fb0e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c10f7bde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c10f7bdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f90e571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f90e571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f90e571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c10f7bda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c (2771 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvsintload -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vln8_v_i8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vln8_v_i8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vln8_v_i8mf2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vln8_v_i8m1_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.nds.vln.mask.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vln.mask.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vln8_v_i8m2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.nds.vln.mask.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.nds.vln.mask.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i8> @test_nds_vln8_v_i8m4_m(<vscale x 32 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.nds.vln.mask.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %1, <vscale x 32 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.nds.vln.mask.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_nds_vln8_v_i8m8_m(<vscale x 64 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.nds.vln.mask.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %1, <vscale x 64 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.nds.vln.mask.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), <vscale x 64 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xandesvsintload,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xandesvsintload5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e36db1beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e36db18e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e36db1c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6b33d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6b33d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6b33d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6b33d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e36dab1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e36dab1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e36da968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e36d745e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e36d745b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6b33d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6b33d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6b33d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e36d745a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c (2772 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f16m1x5(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f32m1x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f64m1x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei64_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560a6480ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560a64809e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560a6480d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5458733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f545878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5458733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f545871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a647a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560a647a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560a647878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560a64436e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560a64436b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f545871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f545871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f545871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a64436a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c (2773 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_i8mf8x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_i8mf4x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_i8mf2x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8_v_i8m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_u8mf8x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_u8mf4x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_u8mf2x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8_v_u8m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_i8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_i8mf2x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = c
# | ...
# `---data was truncated (10240/16451) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d591643eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d591640e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d59164462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa27121bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa2712725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa27121ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa271203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d5915d9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d5915d9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d5915be8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d59126de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d59126db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa271204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa2712050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa2712050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d59126da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c (2774 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_i16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_i16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_i16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_u16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca 
# | ...
# `---data was truncated (10240/60551) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b2f68f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b2f68efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b2f68f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4dfa41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4dfa4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4dfa41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4dfa403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b2f6888bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b2f6888a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b2f686d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b2f651ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b2f651cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4dfa404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4dfa4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4dfa4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b2f651ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c (2775 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmor_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmor.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmor.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmor_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmor.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmor.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmor_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmor.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmor.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmor_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmor.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmor.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmor_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmor.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmor.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmor_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmor.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmor_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmor.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmor.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f63ec4ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f63ec49e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f63ec4d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd6dc505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd6dc55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd6dc505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd6dc4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f63ebe2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f63ebe2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f63ebc78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f63e876e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f63e876b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd6dc4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd6dc4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd6dc4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f63e876a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c (2776 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmul_vv_i16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmul_vx_i16mf4(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmul_vv_i16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmul_vx_i16mf2(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmul_vv_i16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmul_vx_i16m1(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmul_vv_i16m2(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmul_vx_i16m2(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmul_vv_i16m4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmul_vx_i16m4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_
# | ...
# `---data was truncated (10240/68065) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ab430c6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ab430c3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ab430c762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9199d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9199d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9199d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9199d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ab4305cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ab4305ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ab430418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ab42cf0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ab42cf0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9199d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9199d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9199d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ab42cf0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c (2777 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte64_f64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vlte64.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte64_i64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte64_u64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b29b2faeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b29b2f7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b29b2fb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d51933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d5198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d51933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d5191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b29b290bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b29b290a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b29b2758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b29af24e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b29af24b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8d5191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d5191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d5191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b29af24a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c (2778 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f16m1x3(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_f16m2x3(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f32m1x3(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_f32m2x3(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f64m1x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.
# | ...
# `---data was truncated (10240/87884) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561c48563eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561c48560e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561c4856462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f14c861bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f14c86725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f14c861ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f14c8603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561c484f9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561c484f9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561c484de8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561c4818de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561c4818db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f14c8604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f14c86050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f14c86050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561c4818da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c (2779 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_f64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_f64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_i64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_i64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_u64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_u64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_f64m1x4_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_f64m2x4_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %2, <vscale x 2 x i1> %0, i64 
# | ...
# `---data was truncated (10240/32125) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005629ed231eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005629ed22ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005629ed23262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f928a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f928a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f928a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f928a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005629ed1c7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005629ed1c7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005629ed1ac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005629ece5be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005629ece5bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f928a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f928a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f928a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005629ece5ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c (2780 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("risc
# | ...
# `---data was truncated (10240/21103) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d26012eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d26012be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d26012f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb9d4649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb9d46a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb9d4649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb9d4631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d2600c4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d2600c4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d2600a98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d25fd58e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d25fd58b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb9d4632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb9d46330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb9d46330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d25fd58a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c (2781 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8mf8(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i8.p0.i64(<vscale x 1 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8mf4(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i8.p0.i64(<vscale x 2 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i8.p0.i64(<vscale x 4 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8m1(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8i8.p0.i64(<vscale x 8 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8m2(ptr noundef %base, i64 noundef %bstride, <vscale x 16 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 16 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv16i8.p0.i64(<vscale x 16 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8m4(ptr noundef %base, i64 noundef %bstride, <vscale x 32 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 32 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv32i8.p0.i64(<vscale x 32 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8m8(ptr noundef %base, i64 noundef %bstride, <vscale x 64 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 64 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 64 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv64i8.p0.i64(<vscale x 64 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_u8mf8(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i8.p0.i64(<vscale x 1 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_u8mf4(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i8.p0.i64(<vscale x 2 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_u8mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i8.p0.i64(<vscale x 4 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_u8m1(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %bas
# | ...
# `---data was truncated (10240/29817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c4c4855eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c4c4852e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c4c485662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb08933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb0898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb08933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb0891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c4c47ebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c4c47eba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c4c47d08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c4c447fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c4c447fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feb0891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb0891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb0891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c4c447fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c (2782 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4(<vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2(<vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1(<vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfabs_v_bf16m2(<vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfabs_v_bf16m4(<vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfabs_v_bf16m8(<vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfabs_v_bf16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>
# | ...
# `---data was truncated (10240/13290) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c7f0ea0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c7f0e9de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c7f0ea162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f00a9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f00a9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f00a9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f00a9f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c7f0e36bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c7f0e36a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c7f0e1b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c7f0acae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c7f0acab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f00a9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f00a9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f00a9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c7f0acaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c (2783 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16mf2_bf16mf4(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv2bf16(<vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv2bf16(<vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m1_bf16mf4(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv4bf16(<vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv4bf16(<vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m1_bf16mf2(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv4bf16(<vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv4bf16(<vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m2_bf16mf4(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv8bf16(<vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv8bf16(<vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m2_bf16mf2(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_trunc_v_bf16m2_bf16m1(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16mf4(<vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16mf2(<vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16m1(<vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16m2(<vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16mf4(<vscale x 32 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16mf2(<vscale x 32 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16m1(<vscale x 32 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16m2(<vscale x 32 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16m4(<vscale x
# | ...
# `---data was truncated (10240/11396) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a48d148eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a48d145e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a48d14962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9d83049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9d830a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9d83049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9d83031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a48d0debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a48d0dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a48d0c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a48cd72e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a48cd72b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9d83032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9d830330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9d830330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a48cd72a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c (2784 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f16m1x6(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f32m1x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f64m1x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei64_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de9bfafeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055de9bface85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055de9bfb062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff8db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff8db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff8db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff8db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de9bf45bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055de9bf45a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055de9bf2a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055de9bbd9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055de9bbd9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007eff8db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff8db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff8db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de9bbd9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c (2785 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfadd_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfadd_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfadd_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfadd_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfadd_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfadd_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfadd_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfadd_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfadd.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, ha
# | ...
# `---data was truncated (10240/125649) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e1e297deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e1e297ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e1e297e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f018fd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f018fd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f018fd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f018fced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e1e2913bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e1e2913a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e1e28f88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e1e25a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e1e25a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f018fceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f018fcef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f018fcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e1e25a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/distributed-thin-lto/cfi.ll (2786 of 27911)
******************** TEST 'Clang :: CodeGen/distributed-thin-lto/cfi.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi.ll
# |  #0 0x000055cb369a3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cb369a0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cb369a462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff677c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff677ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff677c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff677c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb36939bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cb36939a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cb3691e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cb365cde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cb365cdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff677c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff677c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff677c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb365cda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c (2787 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfslide1up_vf_f16mf4(<vscale x 1 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfslide1up_vf_f16mf2(<vscale x 2 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfslide1up_vf_f16m1(<vscale x 4 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfslide1up_vf_f16m2(<vscale x 8 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfslide1up_vf_f16m4(<vscale x 16 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfslide1up_vf_f16m8(<vscale x 32 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfslide1up_vf_f32mf2(<vscale x 1 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfslide1up_vf_f32m1(<vscale x 2 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfslide1up_vf_f32m2(<vscale x 4 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfslide1up.nxv4f32.f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, float %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfslide1up.nxv4f32.f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfslide1up_vf_f32m4(<vscale x 8 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfslide1up.nxv8f32.f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, float %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfslide1up.nxv8f32.f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,
# | ...
# `---data was truncated (10240/34589) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d2d88ebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d2d88e8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d2d88ec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f798c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f798c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f798c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f798c51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d2d8881bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d2d8881a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d2d88668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d2d8515e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d2d8515b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f798c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f798c51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f798c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d2d8515a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c (2788 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +xandesvbfhcvt -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_nds_vfwcvt_s_bf16_f32mf2(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_nds_vfwcvt_s_bf16_f32m1(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_nds_vfwcvt_s_bf16_f32m2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_nds_vfwcvt_s_bf16_f32m4(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_nds_vfwcvt_s_bf16_f32m8(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b571601eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b5715fee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b57160262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9bace49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9bacea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9bace49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9bace31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b571597bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b571597a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b57157c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b57122be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b57122bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9bace32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9bace330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9bace330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b57122ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c (2789 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_f16m1x2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_f16m2x2(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei32_v_f16m4x2(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_f32m1x2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_f32m2x2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vect
# | ...
# `---data was truncated (10240/108856) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a35e192eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a35e18fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a35e19362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9c08249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9c082a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9c08249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9c08231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a35e128bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a35e128a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a35e10d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a35ddbce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a35ddbcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9c08232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9c082330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9c082330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a35ddbca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c (2790 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_4x8x4_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_4x8x4_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_4x8x4_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_4x8x4_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560404242eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056040423fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056040424362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efd3ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efd3aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efd3ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efd3ac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005604041d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005604041d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005604041bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560403e6ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560403e6cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efd3ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efd3ac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efd3ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560403e6ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c (2791 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vv_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vf_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vv_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vf_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vv_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vf_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vv_bf16m2_f32m4(<vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vf_bf16m2_f32m4(<vscale x 8 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwmul_vv_bf16m4_f32m8(<vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwmul.nxv16f32.nxv16bf16.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwmul.nxv16f32.nxv16bf16.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwmul_vf_bf16m4_f32m8(<vscale x 16 x bfloat> %v
# | ...
# `---data was truncated (10240/43948) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d82c3b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d82c3b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d82c3b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3c48449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3c484a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3c48449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3c48431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d82c34bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d82c34ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d82c3308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d82bfdfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d82bfdfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3c48432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3c484330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3c484330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d82bfdfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c (2792 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsub_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsub_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsub_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsub_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsub_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsub_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsub_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsub_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <v
# | ...
# `---data was truncated (10240/64252) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561d9ec87eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561d9ec84e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561d9ec8862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0c34a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0c34aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0c34a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0c34a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561d9ec1dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561d9ec1da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561d9ec028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561d9e8b1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561d9e8b1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0c34a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0c34a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0c34a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561d9e8b1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c (2793 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_f16mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_f16mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_f16m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_f16m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_i16mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_i16mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_i16m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_i16m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_u16mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_u16mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_
# | ...
# `---data was truncated (10240/26936) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056210cfcceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056210cfc9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056210cfcd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ef2649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ef26a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ef2649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ef2631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056210cf62bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056210cf62a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056210cf478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056210cbf6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056210cbf6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5ef2632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ef26330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ef26330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056210cbf6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c (2794 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005620d5acdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005620d5acae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005620d5ace62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c45c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c45c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c45c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c45c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005620d5a63bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005620d5a63a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005620d5a488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005620d56f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005620d56f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7c45c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c45c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c45c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005620d56f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c (2795 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dedd1a3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dedd1a0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dedd1a462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3575f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3575f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3575f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3575f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dedd139bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dedd139a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dedd11e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dedcdcde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dedcdcdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3575f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3575f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3575f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dedcdcda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c (2796 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.
# | ...
# `---data was truncated (10240/18498) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558e7b649eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558e7b646e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558e7b64a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f31cd649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f31cd6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f31cd649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f31cd631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558e7b5dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558e7b5dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558e7b5c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558e7b273e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558e7b273b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f31cd632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31cd6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31cd6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558e7b273a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c (2797 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4r_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4r.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4r.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4r_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4r_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4r_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm4r_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4r_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4r_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @ll
# | ...
# `---data was truncated (10240/20090) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aa0fd4deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aa0fd4ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aa0fd4e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa053449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa0534a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa053449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa053431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa0fce3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aa0fce3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aa0fcc88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aa0f977e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aa0f977b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa053432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa0534330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa0534330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa0f977a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-cde-reinterpret.c (2798 of 27911)
******************** TEST 'Clang :: CodeGen/arm-cde-reinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi    -target-feature +cdecp0 -target-feature +mve.fp    -mfloat-abi hard -O0 -disable-O0-optnone    -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c --check-prefixes=CHECK,CHECK-LE
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_s8(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <16 x i8>, ptr %x.addr, align 8
# |   ret <16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_u16(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <16 x i8>, ptr %x.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_s32(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <16 x i8>, ptr %x.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <4 x i32>
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_u32(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <16 x i8>, ptr %x.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <4 x i32>
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_s64(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <16 x i8>, ptr %x.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <2 x i64>
# |   ret <2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_u64(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <16 x i8>, ptr %x.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <2 x i64>
# |   ret <2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_f16(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <16 x i8>, ptr %x.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_f32(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <16 x i8>, ptr %x.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+cdecp0,+mve.fp,+thumb-mode" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056489f05aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056489f057e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056489f05b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc901b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc901b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc901b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc901b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056489eff0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056489eff0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056489efd58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056489ec84e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056489ec84b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc901b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc901b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc901b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056489ec84a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c --check-prefixes=CHECK,CHECK-LE
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c --check-prefixes=CHECK,CHECK-LE
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c (2799 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +xandesvbfhcvt -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4_rm_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2_rm_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1_rm_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2_rm_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4_rm_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwin
# | ...
# `---data was truncated (10240/10610) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a676486eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a676483e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a67648762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3411649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f34116a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3411649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3411631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a67641cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a67641ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a6764018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a6760b0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a6760b0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3411632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f34116330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f34116330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a6760b0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c (2800 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_rtz_x_f_v_i16mf4(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_rtz_x_f_v_i16mf2(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_rtz_x_f_v_i16m1(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_rtz_x_f_v_i16m2(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_rtz_x_f_v_i16m4(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_rtz_x_f_v_i16m8(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_rtz_xu_f_v_u16mf4(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_rtz_xu_f_v_u16mf2(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_rtz_xu_f_v_u16m1(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_rtz_xu_f_v_u16m2(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_rtz_xu_f_v_u16m4(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_rtz_xu_f_v_u16m8(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.v
# | ...
# `---data was truncated (10240/58683) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d76b8b4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d76b8b1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d76b8b562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0653733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f065378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0653733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f065371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d76b84abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d76b84aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d76b82f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d76b4dee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d76b4deb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f065371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f065371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f065371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d76b4dea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c (2801 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_i16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_i16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_i16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_i16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e1
# | ...
# `---data was truncated (10240/63053) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d7b3af8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d7b3af5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d7b3af962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f235e905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f235e95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f235e905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f235e8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d7b3a8ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d7b3a8ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d7b3a738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d7b3722e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d7b3722b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f235e8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f235e8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f235e8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d7b3722a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c (2802 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8mf8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 5)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8mf4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 6)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8mf2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 7)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8m1(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8m2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8m4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8m8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16mf4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 6)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16mf2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 7)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16m1(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16m2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16m4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16m8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32mf2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 7)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32m1(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32m2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32m4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32m8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e64m1(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e64m2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e64m4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e64m8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 3)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055814161feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055814161ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055814162062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f557fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f557faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f557fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f557fa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005581415b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005581415b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055814159a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558141249e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558141249b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f557fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f557fa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f557fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558141249a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c (2803 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f16m1x6(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f32m1x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f64m1x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i32> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563ba5678eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563ba5675e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563ba567962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb1e9733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb1e978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb1e9733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb1e971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ba560ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563ba560ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563ba55f38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563ba52a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563ba52a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb1e971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb1e971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb1e971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ba52a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c (2804 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f16m1x4(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_f16m2x4(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f32m1x4(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_f32m2x4(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f64m1x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/87892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564cc2e3eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564cc2e3be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564cc2e3f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7730505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f773055c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7730505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f77304ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564cc2dd4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564cc2dd4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564cc2db98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564cc2a68e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564cc2a68b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f77304eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f77304ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f77304ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564cc2a68a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c (2805 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvpackfph -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadb_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadb_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadb_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadb_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half>, <vscale x 8 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_nds_vfpmadb_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half>, <vscale x 16 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_nds_vfpmadb_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half>, <vscale x 32 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadb_vf_f16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load float, ptr %op2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half> %1, <vscale x 1 x half> %2, float %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadb_vf_f16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load float, ptr %op2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64(<vscale x 2 x half> %1, <vscale x 2 x half> %2, float %3, <vscale x 2 
# | ...
# `---data was truncated (10240/59595) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bc339fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bc339f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bc339fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe1c4133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe1c418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe1c4133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe1c411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bc33992bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bc33992a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bc339778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bc33626e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bc33626b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe1c411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe1c411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe1c411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bc33626a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c (2806 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8ff_v_i8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8ff_v_i8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8ff_v_i8m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_u8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8ff_v_u8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8ff
# | ...
# `---data was truncated (10240/54702) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563a58297eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563a58294e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563a5829862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7ae9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7ae9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7ae9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7ae9b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a5822dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563a5822da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563a582128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563a57ec1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563a57ec1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7ae9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7ae9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7ae9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a57ec1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c (2807 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f16m1x6(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f32m1x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f64m1x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563615e44eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563615e41e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563615e4562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb7d0c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb7d0ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb7d0c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb7d0c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563615ddabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563615ddaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563615dbf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563615a6ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563615a6eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb7d0c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb7d0c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb7d0c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563615a6ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c (2808 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesem_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesem.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesem.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesem_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesem_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesem_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesem_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesem_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesem_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretur
# | ...
# `---data was truncated (10240/20190) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561c2b9e2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561c2b9dfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561c2b9e362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3136249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f31362a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3136249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3136231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561c2b978bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561c2b978a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561c2b95d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561c2b60ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561c2b60cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3136232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31362330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31362330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561c2b60ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c (2809 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmorn_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmorn.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmorn.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmorn_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmorn.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmorn.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmorn_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmorn.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmorn.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmorn_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmorn.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmorn.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmorn_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmorn.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmorn.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmorn_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmorn.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmorn.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmorn_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmorn.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmorn.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005581542f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005581542eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005581542f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcbab649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcbab6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcbab649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcbab631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558154287bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558154287a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055815426c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558153f1be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558153f1bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcbab632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcbab6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcbab6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558153f1ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c (2810 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_f16mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_f16mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_f16m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_i16mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_i16mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_i16m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_u16mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_u16mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_u16m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_f16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.ri
# | ...
# `---data was truncated (10240/20449) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d7c55a8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d7c55a5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d7c55a962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe553c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe553ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe553c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe553c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d7c553ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d7c553ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d7c55238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d7c51d2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d7c51d2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe553c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe553c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe553c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d7c51d2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c (2811 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_s_u_w4_i8m8_u8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.s.u.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.s.u.i64.nxv64i8.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d8b665ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d8b6659e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d8b665d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff9fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff9fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff9fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff9fc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d8b65f2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d8b65f2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d8b65d78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d8b6286e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d8b6286b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007eff9fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff9fc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff9fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d8b6286a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c (2812 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_4x8x4_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_4x8x4_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_4x8x4_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_4x8x4_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556a79f2feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556a79f2ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556a79f3062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f60efa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f60efaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f60efa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f60efa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556a79ec5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556a79ec5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556a79eaa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556a79b59e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556a79b59b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f60efa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f60efa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f60efa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556a79b59a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c (2813 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmacc_2x8x2_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmacc_2x8x2_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmacc_2x8x2_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmacc_2x8x2_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d42ea7aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d42ea77e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d42ea7b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb023e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb023ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb023e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb023e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d42ea10bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d42ea10a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d42e9f58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d42e6a4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d42e6a4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb023e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb023e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb023e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d42e6a4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c (2814 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf8_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> %0, <vscale x 1 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16>, <vscale x 1 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> %0, <vscale x 2 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16>, <vscale x 2 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf2_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m1_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> %0, <vscale x 8 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16>, <vscale x 8 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m2_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> %0, <vscale x 16 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16>, <vscale x 16 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> %0, <vscale x 32 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16>, <vscale x 32 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m8_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> %0, <vscale x 64 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16>, <vscale x 64 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16mf4_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(<vscale x 2 x i32>
# | ...
# `---data was truncated (10240/51185) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b7b1a6feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b7b1a6ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b7b1a7062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2136133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f213618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2136133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f213611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b7b1a05bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b7b1a05a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b7b19ea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b7b1699e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b7b1699b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f213611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f213611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f213611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b7b1699a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c (2815 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvsintload -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vln8_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.nds.vln.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vln.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vln8_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.nds.vln.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vln.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vln8_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.nds.vln.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vln.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vln8_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.nds.vln.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vln.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vln8_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.nds.vln.nxv16i8.p0.i64(<vscale x 16 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.nds.vln.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i8> @test_nds_vln8_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.nds.vln.nxv32i8.p0.i64(<vscale x 32 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.nds.vln.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_nds_vln8_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.nds.vln.nxv64i8.p0.i64(<vscale x 64 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.nds.vln.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vln8_v_i8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8> %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vln8_v_i8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8> %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vln8_v_i8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64(<vscale x 4 x i8> %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x
# | ...
# `---data was truncated (10240/29379) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005563b4dedeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005563b4deae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005563b4dee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff8be705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff8be75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff8be705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff8be6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005563b4d83bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005563b4d83a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005563b4d688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005563b4a17e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005563b4a17b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff8be6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff8be6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff8be6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005563b4a17a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c (2816 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfabs_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfabs_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfabs_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfabs_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfabs_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfabs_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfabs_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfabs_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfabs_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfabs_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfsgnjx.nxv8f32.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfsgnjx.nxv8f32.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfabs_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfsgnjx.nxv16f32.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfsgnjx.nxv16f32.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfabs_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.
# | ...
# `---data was truncated (10240/30869) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a0e585eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a0e585be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a0e585f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbf7fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbf7fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbf7fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbf7fc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a0e57f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a0e57f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a0e57d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a0e5488e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a0e5488b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbf7fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbf7fc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbf7fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a0e5488a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c (2817 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_u64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_u64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <v
# | ...
# `---data was truncated (10240/16552) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562880376eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562880373e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056288037762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee27105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee2715c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee27105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee270ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056288030cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056288030ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005628802f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056287ffa0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056287ffa0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fee270eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee270ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee270ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056287ffa0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c (2818 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vcompress_vm_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vcompress_vm_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vcompress_vm_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vcompress_vm_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vcompress_vm_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vcompress_vm_bf16m8(<vscale x 32 x bfloat> %vs2, <vscale x 32 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055771c3beeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055771c3bbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055771c3bf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3fdf733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3fdf78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3fdf733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3fdf71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055771c354bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055771c354a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055771c3398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055771bfe8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055771bfe8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3fdf71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3fdf71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3fdf71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055771bfe8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c (2819 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005630c50e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005630c50e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005630c50e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8fd5649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8fd56a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8fd5649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8fd5631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005630c507abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005630c507aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005630c505f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005630c4d0ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005630c4d0eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8fd5632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8fd56330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8fd56330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005630c4d0ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c (2820 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4au_vx_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4au_vx_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noin
# | ...
# `---data was truncated (10240/25042) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559afa497eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559afa494e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559afa49862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0753249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f07532a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0753249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0753231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559afa42dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559afa42da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559afa4128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559afa0c1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559afa0c1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0753232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f07532330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f07532330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559afa0c1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c (2821 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmin_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmin_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmin_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmin_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmin_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmin_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmin_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmin_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmin_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfmin.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmin.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmin_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>
# | ...
# `---data was truncated (10240/29062) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557d78eceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557d78ecbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557d78ecf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbe4c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbe4c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbe4c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbe4c31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557d78e64bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557d78e64a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557d78e498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557d78af8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557d78af8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbe4c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbe4c31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbe4c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557d78af8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c (2822 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsub_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsub_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsub_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsub_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsub_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsub_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsub_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsub_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3
# | ...
# `---data was truncated (10240/64366) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565073136eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565073133e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056507313762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff81ae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff81aea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff81ae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff81ae31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005650730ccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005650730cca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005650730b18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565072d60e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565072d60b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff81ae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff81ae330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff81ae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565072d60a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c (2823 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_f16mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_f16mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_f16m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_i16mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_i16mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_i16m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_u16mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_u16mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_u16m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, pt
# | ...
# `---data was truncated (10240/24016) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005620a3f62eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005620a3f5fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005620a3f6362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc19f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc19f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc19f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc19f631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005620a3ef8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005620a3ef8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005620a3edd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005620a3b8ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005620a3b8cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc19f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc19f6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc19f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005620a3b8ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c (2824 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4(<vscale x 16 x half> %
# | ...
# `---data was truncated (10240/149145) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a1a0ed2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a1a0ecfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a1a0ed362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fde55b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fde55b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fde55b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fde55b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a1a0e68bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a1a0e68a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a1a0e4d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a1a0afce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a1a0afcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fde55b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fde55b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fde55b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a1a0afca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c (2825 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei8_v_f16mf4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei8_v_f16mf2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei8_v_f16m1(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei8_v_f16m2(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei8_v_f16m4(ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vluxei8_v_f16m8(ptr noundef %base, <vscale x 32 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> poison, ptr %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei8_v_f32mf2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei8_v_f32m1(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei8_v_f32m2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei8_v_f32m4(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i8.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i8.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline noun
# | ...
# `---data was truncated (10240/121187) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d687b4deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d687b4ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d687b4e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8381333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f838138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8381333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f838131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d687ae3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d687ae3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d687ac88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d687777e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d687777b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f838131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f838131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f838131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d687777a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c (2826 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_i8mf8x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_i8mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e8_v_i8mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e8_v_i8m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_u8mf8x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_u8mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e8_v_u8mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e8_v_u8m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_i8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 
# | ...
# `---data was truncated (10240/19037) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ebdff05eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ebdff02e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ebdff0662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6ee3b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6ee3b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6ee3b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6ee3b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ebdfe9bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ebdfe9ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ebdfe808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ebdfb2fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ebdfb2fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6ee3b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6ee3b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6ee3b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ebdfb2fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c (2827 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f16m1x4(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_f16m2x4(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f32m1x4(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_f32m2x4(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f64m1x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.
# | ...
# `---data was truncated (10240/87884) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b330810eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b33080de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b33081162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc197849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc1978a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc197849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc197831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b3307a6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b3307a6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b33078b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b33043ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b33043ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc197832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc1978330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc1978330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b33043aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c (2828 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfle_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfle_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfle_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 3
# | ...
# `---data was truncated (10240/27794) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563bf8fbfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563bf8fbce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563bf8fc062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8012133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f801218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8012133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f801211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563bf8f55bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563bf8f55a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563bf8f3a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563bf8be9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563bf8be9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f801211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f801211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f801211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563bf8be9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vbicq.c (2829 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vbicq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vbicq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = xor <16 x i8> %1, splat (i8 -1)
# |   %3 = and <16 x i8> %0, %2
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = xor <8 x i16> %1, splat (i16 -1)
# |   %3 = and <8 x i16> %0, %2
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = xor <4 x i32> %1, splat (i32 -1)
# |   %3 = and <4 x i32> %0, %2
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vbicq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = xor <4 x i32> %3, splat (i32 -1)
# |   %5 = and <4 x i32> %1, %4
# |   %6 = bitcast <4 x i32> %5 to <4 x float>
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vbicq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.bic.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.bic.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vbicq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <8 x i16>
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = bitcast <8 x half> %2 to <8 x i16>
# |   %4 = load i16, ptr %p.addr, align 2
# |   %5 = zext i16 %4 to i32
# |   %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5)
# |   %7 = load <8 x half>, ptr %inactive.addr, align 8
# |   %8 = bitcast <8 x half> %7 to <8 x i16>
# |   %9 = call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8)
# |   %10 = bitcast <8 x i16> %9 to <8 x half>
# |   ret <8 x half> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vbicq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.bic.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vbicq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = load i16, ptr %p.addr
# | ...
# `---data was truncated (10240/11060) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fcda393eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fcda390e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fcda39462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb05e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb05e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb05e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb05e831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fcda329bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fcda329a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fcda30e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fcd9fbde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fcd9fbdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb05e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb05e8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb05e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fcd9fbda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c (2830 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_f16mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_f16mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_f16m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_i16mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_i16mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_i16m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_u16mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_u16mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_u16m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_f16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.v
# | ...
# `---data was truncated (10240/20439) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560a26ee4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560a26ee1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560a26ee562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f57ca533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57ca58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f57ca533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f57ca51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a26e7abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560a26e7aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560a26e5f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560a26b0ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560a26b0eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f57ca51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57ca51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57ca51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a26b0ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c (2831 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16mf2(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.insert.nxv2bf16.nxv1bf16(<vscale x 2 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.insert.nxv2bf16.nxv1bf16(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m1(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv1bf16(<vscale x 4 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv1bf16(<vscale x 4 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m2(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv1bf16(<vscale x 8 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv1bf16(<vscale x 8 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m4(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv1bf16(<vscale x 16 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv1bf16(<vscale x 16 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m8(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv1bf16(<vscale x 32 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv1bf16(<vscale x 32 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m1(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv2bf16(<vscale x 4 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv2bf16(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m2(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv2bf16(<vscale x 8 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv2bf16(<vscale x 8 x bfloat>, <vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m4(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv2bf16(<vscale x 16 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv2bf16(<vscale x 16 x bfloat>, <vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m8(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv2bf16(<vscale x 32 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv2bf16(<vscale x 32 x bfloat>, <vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_ext_v_bf16m1_bf16m2(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16m1_bf16m4(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16m1_bf16m8(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16m2_bf16m4(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16m2_bf16m8(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca
# | ...
# `---data was truncated (10240/12137) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb3f360eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fb3f35de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fb3f36162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f70dc649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f70dc6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f70dc649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f70dc631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb3f2f6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fb3f2f6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fb3f2db8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fb3ef8ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fb3ef8ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f70dc632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f70dc6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f70dc6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb3ef8aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c (2832 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_f16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_f16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_f16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_i16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_i16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_i16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_u16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_u16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_u16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", 
# | ...
# `---data was truncated (10240/23365) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005587163d2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005587163cfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005587163d362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcafee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcafeea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcafee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcafee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558716368bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558716368a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055871634d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558715ffce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558715ffcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcafee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcafee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcafee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558715ffca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c (2833 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16mf4x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16mf2x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16m1x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556bce652eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556bce64fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556bce65362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6804933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f680498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6804933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f680491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556bce5e8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556bce5e8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556bce5cd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556bce27ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556bce27cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f680491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f680491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f680491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556bce27ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c (2834 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_f32mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_f32m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_i32mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_i32m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_u32mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_u32m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs:
# | ...
# `---data was truncated (10240/16382) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005643ddd53eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005643ddd50e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005643ddd5462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f263d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f263d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f263d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f263d031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005643ddce9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005643ddce9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005643ddcce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005643dd97de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005643dd97db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f263d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f263d0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f263d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005643dd97da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c (2835 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_f32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_f32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_i32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_i32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_u32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_u32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vsca
# | ...
# `---data was truncated (10240/15944) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005628f5912eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005628f590fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005628f591362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4de7933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4de798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4de7933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4de791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005628f58a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005628f58a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005628f588d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005628f553ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005628f553cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4de791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4de791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4de791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005628f553ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c (2836 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_bf16mf4_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_bf16mf2_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_bf16m1_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_bf16m2_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_bf16m4_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_bf16m8_i8m4_tu(<vscale x 32 x i8> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> %0, <vscale x 32 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_bf16mf4_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_bf16mf2_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_bf16m1_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_bf16m2_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %v
# | ...
# `---data was truncated (10240/142327) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee97d48eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ee97d45e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ee97d4962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fea62e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fea62ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fea62e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fea62e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee97cdebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ee97cdea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ee97cc38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ee97972e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ee97972b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fea62e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fea62e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fea62e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee97972a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c (2837 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_rod_f_f_w_f16mf4(<vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_rod_f_f_w_f16mf2(<vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfncvt_rod_f_f_w_f16m1(<vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfncvt_rod_f_f_w_f16m2(<vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfncvt_rod_f_f_w_f16m4(<vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfncvt_rod_f_f_w_f32mf2(<vscale x 1 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> poison, <vscale x 1 x double> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfncvt_rod_f_f_w_f32m1(<vscale x 2 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> poison, <vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfncvt_rod_f_f_w_f32m2(<vscale x 4 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> poison, <vscale x 4 x double> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfncvt_rod_f_f_w_f32m4(<vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> poison, <vscale x 8 x double> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_rod_f_f_w_f16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_rod_f_f_w_f16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define 
# | ...
# `---data was truncated (10240/18595) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056347ae4aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056347ae47e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056347ae4b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb849733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb84978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb849733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb84971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056347ade0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056347ade0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056347adc58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056347aa74e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056347aa74b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb84971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb84971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb84971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056347aa74a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c (2838 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8mf8x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_u8mf8x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_u8mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_u8mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_u8m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   
# | ...
# `---data was truncated (10240/21558) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563056ce4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563056ce1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563056ce562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe716533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe71658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe716533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe71651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563056c7abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563056c7aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563056c5f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056305690ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056305690eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe71651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe71651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe71651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056305690ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c (2839 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb9cc73eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fb9cc70e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fb9cc7462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f77e5849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f77e58a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f77e5849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f77e5831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb9cc09bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fb9cc09a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fb9cbee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fb9c89de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fb9c89db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f77e5832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f77e58330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f77e58330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb9c89da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c (2840 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_bf16mf4_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_bf16mf4_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_bf16mf2_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_bf16mf2_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_bf16m1_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_bf16m1_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_bf16m2_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_bf16m2_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.
# | ...
# `---data was truncated (10240/51804) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556983a1beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556983a18e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556983a1c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b16a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b16aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b16a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b16a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005569839b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005569839b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005569839968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556983645e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556983645b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8b16a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b16a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b16a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556983645a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c (2841 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_f64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_f64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_i64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_i64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_u64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_u64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_f64m1x3_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale
# | ...
# `---data was truncated (10240/40852) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559a8bd8aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559a8bd87e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559a8bd8b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f37d7c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f37d7ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f37d7c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f37d7c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a8bd20bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559a8bd20a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559a8bd058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559a8b9b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559a8b9b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f37d7c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f37d7c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f37d7c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a8b9b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c (2842 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556c1a399eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556c1a396e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556c1a39a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7b3aa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7b3aa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7b3aa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7b3aa03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556c1a32fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556c1a32fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556c1a3148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556c19fc3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556c19fc3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7b3aa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7b3aa050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7b3aa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556c19fc3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c (2843 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_f32mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_f32m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_f32m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_i32mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_i32m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_i32m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_u32mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_u32m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_u32m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_f32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | decl
# | ...
# `---data was truncated (10240/20497) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558e643bfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558e643bce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558e643c062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f90a8a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f90a8aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f90a8a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f90a8a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558e64355bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558e64355a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558e6433a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558e63fe9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558e63fe9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f90a8a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f90a8a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f90a8a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558e63fe9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-neon-endianness.c (2844 of 27911)
******************** TEST 'Clang :: CodeGen/arm-neon-endianness.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8a-arm-none-eabihf -target-cpu generic -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c -disable-O0-optnone |  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c --check-prefix=LE
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8a-arm-none-eabihf -target-cpu generic -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8a-arm-none-eabihf"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @int32x4_t_lane_0(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <4 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   store <4 x i32> %0, ptr %__s0, align 8
# |   %1 = load <4 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i32> %1, i32 0
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @int32x4_t_lane_1(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <4 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   store <4 x i32> %0, ptr %__s0, align 8
# |   %1 = load <4 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i32> %1, i32 1
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @int32x4_t_lane_2(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <4 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   store <4 x i32> %0, ptr %__s0, align 8
# |   %1 = load <4 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i32> %1, i32 2
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @int32x4_t_lane_3(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <4 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   store <4 x i32> %0, ptr %__s0, align 8
# |   %1 = load <4 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i32> %1, i32 3
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @int32x2_t_lane_0(<2 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0, align 8
# |   %1 = load <2 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x i32> %1, i32 0
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @int32x2_t_lane_1(<2 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0, align 8
# |   %1 = load <2 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x i32> %1, i32 1
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @int64x2_t_lane_0(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   %__ret = alloca i64, align 8
# |   %__s0 = alloca <2 x i64>, align 8
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   store <2 x i64> %0, ptr %__s0, align 8
# |   %1 = load <2 x i64>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x i64> %1, i32 0
# |   store i64 %vget_lane, ptr %ref.tmp, align 8
# |   %2 = load i64, ptr %ref.tmp, align 8
# |   store i64 %2, ptr %__ret, align 8
# |   %3 = load i64, ptr %__ret, align 8
# |   store i64 %3, ptr %tmp, align 8
# |   %4 = load i64, ptr %tmp, align 8
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @int64x2_t_lane_1(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   %__ret = alloca i64, align 8
# |   %__s0 = alloca <2 x i64>, align 8
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   store <2 x i64> %0, ptr %__s0, align 8
# |   %1 = load <2 x i64>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x i64> %1, i32 1
# |   store i64 %vget_lane, ptr %ref.tmp, align 8
# |   %2 = load i64, ptr %ref.tmp, align 8
# |   store i64 %2, ptr %__ret, align 8
# |   %3 = load i64, ptr %__ret, align 8
# |   store i64 %3, ptr %tmp, align 8
# |   %4 = load i64, ptr %tmp, align 8
# |   ret i64 %4
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+aes,+armv8-a,+crc,+d32,+dsp,+fp-armv8,+fp-armv8d16,+fp-armv8d16sp,+fp-armv8sp,+fp16,+fp64,+hwdiv,+hwdiv-arm,+neon,+sha2,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp,-thumb-mode" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"aapcs"}
# | !1 = !{i32 1, !"min_enum_size", i32 4}
# | !2 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !3 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine -o -
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine -o -
# |  #0 0x0000557cd0cdbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557cd0cd8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557cd0cdc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ea5e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ea5ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ea5e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ea5e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557cd0c71bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557cd0c71a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557cd0c568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557cd0905e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557cd0905b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5ea5e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ea5e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ea5e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557cd0905a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c --check-prefix=LE
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c --check-prefix=LE
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c (2845 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vtdiscard() #0 {
# | entry:
# |   call void @llvm.riscv.sf.vtdiscard()
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtdiscard() #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005632b4670eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005632b466de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005632b467162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3e25d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3e25d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3e25d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3e25ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005632b4606bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005632b4606a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005632b45eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005632b429ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005632b429ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3e25ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3e25cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3e25cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005632b429aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c (2846 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_i16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_i16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_i16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_u16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_u16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7),
# | ...
# `---data was truncated (10240/53330) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005577eaa55eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005577eaa52e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005577eaa5662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcfaca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcfacaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcfaca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcfaca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005577ea9ebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005577ea9eba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005577ea9d08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005577ea67fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005577ea67fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcfaca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcfaca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcfaca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005577ea67fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c (2847 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005593788f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005593788f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005593788f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f263b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f263b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f263b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f263b71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055937888ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055937888ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005593788738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559378522e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559378522b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f263b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f263b71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f263b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559378522a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c (2848 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrsub_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrsub_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrsub_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrsub_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrsub_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrsub_vf_f16m8(<vscale x 32 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrsub_vf_f32mf2(<vscale x 1 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrsub_vf_f32m1(<vscale x 2 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrsub_vf_f32m2(<vscale x 4 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfrsub.nxv4f32.f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrsub.nxv4f32.f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrsub_vf_f32m4(<vscale x 8 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfrsub.nxv8f32.f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfrsub.nxv8f32.f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @
# | ...
# `---data was truncated (10240/61058) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c7f9bd8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c7f9bd5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c7f9bd962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f78e0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f78e08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f78e0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f78e0831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c7f9b6ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c7f9b6ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c7f9b538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c7f9802e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c7f9802b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f78e0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f78e08330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f78e08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c7f9802a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c (2849 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i64> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %3, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, <vscale x 8 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target
# | ...
# `---data was truncated (10240/10700) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b972c33eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b972c30e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b972c3462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f9bd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f9bd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f9bd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f9bced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b972bc9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b972bc9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b972bae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b97285de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b97285db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6f9bceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f9bcef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f9bcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b97285da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c (2850 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractva
# | ...
# `---data was truncated (10240/27866) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563dd6bbaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563dd6bb7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563dd6bbb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f499fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f499fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f499fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f499fd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563dd6b50bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563dd6b50a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563dd6b358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563dd67e4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563dd67e4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f499fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f499fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f499fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563dd67e4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c (2851 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_i8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_i8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8_v_i8m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_u8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_u8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_u8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8_v_u8m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_i8mf8x8_tum(<vscale x 1 x 
# | ...
# `---data was truncated (10240/43119) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cd44fd0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cd44fcde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cd44fd162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffadeb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffadeb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffadeb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffadeb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cd44f66bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cd44f66a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cd44f4b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cd44bfae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cd44bfab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffadeb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffadeb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffadeb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cd44bfaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c (2852 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_f32mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_f32m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_f32m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_i32mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_i32m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_i32m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_u32mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_u32m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_u32m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_f32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void
# | ...
# `---data was truncated (10240/20489) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557698556eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557698553e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055769855762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f13c5f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13c5f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f13c5f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f13c5f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005576984ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005576984eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005576984d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557698180e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557698180b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f13c5f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13c5f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13c5f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557698180a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c (2853 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005568fdd29eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005568fdd26e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005568fdd2a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb1b9849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb1b98a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb1b9849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb1b9831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005568fdcbfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005568fdcbfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005568fdca48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005568fd953e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005568fd953b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb1b9832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb1b98330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb1b98330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005568fd953a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/riscv-xandesperf-rv32.c (2854 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesperf-rv32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c --check-prefix=CHECK-RV32
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ffb(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.nds.ffb.i32(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i32 @llvm.riscv.nds.ffb.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ffzmism(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.nds.ffzmism.i32(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i32 @llvm.riscv.nds.ffzmism.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ffmism(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.nds.ffmism.i32(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i32 @llvm.riscv.nds.ffmism.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_flmism(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.nds.flmism.i32(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i32 @llvm.riscv.nds.flmism.i32(i32, i32) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+xandesperf" }
# | attributes #1 = { nounwind speculatable memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_xandesperf5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056258cb76eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056258cb73e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056258cb7762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f126f41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f126f4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f126f41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f126f403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056258cb0cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056258cb0ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056258caf18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056258c7a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056258c7a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f126f404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f126f4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f126f4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056258c7a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c --check-prefix=CHECK-RV32
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c --check-prefix=CHECK-RV32
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c (2855 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vunzipe_v_bf16mf4(<vscale x 2 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vunzipe_v_bf16mf2(<vscale x 4 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vunzipe_v_bf16m1(<vscale x 8 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vunzipe_v_bf16m2(<vscale x 16 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vunzipe_v_bf16m4(<vscale x 32 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee563e8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ee563e5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ee563e962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc88333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc8838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc88333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc8831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee5637ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ee5637ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ee563638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ee56012e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ee56012b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efc8831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc8831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc8831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee56012a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c (2856 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_f32mf2x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32ff_v_f32m1x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32ff_v_f32m2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32ff_v_f32m4x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_i32mf2x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32ff_v_i32m1x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32ff_v_i32m2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.
# | ...
# `---data was truncated (10240/17879) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f16215eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564f16212e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564f1621662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb48f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb48f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb48f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb48f91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f161abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564f161aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564f161908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564f15e3fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564f15e3fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb48f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb48f91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb48f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f15e3fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c (2857 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_i16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_i16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_i16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_u16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_u16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x 
# | ...
# `---data was truncated (10240/53338) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560b96b26eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560b96b23e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560b96b2762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4112c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4112ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4112c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4112c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b96abcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560b96abca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560b96aa18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560b96750e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560b96750b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4112c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4112c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4112c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b96750a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c (2858 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4aus_vx_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4aus_vx_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs:
# | ...
# `---data was truncated (10240/13649) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005588cf0e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005588cf0e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005588cf0e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f26a4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f26a438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f26a4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f26a431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005588cf07abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005588cf07aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005588cf05f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005588ced0ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005588ced0eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f26a431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f26a431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f26a431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005588ced0ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c (2859 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_f16mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_f16mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_f16m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_f16m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_i16mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_i16mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_i16m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_i16m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_u16mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_u16mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.
# | ...
# `---data was truncated (10240/26921) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563dbe2bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563dbe2b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563dbe2bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9c7a81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9c7a8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9c7a81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9c7a803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563dbe251bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563dbe251a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563dbe2368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563dbdee5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563dbdee5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9c7a804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9c7a8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9c7a8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563dbdee5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c (2860 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_f64m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_f64m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_i64m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_i64m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_u64m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_u64m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_i64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_i64m2x3_m(<vscale x 2 x i1
# | ...
# `---data was truncated (10240/14031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b985cb6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b985cb3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b985cb762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f95c1649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f95c16a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f95c1649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f95c1631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b985c4cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b985c4ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b985c318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b9858e0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b9858e0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f95c1632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f95c16330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f95c16330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b9858e0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c (2861 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmerge_vfm_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmerge_vfm_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmerge_vfm_f16m1(<vscale x 4 x half> %op1, half noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmerge_vfm_f16m2(<vscale x 8 x half> %op1, half noundef %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmerge_vfm_f16m4(<vscale x 16 x half> %op1, half noundef %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, <vscale x 16 x i1> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfmerge_vfm_f16m8(<vscale x 32 x half> %op1, half noundef %op2, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, <vscale x 32 x i1> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfmerge_vfm_f32mf2(<vscale x 1 x float> %op1, float noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfmerge_vfm_f32m1(<vscale x 2 x float> %op1, float noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfmerge.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfmerge.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfmerge_vfm_f32m2(<vscale x 4 x float> %op1, float noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %mask.addr = alloca <vscale x 4 x i1>, align
# | ...
# `---data was truncated (10240/19041) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aa8a107eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aa8a104e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aa8a10862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f775a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f775a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f775a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f775a431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa8a09dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aa8a09da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aa8a0828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aa89d31e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aa89d31b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f775a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f775a4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f775a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa89d31a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c (2862 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005626ad45feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005626ad45ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005626ad46062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc631e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc631ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc631e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc631e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005626ad3f5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005626ad3f5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005626ad3da8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005626ad089e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005626ad089b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc631e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc631e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc631e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005626ad089a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c (2863 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4aus_vx_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4aus_vx_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) 
# | ...
# `---data was truncated (10240/25094) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560d45074eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560d45071e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560d4507562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2376b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2376b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2376b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2376b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560d4500abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560d4500aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560d44fef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560d44c9ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560d44c9eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2376b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2376b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2376b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560d44c9ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c (2864 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei16_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, ali
# | ...
# `---data was truncated (10240/14621) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055625e1bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055625e1b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055625e1bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9f2b21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9f2b2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9f2b21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9f2b203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055625e152bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055625e152a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055625e1378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055625dde6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055625dde6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9f2b204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9f2b2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9f2b2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055625dde6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c (2865 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4asu_vx_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4asu_vx_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs:
# | ...
# `---data was truncated (10240/13649) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559c4db4aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559c4db47e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559c4db4b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0291c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0291ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0291c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0291c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c4dae0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559c4dae0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559c4dac58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559c4d774e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559c4d774b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0291c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0291c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0291c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c4d774a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c (2866 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_i8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e8_v_i8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e8_v_i8m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_u8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_u8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e8_v_u8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/48305) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d5afa9aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d5afa97e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d5afa9b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4a0e41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4a0e4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4a0e41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4a0e403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d5afa30bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d5afa30a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d5afa158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d5af6c4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d5af6c4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4a0e404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4a0e4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4a0e4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d5af6c4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c (2867 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgtu_vv_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgtu_vx_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgtu_vv_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgtu_vx_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgtu_vv_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgtu_vx_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgtu_vv_u8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8
# | ...
# `---data was truncated (10240/63713) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d20c849eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d20c846e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d20c84a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f58b3d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f58b3d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f58b3d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f58b3d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d20c7dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d20c7dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d20c7c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d20c473e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d20c473b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f58b3d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f58b3d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f58b3d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d20c473a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c (2868 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005590b3807eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005590b3804e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005590b380862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5afba1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5afba725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5afba1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5afba03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005590b379dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005590b379da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005590b37828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005590b3431e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005590b3431b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5afba04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5afba050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5afba050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005590b3431a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c (2869 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_s_s_w4_i8m8_i8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.s.s.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.s.s.i64.nxv64i8.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564cd43fbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564cd43f8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564cd43fc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac1d61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac1d6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac1d61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac1d603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564cd4391bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564cd4391a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564cd43768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564cd4025e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564cd4025b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fac1d604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac1d6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac1d6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564cd4025a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c (2870 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16mf4x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16mf2x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16m1x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16m2x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16m4x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store targ
# | ...
# `---data was truncated (10240/14667) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c57ee8feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c57ee8ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c57ee9062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6b70133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6b7018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6b70133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6b7011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c57ee25bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c57ee25a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c57ee0a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c57eab9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c57eab9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6b7011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6b7011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6b7011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c57eab9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c (2871 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 8 x i64>, ptr %
# | ...
# `---data was truncated (10240/20631) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba59ee1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ba59edee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ba59ee262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff393c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff393ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff393c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff393c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba59e77bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ba59e77a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ba59e5c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ba59b0be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ba59b0bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff393c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff393c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff393c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba59b0ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c (2872 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16bf16.p0.i64(<vscale x 16 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv32bf16.p0.i64(<vscale x 32 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %2, ptr %1, <vscale x 1 x i1> %0, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %2, ptr %1, <vscale x 2 x i1> %0, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %2, ptr %1, <vscale x 4 x i1> %0, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %2, ptr %1, <vscale x 8 x i1> %0, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m4_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# | 
# | ...
# `---data was truncated (10240/12652) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dcdcacdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dcdcacae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dcdcace62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa1dd449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa1dd4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa1dd449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa1dd431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dcdca63bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dcdca63a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dcdca488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dcdc6f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dcdc6f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa1dd432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa1dd4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa1dd4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dcdc6f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c (2873 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfdiv_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfdiv_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfdiv_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfdiv_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfdiv_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfdiv_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfdiv_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfdiv_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfdiv_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfdiv.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfdiv.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfdiv_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfdiv.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, ha
# | ...
# `---data was truncated (10240/125649) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055998ee88eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055998ee85e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055998ee8962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ec0f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ec0f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ec0f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ec0f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055998ee1ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055998ee1ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055998ee038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055998eab2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055998eab2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5ec0f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ec0f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ec0f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055998eab2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c (2874 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8mf8x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_u8mf8x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_u8mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_u8mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_u8m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, al
# | ...
# `---data was truncated (10240/21566) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cf6cd49eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cf6cd46e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cf6cd4a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1fe2049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1fe20a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1fe2049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1fe2031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf6ccdfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cf6ccdfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cf6ccc48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cf6c973e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cf6c973b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1fe2032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1fe20330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1fe20330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf6c973a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/load-store.c (2875 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/load-store.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vld1q_f16(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x half>, ptr %0, align 2
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vld1q_f32(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <4 x float>, ptr %0, align 4
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vld1q_s8(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <16 x i8>, ptr %0, align 1
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vld1q_s16(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x i16>, ptr %0, align 2
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vld1q_s32(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <4 x i32>, ptr %0, align 4
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vld1q_u8(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <16 x i8>, ptr %0, align 1
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vld1q_u16(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x i16>, ptr %0, align 2
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vld1q_u32(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <4 x i32>, ptr %0, align 4
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vld1q_z_f16(ptr noundef %base, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = call <8 x half> @llvm.masked.load.v8f16.p0(ptr align 2 %0, <8 x i1> %3, <8 x half> zeroinitializer)
# |   ret <8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <8 x half> @llvm.masked.load.v8f16.p0(ptr captures(none), <8 x i1>, <8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vld1q_z_f32(ptr noundef %base, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = call <4 x float> @llvm.masked.load.v4f32.p0(ptr align 4 %0, <4 x i1> %3, <4 x float> zeroinitializer)
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <4 x float> @llvm.masked.load.v4f32.p0(ptr captures(none), <4 x i1>, <4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vld1q_z_s8(ptr noundef %base, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr align 1 %0, <16 x i1> %3, <16 x i8> zeroinitializer)
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <16 x i8> @llvm.masked.load.v16i8.p0(ptr captures(none), <16 x i1>, <16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vld1q_z_s16(ptr noundef %base, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr align 2 %0, <8 x i1> %3, <8 x i16> zeroinitializer)
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <8 x i16> @llvm.masked.load.v8i16.p0(ptr captures(none), <8 x i1>, <8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vld1q_z_s32(ptr noundef %base, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 4 %0, <4 x i1> %3, <4 x i32> zeroinitializer)
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr captures(none), <4 x i1>, <4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vld1q_z_u8(ptr noundef %base, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr align 1 %0, <16 x i1> %3, <16 x i8> zeroinitializer)
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vld1q_z_u16(ptr noundef %base, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr align 2 %0, <8 x i1> %3, <8 x i16> zeroinitializer)
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vld1q_z_u32(ptr noundef %base, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 4 %0, <4 x i1> %3, <4 x i32> zeroinitializer)
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_s8(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <16 x i8>, ptr %0, align 1
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_s16(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x i8>, ptr %0, align 1
# |   %2 = sext <8 x i8> %1 to <8 x i16>
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_s32(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <4 x i8>, ptr %0, align 1
# |   %2 = sext <4 x i8> %1 to <4 x i32>
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_u8(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <16 x i8>, ptr %0, align 1
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_u16(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = a
# | ...
# `---data was truncated (10240/50873) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564b3588aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564b35887e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564b3588b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9bc6733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9bc678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9bc6733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9bc671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564b35820bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564b35820a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564b358058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564b354b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564b354b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9bc671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9bc671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9bc671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564b354b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c (2876 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmax_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmax_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmax_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmax_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmax_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmax_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmax_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmax_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ...
# `---data was truncated (10240/64958) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f2f076feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f2f076ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f2f077062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb19a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb19a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb19a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb19a831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f2f0705bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f2f0705a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f2f06ea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f2f0399e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f2f0399b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb19a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb19a8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb19a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f2f0399a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c (2877 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_rod_f_f_w_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_rod_f_f_w_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfncvt_rod_f_f_w_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfncvt_rod_f_f_w_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfncvt_rod_f_f_w_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfncvt_rod_f_f_w_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> %0, <vscale x 1 x double> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfncvt_rod_f_f_w_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> %0, <vscale x 2 x double> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfncvt_rod_f_f_w_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> %0, <vscale x 4 x double> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfncvt_rod_f_f_w_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> %0, <vscale x 8 x double> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_rod_f_f_w_f16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x half> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i
# | ...
# `---data was truncated (10240/41934) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056477aa79eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056477aa76e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056477aa7a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f09b8249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f09b82a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f09b8249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f09b8231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056477aa0fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056477aa0fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056477a9f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056477a6a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056477a6a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f09b8232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f09b82330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f09b82330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056477a6a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c (2878 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/14613) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561de6709eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561de6706e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561de670a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f29f0649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f29f06a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f29f0649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f29f0631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561de669fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561de669fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561de66848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561de6333e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561de6333b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f29f0632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f29f06330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f29f06330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561de6333a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c (2879 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_i8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e8_v_i8mf2x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e8_v_i8m1x6_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_u8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_u8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e8_v_u8mf2x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e8_v_u8m1x6_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv8i1(target("riscv.vector.tup
# | ...
# `---data was truncated (10240/11031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560fedd0beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560fedd08e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560fedd0c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f997c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f997c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f997c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f997c031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560fedca1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560fedca1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560fedc868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560fed935e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560fed935b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f997c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f997c0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f997c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560fed935a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqsubq.c (2880 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqsubq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqsubq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i8> @llvm.usub.sat.v16i8(<16 x i8>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqsubq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqsubq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i32> @llvm.usub.sat.v4i32(<4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqsubq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.qsub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.qsub.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqsubq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.qsub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.qsub.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqsubq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.qsub.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.qsub.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqsubq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %0, <16 x i8> %.splat)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqsubq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %0, <8 x i16> %.splat)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqsubq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %0, <4 x i32> %.splat)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqsubq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.qsub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqsubq_m_n_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.qsub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, i32 1, <8 x i1> %4, <8 
# | ...
# `---data was truncated (10240/12015) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f9a5743eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f9a5740e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f9a574462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd416733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd41678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd416733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd41671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f9a56d9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f9a56d9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f9a56be8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f9a536de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f9a536db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd41671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd41671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd41671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f9a536da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c (2881 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f16m1x3(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_f16m2x3(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f32m1x3(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_f32m2x3(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f64m1x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.
# | ...
# `---data was truncated (10240/82975) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f027c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564f027c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564f027c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feda0d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feda0d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feda0d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feda0d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f0275abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564f0275aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564f0273f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564f023eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564f023eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feda0d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feda0d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feda0d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f023eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c (2882 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nx
# | ...
# `---data was truncated (10240/18660) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ad03b95eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ad03b92e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ad03b9662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffa95d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffa95d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffa95d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffa95ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad03b2bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ad03b2ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ad03b108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ad037bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ad037bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffa95ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffa95cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffa95cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad037bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c (2883 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i64> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %3, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, <vscale x 8 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-feature
# | ...
# `---data was truncated (10240/10692) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561f34632eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561f3462fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561f3463362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1cc9705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1cc975c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1cc9705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1cc96ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f345c8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561f345c8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561f345ad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561f3425ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561f3425cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1cc96eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1cc96ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1cc96ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f3425ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c (2884 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xtheadbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c  -check-prefix=RV64XTHEADBB
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xtheadbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @clz_32(i32 noundef signext %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call i32 @llvm.ctlz.i32(i32 %0, i1 false)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.ctlz.i32(i32, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @clo_32(i32 noundef signext %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %not = xor i32 %0, -1
# |   %1 = call i32 @llvm.ctlz.i32(i32 %not, i1 false)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @clz_64(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = call i64 @llvm.ctlz.i64(i64 %0, i1 false)
# |   %cast = trunc i64 %1 to i32
# |   ret i32 %cast
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.ctlz.i64(i64, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @clo_64(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %not = xor i64 %0, -1
# |   %1 = call i64 @llvm.ctlz.i64(i64 %not, i1 false)
# |   %cast = trunc i64 %1 to i32
# |   ret i32 %cast
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xtheadbb" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_xtheadbb1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f68c16ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f68c169e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f68c16d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd991733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd99178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd991733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd99171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f68c102bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f68c102a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f68c0e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f68bd96e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f68bd96b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd99171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd99171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd99171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f68bd96a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c -check-prefix=RV64XTHEADBB
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c -check-prefix=RV64XTHEADBB
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c (2885 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgt_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgt_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgt_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgt_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgt_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgt_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgt_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgt_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgt_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgt_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsgt_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsgt.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> %0, 
# | ...
# `---data was truncated (10240/95081) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560a5ff21eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560a5ff1ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560a5ff2262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9b3e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9b3e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9b3e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9b3e51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a5feb7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560a5feb7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560a5fe9c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560a5fb4be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560a5fb4bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9b3e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9b3e51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9b3e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a5fb4ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c (2886 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>
# | ...
# `---data was truncated (10240/19492) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055abf89f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055abf89f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055abf89fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe391c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe391c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe391c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe391c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055abf898fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055abf898fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055abf89748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055abf8623e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055abf8623b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe391c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe391c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe391c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055abf8623a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c (2887 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +xandesvbfhcvt -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_nds_vfwcvt_s_bf16_f32mf2(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_nds_vfwcvt_s_bf16_f32m1(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_nds_vfwcvt_s_bf16_f32m2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_nds_vfwcvt_s_bf16_f32m4(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_nds_vfwcvt_s_bf16_f32m8(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d0d87edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d0d87eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d0d87ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5874533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f587458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5874533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f587451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0d8783bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d0d8783a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d0d87688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d0d8417e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d0d8417b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f587451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f587451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f587451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d0d8417a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c (2888 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_bf16m4x2_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e89c8e6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e89c8e3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e89c8e762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f54de81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54de8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f54de81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f54de803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e89c87cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e89c87ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e89c8618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e89c510e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e89c510b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f54de804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54de8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54de8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e89c510a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c (2889 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f16m1x7(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f32m1x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f64m1x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei64_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565016883eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565016880e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056501688462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff159849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff1598a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff159849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff159831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565016819bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565016819a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005650167fe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005650164ade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005650164adb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff159832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff1598330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff1598330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005650164ada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c (2890 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: noca
# | ...
# `---data was truncated (10240/100960) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c569078eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c569075e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c56907962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa3dd733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa3dd78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa3dd733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa3dd71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c56900ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c56900ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c568ff38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c568ca2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c568ca2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa3dd71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa3dd71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa3dd71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c568ca2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c (2891 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei32_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, ali
# | ...
# `---data was truncated (10240/14621) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055df22f44eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055df22f41e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055df22f4562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff4da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff4daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff4da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff4da31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055df22edabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055df22edaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055df22ebf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055df22b6ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055df22b6eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007eff4da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff4da330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff4da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055df22b6ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c (2892 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8mf8x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_u8mf8x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_u8mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_u8mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_u8m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |  
# | ...
# `---data was truncated (10240/26713) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056394fe16eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056394fe13e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056394fe1762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f903b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f903b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f903b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f903b91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056394fdacbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056394fdaca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056394fd918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056394fa40e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056394fa40b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f903b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f903b91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f903b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056394fa40a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c (2893 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560c3057deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560c3057ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560c3057e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f56c7933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56c798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f56c7933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f56c791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c30513bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560c30513a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560c304f88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560c301a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560c301a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f56c791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56c791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56c791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c301a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c (2894 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561eb65c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561eb65bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561eb65c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcee0f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcee0f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcee0f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcee0f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561eb6558bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561eb6558a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561eb653d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561eb61ece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561eb61ecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcee0f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcee0f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcee0f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561eb61eca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c (2895 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f16m1x5(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f32m1x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f64m1x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i32> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560b0d9a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560b0d9a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560b0d9a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3c89649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3c896a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3c89649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3c89631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b0d93bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560b0d93ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560b0d9208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560b0d5cfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560b0d5cfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3c89632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3c896330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3c896330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b0d5cfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c (2896 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_i16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_i16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_i16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_u16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_u16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_u16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("ri
# | ...
# `---data was truncated (10240/47480) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005597225a4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005597225a1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005597225a562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce48d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce48d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce48d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce48d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055972253abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055972253aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055972251f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005597221cee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005597221ceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fce48d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce48d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce48d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005597221cea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c (2897 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f16m1x3(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_f16m2x3(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f32m1x3(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_f32m2x3(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f64m1x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/82983) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f8cf60aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f8cf607e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f8cf60b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fed89e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fed89ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fed89e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fed89e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f8cf5a0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f8cf5a0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f8cf5858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f8cf234e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f8cf234b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fed89e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fed89e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fed89e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f8cf234a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c (2898 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_i8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_i8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8_v_i8m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_u8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_u8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_u8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8_v_u8m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_i8mf8x7_tum(<vscale x 1 x 
# | ...
# `---data was truncated (10240/43119) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b6fc395eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b6fc392e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b6fc39662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4393b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4393b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4393b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4393b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b6fc32bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b6fc32ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b6fc3108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b6fbfbfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b6fbfbfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4393b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4393b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4393b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b6fbfbfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c (2899 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_f64m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_f64m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_i64m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_i64m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_u64m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_u64m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_i64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_i64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_u64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.t
# | ...
# `---data was truncated (10240/12089) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005565bcf2aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005565bcf27e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005565bcf2b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f27b8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f27b878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f27b8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f27b871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005565bcec0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005565bcec0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005565bcea58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005565bcb54e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005565bcb54b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f27b871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f27b871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f27b871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005565bcb54a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/thinlto-multi-module.ll (2900 of 27911)
******************** TEST 'Clang :: CodeGen/thinlto-multi-module.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-multi-module.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-multi-module.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-multi-module.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-multi-module.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-multi-module.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-multi-module.ll
# |  #0 0x0000557672ca0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557672c9de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557672ca162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f615db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f615db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f615db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f615db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557672c36bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557672c36a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557672c1b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005576728cae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005576728cab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f615db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f615db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f615db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005576728caa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c (2901 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d39a845eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d39a842e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d39a84662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f477d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f477d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f477d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f477d91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d39a7dbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d39a7dba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d39a7c08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d39a46fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d39a46fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f477d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f477d91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f477d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d39a46fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c (2902 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmmv_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmmv_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmmv_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmmv_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmmv_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmmv_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmmv_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005571a9e99eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005571a9e96e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005571a9e9a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f43a8d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f43a8d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f43a8d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f43a8d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005571a9e2fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005571a9e2fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005571a9e148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005571a9ac3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005571a9ac3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f43a8d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f43a8d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f43a8d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005571a9ac3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c (2903 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_f64m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_f64m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_i64m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_i64m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_u64m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_u64m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_i64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_i64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64
# | ...
# `---data was truncated (10240/14036) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b17123eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b17123be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b17123f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f975e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f975e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f975e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f975e11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b1711d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b1711d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b1711b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b170e68e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b170e68b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f975e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f975e11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f975e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b170e68a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c (2904 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_vv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_wv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_wx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_vv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_wv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_wx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwadd_vv_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale
# | ...
# `---data was truncated (10240/306025) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec4b4b8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ec4b4b5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ec4b4b962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f579a105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f579a15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f579a105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f579a0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec4b44ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ec4b44ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ec4b4338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ec4b0e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ec4b0e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f579a0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f579a0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f579a0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec4b0e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c (2905 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d67471feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d67471ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d67472062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9aab705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9aab75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9aab705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9aab6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d6746b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d6746b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d67469a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d674349e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d674349b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9aab6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9aab6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9aab6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d674349a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c (2906 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f    -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_sf_vfexp_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_sf_vfexp_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_sf_vfexp_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_sf_vfexp_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_sf_vfexp_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_sf_vfexp_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_sf_vfexp_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_sf_vfexp_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_sf_vfexp_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(<vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 
# | ...
# `---data was truncated (10240/27063) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005629d7226eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005629d7223e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005629d722762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a2a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a2a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a2a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a2a11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005629d71bcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005629d71bca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005629d71a18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005629d6e50e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005629d6e50b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2a2a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a2a11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a2a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005629d6e50a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c (2907 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8mf8x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8mf4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_u8mf8x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_u8mf4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_u8mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_u8m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %
# | ...
# `---data was truncated (10240/27994) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556d85090eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556d8508de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556d8509162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faea6d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faea6d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faea6d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faea6ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556d85026bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556d85026a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556d8500b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556d84cbae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556d84cbab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faea6ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faea6cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faea6cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556d84cbaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c (2908 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_2x8x2_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_2x8x2_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_2x8x2_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_2x8x2_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005645ef301eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005645ef2fee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005645ef30262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f47f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f47f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f47f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f47f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005645ef297bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005645ef297a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005645ef27c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005645eef2be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005645eef2bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4f47f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f47f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f47f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005645eef2ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c (2909 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_f16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_f16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_f16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_i16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_i16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_i16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_u16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_u16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_u16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale 
# | ...
# `---data was truncated (10240/23357) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005572799f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005572799efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005572799f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3a84b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3a84b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3a84b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3a84aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557279988bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557279988a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055727996d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055727961ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055727961cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3a84aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3a84aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3a84aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055727961ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vsubq.c (2910 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vsubq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsubq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = sub <4 x i32> %0, %1
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vsubq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = fsub <8 x half> %0, %1
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vsubq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.sub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.sub.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vsubq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x float>, ptr %inactive.addr, align 8
# |   %6 = call <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4, <4 x float> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vsubq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.sub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.sub.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vsubq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x half> @llvm.arm.mve.sub.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4, <8 x half> undef)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.sub.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsubq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = sub <4 x i32> %0, %.splat
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vsubq_n_f16(<8 x half> noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca half, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load half, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x half> poison, half %1, i64 0
# |   %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
# |   %2 = fsub <8 x half> %0, %.splat
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vsubq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.sub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vsubq_m_n_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, float noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca float, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store float %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load float, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x float> poison, float %1, i64 0
# |   %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x float>, ptr %inactive.addr, align 8
# |   %6 = call <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %.splat, <4 x i1> %4, <4 x float> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vsubq_x_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.sub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @t
# | ...
# `---data was truncated (10240/11617) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055e93a645eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e93a642e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e93a64662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb67d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb67d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb67d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb67d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e93a5dbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e93a5dba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e93a5c08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e93a26fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e93a26fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffb67d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb67d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb67d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e93a26fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c (2911 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f16m1x8(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f32m1x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f64m1x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei64_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555c49c74eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555c49c71e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555c49c7562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbb9e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbb9e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbb9e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbb9e431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555c49c0abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555c49c0aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555c49bef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555c4989ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555c4989eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbb9e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbb9e4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbb9e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555c4989ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c (2912 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005592ec46ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005592ec469e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005592ec46d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5e06705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5e0675c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5e06705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5e066ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005592ec402bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005592ec402a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005592ec3e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005592ec096e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005592ec096b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5e066eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5e066ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5e066ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005592ec096a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c (2913 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4a_vx_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4a_vx_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | ...
# `---data was truncated (10240/24982) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055899db2deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055899db2ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055899db2e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa481c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa481ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa481c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa481c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055899dac3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055899dac3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055899daa88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055899d757e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055899d757b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa481c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa481c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa481c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055899d757a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c (2914 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f16m1x8(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f32m1x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f64m1x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei8_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vsca
# | ...
# `---data was truncated (10240/61665) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fe5fddceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fe5fdd9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fe5fddd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f959df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f959df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f959df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f959df1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fe5fd72bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fe5fd72a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fe5fd578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fe5fa06e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fe5fa06b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f959df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f959df1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f959df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fe5fa06a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c (2915 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmerge_vfm_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmerge_vfm_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmerge_vfm_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmerge_vfm_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmerge_vfm_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, half noundef %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4)
# |   ret <vscale x 16 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfmerge_vfm_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, half noundef %op2, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, <vscale x 32 x i1> %3, i64 %4)
# |   ret <vscale x 32 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfmerge_vfm_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, float noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function
# | ...
# `---data was truncated (10240/22375) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c734eeeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c734eebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c734eef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe2f9133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe2f918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe2f9133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe2f911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c734e84bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c734e84a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c734e698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c734b18e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c734b18b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe2f911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe2f911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe2f911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c734b18a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c (2916 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8(<vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4(<vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2(<vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1(<vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_x_f_qf_i8m2(<vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: 
# | ...
# `---data was truncated (10240/12431) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559e216f7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559e216f4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559e216f862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f407d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f407d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f407d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f407d31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e2168dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559e2168da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559e216728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559e21321e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559e21321b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f407d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f407d31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f407d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e21321a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c (2917 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.
# | ...
# `---data was truncated (10240/101394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a0c7080eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a0c707de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a0c708162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f53b8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f53b878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f53b8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f53b871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a0c7016bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a0c7016a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a0c6ffb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a0c6caae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a0c6caab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f53b871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f53b871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f53b871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a0c6caaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c (2918 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_i32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_i32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_u32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_u32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ea015a9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ea015a6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ea015aa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e67649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e676a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e67649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e67631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ea0153fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ea0153fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ea015248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ea011d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ea011d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1e67632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e676330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e676330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ea011d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c (2919 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsub_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsub_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsub_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsub_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsub_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsub_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsub_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsub_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7
# | ...
# `---data was truncated (10240/64374) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c94f40eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c94f40be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c94f40f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8764649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87646a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8764649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8764631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c94f3a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c94f3a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c94f3898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c94f038e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c94f038b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8764632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87646330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87646330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c94f038a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c (2920 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwi
# | ...
# `---data was truncated (10240/44369) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557b0428deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557b0428ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557b0428e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f02e8f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f02e8f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f02e8f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f02e8f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b04223bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557b04223a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557b042088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557b03eb7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557b03eb7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f02e8f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f02e8f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f02e8f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b03eb7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c (2921 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8mf8(ptr noundef %base, <vscale x 1 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i8.p0.i64(<vscale x 1 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8mf4(ptr noundef %base, <vscale x 2 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i8.p0.i64(<vscale x 2 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8mf2(ptr noundef %base, <vscale x 4 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i8.p0.i64(<vscale x 4 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8m1(ptr noundef %base, <vscale x 8 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i8.p0.i64(<vscale x 8 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8m2(ptr noundef %base, <vscale x 16 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16i8.p0.i64(<vscale x 16 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8m4(ptr noundef %base, <vscale x 32 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv32i8.p0.i64(<vscale x 32 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8m8(ptr noundef %base, <vscale x 64 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 64 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 64 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv64i8.p0.i64(<vscale x 64 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8mf8(ptr noundef %base, <vscale x 1 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i8.p0.i64(<vscale x 1 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8mf4(ptr noundef %base, <vscale x 2 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i8.p0.i64(<vscale x 2 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8mf2(ptr noundef %base, <vscale x 4 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i8.p0.i64(<vscale x 4 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8m1(ptr noundef %base, <vscale x 8 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i8.p0.i64(<vscale x 8 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8m2(ptr noundef %base, <vscale x 16 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16i8.p0.i64(<vscale x 16 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8m4(ptr noundef %base, <vscale x 32 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv32i8.p0.i64(<vscale x 32 x i8> %1, ptr %0, i64 %2)
# |   ret 
# | ...
# `---data was truncated (10240/25287) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555f2fc04eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555f2fc01e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555f2fc0562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f235ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f235eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f235ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f235ec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f2fb9abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555f2fb9aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555f2fb7f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555f2f82ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555f2f82eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f235ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f235ec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f235ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f2f82ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c (2922 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vctz_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vctz_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vctz.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vctz.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vctz_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vctz.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vctz.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vctz_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vctz.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vctz.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vctz_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vctz.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vctz.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vctz_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vctz.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vctz.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vctz_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vctz.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vctz.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vctz_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vctz.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vctz.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vctz_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vctz.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vctz.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vctz_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vctz.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vctz.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vctz_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vctz.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vctz.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vctz_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vctz.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vctz.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vctz_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vctz.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(
# | ...
# `---data was truncated (10240/40661) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aee42f5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aee42f2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aee42f662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9933449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f99334a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9933449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9933431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aee428bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aee428ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aee42708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aee3f1fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aee3f1fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9933432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f99334330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f99334330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aee3f1fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c (2923 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32ff_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32ff_v_f32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32ff_v_f32m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_i32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32ff_v_i32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale
# | ...
# `---data was truncated (10240/80640) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005582cfbb3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005582cfbb0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005582cfbb462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f36eb849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f36eb8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f36eb849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f36eb831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005582cfb49bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005582cfb49a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005582cfb2e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005582cf7dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005582cf7ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f36eb832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f36eb8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f36eb8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005582cf7dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c (2924 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_bf16mf4_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1bf16.i64(<vscale x 1 x i16> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1bf16.i64(<vscale x 1 x i16>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_bf16mf2_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2bf16.i64(<vscale x 2 x i16> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2bf16.i64(<vscale x 2 x i16>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_bf16m1_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4bf16.i64(<vscale x 4 x i16> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4bf16.i64(<vscale x 4 x i16>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_bf16m2_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8bf16.i64(<vscale x 8 x i16> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8bf16.i64(<vscale x 8 x i16>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_bf16m4_u16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16bf16.i64(<vscale x 16 x i16> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16bf16.i64(<vscale x 16 x i16>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfclass_v_bf16m8_u16m8_tu(<vscale x 32 x i16> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32bf16.i64(<vscale x 32 x i16> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32bf16.i64(<vscale x 32 x i16>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_bf16mf4_u16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i16> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1bf16.i64(<vscale x 1 x i16> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1bf16.i64(<vscale x 1 x i16>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_bf16mf2_u16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i16> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2bf16.i64(<vscale x 2 x i16> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2bf16.i64(<vscale x 2 x i16>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_bf16m1_u16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i16> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4bf16.i64(<vscale x 4 x i16> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4bf16.i64(<vscale x 4 x i16>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_bf16m2_u16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x i16> %vd, <vscale x 8 x bfloat> %vs2, i64 nounde
# | ...
# `---data was truncated (10240/26592) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005580ae6aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005580ae6a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005580ae6ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e90c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e90ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e90c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e90c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005580ae642bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005580ae642a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005580ae6278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005580ae2d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005580ae2d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6e90c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e90c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e90c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005580ae2d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c (2925 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_e4m3_e4m3_w4_f8e4m3m8_f8e4m3m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565110df3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000565110df0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000565110df462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e12933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e1298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e12933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e1291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565110d89bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000565110d89a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000565110d6e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000565110a1de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000565110a1db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1e1291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e1291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e1291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565110a1da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c (2926 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b2a02e2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b2a02dfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b2a02e362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e75f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e75f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e75f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e75f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b2a0278bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b2a0278a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b2a025d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b29ff0ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b29ff0cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1e75f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e75f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e75f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b29ff0ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c (2927 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vle32ff_v_f32mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(<vscale x 1 x float> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x float>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x float>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(<vscale x 1 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vle32ff_v_f32m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(<vscale x 2 x float> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x float>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x float>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(<vscale x 2 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vle32ff_v_f32m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(<vscale x 4 x float> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x float>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x float>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(<vscale x 4 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vle32ff_v_f32m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(<vscale x 8 x float> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 8 x float>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 8 x float>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(<vscale x 8 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vle32ff_v_f32m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(<vscale x 16 x float> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 16 x float>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 16 x float>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 16 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(<vscale x 16 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32ff_v_i32mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(<vscale x 1 x i32> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x i32>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x i32>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(<vscale x 1 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32ff_v_i32m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(<vscale x 2 x i32> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x i32>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i32>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(<vscale x 2 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32ff_v_i32m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.nxv4i32.i64.p0(<vscale x 4 x i32> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x i32>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i32>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.nxv4i32.i64.p0(<vscale x 4 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vle32ff_v_i32m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 8 x i32>, i64 } @llvm.riscv.vleff.nxv8i32.i64.p0(<vscale x 8 x i32> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 8 x i32>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 8 x i32>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x i32>, i64 } @llvm.riscv.vleff.nxv8i32.i64.p0(<vscale x 8 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vle32ff_v_i32m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 16 x i32>, i64 } @llvm.riscv.vleff.nxv16i32.i64.p0(<vscale x 16 x i32> poison, ptr %0, i64 %2)
# |   %4 =
# | ...
# `---data was truncated (10240/33471) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005600358ebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005600358e8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005600358ec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3972849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f39728a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3972849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3972831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560035881bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560035881a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005600358668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560035515e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560035515b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3972832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f39728330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f39728330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560035515a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c (2928 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zvfhmin -target-feature +zvfbfmin    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte16_bf16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vlte16.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte16_f16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte16_i16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte16_u16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvfbfmin,+zvfhmin,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfhmin1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ad9117aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ad91177e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ad9117b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8162333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f816238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8162333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f816231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad91110bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ad91110a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ad910f58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ad90da4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ad90da4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f816231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f816231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f816231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad90da4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c (2929 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf8x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_u8mf8x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_u8mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_u8mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_u8m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.
# | ...
# `---data was truncated (10240/18972) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e2146dbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e2146d8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e2146dc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6216933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f621698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6216933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f621691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e214671bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e214671a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e2146568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e214305e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e214305b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f621691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f621691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f621691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e214305a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c (2930 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dots_vv_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dots_vv_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dots_vv_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dots_vv_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dots_vv_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dots_vv_i64m1_tu(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dots_vv_i64m2_tu(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dots_vv_i64m4_tu(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4i64.nxv1
# | ...
# `---data was truncated (10240/47628) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055705dbbaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055705dbb7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055705dbbb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba43333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba4338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba43333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba4331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055705db50bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055705db50a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055705db358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055705d7e4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055705d7e4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fba4331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba4331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba4331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055705d7e4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c (2931 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_bf16m1x4_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   s
# | ...
# `---data was truncated (10240/24381) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560bc6d9ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560bc6d99e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560bc6d9d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9cdf049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9cdf0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9cdf049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9cdf031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560bc6d32bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560bc6d32a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560bc6d178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560bc69c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560bc69c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9cdf032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9cdf0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9cdf0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560bc69c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c (2932 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_f64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_f64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_f64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_i64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_i64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_i64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_u64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_u64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_u64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target
# | ...
# `---data was truncated (10240/23439) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005608d75a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005608d759fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005608d75a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f15ca049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f15ca0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f15ca049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f15ca031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005608d7538bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005608d7538a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005608d751d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005608d71cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005608d71ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f15ca032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15ca0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15ca0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005608d71cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c (2933 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a1ff6f0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a1ff6ede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a1ff6f162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb6d4133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb6d418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb6d4133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb6d411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a1ff686bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a1ff686a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a1ff66b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a1ff31ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a1ff31ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb6d411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb6d411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb6d411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a1ff31aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c (2934 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredor_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <
# | ...
# `---data was truncated (10240/112825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aff97a8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aff97a5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aff97a962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbfb3a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbfb3a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbfb3a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbfb3a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aff973ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aff973ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aff97238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aff93d2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aff93d2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbfb3a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbfb3a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbfb3a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aff93d2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c (2935 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei8_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vect
# | ...
# `---data was truncated (10240/31946) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005610e9381eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005610e937ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005610e938262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ea8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ea818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ea8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ea811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005610e9317bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005610e9317a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005610e92fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005610e8fabe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005610e8fabb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3ea811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ea811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ea811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005610e8faba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmaxq.c (2936 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmaxq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = icmp sge <16 x i8> %0, %1
# |   %3 = select <16 x i1> %2, <16 x i8> %0, <16 x i8> %1
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = icmp uge <8 x i16> %0, %1
# |   %3 = select <8 x i1> %2, <8 x i16> %0, <8 x i16> %1
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = icmp sge <4 x i32> %0, %1
# |   %3 = select <4 x i1> %2, <4 x i32> %0, <4 x i32> %1
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxq_m_u8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.max.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.max.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.max.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.max.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxq_m_u32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.max.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.max.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxq_x_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056206058feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056206058ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056206059062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd697933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd69798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd697933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd69791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562060525bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562060525a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056206050a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005620601b9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005620601b9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd69791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd69791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd69791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005620601b9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c (2937 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ff171f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ff171f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ff171fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fda97e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fda97e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fda97e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fda97e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ff1718fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ff1718fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ff171748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ff16e23e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ff16e23b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fda97e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fda97e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fda97e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ff16e23a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c (2938 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557709abfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557709abce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557709ac062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f99ecb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f99ecb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f99ecb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f99ecb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557709a55bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557709a55a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557709a3a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005577096e9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005577096e9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f99ecb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f99ecb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f99ecb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005577096e9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c (2939 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvt_f_f_v_f32m1(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvt_f_f_v_f32m2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvt_f_f_v_f32m4(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvt_f_f_v_f32m8(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwcvt_f_f_v_f64m1(<vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vfwcvt_f_f_v_f64m2(<vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vfwcvt_f_f_v_f64m4(<vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vfwcvt_f_f_v_f64m8(<vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2_m(<vscale x 1 x i1> %mask, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvt_f_f_v_f32m1_m(<vscale x 2 x i1> %mask, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvt_f_f_v_f32m2_m(<vscale x 4 x i1> %mask, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %ma
# | ...
# `---data was truncated (10240/18353) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558e76e8beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558e76e88e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558e76e8c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb50cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb50cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb50cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb50cd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558e76e21bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558e76e21a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558e76e068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558e76ab5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558e76ab5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb50cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb50cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb50cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558e76ab5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c (2940 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmerge_vfm_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmerge_vfm_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmerge_vfm_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmerge_vfm_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmerge_vfm_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, bfloat %1, <vscale x 16 x i1> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfmerge_vfm_bf16m8(<vscale x 32 x bfloat> %op1, bfloat noundef %op2, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, bfloat %1, <vscale x 32 x i1> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, <vscale x 32 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561246999eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561246996e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056124699a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6de1933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6de198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6de1933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6de191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056124692fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056124692fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005612469148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005612465c3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005612465c3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6de191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6de191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6de191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005612465c3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c (2941 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { targ
# | ...
# `---data was truncated (10240/21111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005630600c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005630600c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005630600c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8191849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f81918a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8191849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8191831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056306005ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056306005ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005630600438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056305fcf2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056305fcf2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8191832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f81918330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f81918330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056305fcf2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c (2942 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f16m1x7(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f32m1x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f64m1x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei8_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none
# | ...
# `---data was truncated (10240/61673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a4df902eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a4df8ffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a4df90362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd5b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd5b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd5b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd5b231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a4df898bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a4df898a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a4df87d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a4df52ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a4df52cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdd5b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd5b2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd5b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a4df52ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c (2943 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_f64m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_i64m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_u64m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056395e173eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056395e170e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056395e17462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f787d61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f787d6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f787d61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f787d603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056395e109bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056395e109a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056395e0ee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056395dd9de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056395dd9db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f787d604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f787d6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f787d6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056395dd9da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c (2944 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfgt
# | ...
# `---data was truncated (10240/18668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556874c92eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556874c8fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556874c9362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c60b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c60b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c60b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c60b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556874c28bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556874c28a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556874c0d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005568748bce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005568748bcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1c60b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c60b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c60b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005568748bca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c (2945 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_i32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_i32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_u32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_u32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_f32mf2x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_f32m1x6_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret ta
# | ...
# `---data was truncated (10240/32031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564cb5a65eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564cb5a62e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564cb5a6662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa746733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa74678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa746733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa74671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564cb59fbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564cb59fba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564cb59e08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564cb568fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564cb568fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa74671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa74671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa74671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564cb568fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminaq.c (2946 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminaq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminaq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %b.addr, align 8
# |   %1 = icmp slt <16 x i8> %0, zeroinitializer
# |   %2 = sub <16 x i8> zeroinitializer, %0
# |   %3 = select <16 x i1> %1, <16 x i8> %2, <16 x i8> %0
# |   %4 = load <16 x i8>, ptr %a.addr, align 8
# |   %5 = icmp ule <16 x i8> %4, %3
# |   %6 = select <16 x i1> %5, <16 x i8> %4, <16 x i8> %3
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminaq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = icmp slt <8 x i16> %0, zeroinitializer
# |   %2 = sub <8 x i16> zeroinitializer, %0
# |   %3 = select <8 x i1> %1, <8 x i16> %2, <8 x i16> %0
# |   %4 = load <8 x i16>, ptr %a.addr, align 8
# |   %5 = icmp ule <8 x i16> %4, %3
# |   %6 = select <8 x i1> %5, <8 x i16> %4, <8 x i16> %3
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminaq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = icmp slt <4 x i32> %0, zeroinitializer
# |   %2 = sub <4 x i32> zeroinitializer, %0
# |   %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %0
# |   %4 = load <4 x i32>, ptr %a.addr, align 8
# |   %5 = icmp ule <4 x i32> %4, %3
# |   %6 = select <4 x i1> %5, <4 x i32> %4, <4 x i32> %3
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminaq_m_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vmina.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vmina.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminaq_m_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vmina.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vmina.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminaq_m_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.vmina.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vmina.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d6636eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558d6636be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558d6636f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd28eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd28eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd28eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd28eb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d66304bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558d66304a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558d662e98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558d65f98e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558d65f98b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd28eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd28eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd28eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d65f98a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c (2947 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_i32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_i32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_u32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_u32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ea4b4b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ea4b4b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ea4b4b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3d93905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3d9395c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3d93905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3d938ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ea4b44dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ea4b44da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ea4b4328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ea4b0e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ea4b0e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3d938eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3d938ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3d938ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ea4b0e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c (2948 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e319580eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e31957de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e31958162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1500c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1500ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1500c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1500c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e319516bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e319516a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e3194fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e3191aae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e3191aab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1500c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1500c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1500c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e3191aaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c (2949 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei16_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>,
# | ...
# `---data was truncated (10240/296943) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d8646ffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d8646fce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d86470062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1b5c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1b5c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1b5c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1b5c231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d864695bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d864695a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d86467a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d864329e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d864329b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1b5c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1b5c2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1b5c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d864329a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c (2950 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_f32mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_f32m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_i32mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_i32m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_u32mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_u32m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_i32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_i32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %
# | ...
# `---data was truncated (10240/14001) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562324b11eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562324b0ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562324b1262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1467849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f14678a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1467849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1467831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562324aa7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562324aa7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562324a8c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056232473be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056232473bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1467832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f14678330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f14678330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056232473ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c (2951 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c9d28caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c9d28c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c9d28cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa2bf449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa2bf4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa2bf449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa2bf431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9d2860bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c9d2860a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c9d28458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c9d24f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c9d24f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa2bf432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa2bf4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa2bf4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c9d24f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c (2952 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_4x8x4_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_4x8x4_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_4x8x4_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_4x8x4_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560d019aeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560d019abe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560d019af62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6955f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6955f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6955f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6955eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560d01944bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560d01944a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560d019298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560d015d8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560d015d8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6955eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6955eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6955eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560d015d8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c (2953 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_f64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_f64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_i64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_i64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_u64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_u64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs
# | ...
# `---data was truncated (10240/15978) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564a30680eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564a3067de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564a3068162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f927c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f927c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f927c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f927c031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564a30616bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564a30616a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564a305fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564a302aae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564a302aab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f927c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f927c0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f927c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564a302aaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c (2954 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556a9ed24eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556a9ed21e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556a9ed2562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f51f6c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f51f6ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f51f6c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f51f6c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556a9ecbabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556a9ecbaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556a9ec9f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556a9e94ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556a9e94eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f51f6c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51f6c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51f6c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556a9e94ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c (2955 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a579a87eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a579a84e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a579a8862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f96dc733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f96dc78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f96dc733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f96dc71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a579a1dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a579a1da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a579a028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a5796b1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a5796b1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f96dc71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f96dc71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f96dc71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a5796b1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c (2956 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005596b0f36eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005596b0f33e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005596b0f3762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f793c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f793c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f793c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f793c231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005596b0eccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005596b0ecca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005596b0eb18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005596b0b60e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005596b0b60b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f793c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f793c2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f793c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005596b0b60a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c (2957 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_2x8x2_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_2x8x2_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_2x8x2_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_2x8x2_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d4436dbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d4436d8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d4436dc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1649305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f164935c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1649305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f16492ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d443671bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d443671a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d4436568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d443305e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d443305b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f16492eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f16492ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f16492ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d443305a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c (2958 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b81cc75eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b81cc72e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b81cc7662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7330733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f733078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7330733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f733071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b81cc0bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b81cc0ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b81cbf08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b81c89fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b81c89fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f733071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f733071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f733071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b81c89fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c (2959 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zve64x    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e8w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.sf.vsettnt.i64(i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e8w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e8w4(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e16w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e16w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e16w4(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e32w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 2, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e32w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 2, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e64w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 3, i64 1)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005629354c3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005629354c0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005629354c462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbeb6f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbeb6f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbeb6f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbeb6f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562935459bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562935459a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056293543e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005629350ede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005629350edb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbeb6f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbeb6f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbeb6f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005629350eda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c (2960 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_f64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_f64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_f64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_i64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_i64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_i64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_u64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_u64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca targe
# | ...
# `---data was truncated (10240/53556) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b00758eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563b00755e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563b0075962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b73533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b7358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b73533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b7351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b006eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563b006eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563b006d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563b00382e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563b00382b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5b7351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b7351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b7351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b00382a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c (2961 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei32_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/14613) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559bafacfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559bafacce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559bafad062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc87a049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc87a0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc87a049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc87a031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559bafa65bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559bafa65a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559bafa4a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559baf6f9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559baf6f9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc87a032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc87a0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc87a0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559baf6f9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c (2962 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_i32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_i32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_u32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_u32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_f32mf2x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_f32m1x7_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("ri
# | ...
# `---data was truncated (10240/32023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564c480b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564c480b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564c480b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5398105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f539815c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5398105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f53980ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c48049bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564c48049a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564c4802e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564c47cdde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564c47cddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f53980eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f53980ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f53980ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c47cdda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbb.c (2963 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c  -check-prefix=RV32ZBB
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @orc_b_32(i32 noundef %a) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.orc.b.i32(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clz_32(i32 noundef %a) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @ctz_32(i32 noundef %a) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.cttz.i32(i32 %1, i1 false)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @cpop_32(i32 noundef %a) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.ctpop.i32(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.orc.b.i32(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.ctlz.i32(i32, i1 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.cttz.i32(i32, i1 immarg) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.ctpop.i32(i32) #2
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbb" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zbb1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555bae3e7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555bae3e4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555bae3e862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faa93049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faa930a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faa93049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faa93031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555bae37dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555bae37da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555bae3628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555bae011e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555bae011b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faa93032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faa930330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faa930330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555bae011a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c -check-prefix=RV32ZBB
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c -check-prefix=RV32ZBB
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c (2964 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f1302e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f1302e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f1302e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f18ed105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f18ed15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f18ed105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f18ed0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f130279bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f130279a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f13025e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f12ff0de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f12ff0db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f18ed0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f18ed0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f18ed0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f12ff0da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c (2965 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei16_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei16_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei16_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei16_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei16_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vluxei16_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, <vscale x 32 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei16_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei16_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captur
# | ...
# `---data was truncated (10240/30617) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055af3d91eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055af3d91be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055af3d91f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab49849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab498a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab49849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab49831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055af3d8b4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055af3d8b4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055af3d8998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055af3d548e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055af3d548b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fab49832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab498330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab498330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055af3d548a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c (2966 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_f64m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_i64m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_u64m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ae2dd00eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ae2dcfde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ae2dd0162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f58efb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f58efb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f58efb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f58efb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ae2dc96bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ae2dc96a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ae2dc7b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ae2d92ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ae2d92ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f58efb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f58efb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f58efb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ae2d92aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c (2967 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8mf8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 5)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vsetvlimax.i64(i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8mf4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 6)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8mf2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8m1() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8m2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8m4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8m8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16mf4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 6)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16mf2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16m1() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16m2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16m4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16m8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32mf2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32m1() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32m2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32m4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32m8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e64m1() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e64m2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e64m4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e64m8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 3)
# |   ret i64 %0
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005650a0833eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005650a0830e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005650a083462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5e3f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5e3f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5e3f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5e3f031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005650a07c9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005650a07c9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005650a07ae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005650a045de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005650a045db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5e3f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5e3f0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5e3f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005650a045da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c (2968 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564aca1b8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564aca1b5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564aca1b962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc3dd533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc3dd58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc3dd533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc3dd51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564aca14ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564aca14ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564aca1338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564ac9de2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564ac9de2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc3dd51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc3dd51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc3dd51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ac9de2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c (2969 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei32_v_i8mf8x5
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ecb160aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ecb1607e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ecb160b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f897db05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f897db5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f897db05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f897daed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ecb15a0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ecb15a0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ecb15858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ecb1234e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ecb1234b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f897daeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f897daef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f897daef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ecb1234a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c (2970 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f16m1x7(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f32m1x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f64m1x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei16_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005600c8bf6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005600c8bf3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005600c8bf762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff742733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff74278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff742733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff74271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005600c8b8cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005600c8b8ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005600c8b718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005600c8820e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005600c8820b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff74271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff74271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff74271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005600c8820a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c (2971 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056052d1e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056052d1e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056052d1ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f55ad133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f55ad18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f55ad133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f55ad11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056052d17fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056052d17fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056052d1648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056052ce13e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056052ce13b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f55ad11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f55ad11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f55ad11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056052ce13a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c (2972 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c  -check-prefix=RV64ZKND-ZKNE
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @aes64ks1i(i64 noundef %rs1) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = call i64 @llvm.riscv.aes64ks1i(i64 %0, i32 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.aes64ks1i(i64, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @aes64ks2(i64 noundef %rs1, i64 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %__y.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %rs2.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   store i64 %1, ptr %__y.addr.i, align 8
# |   %2 = load i64, ptr %__x.addr.i, align 8
# |   %3 = load i64, ptr %__y.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.aes64ks2(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.aes64ks2(i64, i64) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zknd" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zknd1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561ed774eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561ed774be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561ed774f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0414849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f04148a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0414849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0414831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561ed76e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561ed76e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561ed76c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561ed7378e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561ed7378b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0414832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f04148330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f04148330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561ed7378a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c -check-prefix=RV64ZKND-ZKNE
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c -check-prefix=RV64ZKND-ZKNE
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c (2973 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1up_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1up_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1up_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfslide1up_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfslide1up_vf_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfslide1up_vf_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1up_vf_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %3 = load bfloat, ptr %value.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1up_vf_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, alig
# | ...
# `---data was truncated (10240/32578) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005626bef08eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005626bef05e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005626bef0962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f010a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f010a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f010a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f010a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005626bee9ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005626bee9ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005626bee838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005626beb32e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005626beb32b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f010a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f010a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f010a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005626beb32a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c (2974 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f16m1x8(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f32m1x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f64m1x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei32_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005617c8c7ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005617c8c79e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005617c8c7d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a71f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a71f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a71f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a71f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005617c8c12bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005617c8c12a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005617c8bf78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005617c88a6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005617c88a6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2a71f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a71f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a71f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005617c88a6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c (2975 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f16m1x5(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f32m1x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f64m1x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei16_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b2d7321eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b2d731ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b2d732262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff7a9105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff7a915c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff7a9105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff7a90ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b2d72b7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b2d72b7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b2d729c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b2d6f4be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b2d6f4bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff7a90eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff7a90ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff7a90ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b2d6f4ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c (2976 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_i16mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_i16mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_i16m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_i16m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %b
# | ...
# `---data was truncated (10240/38307) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563e5973deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563e5973ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563e5973e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f98d5933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f98d598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f98d5933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f98d591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e596d3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563e596d3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563e596b88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563e59367e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563e59367b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f98d591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f98d591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f98d591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e59367a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c (2977 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561814312eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056181430fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056181431362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf1e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf1e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf1e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf1e231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005618142a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005618142a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056181428d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561813f3ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561813f3cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdf1e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf1e2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf1e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561813f3ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c (2978 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasubu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasubu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasubu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasubu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasubu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasubu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasubu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasubu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasubu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasubu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_lo
# | ...
# `---data was truncated (10240/99851) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562012358eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562012355e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056201235962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa0b661bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa0b66725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa0b661ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa0b6603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005620122eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005620122eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005620122d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562011f82e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562011f82b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa0b6604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa0b66050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa0b66050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562011f82a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c (2979 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dots_vv_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dots_vv_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dots_vv_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dots_vv_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dots_vv_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dots_vv_i64m1_tu(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dots_vv_i64m2_tu(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dots_vv_i64m4_tu(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4
# | ...
# `---data was truncated (10240/47636) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f03c176eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f03c173e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f03c17762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa066f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa066f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa066f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa066f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f03c10cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f03c10ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f03c0f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f03bda0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f03bda0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa066f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa066f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa066f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f03bda0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c (2980 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmor_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmor.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmor.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmor_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmor.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmor.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmor_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmor.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmor.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmor_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmor.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmor.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmor_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmor.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmor.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmor_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmor.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmor_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmor.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmor.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b38dbaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563b38db7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563b38dbb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb87d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb87d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb87d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb87d431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b38d50bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563b38d50a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563b38d358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563b389e4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563b389e4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb87d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb87d4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb87d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b389e4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c (2981 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf4_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> %0, <vscale x 1 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float>, <vscale x 1 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 4 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> %0, <vscale x 4 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float>, <vscale x 4 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 8 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> %0, <vscale x 8 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float>, <vscale x 8 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m4_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 16 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> %0, <vscale x 16 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float>, <vscale x 16 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m8_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 32 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float>, <vscale x 32 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32mf2_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 1 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x double> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m1_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 2 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca 
# | ...
# `---data was truncated (10240/60342) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aeb2dceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aeb2dcbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aeb2dcf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9b80649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9b806a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9b80649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9b80631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aeb2d64bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aeb2d64a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aeb2d498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aeb29f8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aeb29f8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9b80632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9b806330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9b806330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aeb29f8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c (2982 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_f16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_f16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_f16m1x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_i16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_i16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_i16m1x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_u16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("ri
# | ...
# `---data was truncated (10240/13634) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561f13986eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561f13983e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561f1398762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe105505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe10555c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe105505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe1054ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f1391cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561f1391ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561f139018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561f135b0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561f135b0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe1054eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe1054ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe1054ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f135b0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c (2983 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfclass_v_u16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfclass_v_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfclass_v_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfclass_v_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfclass_v_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8f32.i64(<vscale x 8 x i32> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: n
# | ...
# `---data was truncated (10240/66314) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555b8479feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555b8479ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555b847a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff808533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff80858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff808533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff80851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b84735bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555b84735a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555b8471a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555b843c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555b843c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff80851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff80851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff80851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b843c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c (2984 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005622b1755eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005622b1752e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005622b175662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8cf3733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8cf378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8cf3733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8cf371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005622b16ebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005622b16eba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005622b16d08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005622b137fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005622b137fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8cf371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8cf371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8cf371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005622b137fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c (2985 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dotsu_vv_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dotsu_vv_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dotsu_vv_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dotsu_vv_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dotsu_vv_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dotsu_vv_i64m1_tu(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dotsu_vv_i64m2_tu(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dotsu_vv_i64m4_tu(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotsu.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @ll
# | ...
# `---data was truncated (10240/47728) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055831a88eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055831a88be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055831a88f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5df3105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5df315c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5df3105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5df30ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055831a824bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055831a824a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055831a8098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055831a4b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055831a4b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5df30eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5df30ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5df30ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055831a4b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c (2986 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmxor_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmxor.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmxor.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmxor_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmxor.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmxor.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmxor_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmxor.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmxor.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmxor_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmxor.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmxor.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmxor_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmxor.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmxor.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmxor_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmxor.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmxor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmxor_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmxor.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmxor.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bb07cabeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bb07ca8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bb07cac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc24a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc24a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc24a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc24a31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bb07c41bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bb07c41a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bb07c268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bb078d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bb078d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc24a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc24a31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc24a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bb078d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c (2987 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmax_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor
# | ...
# `---data was truncated (10240/61929) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055670f0e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055670f0e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055670f0e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f13fbe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13fbea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f13fbe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f13fbe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055670f079bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055670f079a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055670f05e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055670ed0de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055670ed0db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f13fbe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13fbe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13fbe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055670ed0da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c (2988 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_tu(<vscale x 16 x half> %vd, <vsc
# | ...
# `---data was truncated (10240/295319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558842d4aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558842d47e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558842d4b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f75fa705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f75fa75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f75fa705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f75fa6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558842ce0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558842ce0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558842cc58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558842974e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558842974b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f75fa6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f75fa6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f75fa6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558842974a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c (2989 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16mf4x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16mf2x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16m1x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563a77ff0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563a77fede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563a77ff162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f61d5905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f61d595c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f61d5905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f61d58ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a77f86bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563a77f86a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563a77f6b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563a77c1ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563a77c1ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f61d58eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61d58ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61d58ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a77c1aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c (2990 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558f05ba0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558f05b9de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558f05ba162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb665733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb66578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb665733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb66571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f05b36bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558f05b36a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558f05b1b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558f057cae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558f057cab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb66571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb66571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb66571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f057caa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c (2991 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f16m1x8(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f32m1x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f64m1x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c020dedeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c020deae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c020dee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbac6c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbac6ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbac6c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbac6c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c020d83bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c020d83a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c020d688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c020a17e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c020a17b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbac6c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbac6c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbac6c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c020a17a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c (2992 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbc_vvm_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbc_vxm_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbc_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbc_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbc_vvm_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbc_vxm_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbc_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbc_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbc_vvm_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbc_vxm_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>,
# | ...
# `---data was truncated (10240/170497) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bd4fc27eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bd4fc24e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bd4fc2862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0791249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f07912a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0791249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0791231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bd4fbbdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bd4fbbda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bd4fba28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bd4f851e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bd4f851b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0791232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f07912330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f07912330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bd4f851a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c (2993 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m1_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m8_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, al
# | ...
# `---data was truncated (10240/81312) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ea5ffa2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ea5ff9fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ea5ffa362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3955533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f395558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3955533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f395551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ea5ff38bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ea5ff38a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ea5ff1d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ea5fbcce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ea5fbccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f395551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f395551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f395551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ea5fbcca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c (2994 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_i8mf8x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8ff_v_i8mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8ff_v_i8mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8ff_v_i8m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_u8mf8x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8ff_v_u8mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8ff_v_u8mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8ff_v_u8m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %m
# | ...
# `---data was truncated (10240/22258) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563ec87e2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563ec87dfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563ec87e362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2918305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f291835c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2918305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f29182ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ec8778bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563ec8778a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563ec875d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563ec840ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563ec840cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f29182eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f29182ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f29182ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ec840ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c (2995 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005573a29baeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005573a29b7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005573a29bb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f317bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f317bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f317bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f317bf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005573a2950bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005573a2950a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005573a29358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005573a25e4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005573a25e4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f317bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f317bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f317bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005573a25e4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c (2996 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f90e68eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f90e68be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f90e68f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f113201bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f11320725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f113201ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1132003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f90e624bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f90e624a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f90e6098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f90e2b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f90e2b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1132004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f11320050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f11320050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f90e2b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c (2997 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ee36c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564ee36bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564ee36c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1919849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f19198a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1919849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1919831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ee3658bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564ee3658a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564ee363d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564ee32ece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564ee32ecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1919832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f19198330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f19198330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ee32eca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c (2998 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmxnor_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmxnor.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmxnor.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmxnor_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmxnor.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmxnor.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmxnor_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmxnor.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmxnor.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmxnor_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmxnor.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmxnor.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmxnor_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmxnor.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmxnor.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmxnor_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmxnor.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmxnor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmxnor_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmxnor.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmxnor.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560849a62eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560849a5fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560849a6362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fef8d01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fef8d0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fef8d01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fef8d003507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005608499f8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005608499f8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005608499dd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056084968ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056084968cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fef8d004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fef8d0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fef8d0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056084968ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c (2999 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_i8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_i8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vle.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.vle.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8_v_i8mf2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vle.mask.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.vle.mask.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8_v_i8m1_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vle.mask.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.vle.mask.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8_v_i8m2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vle.mask.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.vle.mask.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8_v_i8m4_m(<vscale x 32 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vle.mask.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %1, <vscale x 32 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.vle.mask.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8_v_i8m8_m(<vscale x 64 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vle.mask.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %1, <vscale x 64 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.vle.mask.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), <vscale x 64 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_u8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_u8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vle.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8_v_u8mf2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vle.mask.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8_v_u8m1_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vle.mask.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <v
# | ...
# `---data was truncated (10240/13125) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d78c0b2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d78c0afe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d78c0b362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb51db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb51db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb51db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb51db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d78c048bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d78c048a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d78c02d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d78bcdce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d78bcdcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb51db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb51db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb51db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d78bcdca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c (3000 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabda_vv_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabda_vx_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabda_vv_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabda_vx_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabda_vv_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabda_vx_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabda_vv_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabda_vx_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwabda_vv_u16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, ali
# | ...
# `---data was truncated (10240/58334) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555b9878beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555b98788e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555b9878c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc795e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc795ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc795e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc795e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b98721bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555b98721a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555b987068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555b983b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555b983b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc795e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc795e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc795e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b983b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c (3001 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bce8f58eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bce8f55e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bce8f5962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc893b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc893b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc893b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc893aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bce8eeebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bce8eeea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bce8ed38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bce8b82e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bce8b82b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc893aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc893aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc893aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bce8b82a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c (3002 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_bf16m1x3_tum(<v
# | ...
# `---data was truncated (10240/25687) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005557c1a1feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005557c1a1ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005557c1a2062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6615249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f66152a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6615249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6615231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005557c19b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005557c19b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005557c199a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005557c1649e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005557c1649b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6615232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f66152330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f66152330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005557c1649a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c (3003 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh    -target-feature +xsfvfexp16e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexp_v_f16mf4(<vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.sf.vfexp.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexp.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexp_v_f16mf2(<vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexp_v_f16m1(<vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexp_v_f16m2(<vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexp_v_f16m4(<vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vfexp_v_f16m8(<vscale x 32 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexp_v_f16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexp_v_f16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexp_v_f16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexp_v_f16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexp_v_f16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.sf.vfexp.mask.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | de
# | ...
# `---data was truncated (10240/12091) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561ad0947eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561ad0944e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561ad094862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8eee733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8eee78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8eee733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8eee71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561ad08ddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561ad08dda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561ad08c28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561ad0571e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561ad0571b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8eee71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8eee71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8eee71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561ad0571a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c (3004 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_f32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_f32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_f32m2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_i32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_i32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_i32m2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_u32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_u32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_u32m2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0
# | ...
# `---data was truncated (10240/10425) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055beff49ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055beff499e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055beff49d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d21533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d2158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d21533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d2151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055beff432bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055beff432a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055beff4178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055beff0c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055beff0c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1d2151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d2151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d2151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055beff0c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c (3005 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaeskf1_vi_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaeskf1_vi_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaeskf1_vi_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaeskf1_vi_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaeskf1_vi_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ce0b42feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ce0b42ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ce0b43062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdad8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdad878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdad8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdad871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ce0b3c5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ce0b3c5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ce0b3aa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ce0b059e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ce0b059b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdad871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdad871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdad871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ce0b059a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c (3006 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), pt
# | ...
# `---data was truncated (10240/19484) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eddefafeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eddeface85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eddefb062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa3aaa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa3aaa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa3aaa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa3aaa03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eddef45bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eddef45a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eddef2a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eddebd9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eddebd9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa3aaa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa3aaa050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa3aaa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eddebd9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c (3007 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f16m1x8(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f32m1x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f64m1x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei32_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560499c87eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560499c84e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560499c8862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feca8305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feca835c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feca8305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feca82ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560499c1dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560499c1da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560499c028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005604998b1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005604998b1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feca82eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feca82ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feca82ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005604998b1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c (3008 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf4_i32m1(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf4_i32m2(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vsext_vf4_i32m4(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vsext_vf4_i32m8(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf4_i64m1(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf4_i64m2(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf4_i64m4(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf4_i64m8(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf4_i32m1_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf4_i32m2_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsext.mask.nxv4i32.nxv4
# | ...
# `---data was truncated (10240/17503) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558b9775eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558b9775be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558b9775f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc0dc333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc0dc38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc0dc333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc0dc31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558b976f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558b976f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558b976d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558b97388e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558b97388b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc0dc31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc0dc31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc0dc31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558b97388a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c (3009 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_f64m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_f64m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_i64m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_i64m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_u64m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_u64m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_i64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_i64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_u64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.t
# | ...
# `---data was truncated (10240/12089) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d3c6618eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d3c6615e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d3c661962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f30a2733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f30a278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f30a2733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f30a271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d3c65aebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d3c65aea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d3c65938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d3c6242e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d3c6242b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f30a271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f30a271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f30a271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d3c6242a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c (3010 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2ms_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2ms_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2ms_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2ms_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2ms_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2ms_vv_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2ms_vv_u64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2ms_vv_u64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define d
# | ...
# `---data was truncated (10240/12208) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563738aeaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563738ae7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563738aeb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe2f9705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe2f975c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe2f9705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe2f96ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563738a80bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563738a80a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563738a658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563738714e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563738714b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe2f96eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe2f96ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe2f96ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563738714a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c (3011 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b1bb8aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b1bb8a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b1bb8ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f7421bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f742725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f7421ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f74203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b1bb842bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b1bb842a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b1bb8278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b1bb4d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b1bb4d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2f74204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f742050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f742050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b1bb4d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c (3012 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a3ff2adeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a3ff2aae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a3ff2ae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feda7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feda778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feda7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feda771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a3ff243bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a3ff243a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a3ff2288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a3feed7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a3feed7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feda771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feda771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feda771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a3feed7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c (3013 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_i8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_i8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8_v_i8m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_u8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_u8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_u8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8_v_u8m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_i8mf8x6_tum(<vscale x 1 x i1> %mas
# | ...
# `---data was truncated (10240/43111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aba4ceaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aba4ce7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aba4ceb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b8d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b8d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b8d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b8d031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aba4c80bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aba4c80a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aba4c658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aba4914e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aba4914b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5b8d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b8d0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b8d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aba4914a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c (3014 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8mf8x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8mf8x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @
# | ...
# `---data was truncated (10240/23479) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056036ba3deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056036ba3ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056036ba3e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee5dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee5dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee5dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee5dc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056036b9d3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056036b9d3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056036b9b88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056036b667e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056036b667b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fee5dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee5dc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee5dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056036b667a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c (3015 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_f32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_f32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_i32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_i32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_u32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_u32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounw
# | ...
# `---data was truncated (10240/15952) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055835f756eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055835f753e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055835f75762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd954133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd95418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd954133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd95411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055835f6ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055835f6eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055835f6d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055835f380e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055835f380b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd95411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd95411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd95411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055835f380a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c (3016 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556bd1ff2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556bd1fefe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556bd1ff362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f04d9333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f04d938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f04d9333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f04d931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556bd1f88bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556bd1f88a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556bd1f6d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556bd1c1ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556bd1c1cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f04d931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f04d931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f04d931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556bd1c1ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c (3017 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_f64m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_i64m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_u64m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055763b638eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055763b635e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055763b63962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9c91649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9c916a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9c91649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9c91631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055763b5cebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055763b5cea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055763b5b38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055763b262e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055763b262b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9c91632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9c916330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9c916330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055763b262a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c (3018 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabs_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabs_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabs_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabs_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabs_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vabs_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vabs_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vabs_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vabs_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vabs_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vabs_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vabd.nxv8i16.i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vabd.nxv8i16.i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vabs_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vabd.nxv16i16.i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vabd.nxv16i16.i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vabs_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale 
# | ...
# `---data was truncated (10240/41102) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ca395c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ca395bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ca395c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd0f8449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd0f84a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd0f8449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd0f8431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ca39557bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ca39557a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ca3953c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ca391ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ca391ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd0f8432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd0f84330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd0f84330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ca391eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c (3019 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16bf16.p0.i64(<vscale x 16 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv32bf16.p0.i64(<vscale x 32 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %2, ptr %1, <vscale x 1 x i1> %0, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %2, ptr %1, <vscale x 2 x i1> %0, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %2, ptr %1, <vscale x 4 x i1> %0, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %2, ptr %1, <vscale x 8 x i1> %0, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m4_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store 
# | ...
# `---data was truncated (10240/12644) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559b4dc55eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559b4dc52e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559b4dc5662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f216c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f216c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f216c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f216c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559b4dbebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559b4dbeba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559b4dbd08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559b4d87fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559b4d87fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f216c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f216c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f216c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559b4d87fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmulltq.c (3020 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmulltq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulltq_int_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8>, <16 x i8>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulltq_int_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmulltq_int_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1, i32 1)
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulltq_poly_p16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulltq_int_m_s8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 0, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulltq_int_m_u16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 1, i32 1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmulltq_int_m_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <2 x i64>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <2 x i64> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3)
# |   %5 = load <2 x i64>, ptr %inactive.addr, align 8
# |   %6 = call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %1, i32 0, i32 1, <2 x i1> %4, <2 x i64> %5)
# |   ret <2 x i64> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32>, <4 x i32>, i32, i32, <2 x i1>, <2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulltq_poly_m_p8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulltq_int_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 1, i32 1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulltq_int_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 0, i32 1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmulltq_int_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |  
# | ...
# `---data was truncated (10240/11851) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de23485eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055de23482e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055de2348662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb148449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb1484a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb148449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb148431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de2341bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055de2341ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055de234008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055de230afe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055de230afb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb148432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb1484330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb1484330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de230afa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c (3021 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlse16_v_f16mf4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vlse.mask.nxv1f16.p0.i64(<vscale x 1 x half> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vlse.mask.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlse16_v_f16mf2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vlse.mask.nxv2f16.p0.i64(<vscale x 2 x half> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vlse.mask.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlse16_v_f16m1_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vlse.mask.nxv4f16.p0.i64(<vscale x 4 x half> poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vlse.mask.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlse16_v_f16m2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vlse.mask.nxv8f16.p0.i64(<vscale x 8 x half> poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vlse.mask.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlse16_v_f16m4_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vlse.mask.nxv16f16.p0.i64(<vscale x 16 x half> poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vlse.mask.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlse16_v_f16m8_m(<vscale x 32 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vlse.mask.nxv32f16.p0.i64(<vscale x 32 x half> poison, ptr %1, i64 %2, <vscale x 32 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vlse.mask.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64, <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vlse16_v_i16mf4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vlse.mask.nxv1i16.p0.i64(<vscale x 1 x i16> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i16> @llvm.riscv.vlse.mask.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vlse16_v_i16mf2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vlse.mask.nxv2i16.p0.i64(<vscale x 2 x i16> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i16> @llvm.riscv.vlse.mask.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vlse16_v_i16m1_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, 
# | ...
# `---data was truncated (10240/20307) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557a45402eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557a453ffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557a4540362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f128f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f128f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f128f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f128f031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557a45398bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557a45398a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557a4537d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557a4502ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557a4502cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f128f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f128f0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f128f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557a4502ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c (3022 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16mf4_f16m1(<vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16mf2_f16m1(<vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m1_f16m1(<vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m2_f16m1(<vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m4_f16m1(<vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m8_f16m1(<vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32mf2_f32m1(<vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32m1_f32m1(<vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32m2_f32m1(<vscale x 4 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_loc
# | ...
# `---data was truncated (10240/37556) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c22dcf2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c22dcefe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c22dcf362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f15133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f1518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f15133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f1511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c22dc88bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c22dc88a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c22dc6d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c22d91ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c22d91cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1f1511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f1511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f1511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c22d91ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c (3023 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlsseg3e8_v_i8mf8x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e8_v_i8mf4x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e8_v_i8mf2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e8_v_i8m1x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e8_v_i8m2x3_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlsseg3e8_v_u8mf8x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e8_v_u8mf4x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e8_v_u8mf2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.
# | ...
# `---data was truncated (10240/13557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561c27a10eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561c27a0de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561c27a1162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f4921bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f492725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f4921ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f49203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561c279a6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561c279a6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561c2798b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561c2763ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561c2763ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2f49204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f492050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f492050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561c2763aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c (3024 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsle_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsle_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsle_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsle_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsle_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsle_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsle_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | 
# | ...
# `---data was truncated (10240/63571) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005577cdae5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005577cdae2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005577cdae662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f05a9449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f05a94a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f05a9449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f05a9431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005577cda7bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005577cda7ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005577cda608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005577cd70fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005577cd70fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f05a9432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f05a94330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f05a94330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005577cd70fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c (3025 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16mf4(ptr noundef %rs1, i64 noundef %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16mf2(ptr noundef %rs1, i64 noundef %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m1(ptr noundef %rs1, i64 noundef %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m2(ptr noundef %rs1, i64 noundef %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m4(ptr noundef %rs1, i64 noundef %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv16bf16.p0.i64(<vscale x 16 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m8(ptr noundef %rs1, i64 noundef %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv32bf16.p0.i64(<vscale x 32 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, <vscale x 8 x bflo
# | ...
# `---data was truncated (10240/14338) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a5db0d2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a5db0cfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a5db0d362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc7b9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc7b9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc7b9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc7b9b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a5db068bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a5db068a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a5db04d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a5dacfce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a5dacfcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc7b9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc7b9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc7b9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a5dacfca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c (3026 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_f16mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_f16mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_f16m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_i16mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_i16mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_i16m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_u16mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_u16mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_u16m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_f16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsse
# | ...
# `---data was truncated (10240/20441) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d153ea9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d153ea6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d153eaa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f352a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f352a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f352a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f352a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d153e3fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d153e3fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d153e248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d153ad3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d153ad3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f352a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f352a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f352a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d153ad3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c (3027 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4au_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4au_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 
# | ...
# `---data was truncated (10240/26520) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563e800edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563e800eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563e800ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff44a21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff44a2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff44a21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff44a203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e80083bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563e80083a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563e800688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563e7fd17e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563e7fd17b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff44a204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff44a2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff44a2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e7fd17a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c (3028 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +fullfp16  -disable-O0-optnone  -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vceqzh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp oeq half %1, 0.000000e+00
# |   %vceqz = sext i1 %2 to i16
# |   store i16 %vceqz, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcgezh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp oge half %1, 0.000000e+00
# |   %vcgez = sext i1 %2 to i16
# |   store i16 %vcgez, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcgtzh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp ogt half %1, 0.000000e+00
# |   %vcgtz = sext i1 %2 to i16
# |   store i16 %vcgtz, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vclezh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp ole half %1, 0.000000e+00
# |   %vclez = sext i1 %2 to i16
# |   store i16 %vclez, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcltzh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp olt half %1, 0.000000e+00
# |   %vcltz = sext i1 %2 to i16
# |   store i16 %vcltz, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_s16(i16 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i16, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %__s0, align 2
# |   %1 = load i16, ptr %__s0, align 2
# |   %2 = sitofp i16 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_s32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i32, align 4
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__s0, align 4
# |   %1 = load i32, ptr %__s0, align 4
# |   %2 = sitofp i32 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_s64(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i64, align 8
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   store i64 %0, ptr %__s0, align 8
# |   %1 = load i64, ptr %__s0, align 8
# |   %2 = sitofp i64 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_u16(i16 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i16, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %__s0, align 2
# |   %1 = load i16, ptr %__s0, align 2
# |   %2 = uitofp i16 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_u32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i32, align 4
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__s0, align 4
# |   %1 = load i32, ptr %__s0, align 4
# |   %2 = uitofp i32 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_u64(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i64, align 8
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   store i64 %0, ptr %__s0, align 8
# |   %1 = load i64, ptr %__s0, align 8
# |   %2 = uitofp i64 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcvth_s16_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vcvth_s16_f16 = call i16 @llvm.fptosi.sat.i16.f16(half %1)
# |   store i16 %vcvth_s16_f16, ptr %ref.tmp, align 2
# |   %2 = load i16, ptr %ref.tmp, align 2
# |   store i16 %2, ptr %__ret, align 2
# |   %3 = load i16, ptr %__ret, align 2
# |   store i16 %3, ptr %tmp, align 2
# |   %4 = load i16, ptr %tmp, align 2
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.fptosi.sat.i16.f16(half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_vcvth_s32_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vcvth_s32_f16 = call i32 @llvm.fptosi.sat.i32.f16(half %1)
# |   store i32 %vcvth_s32_f16, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.fptosi.sat.i32.f16(half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_vcvth_s64_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i64, align 8
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, al
# | ...
# `---data was truncated (10240/28866) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559762794eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559762791e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055976279562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9aff133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9aff18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9aff133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9aff11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055976272abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055976272aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055976270f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005597623bee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005597623beb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9aff11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9aff11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9aff11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005597623bea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c (3029 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_f16mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_f16mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_f16m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_f16m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_i16mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_i16mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_i16m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_i16m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_u16mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_u16mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.
# | ...
# `---data was truncated (10240/26921) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556bc49d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556bc49d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556bc49d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5f7cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5f7cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5f7cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5f7cd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556bc496bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556bc496ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556bc49508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556bc45ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556bc45ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5f7cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5f7cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5f7cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556bc45ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c (3030 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_f32mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_f32m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_f32m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_i32mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_i32m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_i32m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_u32mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_u32m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_u32m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_f32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg
# | ...
# `---data was truncated (10240/20483) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559c68bc5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559c68bc2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559c68bc662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc0c3249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc0c32a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc0c3249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc0c3231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c68b5bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559c68b5ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559c68b408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559c687efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559c687efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc0c3232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc0c32330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc0c32330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c687efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c (3031 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvpackfph -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadt_vf_f16mf4(<vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadt_vf_f16mf2(<vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadt_vf_f16m1(<vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadt_vf_f16m2(<vscale x 8 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(<vscale x 8 x half>, <vscale x 8 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_nds_vfpmadt_vf_f16m4(<vscale x 16 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(<vscale x 16 x half>, <vscale x 16 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_nds_vfpmadt_vf_f16m8(<vscale x 32 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(<vscale x 32 x half>, <vscale x 32 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadt_vf_f16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %1, float %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadt_vf_f16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %1, float %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadt_vf_f16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.mask.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %1, float %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.mask.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadt_vf_f16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x half> %op1, float noun
# | ...
# `---data was truncated (10240/25091) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056348b022eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056348b01fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056348b02362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce48105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce4815c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce48105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce480ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056348afb8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056348afb8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056348af9d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056348ac4ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056348ac4cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fce480eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce480ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce480ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056348ac4ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c (3032 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vf_f32mf2(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vf_f32m1(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vf_f32m2(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vf_f32m4(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i6
# | ...
# `---data was truncated (10240/90867) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e2e6536eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e2e6533e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e2e653762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc7b9e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc7b9ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc7b9e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc7b9e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e2e64ccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e2e64cca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e2e64b18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e2e6160e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e2e6160b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc7b9e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc7b9e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc7b9e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2e6160a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c (3033 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_i32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_i32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_u32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_u32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_f32mf2x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedof
# | ...
# `---data was truncated (10240/40734) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005647574a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005647574a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005647574a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0fce933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0fce98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0fce933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0fce91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056475743dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056475743da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005647574228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005647570d1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005647570d1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0fce91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0fce91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0fce91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005647570d1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c (3034 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562b913cfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562b913cce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562b913d062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe394e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe394ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe394e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe394e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b91365bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562b91365a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562b9134a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562b90ff9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562b90ff9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe394e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe394e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe394e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b90ff9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c (3035 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlse16_v_bf16mf4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vlse.nxv1bf16.p0.i64(<vscale x 1 x bfloat> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vlse.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlse16_v_bf16mf2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vlse.nxv2bf16.p0.i64(<vscale x 2 x bfloat> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vlse.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlse16_v_bf16m1(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vlse.nxv4bf16.p0.i64(<vscale x 4 x bfloat> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vlse.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlse16_v_bf16m2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vlse.nxv8bf16.p0.i64(<vscale x 8 x bfloat> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vlse.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlse16_v_bf16m4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vlse.nxv16bf16.p0.i64(<vscale x 16 x bfloat> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vlse.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlse16_v_bf16m8(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vlse.nxv32bf16.p0.i64(<vscale x 32 x bfloat> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vlse.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlse16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlse16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlse16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vlse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vlse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlse16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vlse.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat> poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vlse.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | defin
# | ...
# `---data was truncated (10240/13035) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056298abfeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056298abfbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056298abff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f95c7b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f95c7b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f95c7b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f95c7b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056298ab94bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056298ab94a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056298ab798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056298a828e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056298a828b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f95c7b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f95c7b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f95c7b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056298a828a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c (3036 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei16_v_i8mf8x5
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d754a5eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d754a5be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d754a5f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feddc533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feddc58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feddc533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feddc51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d7549f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d7549f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d7549d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d754688e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d754688b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feddc51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feddc51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feddc51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d754688a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/2005-06-15-ExpandGotoInternalProblem.c (3037 of 27911)
******************** TEST 'Clang :: CodeGen/2005-06-15-ExpandGotoInternalProblem.c' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wno-error=return-type -std=c99 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c -emit-llvm -o - |     /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 -disable-output
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wno-error=return-type -std=c99 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c -emit-llvm -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | @X = global i32 0, align 4
# | @Y = global i32 0, align 4
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @foo() #0 {
# | entry:
# |   %retval = alloca i32, align 4
# |   %i = alloca i32, align 4
# |   store i32 0, ptr %i, align 4
# |   br label %for.cond
# | 
# | for.cond:                                         ; preds = %for.inc, %entry
# |   %0 = load i32, ptr %i, align 4
# |   %cmp = icmp slt i32 %0, 100
# |   br i1 %cmp, label %for.body, label %for.end
# | 
# | for.body:                                         ; preds = %for.cond
# |   br label %for.end
# | 
# | for.inc:                                          ; No predecessors!
# |   %1 = load i32, ptr %i, align 4
# |   %inc = add nsw i32 %1, 1
# |   store i32 %inc, ptr %i, align 4
# |   br label %for.cond
# | 
# | for.end:                                          ; preds = %for.body, %for.cond
# |   %2 = load i32, ptr %retval, align 4
# |   ret i32 %2
# | }
# | 
# | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# .---command stderr------------
# | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c:13:1: warning: non-void function does not return a value [-Wreturn-type]
# |    13 | }
# |       | ^
# | 1 warning generated.
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 -disable-output
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 -disable-output
# |  #0 0x000055eab4d34eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eab4d31e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eab4d3562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe04361bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe0436725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe04361ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe043603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eab4ccabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eab4ccaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eab4caf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eab495ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eab495eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe043604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe0436050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe0436050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eab495ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c (3038 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_i64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_i64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_u64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_u64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de9c164eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055de9c161e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055de9c16562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff5ebf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff5ebf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff5ebf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff5ebf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de9c0fabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055de9c0faa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055de9c0df8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055de9bd8ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055de9bd8eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff5ebf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff5ebf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff5ebf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de9bd8ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c (3039 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8mf8x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_u8mf8x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_u8mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_u8mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_u8m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   
# | ...
# `---data was truncated (10240/21558) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005571af1cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005571af1c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005571af1cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1ebcb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1ebcb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1ebcb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1ebcb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005571af161bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005571af161a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005571af1468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005571aedf5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005571aedf5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1ebcb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1ebcb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1ebcb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005571aedf5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c (3040 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei8_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple
# | ...
# `---data was truncated (10240/31938) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557bb668deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557bb668ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557bb668e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fedd4f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fedd4f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fedd4f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fedd4eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557bb6623bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557bb6623a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557bb66088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557bb62b7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557bb62b7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fedd4eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fedd4eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fedd4eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557bb62b7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c (3041 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005629cf038eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005629cf035e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005629cf03962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f46d9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f46d9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f46d9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f46d9f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005629cefcebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005629cefcea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005629cefb38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005629cec62e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005629cec62b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f46d9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f46d9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f46d9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005629cec62a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c (3042 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_xu_f_qf_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %1, <vscale x 1 x float> %2, float %3, <vscale x 1 x i1> %0, i64 2, i64 %4, i64 2)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %1, <vscale x 2 x float> %2, float %3, <vscale x 2 x i1> %0, i64 2, i64 %4, i64 2)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.ad
# | ...
# `---data was truncated (10240/26762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558e8646deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558e8646ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558e8646e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0944933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f094498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0944933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f094491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558e86403bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558e86403a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558e863e88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558e86097e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558e86097b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f094491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f094491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f094491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558e86097a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c (3043 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005610af1c9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005610af1c6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005610af1ca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9de881bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9de88725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9de881ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9de8803507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005610af15fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005610af15fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005610af1448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005610aedf3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005610aedf3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9de8804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9de88050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9de88050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005610aedf3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c (3044 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_f16mf4x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_f16mf2x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_f16m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_i16mf4x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_i16mf2x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_i16m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_u16mf4x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_u16mf2x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_u16m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_f16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_f16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_f16m1x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 
# | ...
# `---data was truncated (10240/17523) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dda1f77eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dda1f74e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dda1f7862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe322333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe32238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe322333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe32231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dda1f0dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dda1f0da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dda1ef28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dda1ba1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dda1ba1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe32231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe32231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe32231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dda1ba1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c (3045 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willr
# | ...
# `---data was truncated (10240/44361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560a0cb10eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560a0cb0de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560a0cb1162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb7d4449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb7d44a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb7d4449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb7d4431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a0caa6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560a0caa6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560a0ca8b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560a0c73ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560a0c73ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb7d4432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb7d44330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb7d44330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a0c73aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c (3046 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv1i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv1i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8ff_v_i8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8ff_v_i8mf2x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8ff_v_i8m1x7_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_u8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv1i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8ff_v_u8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8ff_v_u8mf2x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>,
# | ...
# `---data was truncated (10240/12668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560044ff4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560044ff1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560044ff562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff1ab049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff1ab0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff1ab049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff1ab031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560044f8abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560044f8aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560044f6f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560044c1ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560044c1eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff1ab032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff1ab0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff1ab0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560044c1ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmovn.c (3047 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmovn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovnbq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = shufflevector <16 x i8> %1, <16 x i8> poison, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
# |   %3 = bitcast <16 x i8> %2 to <8 x i16>
# |   %4 = shufflevector <8 x i16> %0, <8 x i16> %3, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
# |   %5 = trunc <16 x i16> %4 to <16 x i8>
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovnbq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = load <8 x i16>, ptr %a.addr, align 8
# |   %2 = shufflevector <8 x i16> %1, <8 x i16> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
# |   %3 = bitcast <8 x i16> %2 to <4 x i32>
# |   %4 = shufflevector <4 x i32> %0, <4 x i32> %3, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
# |   %5 = trunc <8 x i32> %4 to <8 x i16>
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovnbq_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = shufflevector <16 x i8> %1, <16 x i8> poison, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
# |   %3 = bitcast <16 x i8> %2 to <8 x i16>
# |   %4 = shufflevector <8 x i16> %0, <8 x i16> %3, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
# |   %5 = trunc <16 x i16> %4 to <16 x i8>
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovnbq_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = load <8 x i16>, ptr %a.addr, align 8
# |   %2 = shufflevector <8 x i16> %1, <8 x i16> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
# |   %3 = bitcast <8 x i16> %2 to <4 x i32>
# |   %4 = shufflevector <4 x i32> %0, <4 x i32> %3, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
# |   %5 = trunc <8 x i32> %4 to <8 x i16>
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovntq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <8 x i16>
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
# |   %4 = trunc <16 x i16> %3 to <16 x i8>
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovntq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x i16> %0 to <4 x i32>
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
# |   %4 = trunc <8 x i32> %3 to <8 x i16>
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovntq_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <8 x i16>
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
# |   %4 = trunc <16 x i16> %3 to <16 x i8>
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovntq_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x i16> %0 to <4 x i32>
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
# |   %4 = trunc <8 x i32> %3 to <8 x i16>
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovnbq_m_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 0, <8 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vmovn.predicated.v16i8.v8i16.v8i1(<16 x i8>, <8 x i16>, i32, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovnbq_m_s32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 0, <4 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vmovn.predicated.v8i16.v4i32.v4i1(<8 x i16>, <4 x i32>, i32, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovnbq_m_u16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 0, <8 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovnbq_m_u32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 0, <4 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovntq_m_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, a
# | ...
# `---data was truncated (10240/13410) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ae624d0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ae624cde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ae624d162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3c8681bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3c868725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3c8681ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3c86803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ae62466bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ae62466a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ae6244b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ae620fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ae620fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3c86804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3c868050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3c868050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ae620faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c (3048 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_f32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_f32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_f32m2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_i32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_i32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_i32m2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_u32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_u32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_u3
# | ...
# `---data was truncated (10240/11880) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005603f3c09eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005603f3c06e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005603f3c0a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff30b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff30b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff30b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff30b71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005603f3b9fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005603f3b9fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005603f3b848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005603f3833e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005603f3833b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff30b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff30b71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff30b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005603f3833a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c (3049 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredxor_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredxor_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredxor_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   stor
# | ...
# `---data was truncated (10240/94371) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fc8e46deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fc8e46ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fc8e46e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a38d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a38d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a38d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a38d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fc8e403bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fc8e403a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fc8e3e88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fc8e097e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fc8e097b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2a38d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a38d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a38d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fc8e097a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-neon-vget.c (3050 of 27911)
******************** TEST 'Clang :: CodeGen/arm-neon-vget.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-apple-darwin    -target-abi apcs-gnu    -target-cpu cortex-a8    -mfloat-abi soft    -target-feature +soft-float-abi    -ffreestanding    -disable-O0-optnone -emit-llvm -w -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-apple-darwin -target-abi apcs-gnu -target-cpu cortex-a8 -mfloat-abi soft -target-feature +soft-float-abi -ffreestanding -disable-O0-optnone -emit-llvm -w -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c"
# | target datalayout = "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
# | target triple = "thumbv7-apple-darwin"
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @low_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @low_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x i16> @low_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x i16> @low_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <2 x i32> @low_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <4 x i32> %1, <4 x i32> %2, <2 x i32> <i32 0, i32 1>
# |   store <2 x i32> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <2 x i32> @low_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <4 x i32> %1, <4 x i32> %2, <2 x i32> <i32 0, i32 1>
# |   store <2 x i32> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <1 x i64> @low_s64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> zeroinitializer
# |   store <1 x i64> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <1 x i64> @low_u64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> zeroinitializer
# |   store <1 x i64> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @low_p8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x i16> @low_p16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <2 x float> @low_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <4 x float> %1, <4 x float> %2, <2 x i32> <i32 0, i32 1>
# |   store <2 x float> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @high_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @high_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x i16> @high_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x i16> @high_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr
# | ...
# `---data was truncated (10240/15571) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cbbe3daeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055cbbe3d7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055cbbe3db62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff147249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff1472a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff147249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff147231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cbbe370bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055cbbe370a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055cbbe3558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055cbbe004e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055cbbe004b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff147232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff1472330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff1472330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cbbe004a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c (3051 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_i64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_u64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_f64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_i64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_u64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vsca
# | ...
# `---data was truncated (10240/20895) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a15e068eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a15e065e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a15e06962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa8e0b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa8e0b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa8e0b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa8e0aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a15dffebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a15dffea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a15dfe38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a15dc92e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a15dc92b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa8e0aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa8e0aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa8e0aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a15dc92a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c (3052 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlsseg4e8_v_i8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e8_v_i8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e8_v_i8mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e8_v_i8m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e8_v_i8m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlsseg4e8_v_u8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e8_v_u8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.ris
# | ...
# `---data was truncated (10240/60220) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c277019eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c277016e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c27701a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f389c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f389c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f389c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f389c831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c276fafbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c276fafa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c276f948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c276c43e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c276c43b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f389c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f389c8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f389c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c276c43a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c (3053 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_i8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_i8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8_v_i8m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_u8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_u8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_u8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8_v_u8m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_i8mf8x5_tum(<vscale x 1 x i1> %mas
# | ...
# `---data was truncated (10240/43111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055856a055eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055856a052e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055856a05662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb4f0333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb4f038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb4f0333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb4f031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558569febbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558569feba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558569fd08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558569c7fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558569c7fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb4f031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb4f031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb4f031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558569c7fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c (3054 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_e5m2_e5m2_w4_f8e5m2m8_f8e5m2m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056517ed93eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056517ed90e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056517ed9462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f152bf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f152bf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f152bf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f152beed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056517ed29bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056517ed29a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056517ed0e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056517e9bde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056517e9bdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f152beeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f152beef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f152beef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056517e9bda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c (3055 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vlse64_v_f64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.vlse.mask.nxv1f64.p0.i64(<vscale x 1 x double> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x double> @llvm.riscv.vlse.mask.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vlse64_v_f64m2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x double> @llvm.riscv.vlse.mask.nxv2f64.p0.i64(<vscale x 2 x double> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.riscv.vlse.mask.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vlse64_v_f64m4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x double> @llvm.riscv.vlse.mask.nxv4f64.p0.i64(<vscale x 4 x double> poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x double> @llvm.riscv.vlse.mask.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vlse64_v_f64m8_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x double> @llvm.riscv.vlse.mask.nxv8f64.p0.i64(<vscale x 8 x double> poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x double> @llvm.riscv.vlse.mask.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vlse64_v_i64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vlse.mask.nxv1i64.p0.i64(<vscale x 1 x i64> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i64> @llvm.riscv.vlse.mask.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vlse64_v_i64m2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vlse.mask.nxv2i64.p0.i64(<vscale x 2 x i64> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i64> @llvm.riscv.vlse.mask.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vlse64_v_i64m4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vlse.mask.nxv4i64.p0.i64(<vscale x 4 x i64> poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i64> @llvm.riscv.vlse.mask.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vlse64_v_i64m8_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vlse.mask.nxv8i64.p0.i64(<vscale x 8 x i64> poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i64> @llvm.riscv.vlse.mask.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vlse64_v_u64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.ad
# | ...
# `---data was truncated (10240/13903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557096498eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557096495e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055709649962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f110e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f110e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f110e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f110e71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055709642ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055709642ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005570964138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005570960c2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005570960c2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f110e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f110e71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f110e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005570960c2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c (3056 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmadd_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmadd_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmadd_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmadd_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmadd_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmadd_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmadd_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmadd_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 
# | ...
# `---data was truncated (10240/64244) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563bd73a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563bd739fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563bd73a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc5e5049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5e50a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc5e5049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc5e5031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563bd7338bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563bd7338a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563bd731d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563bd6fcce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563bd6fccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc5e5032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5e50330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5e50330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563bd6fcca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c (3057 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vslide1down_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vslide1down_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vslide1down_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vslide1down_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vslide1down_vx_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vslide1down_vx_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vslide1down_vx_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vslide1down_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i16, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vslide1down_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# | 
# | ...
# `---data was truncated (10240/211223) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559d1a541eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559d1a53ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559d1a54262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f976b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f976b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f976b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f976b91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559d1a4d7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559d1a4d7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559d1a4bc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559d1a16be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559d1a16bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f976b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f976b91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f976b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559d1a16ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c (3058 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_f16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_f16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_f16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_i16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_i16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_i16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_u16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_u16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_u16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", 
# | ...
# `---data was truncated (10240/23365) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556aa6dddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556aa6ddae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556aa6dde62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa175133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa17518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa175133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa17511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556aa6d73bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556aa6d73a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556aa6d588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556aa6a07e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556aa6a07b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa17511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa17511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa17511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556aa6a07a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c (3059 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e5b3c09eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e5b3c06e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e5b3c0a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3684533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f368458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3684533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f368451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e5b3b9fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e5b3b9fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e5b3b848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e5b3833e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e5b3833b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f368451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f368451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f368451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e5b3833a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c (3060 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei32_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a2f56b9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a2f56b6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a2f56ba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f093d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f093d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f093d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f093d31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a2f564fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a2f564fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a2f56348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a2f52e3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a2f52e3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f093d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f093d31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f093d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a2f52e3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c (3061 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf8_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf4_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf2_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m1_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m2_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m4_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m8_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmaxu_vs_u16mf4_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync 
# | ...
# `---data was truncated (10240/62063) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a2ba616eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a2ba613e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a2ba61762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2c68c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2c68c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2c68c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2c68c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a2ba5acbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a2ba5aca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a2ba5918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a2ba240e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a2ba240b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2c68c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2c68c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2c68c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a2ba240a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c (3062 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557eca594eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557eca591e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557eca59562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f24a4105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f24a415c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f24a4105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f24a40ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557eca52abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557eca52aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557eca50f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557eca1bee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557eca1beb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f24a40eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f24a40ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f24a40ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557eca1bea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c (3063 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosy
# | ...
# `---data was truncated (10240/12666) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557b684c9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557b684c6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557b684ca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4470505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f447055c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4470505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f44704ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b6845fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557b6845fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557b684448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557b680f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557b680f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f44704eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44704ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44704ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b680f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c (3064 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_f16mf4x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_f16mf2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_f16m1x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16ff_v_f16m2x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16ff_v_f16m4x2_m(<vscale x 16 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_i16mf4x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_i16mf2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |  
# | ...
# `---data was truncated (10240/22074) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bc15720eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bc1571de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bc1572162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6178333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f617838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6178333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f617831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bc156b6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bc156b6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bc1569b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bc1534ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bc1534ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f617831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f617831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f617831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bc1534aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c (3065 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vunzipe_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 2 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vunzipe_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 4 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vunzipe_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 8 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vunzipe_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 16 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vunzipe_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 32 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555820cbbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555820cb8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555820cbc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc06b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc06b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc06b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc06aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555820c51bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555820c51a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555820c368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005558208e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005558208e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdc06aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc06aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc06aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005558208e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c (3066 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558ee7aeeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558ee7aebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558ee7aef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0d0c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0d0c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0d0c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0d0c031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558ee7a84bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558ee7a84a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558ee7a698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558ee7718e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558ee7718b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0d0c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0d0c0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0d0c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558ee7718a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c (3067 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), pt
# | ...
# `---data was truncated (10240/19484) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005649c7460eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005649c745de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005649c746162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f58305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f5835c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f58305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f582ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005649c73f6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005649c73f6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005649c73db8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005649c708ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005649c708ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6f582eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f582ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f582ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005649c708aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c (3068 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zkne -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c  -check-prefix=RV64ZKNE
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zkne -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @aes64es(i64 noundef %rs1, i64 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %__y.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %rs2.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   store i64 %1, ptr %__y.addr.i, align 8
# |   %2 = load i64, ptr %__x.addr.i, align 8
# |   %3 = load i64, ptr %__y.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.aes64es(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @aes64esm(i64 noundef %rs1, i64 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %__y.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %rs2.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   store i64 %1, ptr %__y.addr.i, align 8
# |   %2 = load i64, ptr %__x.addr.i, align 8
# |   %3 = load i64, ptr %__y.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.aes64esm(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.aes64es(i64, i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.aes64esm(i64, i64) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zkne" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zkne1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c5821baeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c5821b7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c5821bb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcdd2133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcdd218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcdd2133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcdd211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c582150bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c582150a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c5821358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c581de4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c581de4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcdd211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcdd211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcdd211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c581de4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c -check-prefix=RV64ZKNE
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c -check-prefix=RV64ZKNE
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c (3069 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# | ...
# `---data was truncated (10240/18506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d055722eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d05571fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d05572362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f602f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f602f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f602f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f602f11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0556b8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d0556b8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d05569d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d05534ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d05534cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f602f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f602f11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f602f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d05534ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c (3070 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf8_u8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf4_u8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf2_u8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m1_u8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m2_u8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m4_u8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m8_u8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16mf4_u16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16mf2_u16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16m1_u16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %sc
# | ...
# `---data was truncated (10240/52741) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eca6a58eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055eca6a55e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055eca6a5962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f52d4449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f52d44a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f52d4449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f52d4431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eca69eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055eca69eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055eca69d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055eca6682e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055eca6682b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f52d4432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f52d44330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f52d44330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eca6682a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c (3071 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vunzipo_v_bf16mf4(<vscale x 2 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vunzipo_v_bf16mf2(<vscale x 4 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vunzipo_v_bf16m1(<vscale x 8 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vunzipo_v_bf16m2(<vscale x 16 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vunzipo_v_bf16m4(<vscale x 32 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fdc72c6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fdc72c3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fdc72c762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f617bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f617bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f617bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f617bd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fdc725cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fdc725ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fdc72418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fdc6ef0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fdc6ef0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f617bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f617bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f617bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fdc6ef0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c (3072 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_i8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e8_v_i8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e8_v_i8m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_u8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_u8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e8_v_u8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/48305) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005655089b6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005655089b3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005655089b762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fda74333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fda7438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fda74333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fda7431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056550894cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056550894ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005655089318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005655085e0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005655085e0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fda7431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fda7431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fda7431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005655085e0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c (3073 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vsc
# | ...
# `---data was truncated (10240/11789) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ab70d43eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ab70d40e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ab70d4462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0dc4305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0dc435c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0dc4305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0dc42ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ab70cd9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ab70cd9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ab70cbe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ab7096de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ab7096db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0dc42eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0dc42ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0dc42ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ab7096da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c (3074 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a657760eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a65775de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a65776162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f747161bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f74716725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f747161ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7471603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a6576f6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a6576f6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a6576db8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a65738ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a65738ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7471604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f74716050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f74716050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a65738aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c (3075 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16mf4x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16mf2x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16m1x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561549578eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561549575e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056154957962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5e5f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5e5f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5e5f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5e5f231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056154950ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056154950ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005615494f38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005615491a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005615491a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5e5f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5e5f2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5e5f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615491a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/builtins-arm.c (3076 of 27911)
******************** TEST 'Clang :: CodeGen/builtins-arm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple thumbv7-eabi -target-cpu cortex-a8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple thumbv7-eabi -target-cpu cortex-a8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv7-unknown-unknown-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local ptr @f0() #0 {
# | entry:
# |   %0 = call ptr @llvm.thread.pointer.p0()
# |   ret ptr %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare ptr @llvm.thread.pointer.p0() #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @f1(ptr noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 4
# |   %b.addr = alloca ptr, align 4
# |   store ptr %a, ptr %a.addr, align 4
# |   store ptr %b, ptr %b.addr, align 4
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %1 = load ptr, ptr %b.addr, align 4
# |   call void @llvm.clear_cache.p0(ptr %0, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.clear_cache.p0(ptr, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vcvtrf0(float noundef %f) #0 {
# | entry:
# |   %f.addr = alloca float, align 4
# |   store float %f, ptr %f.addr, align 4
# |   %0 = load float, ptr %f.addr, align 4
# |   %vcvtr = call float @llvm.arm.vcvtr.f32(float %0)
# |   ret float %vcvtr
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.vcvtr.f32(float) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vcvtrf1(float noundef %f) #0 {
# | entry:
# |   %f.addr = alloca float, align 4
# |   store float %f, ptr %f.addr, align 4
# |   %0 = load float, ptr %f.addr, align 4
# |   %vcvtr = call float @llvm.arm.vcvtru.f32(float %0)
# |   ret float %vcvtr
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.vcvtru.f32(float) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_vcvtrd0(double noundef %d) #0 {
# | entry:
# |   %d.addr = alloca double, align 8
# |   store double %d, ptr %d.addr, align 8
# |   %0 = load double, ptr %d.addr, align 8
# |   %vcvtr = call float @llvm.arm.vcvtr.f64(double %0)
# |   %conv = fpext float %vcvtr to double
# |   ret double %conv
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.vcvtr.f64(double) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_vcvtrd1(double noundef %d) #0 {
# | entry:
# |   %d.addr = alloca double, align 8
# |   store double %d, ptr %d.addr, align 8
# |   %0 = load double, ptr %d.addr, align 8
# |   %vcvtr = call float @llvm.arm.vcvtru.f64(double %0)
# |   %conv = fpext float %vcvtr to double
# |   ret double %conv
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.vcvtru.f64(double) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_eh_return_data_regno() #0 {
# | entry:
# |   %res = alloca i32, align 4
# |   store volatile i32 0, ptr %res, align 4
# |   store volatile i32 1, ptr %res, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @nop() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.hint(i32) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @yield() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @wfe() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @wfi() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @sev() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @sevl() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @dbg() #0 {
# | entry:
# |   call void @llvm.arm.dbg(i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.dbg(i32) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_barrier() #0 {
# | entry:
# |   call void @llvm.arm.dmb(i32 1)
# |   call void @llvm.arm.dsb(i32 2)
# |   call void @llvm.arm.isb(i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.dmb(i32) #2
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.dsb(i32) #2
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.isb(i32) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @rbit(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %rbit = call i32 @llvm.bitreverse.i32(i32 %0)
# |   ret i32 %rbit
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.bitreverse.i32(i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @prefetch(i32 noundef %i) #0 {
# | entry:
# |   %i.addr = alloca i32, align 4
# |   store i32 %i, ptr %i.addr, align 4
# |   call void @llvm.prefetch.p0(ptr %i.addr, i32 0, i32 3, i32 1)
# |   call void @llvm.prefetch.p0(ptr %i.addr, i32 1, i32 3, i32 1)
# |   call void @llvm.prefetch.p0(ptr %i.addr, i32 1, i32 3, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.prefetch.p0(ptr readonly captures(none), i32 immarg range(i32 0, 2), i32 immarg range(i32 0, 4), i32 immarg range(i32 0, 2)) #4
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @ldc(ptr noundef %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 4
# |   store ptr %i, ptr %i.addr, align 4
# |   %0 = load ptr, ptr %i.addr, align 4
# |   call void @llvm.arm.ldc(i32 1, i32 2, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.ldc(i32 immarg, i32 immarg, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @ldcl(ptr noundef %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 4
# |   store ptr %i, ptr %i.addr, align 4
# |   %0 = load ptr, ptr %i.addr, align 4
# |   call void @llvm.arm.ldcl(i32 1, i32 2, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.ldcl(i32 immarg, i32 immarg, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @ldc2(ptr noundef %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 4
# |   store ptr %i, ptr %i.addr, align 4
# |   %0 = load ptr, ptr %i.addr, align 4
# |   call void @llvm.arm.ldc2(i32 1, i32 2, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.ldc2(i32 immarg, i32 immarg, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @ldc2l(ptr noundef %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 4
# |   store ptr %i, ptr %i.addr, align 4
# |   %0 = load ptr, ptr %i.addr, align 4
# |   call void @llvm.arm.ldc2l(i32 1, i32 2, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.ldc2l(i32 immarg, i32 immarg, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @stc(ptr noundef %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 4
# |   store ptr %i, ptr %i.addr, align 4
# |   %0 = load ptr, ptr %i.addr, align 4
# |   call void @llvm.arm.stc(i32 1, i32 2, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.stc(i32 immarg, i32 immarg, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @stcl(ptr noundef %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 4
# |   store ptr %i, ptr %i.addr, align 4
# |   %0 = load ptr, ptr %i.addr, align 4
# |   call void @llvm.arm.stcl(i32 1, i32 2, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.stcl(i32 immarg, i32 immarg, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @stc2(ptr noundef %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 4
# |   store ptr %i, ptr %i.addr, align 4
# |   %0 = load ptr, ptr %i.addr, align 4
# |   call void @llvm.arm.stc2(i32 1, i32 2, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.stc2(i32 immarg, i32 immarg, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @stc2l(ptr noundef %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 4
# |   store ptr %i, ptr %i.addr, align 4
# |   %0 = load ptr, ptr %i.addr, align 4
# |   call void @llvm.arm.stc2l(i32 1, i32 2, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.stc2l(i32 immarg, i32 immarg, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @cdp() #0 {
# | entry:
# |   call void @llvm.arm.cdp(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.cdp(i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @cdp2() #0 {
# | entry:
# |   call void @llvm.arm.cdp2(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.cdp2(i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @mrc() #0 {
# | entry:
# |   %0 = call i32 @llvm.arm.mrc(i32 15, i32 0, i32 13, i32 0, i32 3)
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: nounwind
# | declare i32 @llvm.arm.mrc(i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @mrc2() #0 {
# | entry:
# |   %0 = call i32 @llvm.arm.mrc2(i32 15, i32 0, i32 13, i32 0, i32 3)
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: nounwind
# | declare i32 @llvm.arm.mrc2(i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @mcr(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   call void @llvm.arm.mcr(i32 15, i32 0, i32 %0, i32 13, i32 0, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.mcr(i32 immarg, i32 immarg, i32, i32 immarg, i32 immarg, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @mcr2(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   call void @llvm.arm.mcr2(i32 15, i32 0, i32 %0, i32 13, i32 0, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.mcr2(i32 immarg, i32 immarg, i32, i32 immarg, i32 immarg, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_lo
# | ...
# `---data was truncated (10240/15632) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560e2f356eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560e2f353e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560e2f35762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f51e6249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f51e62a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f51e6249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f51e6231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e2f2ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560e2f2eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560e2f2d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560e2ef80e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560e2ef80b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f51e6232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51e62330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51e62330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e2ef80a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c (3077 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounw
# | ...
# `---data was truncated (10240/12658) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561bd4b6eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561bd4b6be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561bd4b6f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0ac5d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0ac5d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0ac5d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0ac5d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561bd4b04bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561bd4b04a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561bd4ae98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561bd4798e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561bd4798b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0ac5d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0ac5d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0ac5d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561bd4798a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c (3078 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562b40ed1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562b40ecee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562b40ed262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f31ed733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f31ed78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f31ed733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f31ed71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b40e67bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562b40e67a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562b40e4c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562b40afbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562b40afbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f31ed71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31ed71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31ed71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b40afba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c (3079 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_f32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_i32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_i32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_i32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_u32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_u32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_u32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align
# | ...
# `---data was truncated (10240/47596) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005604367c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005604367c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005604367c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe692705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe69275c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe692705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe6926ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056043675ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056043675ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005604367438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005604363f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005604363f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe6926eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe6926ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe6926ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005604363f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c (3080 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_2x8x2_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_2x8x2_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_2x8x2_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_2x8x2_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555cef5bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555cef5b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555cef5bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f00d0f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f00d0f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f00d0f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f00d0eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555cef551bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555cef551a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555cef5368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555cef1e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555cef1e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f00d0eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f00d0eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f00d0eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555cef1e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c (3081 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_f32mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_f32m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_f32m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_f32m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_i32mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_i32m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_i32m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_i32m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_u32mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_u32m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | 
# | ...
# `---data was truncated (10240/26984) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f2e37deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564f2e37ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564f2e37e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efecf649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efecf6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efecf649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efecf631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f2e313bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564f2e313a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564f2e2f88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564f2dfa7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564f2dfa7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efecf632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efecf6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efecf6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f2dfa7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c (3082 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16mf2_bf16mf4(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv2bf16(<vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv2bf16(<vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m1_bf16mf4(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv4bf16(<vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv4bf16(<vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m1_bf16mf2(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv4bf16(<vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv4bf16(<vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m2_bf16mf4(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv8bf16(<vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv8bf16(<vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m2_bf16mf2(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_trunc_v_bf16m2_bf16m1(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16mf4(<vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16mf2(<vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16m1(<vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16m2(<vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16mf4(<vscale x 32 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16mf2(<vscale x 32 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16m1(<vscale x 32 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16m2(<vscale x 32 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16m4(<
# | ...
# `---data was truncated (10240/11404) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055829d617eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055829d614e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055829d61862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f054ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f054cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f054ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f054ce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055829d5adbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055829d5ada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055829d5928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055829d241e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055829d241b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f054ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f054ce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f054ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055829d241a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c (3083 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_i32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_i32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_u32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_u32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056554b3f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056554b3efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056554b3f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9703e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9703e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9703e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9703e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056554b388bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056554b388a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056554b36d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056554b01ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056554b01cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9703e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9703e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9703e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056554b01ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c (3084 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32mf2(ptr noundef %base, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1f32.p0.i64(<vscale x 1 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32m1(ptr noundef %base, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2f32.p0.i64(<vscale x 2 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32m2(ptr noundef %base, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4f32.p0.i64(<vscale x 4 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32m4(ptr noundef %base, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8f32.p0.i64(<vscale x 8 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32m8(ptr noundef %base, <vscale x 16 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16f32.p0.i64(<vscale x 16 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32mf2(ptr noundef %base, <vscale x 1 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i32.p0.i64(<vscale x 1 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32m1(ptr noundef %base, <vscale x 2 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i32.p0.i64(<vscale x 2 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32m2(ptr noundef %base, <vscale x 4 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i32.p0.i64(<vscale x 4 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32m4(ptr noundef %base, <vscale x 8 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i32.p0.i64(<vscale x 8 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32m8(ptr noundef %base, <vscale x 16 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16i32.p0.i64(<vscale x 16 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16i32.p0.i64(<vscale x 16 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_u32mf2(ptr noundef %base, <vscale x 1 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i32.p0.i64(<vscale x 1 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_u32m1(ptr noundef %base, <vscale x 2 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i32.p0.i64(<vscale x 2 x i32> %1, ptr %0,
# | ...
# `---data was truncated (10240/28346) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c133968eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c133965e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c13396962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6bbca1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6bbca725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6bbca1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6bbca03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c1338febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c1338fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c1338e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c133592e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c133592b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6bbca04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6bbca050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6bbca050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c133592a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c (3085 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i32> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale
# | ...
# `---data was truncated (10240/15707) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005572e7952eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005572e794fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005572e795362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f85d5733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f85d578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f85d5733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f85d571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005572e78e8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005572e78e8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005572e78cd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005572e757ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005572e757cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f85d571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f85d571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f85d571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005572e757ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c (3086 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_i64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_i64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_u64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_u64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055efec51aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055efec517e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055efec51b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa636533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa63658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa636533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa63651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055efec4b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055efec4b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055efec4958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055efec144e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055efec144b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa63651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa63651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa63651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055efec144a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c (3087 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16mf4_f16m1(<vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16mf2_f16m1(<vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m1_f16m1(<vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m2_f16m1(<vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m4_f16m1(<vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m8_f16m1(<vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32mf2_f32m1(<vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32m1_f32m1(<vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32m2_f32m1(<vscale x 4 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define
# | ...
# `---data was truncated (10240/37564) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f96441eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f96441be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f96441f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2d70533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2d7058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2d70533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2d7051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f9643b4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f9643b4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f9643998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f964048e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f964048b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2d7051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2d7051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2d7051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f964048a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c (3088 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslideup_vx_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vslideup.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslideup.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslideup_vx_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vslideup.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslideup.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslideup_vx_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vslideup.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslideup.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslideup_vx_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vslideup.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vslideup.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vslideup_vx_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vslideup.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vslideup.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vslideup_vx_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vslideup.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vslideup.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslideup_vx_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vslideup.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslideup.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslideup_vx_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vslideup.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslideup.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale 
# | ...
# `---data was truncated (10240/30627) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555ceb9b0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555ceb9ade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555ceb9b162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe148333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe14838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe148333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe14831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555ceb946bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555ceb946a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555ceb92b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555ceb5dae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555ceb5dab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe14831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe14831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe14831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555ceb5daa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/idup.c (3089 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/idup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vidupq_n_u8(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call { <16 x i8>, i32 } @llvm.arm.mve.vidup.v16i8(i32 %0, i32 4)
# |   %2 = extractvalue { <16 x i8>, i32 } %1, 0
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <16 x i8>, i32 } @llvm.arm.mve.vidup.v16i8(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vidupq_n_u16(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call { <8 x i16>, i32 } @llvm.arm.mve.vidup.v8i16(i32 %0, i32 1)
# |   %2 = extractvalue { <8 x i16>, i32 } %1, 0
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <8 x i16>, i32 } @llvm.arm.mve.vidup.v8i16(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vidupq_n_u32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32 %0, i32 4)
# |   %2 = extractvalue { <4 x i32>, i32 } %1, 0
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vddupq_n_u8(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call { <16 x i8>, i32 } @llvm.arm.mve.vddup.v16i8(i32 %0, i32 2)
# |   %2 = extractvalue { <16 x i8>, i32 } %1, 0
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <16 x i8>, i32 } @llvm.arm.mve.vddup.v16i8(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vddupq_n_u16(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call { <8 x i16>, i32 } @llvm.arm.mve.vddup.v8i16(i32 %0, i32 4)
# |   %2 = extractvalue { <8 x i16>, i32 } %1, 0
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <8 x i16>, i32 } @llvm.arm.mve.vddup.v8i16(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vddupq_n_u32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call { <4 x i32>, i32 } @llvm.arm.mve.vddup.v4i32(i32 %0, i32 2)
# |   %2 = extractvalue { <4 x i32>, i32 } %1, 0
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <4 x i32>, i32 } @llvm.arm.mve.vddup.v4i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_viwdupq_n_u8(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call { <16 x i8>, i32 } @llvm.arm.mve.viwdup.v16i8(i32 %0, i32 %1, i32 4)
# |   %3 = extractvalue { <16 x i8>, i32 } %2, 0
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <16 x i8>, i32 } @llvm.arm.mve.viwdup.v16i8(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_viwdupq_n_u16(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call { <8 x i16>, i32 } @llvm.arm.mve.viwdup.v8i16(i32 %0, i32 %1, i32 2)
# |   %3 = extractvalue { <8 x i16>, i32 } %2, 0
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <8 x i16>, i32 } @llvm.arm.mve.viwdup.v8i16(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_viwdupq_n_u32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call { <4 x i32>, i32 } @llvm.arm.mve.viwdup.v4i32(i32 %0, i32 %1, i32 8)
# |   %3 = extractvalue { <4 x i32>, i32 } %2, 0
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <4 x i32>, i32 } @llvm.arm.mve.viwdup.v4i32(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdwdupq_n_u8(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call { <16 x i8>, i32 } @llvm.arm.mve.vdwdup.v16i8(i32 %0, i32 %1, i32 4)
# |   %3 = extractvalue { <16 x i8>, i32 } %2, 0
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <16 x i8>, i32 } @llvm.arm.mve.vdwdup.v16i8(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdwdupq_n_u16(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call { <8 x i16>, i32 } @llvm.arm.mve.vdwdup.v8i16(i32 %0, i32 %1, i32 8)
# |   %3 = extractvalue { <8 x i16>, i32 } %2, 0
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <8 x i16>, i32 } @llvm.arm.mve.vdwdup.v8i16(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vdwdupq_n_u32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vdwdup.v4i32(i32 %0, i32 %1, i32 1)
# |   %3 = extractvalue { <4 x i32>, i32 } %2, 0
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <4 x i32>, i32 } @llvm.arm.mve.vdwdup.v4i32(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vidupq_wb_u8(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 4
# |   store ptr %a, ptr %a.addr, align 4
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = call { <16 x i8>, i32 } @llvm.arm.mve.vidup.v16i8(i32 %1, i32 8)
# |   %3 = extractvalue { <16 x i8>, i32 } %2, 1
# |   store i32 %3, ptr %0, align 4
# |   %4 = extractvalue { <16 x i8>, i32 } %2, 0
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vidupq_wb_u16(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 4
# |   store ptr %a, ptr %a.addr, align 4
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = call { <8 x i16>, i32 } @llvm.arm.mve.vidup.v8i16(i32 %1, i32 1)
# |   %3 = extractvalue { <8 x i16>, i32 } %2, 1
# |   store i32 %3, ptr %0, align 4
# |   %4 = extractvalue { <8 x i16>, i32 } %2, 0
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vidupq_wb_u32(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 4
# |   store ptr %a, ptr %a.addr, align 4
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32 %1, i32 4)
# |   %3 = extractvalue { <4 x i32>, i32 } %2, 1
# |   store i32 %3, ptr %0, align 4
# |   %4 = extractvalue { <4 x i32>, i32 } %2, 0
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vddupq_wb_u8(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 4
# |   store ptr %a, ptr %a.addr, align 4
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = call { <16 x i8>, i32 } @llvm.arm.mve.vddup.v16i8(i32 %1, i32 2)
# |   %3 = extractvalue { <16 x i8>, i32 } %2, 1
# |   store i32 %3, ptr %0, align 4
# |   %4 = extractvalue { <16 x i8>, i32 } %2, 0
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vddupq_wb_u16(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 4
# |   store ptr %a, ptr %a.addr, align 4
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = call { <8 x i16>, i32 } @llvm.arm.mve.vddup.v8i16(i32 %1, i32 8)
# |   %3 = extractvalue { <8 x i16>, i32 } %2, 1
# |   store i32 %3, ptr %0, align 4
# |   %4 = extractvalue { <8 x i16>, i32 } %2, 0
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vddupq_wb_u32(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 4
# |   store ptr %a, ptr %a.addr, align 4
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vddup.v4i32(i32 %1, i32 2)
# |   %3 = extractvalue { <4 x i32>, i32 } %2, 1
# |   store i32 %3, ptr %0, align 4
# |   %4 = extractvalue { <4 x i32>, i32 } %2, 0
# |   ret <4 x i3
# | ...
# `---data was truncated (10240/57708) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055591a381eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055591a37ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055591a38262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4cd1333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4cd138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4cd1333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4cd131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055591a317bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055591a317a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055591a2fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555919fabe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555919fabb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4cd131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4cd131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4cd131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555919faba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c (3090 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local half @test_vfmv_f_s_f16mf4_f16(<vscale x 1 x half> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = call half @llvm.riscv.vfmv.f.s.nxv1f16(<vscale x 1 x half> %0)
# |   ret half %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.riscv.vfmv.f.s.nxv1f16(<vscale x 1 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local half @test_vfmv_f_s_f16mf2_f16(<vscale x 2 x half> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = call half @llvm.riscv.vfmv.f.s.nxv2f16(<vscale x 2 x half> %0)
# |   ret half %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.riscv.vfmv.f.s.nxv2f16(<vscale x 2 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local half @test_vfmv_f_s_f16m1_f16(<vscale x 4 x half> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = call half @llvm.riscv.vfmv.f.s.nxv4f16(<vscale x 4 x half> %0)
# |   ret half %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.riscv.vfmv.f.s.nxv4f16(<vscale x 4 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local half @test_vfmv_f_s_f16m2_f16(<vscale x 8 x half> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = call half @llvm.riscv.vfmv.f.s.nxv8f16(<vscale x 8 x half> %0)
# |   ret half %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.riscv.vfmv.f.s.nxv8f16(<vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local half @test_vfmv_f_s_f16m4_f16(<vscale x 16 x half> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = call half @llvm.riscv.vfmv.f.s.nxv16f16(<vscale x 16 x half> %0)
# |   ret half %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.riscv.vfmv.f.s.nxv16f16(<vscale x 16 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local half @test_vfmv_f_s_f16m8_f16(<vscale x 32 x half> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = call half @llvm.riscv.vfmv.f.s.nxv32f16(<vscale x 32 x half> %0)
# |   ret half %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.riscv.vfmv.f.s.nxv32f16(<vscale x 32 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @test_vfmv_f_s_f32mf2_f32(<vscale x 1 x float> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = call float @llvm.riscv.vfmv.f.s.nxv1f32(<vscale x 1 x float> %0)
# |   ret float %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.riscv.vfmv.f.s.nxv1f32(<vscale x 1 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @test_vfmv_f_s_f32m1_f32(<vscale x 2 x float> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = call float @llvm.riscv.vfmv.f.s.nxv2f32(<vscale x 2 x float> %0)
# |   ret float %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.riscv.vfmv.f.s.nxv2f32(<vscale x 2 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @test_vfmv_f_s_f32m2_f32(<vscale x 4 x float> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = call float @llvm.riscv.vfmv.f.s.nxv4f32(<vscale x 4 x float> %0)
# |   ret float %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.riscv.vfmv.f.s.nxv4f32(<vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @test_vfmv_f_s_f32m4_f32(<vscale x 8 x float> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = call float @llvm.riscv.vfmv.f.s.nxv8f32(<vscale x 8 x float> %0)
# |   ret float %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.riscv.vfmv.f.s.nxv8f32(<vscale x 8 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @test_vfmv_f_s_f32m8_f32(<vscale x 16 x float> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = call float @llvm.riscv.vfmv.f.s.nxv16f32(<vscale x 16 x float> %0)
# |   ret float %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.riscv.vfmv.f.s.nxv16f32(<vscale x 16 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local double @test_vfmv_f_s_f64m1_f64(<vscale x 1 x double> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %1 = call double @llvm.riscv.vfmv.f.s.nxv1f64(<vscale x 1 x double> %0)
# |   ret double %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.riscv.vfmv.f.s.nxv1f64(<vscale x 1 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local double @test_vfmv_f_s_f64m2_f64(<vscale x 2 x double> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %1 = call double @llvm.riscv.vfmv.f.s.nxv2f64(<vscale x 2 x double> %0)
# |   ret double %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.riscv.vfmv.f.s.nxv2f64(<vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local double @test_vfmv_f_s_f64m4_f64(<vscale x 4 x double> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %1 = call double @llvm.riscv.vfmv.f.s.nxv4f64(<vscale x 4 x double> %0)
# |   ret double %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.riscv.vfmv.f.s.nxv4f64(<vscale x 4 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local double @test_vfmv_f_s_f64m8_f64(<vscale x 8 x double> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %1 = call double @llvm.riscv.vfmv.f.s.nxv8f64(<vscale x 8 x double> %0)
# |   ret double %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.riscv.vfmv.f.s.nxv8f64(<vscale x 8 x double>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055773683deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055773683ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055773683e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa279933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa27998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa279933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa27991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005577367d3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005577367d3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005577367b88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557736467e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557736467b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa27991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa27991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa27991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557736467a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c (3091 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmmv_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmmv_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmmv_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmmv_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmmv_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmmv_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmmv_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555f89315eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555f89312e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555f8931662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb6c7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb6c778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb6c7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb6c771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f892abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555f892aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555f892908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555f88f3fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555f88f3fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb6c771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb6c771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb6c771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f88f3fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c (3092 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_bf16mf4x3(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_bf16mf2x3(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_bf16m1x3(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_bf16m2x3(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556f4771feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556f4771ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556f4772062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1172e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1172ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1172e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1172e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556f476b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556f476b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556f4769a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556f47349e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556f47349b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1172e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1172e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1172e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556f47349a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c (3093 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i8> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i8> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i8> %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> %2, ptr %0, <vscale x 32 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs
# | ...
# `---data was truncated (10240/15504) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c955183eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c955180e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c95518462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa33e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa33e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa33e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa33e11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c955119bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c955119a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c9550fe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c954dade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c954dadb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa33e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa33e11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa33e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c954dada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c (3094 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei32_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/14613) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ca41046eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ca41043e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ca4104762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ea2133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ea218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ea2133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ea211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ca40fdcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ca40fdca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ca40fc18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ca40c70e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ca40c70b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5ea211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ea211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ea211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ca40c70a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c (3095 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055976dc2eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055976dc2be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055976dc2f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff63f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff63f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff63f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff63f91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055976dbc4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055976dbc4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055976dba98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055976d858e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055976d858b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff63f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff63f91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff63f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055976d858a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c (3096 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvsintload -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vlnu8_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vlnu8_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(<vscale x 16 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i8> @test_nds_vlnu8_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(<vscale x 32 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_nds_vlnu8_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(<vscale x 64 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8> %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8> %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(<vscale x 4 x i8> %1, ptr %2, <vscale x 4 x i1> %0,
# | ...
# `---data was truncated (10240/29451) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005607fd9bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005607fd9b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005607fd9bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe7bda1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe7bda725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe7bda1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe7bda03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607fd952bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005607fd952a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005607fd9378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005607fd5e6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005607fd5e6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe7bda04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe7bda050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe7bda050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607fd5e6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c (3097 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabdau_vv_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabdau_vx_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabdau_vv_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabdau_vx_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabdau_vv_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabdau_vx_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabdau_vv_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabdau_vx_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwabdau_vv_u16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd
# | ...
# `---data was truncated (10240/58460) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d60b5c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d60b5c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d60b5c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff920533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff92058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff920533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff92051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d60b55abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d60b55aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d60b53f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d60b1eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d60b1eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff92051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff92051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff92051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d60b1eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/builtins-loongarch.c (3098 of 27911)
******************** TEST 'Clang :: CodeGen/builtins-loongarch.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple loongarch32 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple loongarch32 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "loongarch32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_eh_return_data_regno() #0 {
# | entry:
# |   %res = alloca i32, align 4
# |   store volatile i32 4, ptr %res, align 4
# |   store volatile i32 5, ptr %res, align 4
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit" }
# | 
# | !llvm.module.flags = !{!0}
# | !llvm.ident = !{!1}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32d"}
# | !1 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f6bedeeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f6bedebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f6bedef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f83c9733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83c978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f83c9733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f83c971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f6bed84bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f6bed84a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f6bed698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f6bea18e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f6bea18b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f83c971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83c971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83c971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f6bea18a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c (3099 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_bf16m1x
# | ...
# `---data was truncated (10240/25695) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005587ac813eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005587ac810e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005587ac81462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf27333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf2738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf27333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf2731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005587ac7a9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005587ac7a9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005587ac78e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005587ac43de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005587ac43db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdf2731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf2731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf2731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005587ac43da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c (3100 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563cb3c57eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563cb3c54e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563cb3c5862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2d65533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2d6558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2d65533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2d6551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563cb3bedbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563cb3beda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563cb3bd28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563cb3881e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563cb3881b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2d6551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2d6551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2d6551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563cb3881a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c (3101 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_f64m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_f64m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_i64m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_i64m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_u64m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_u64m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_i64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_i64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tu
# | ...
# `---data was truncated (10240/14044) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fdd4c91eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fdd4c8ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fdd4c9262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1a1ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1a1ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1a1ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1a1ad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fdd4c27bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fdd4c27a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fdd4c0c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fdd48bbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fdd48bbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1a1ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1a1ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1a1ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fdd48bba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c (3102 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_f64m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_i64m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_u64m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557798d4deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557798d4ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557798d4e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7190905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f719095c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7190905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f71908ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557798ce3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557798ce3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557798cc88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557798977e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557798977b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f71908eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f71908ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f71908ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557798977a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c (3103 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_f32mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_f32m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_i32mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_i32m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_u32mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_u32m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_i32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_i32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/14010) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560f3b82ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560f3b829e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560f3b82d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0d3ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0d3caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0d3ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0d3ca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f3b7c2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560f3b7c2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560f3b7a78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560f3b456e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560f3b456b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0d3ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0d3ca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0d3ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f3b456a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c (3104 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmnot_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmnot_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmnot_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmnot_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmnot_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmnot_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmnot_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ef45218eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ef45215e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ef4521962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2c18049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2c180a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2c18049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2c18031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ef451aebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ef451aea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ef451938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ef44e42e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ef44e42b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2c18032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2c180330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2c180330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ef44e42a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c (3105 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlsseg3e8_v_i8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e8_v_i8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e8_v_i8mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e8_v_i8m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e8_v_i8m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlsseg3e8_v_u8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e8_v_u8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @
# | ...
# `---data was truncated (10240/60228) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c9a88edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c9a88eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c9a88ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b27933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b2798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b27933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b2791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9a8883bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c9a8883a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c9a88688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c9a8517e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c9a8517b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4b2791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b2791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b2791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c9a8517a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c (3106 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055975a4feeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055975a4fbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055975a4ff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f31cca1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f31cca725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f31cca1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f31cca03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055975a494bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055975a494a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055975a4798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055975a128e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055975a128b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f31cca04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31cca050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31cca050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055975a128a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/thinlto_embed_bitcode.ll (3107 of 27911)
******************** TEST 'Clang :: CodeGen/thinlto_embed_bitcode.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 6
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/Inputs/start-lib1.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_embed_bitcode.ll.tmp1.bc
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/Inputs/start-lib1.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_embed_bitcode.ll.tmp1.bc
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/Inputs/start-lib1.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_embed_bitcode.ll.tmp1.bc
# |  #0 0x000055b807289eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b807286e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b80728a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc3a6a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc3a6aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc3a6a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc3a6a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b80721fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b80721fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b8072048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b806eb3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b806eb3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc3a6a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc3a6a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc3a6a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b806eb3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c (3108 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf4_f32m1(<vscale x 1 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float>, <vscale x 1 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf2_f32m1(<vscale x 2 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m1_f32m1(<vscale x 4 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float>, <vscale x 4 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m2_f32m1(<vscale x 8 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float>, <vscale x 8 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m4_f32m1(<vscale x 16 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float>, <vscale x 16 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m8_f32m1(<vscale x 32 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float>, <vscale x 32 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32mf2_f64m1(<vscale x 1 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m1_f64m1(<vscale x 2 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(<vscale x 1 x double>, <vscale x 2 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m2_f64m1(<vscale x 4 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2
# | ...
# `---data was truncated (10240/50524) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005559f78feeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005559f78fbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005559f78ff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd7f7e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd7f7ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd7f7e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd7f7e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005559f7894bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005559f7894a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005559f78798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005559f7528e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005559f7528b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd7f7e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd7f7e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd7f7e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005559f7528a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c (3109 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_f32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_f32m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_f32m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_f32m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_i32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_i32m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_i32m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_i32m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_u32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr,
# | ...
# `---data was truncated (10240/30874) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005648e873deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005648e873ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005648e873e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7ded533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7ded58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7ded533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7ded51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005648e86d3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005648e86d3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005648e86b88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005648e8367e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005648e8367b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7ded51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7ded51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7ded51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005648e8367a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c (3110 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vundefined_bf16mf4() #0 {
# | entry:
# |   ret <vscale x 1 x bfloat> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vundefined_bf16mf2() #0 {
# | entry:
# |   ret <vscale x 2 x bfloat> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vundefined_bf16m1() #0 {
# | entry:
# |   ret <vscale x 4 x bfloat> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vundefined_bf16m2() #0 {
# | entry:
# |   ret <vscale x 8 x bfloat> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vundefined_bf16m4() #0 {
# | entry:
# |   ret <vscale x 16 x bfloat> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vundefined_bf16m8() #0 {
# | entry:
# |   ret <vscale x 32 x bfloat> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vundefined_bf16mf4x2() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vundefined_bf16mf4x3() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vundefined_bf16mf4x4() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vundefined_bf16mf4x5() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vundefined_bf16mf4x6() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vundefined_bf16mf4x7() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vundefined_bf16mf4x8() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vundefined_bf16mf2x2() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vundefined_bf16mf2x3() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vundefined_bf16mf2x4() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vundefined_bf16mf2x5() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vundefined_bf16mf2x6() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vundefined_bf16mf2x7() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vundefined_bf16mf2x8() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vundefined_bf16m1x2() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vundefined_bf16m1x3() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vundefined_bf16m1x4() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vundefined_bf16m1x5() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vundefined_bf16m1x6() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vundefined_bf16m1x7() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vundefined_bf16m1x8() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vundefined_bf16m2x2() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vundefined_bf16m2x3() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vundefined_bf16m2x4() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vundefined_bf16m4x2() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b2390b4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b2390b1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b2390b562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3cafd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3cafd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3cafd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3cafd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b23904abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b23904aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b23902f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b238cdee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b238cdeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3cafd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3cafd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3cafd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b238cdea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c (3111 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i8> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>
# | ...
# `---data was truncated (10240/15607) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561d60c7eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561d60c7be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561d60c7f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f15ec849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f15ec8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f15ec849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f15ec831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561d60c14bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561d60c14a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561d60bf98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561d608a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561d608a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f15ec832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15ec8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15ec8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561d608a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c (3112 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_i8mf8(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_i8mf4(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_i8mf2(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_i8m1(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_i8m2(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vncvt_x_x_w_i8m4(<vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8> poison, <vscale x 32 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8>, <vscale x 32 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_u8mf8(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_u8mf4(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_u8mf2(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_u8m1(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_u8m2(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vncvt_x_x_w_u8m4(<vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8> poison, <vscale x 32 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vncvt_x_x_w_i16mf4(<vscale x 1 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i64.i64(<vscale x 1 x i16> poison, <vscale x 1 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i64.i64(<vscale x 1 x i16>, <vscale x 1 x i32>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vncvt_x_x_w_i16mf2(<vscale x 2 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vnsrl.nxv2i16.nxv2i32.i64.i64(<vscale x 2 x i16> po
# | ...
# `---data was truncated (10240/50898) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056159ef4eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056159ef4be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056159ef4f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4cd2049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4cd20a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4cd2049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4cd2031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056159eee4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056159eee4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056159eec98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056159eb78e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056159eb78b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4cd2032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4cd20330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4cd20330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056159eb78a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c (3113 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i32> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i32> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i
# | ...
# `---data was truncated (10240/13153) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c315b9feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c315b9ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c315ba062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1066e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1066ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1066e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1066e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c315b35bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c315b35a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c315b1a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c3157c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c3157c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1066e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1066e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1066e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c3157c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c (3114 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm3c_vi_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm3c_vi_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm3c_vi_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm3c_vi_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm3c_vi_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee79f6deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ee79f6ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ee79f6e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1baf249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1baf2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1baf249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1baf231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee79f03bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ee79f03a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ee79ee88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ee79b97e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ee79b97b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1baf232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1baf2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1baf2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee79b97a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c (3115 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei32_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei32_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   
# | ...
# `---data was truncated (10240/25616) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005626d9e84eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005626d9e81e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005626d9e8562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f143b905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f143b95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f143b905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f143b8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005626d9e1abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005626d9e1aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005626d9dff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005626d9aaee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005626d9aaeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f143b8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f143b8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f143b8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005626d9aaea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c (3116 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdf_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdf.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdf.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdf_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdf_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdf_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesdf_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdf_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdf_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind w
# | ...
# `---data was truncated (10240/20198) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de4bf90eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055de4bf8de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055de4bf9162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f44c0905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f44c095c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f44c0905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f44c08ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de4bf26bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055de4bf26a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055de4bf0b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055de4bbbae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055de4bbbab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f44c08eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44c08ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44c08ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de4bbbaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c (3117 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8mf8x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_u8mf8x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_u8mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(
# | ...
# `---data was truncated (10240/31876) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555f35949eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555f35946e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555f3594a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f853cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f853cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f853cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f853cd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f358dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555f358dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555f358c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555f35573e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555f35573b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f853cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f853cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f853cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f35573a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c (3118 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_f16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_f16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_f16m1x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_i16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_i16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_i16m1x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_u16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_u16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_u16m1x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_
# | ...
# `---data was truncated (10240/10396) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055baae721eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055baae71ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055baae72262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f00c341bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f00c34725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f00c341ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f00c3403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055baae6b7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055baae6b7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055baae69c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055baae34be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055baae34bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f00c3404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f00c34050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f00c34050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055baae34ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c (3119 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vunzipo_v_bf16mf4(<vscale x 2 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vunzipo_v_bf16mf2(<vscale x 4 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vunzipo_v_bf16m1(<vscale x 8 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vunzipo_v_bf16m2(<vscale x 16 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vunzipo_v_bf16m4(<vscale x 32 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f0f3256eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f0f3253e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f0f325762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd37a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd37a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd37a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd37a31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f0f31ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f0f31eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f0f31d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f0f2e80e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f0f2e80b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd37a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd37a31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd37a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f0f2e80a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c (3120 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_u8mf8_f8e4m3mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_u8mf4_f8e4m3mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u8mf2_f8e4m3mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_f8e4m3m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_f8e4m3m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_f8e4m3m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_f8e4m3m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_f8e4m3mf8_u8mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_f8e4m3mf4_u8mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_f8e4m3mf2_u8mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_f8e4m3m1_u8m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_f8e4m3m2_u8m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_f8e4m3m4_u8m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_f8e4m3m8_u8m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_u8mf8_f8e5m2mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_u8mf4_f8e5m2mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u8mf2_f8e5m2mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_f8e5m2m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_f8e5m2m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_f8e5m2m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_f8e5m2m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_f8e5m2mf8_u8mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_f8e5m2mf4_u8mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_f8e5m2mf2_u8mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_f8e5m2m1_u8m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_f8e5m2m2_u8m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_f8e5m2m4_u8m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_f8e5m2m8_u8m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 =
# | ...
# `---data was truncated (10240/10936) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005558e702ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005558e7029e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005558e702d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc7f9649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc7f96a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc7f9649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc7f9631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005558e6fc2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005558e6fc2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005558e6fa78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005558e6c56e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005558e6c56b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc7f9632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc7f96330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc7f96330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005558e6c56a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c (3121 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpaire_vv_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vpaire.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpaire.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpaire_vv_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vpaire.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpaire.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpaire_vv_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vpaire.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vpaire.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vpaire_vv_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vpaire.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vpaire.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vpaire_vv_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vpaire.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vpaire.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vpaire_vv_bf16m8(<vscale x 32 x bfloat> %vs2, <vscale x 32 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vpaire.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vpaire.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpaire_vv_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vpaire.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpaire.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpaire_vv_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vpaire.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpaire.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpaire_vv_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr
# | ...
# `---data was truncated (10240/15320) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056120877ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561208779e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056120877d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6ad0b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6ad0b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6ad0b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6ad0aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561208712bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561208712a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005612086f78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005612083a6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005612083a6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6ad0aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6ad0aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6ad0aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005612083a6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c (3122 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f16m1x8(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f32m1x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f64m1x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei16_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056439c5a3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056439c5a0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056439c5a462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f25e261bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f25e26725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f25e261ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f25e2603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056439c539bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056439c539a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056439c51e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056439c1cde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056439c1cdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f25e2604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f25e26050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f25e26050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056439c1cda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c (3123 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesz_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesz_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesz_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesz_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesz_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesz_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesz_vs_u32m1_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32m2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree n
# | ...
# `---data was truncated (10240/15237) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560f6fde3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560f6fde0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560f6fde462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f453e505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f453e55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f453e505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f453e4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f6fd79bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560f6fd79a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560f6fd5e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560f6fa0de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560f6fa0db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f453e4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f453e4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f453e4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f6fa0da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vrnd.c (3124 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vrnd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c --check-prefixes=CHECK,CHECK-NOSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndaq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.round.v8f16(<8 x half> %0)
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.round.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndaq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.round.v4f32(<4 x float> %0)
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.round.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndmq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.floor.v8f16(<8 x half> %0)
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.floor.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndmq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.floor.v4f32(<4 x float> %0)
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.floor.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndpq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.ceil.v8f16(<8 x half> %0)
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.ceil.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndpq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.ceil.v4f32(<4 x float> %0)
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.ceil.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.trunc.v8f16(<8 x half> %0)
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.trunc.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.trunc.v4f32(<4 x float> %0)
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.trunc.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndxq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.rint.v8f16(<8 x half> %0)
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.rint.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndxq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.rint.v4f32(<4 x float> %0)
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.rint.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndnq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.roundeven.v8f16(<8 x half> %0)
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.roundeven.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndnq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %0)
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.roundeven.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndaq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x half>, ptr %inactive.addr, align 8
# |   %5 = call <8 x half> @llvm.arm.mve.vrinta.predicated.v8f16.v8i1(<8 x half> %0, <8 x i1> %3, <8 x half> %4)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vrinta.predicated.v8f16.v8i1(<8 x half>, <8 x i1>, <8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndaq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x float>, ptr %inactive.addr, align 8
# |   %5 = call <4 x float> @llvm.arm.mve.vrinta.predicated.v4f32.v4i1(<4 x float> %0, <4 x i1> %3, <4 x float> %4)
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vrinta.predicated.v4f32.v4i1(<4 x float>, <4 x i1>, <4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndmq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x half>, ptr %inactive.addr, align 8
# |   %5 = call <8 x half> @llvm.arm.mve.vrintm.predicated.v8f16.v8i1(<8 x half> %0, <8 x i1> %3, <8 x half> %4)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vrintm.predicated.v8f16.v8i1(<8 x half>, <8 x i1>, <8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndmq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1
# | ...
# `---data was truncated (10240/26476) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e703b20eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e703b1de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e703b2162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9a52d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9a52d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9a52d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9a52d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e703ab6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e703ab6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e703a9b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e70374ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e70374ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9a52d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9a52d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9a52d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e70374aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c --check-prefixes=CHECK,CHECK-NOSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c --check-prefixes=CHECK,CHECK-NOSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c (3125 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsac_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsac_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsac_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsac_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsac_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsac_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsac_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsac_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7
# | ...
# `---data was truncated (10240/64374) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c799f58eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c799f55e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c799f5962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb776249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb7762a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb776249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb776231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c799eeebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c799eeea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c799ed38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c799b82e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c799b82b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb776232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb7762330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb7762330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c799b82a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c (3126 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf8_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf4_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf2_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m1_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m2_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m4_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m8_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16mf4_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a222d9eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a222d9be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a222d9f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3f77105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3f7715c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3f77105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3f770ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a222d34bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a222d34a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a222d198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a2229c8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a2229c8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3f770eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3f770ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3f770ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a2229c8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c (3127 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvpackfph -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadt_vf_f16mf4(<vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadt_vf_f16mf2(<vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadt_vf_f16m1(<vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadt_vf_f16m2(<vscale x 8 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(<vscale x 8 x half>, <vscale x 8 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_nds_vfpmadt_vf_f16m4(<vscale x 16 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(<vscale x 16 x half>, <vscale x 16 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_nds_vfpmadt_vf_f16m8(<vscale x 32 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(<vscale x 32 x half>, <vscale x 32 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadt_vf_f16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %1, float %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadt_vf_f16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %1, float %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadt_vf_f16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.mask.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %1, float %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.mask.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadt_vf_f16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x half> %op1, fl
# | ...
# `---data was truncated (10240/25099) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056238577deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056238577ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056238577e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbf32d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbf32d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbf32d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbf32d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562385713bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562385713a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005623856f88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005623853a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005623853a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbf32d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbf32d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbf32d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005623853a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c (3128 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a8fbfeaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a8fbfe7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a8fbfeb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f190c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f190c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f190c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f190c31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a8fbf80bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a8fbf80a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a8fbf658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a8fbc14e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a8fbc14b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f190c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f190c31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f190c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a8fbc14a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/WebAssembly/builtins-table-externref.c (3129 of 27911)
******************** TEST 'Clang :: CodeGen/WebAssembly/builtins-table-externref.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple wasm32 -target-feature +reference-types -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple wasm32 -target-feature +reference-types -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c"
# | target datalayout = "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-i128:128-n32:64-S128-ni:1:10:20"
# | target triple = "wasm32"
# | 
# | @table = internal addrspace(1) global [0 x target("wasm.externref")] zeroinitializer, align 1
# | @const_table = internal addrspace(1) constant [0 x target("wasm.externref")] zeroinitializer, align 1
# | @other_table = internal addrspace(1) global [0 x target("wasm.externref")] zeroinitializer, align 1
# | 
# | ; Function Attrs: noinline nounwind
# | define target("wasm.externref") @test_builtin_wasm_table_get(i32 noundef %index) #0 {
# | entry:
# |   %index.addr = alloca i32, align 4
# |   store i32 %index, ptr %index.addr, align 4
# |   %0 = load i32, ptr %index.addr, align 4
# |   %1 = call target("wasm.externref") @llvm.wasm.table.get.externref(ptr addrspace(1) @table, i32 %0)
# |   ret target("wasm.externref") %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("wasm.externref") @llvm.wasm.table.get.externref(ptr addrspace(1), i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define target("wasm.externref") @test_builtin_wasm_table_get_const(i32 noundef %index) #0 {
# | entry:
# |   %index.addr = alloca i32, align 4
# |   store i32 %index, ptr %index.addr, align 4
# |   %0 = load i32, ptr %index.addr, align 4
# |   %1 = call target("wasm.externref") @llvm.wasm.table.get.externref(ptr addrspace(1) @table, i32 %0)
# |   ret target("wasm.externref") %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define void @test_builtin_wasm_table_set(i32 noundef %index, target("wasm.externref") %ref) #0 {
# | entry:
# |   %index.addr = alloca i32, align 4
# |   %ref.addr = alloca target("wasm.externref"), align 1
# |   store i32 %index, ptr %index.addr, align 4
# |   store target("wasm.externref") %ref, ptr %ref.addr, align 1
# |   %0 = load i32, ptr %index.addr, align 4
# |   %1 = load target("wasm.externref"), ptr %ref.addr, align 1
# |   call void @llvm.wasm.table.set.externref(ptr addrspace(1) @const_table, i32 %0, target("wasm.externref") %1)
# |   %2 = load i32, ptr %index.addr, align 4
# |   %3 = load target("wasm.externref"), ptr %ref.addr, align 1
# |   call void @llvm.wasm.table.set.externref(ptr addrspace(1) @table, i32 %2, target("wasm.externref") %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.wasm.table.set.externref(ptr addrspace(1), i32, target("wasm.externref")) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define void @test_builtin_wasm_table_set_const(i32 noundef %index, target("wasm.externref") %ref) #0 {
# | entry:
# |   %index.addr = alloca i32, align 4
# |   %ref.addr = alloca target("wasm.externref"), align 1
# |   store i32 %index, ptr %index.addr, align 4
# |   store target("wasm.externref") %ref, ptr %ref.addr, align 1
# |   %0 = load i32, ptr %index.addr, align 4
# |   %1 = load target("wasm.externref"), ptr %ref.addr, align 1
# |   call void @llvm.wasm.table.set.externref(ptr addrspace(1) @table, i32 %0, target("wasm.externref") %1)
# |   %2 = load i32, ptr %index.addr, align 4
# |   %3 = load target("wasm.externref"), ptr %ref.addr, align 1
# |   call void @llvm.wasm.table.set.externref(ptr addrspace(1) @const_table, i32 %2, target("wasm.externref") %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define i32 @test_builtin_wasm_table_size() #0 {
# | entry:
# |   %0 = call i32 @llvm.wasm.table.size(ptr addrspace(1) @table)
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare i32 @llvm.wasm.table.size(ptr addrspace(1)) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define i32 @test_builtin_wasm_table_grow(target("wasm.externref") %ref, i32 noundef %nelem) #0 {
# | entry:
# |   %ref.addr = alloca target("wasm.externref"), align 1
# |   %nelem.addr = alloca i32, align 4
# |   store target("wasm.externref") %ref, ptr %ref.addr, align 1
# |   store i32 %nelem, ptr %nelem.addr, align 4
# |   %0 = load target("wasm.externref"), ptr %ref.addr, align 1
# |   %1 = load i32, ptr %nelem.addr, align 4
# |   %2 = call i32 @llvm.wasm.table.grow.externref(ptr addrspace(1) @table, target("wasm.externref") %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare i32 @llvm.wasm.table.grow.externref(ptr addrspace(1), target("wasm.externref"), i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define void @test_builtin_wasm_table_fill(i32 noundef %index, target("wasm.externref") %ref, i32 noundef %nelem) #0 {
# | entry:
# |   %index.addr = alloca i32, align 4
# |   %ref.addr = alloca target("wasm.externref"), align 1
# |   %nelem.addr = alloca i32, align 4
# |   store i32 %index, ptr %index.addr, align 4
# |   store target("wasm.externref") %ref, ptr %ref.addr, align 1
# |   store i32 %nelem, ptr %nelem.addr, align 4
# |   %0 = load i32, ptr %index.addr, align 4
# |   %1 = load target("wasm.externref"), ptr %ref.addr, align 1
# |   %2 = load i32, ptr %nelem.addr, align 4
# |   call void @llvm.wasm.table.fill.externref(ptr addrspace(1) @table, i32 %0, target("wasm.externref") %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.wasm.table.fill.externref(ptr addrspace(1), i32, target("wasm.externref"), i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define void @test_table_copy(i32 noundef %dst_idx, i32 noundef %src_idx, i32 noundef %nelem) #0 {
# | entry:
# |   %dst_idx.addr = alloca i32, align 4
# |   %src_idx.addr = alloca i32, align 4
# |   %nelem.addr = alloca i32, align 4
# |   store i32 %dst_idx, ptr %dst_idx.addr, align 4
# |   store i32 %src_idx, ptr %src_idx.addr, align 4
# |   store i32 %nelem, ptr %nelem.addr, align 4
# |   %0 = load i32, ptr %dst_idx.addr, align 4
# |   %1 = load i32, ptr %src_idx.addr, align 4
# |   %2 = load i32, ptr %nelem.addr, align 4
# |   call void @llvm.wasm.table.copy(ptr addrspace(1) @table, ptr addrspace(1) @other_table, i32 %1, i32 %0, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.wasm.table.copy(ptr addrspace(1), ptr addrspace(1), i32, i32, i32) #3
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+reference-types" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | attributes #3 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c08c9beeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c08c9bbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c08c9bf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3fa4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3fa438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3fa4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3fa431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c08c954bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c08c954a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c08c9398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c08c5e8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c08c5e8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3fa431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3fa431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3fa431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c08c5e8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c (3130 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e342937eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e342934e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e34293862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcba1e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcba1e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcba1e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcba1e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e3428cdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e3428cda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e3428b28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e342561e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e342561b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcba1e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcba1e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcba1e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e342561a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c (3131 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vlse64_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64.p0.i64(<vscale x 1 x double> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vlse64_v_f64m2_tu(<vscale x 2 x double> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64.p0.i64(<vscale x 2 x double> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vlse64_v_f64m4_tu(<vscale x 4 x double> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64.p0.i64(<vscale x 4 x double> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vlse64_v_f64m8_tu(<vscale x 8 x double> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64.p0.i64(<vscale x 8 x double> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vlse64_v_i64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vlse64_v_i64m2_tu(<vscale x 2 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.p0.i64(<vscale x 2 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vlse64_v_i64m4_tu(<vscale x 4 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.p0.i64(<vscale x 4 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vlse64_v_i64m8_tu(<vscale x 8 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.p0.i64(<vscale x 8 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vlse64_v_u64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i6
# | ...
# `---data was truncated (10240/56171) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557c2b3baeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557c2b3b7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557c2b3bb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4713733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f471378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4713733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f471371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557c2b350bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557c2b350a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557c2b3358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557c2afe4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557c2afe4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f471371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f471371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f471371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557c2afe4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-bf16-dotprod-intrinsics.c (3132 of 27911)
******************** TEST 'Clang :: CodeGen/arm-bf16-dotprod-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-arm-none-eabi    -target-feature +neon -target-feature +bf16 -mfloat-abi soft    -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-arm-none-eabi -target-feature +neon -target-feature +bf16 -mfloat-abi soft -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8-arm-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vbfdot_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x bfloat>, align 8
# |   %__p2.addr.i = alloca <4 x bfloat>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   %b.addr = alloca <4 x bfloat>, align 8
# |   store <2 x float> %r, ptr %r.addr, align 8
# |   store <4 x bfloat> %a, ptr %a.addr, align 8
# |   store <4 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %r.addr, align 8
# |   %1 = load <4 x bfloat>, ptr %a.addr, align 8
# |   %2 = load <4 x bfloat>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__p1.addr.i, align 8
# |   store <4 x bfloat> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vbfdot.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vbfdot1.i = bitcast <8 x i8> %4 to <4 x bfloat>
# |   %vbfdot2.i = bitcast <8 x i8> %5 to <4 x bfloat>
# |   %vbfdot3.i = call <2 x float> @llvm.arm.neon.bfdot.v2f32.v4bf16(<2 x float> %vbfdot.i, <4 x bfloat> %vbfdot1.i, <4 x bfloat> %vbfdot2.i)
# |   store <2 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vbfdotq_f32(<4 x float> noundef %r, <8 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__p1.addr.i = alloca <8 x bfloat>, align 8
# |   %__p2.addr.i = alloca <8 x bfloat>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %r.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <8 x bfloat>, align 8
# |   %b.addr = alloca <8 x bfloat>, align 8
# |   store <4 x float> %r, ptr %r.addr, align 8
# |   store <8 x bfloat> %a, ptr %a.addr, align 8
# |   store <8 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %r.addr, align 8
# |   %1 = load <8 x bfloat>, ptr %a.addr, align 8
# |   %2 = load <8 x bfloat>, ptr %b.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   store <8 x bfloat> %1, ptr %__p1.addr.i, align 8
# |   store <8 x bfloat> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 8
# |   %vbfdot.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vbfdot1.i = bitcast <16 x i8> %4 to <8 x bfloat>
# |   %vbfdot2.i = bitcast <16 x i8> %5 to <8 x bfloat>
# |   %vbfdot3.i = call <4 x float> @llvm.arm.neon.bfdot.v4f32.v8bf16(<4 x float> %vbfdot.i, <8 x bfloat> %vbfdot1.i, <8 x bfloat> %vbfdot2.i)
# |   store <4 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vbfdot_lane_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x bfloat>, align 8
# |   %__p2.addr.i = alloca <4 x bfloat>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   %b.addr = alloca <4 x bfloat>, align 8
# |   %__ret_810 = alloca <2 x float>, align 8
# |   %__s0_810 = alloca <2 x float>, align 8
# |   %__s1_810 = alloca <4 x bfloat>, align 8
# |   %__s2_810 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca <2 x float>, align 8
# |   %__ret = alloca <2 x float>, align 8
# |   %__s0 = alloca <2 x float>, align 8
# |   %ref.tmp1 = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x float>, align 8
# |   %tmp2 = alloca <2 x float>, align 8
# |   store <2 x float> %r, ptr %r.addr, align 8
# |   store <4 x bfloat> %a, ptr %a.addr, align 8
# |   store <4 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %r.addr, align 8
# |   store <2 x float> %0, ptr %__s0_810, align 8
# |   %1 = load <4 x bfloat>, ptr %a.addr, align 8
# |   store <4 x bfloat> %1, ptr %__s1_810, align 8
# |   %2 = load <4 x bfloat>, ptr %b.addr, align 8
# |   store <4 x bfloat> %2, ptr %__s2_810, align 8
# |   %3 = load <2 x float>, ptr %__s0_810, align 8
# |   %4 = load <4 x bfloat>, ptr %__s1_810, align 8
# |   %5 = load <2 x float>, ptr %__s2_810, align 8
# |   store <2 x float> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x float>
# |   %lane = shufflevector <2 x float> %7, <2 x float> %7, <2 x i32> zeroinitializer
# |   store <2 x float> %lane, ptr %ref.tmp1, align 8
# |   %8 = load <2 x float>, ptr %ref.tmp1, align 8
# |   store <2 x float> %8, ptr %__ret, align 8
# |   %9 = load <2 x float>, ptr %__ret, align 8
# |   store <2 x float> %9, ptr %tmp, align 8
# |   %10 = load <2 x float>, ptr %tmp, align 8
# |   store <2 x float> %10, ptr %ref.tmp, align 8
# |   %11 = load <4 x bfloat>, ptr %ref.tmp, align 8
# |   store <2 x float> %3, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %4, ptr %__p1.addr.i, align 8
# |   store <4 x bfloat> %11, ptr %__p2.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %14 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vbfdot.i = bitcast <8 x i8> %12 to <2 x float>
# |   %vbfdot1.i = bitcast <8 x i8> %13 to <4 x bfloat>
# |   %vbfdot2.i = bitcast <8 x i8> %14 to <4 x bfloat>
# |   %vbfdot3.i = call <2 x float> @llvm.arm.neon.bfdot.v2f32.v4bf16(<2 x float> %vbfdot.i, <4 x bfloat> %vbfdot1.i, <4 x bfloat> %vbfdot2.i)
# |   store <2 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8
# |   %15 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %15, ptr %__ret.i, align 8
# |   %16 = load <2 x float>, ptr %__ret.i, align 8
# |   store <2 x float> %16, ptr %__ret_810, align 8
# |   %17 = load <2 x float>, ptr %__ret_810, align 8
# |   store <2 x float> %17, ptr %tmp2, align 8
# |   %18 = load <2 x float>, ptr %tmp2, align 8
# |   ret <2 x float> %18
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vbfdotq_laneq_f32(<4 x float> noundef %r, <8 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__p1.addr.i = alloca <8 x bfloat>, align 8
# |   %__p2.addr.i = alloca <8 x bfloat>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %r.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <8 x bfloat>, align 8
# |   %b.addr = alloca <8 x bfloat>, align 8
# |   %__ret_812 = alloca <4 x float>, align 8
# |   %__s0_812 = alloca <4 x float>, align 8
# |   %__s1_812 = alloca <8 x bfloat>, align 8
# |   %__s2_812 = alloca <8 x bfloat>, align 8
# |   %ref.tmp = alloca <4 x float>, align 8
# |   %__ret = alloca <4 x float>, align 8
# |   %__s0 = alloca <4 x float>, align 8
# |   %ref.tmp1 = alloca <16 x i8>, align 8
# |   %tmp = alloca <4 x float>, align 8
# |   %tmp2 = alloca <4 x float>, align 8
# |   store <4 x float> %r, ptr %r.addr, align 8
# |   store <8 x bfloat> %a, ptr %a.addr, align 8
# |   store <8 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %r.addr, align 8
# |   store <4 x float> %0, ptr %__s0_812, align 8
# |   %1 = load <8 x bfloat>, ptr %a.addr, align 8
# |   store <8 x bfloat> %1, ptr %__s1_812, align 8
# |   %2 = load <8 x bfloat>, ptr %b.addr, align 8
# |   store <8 x bfloat> %2, ptr %__s2_812, align 8
# |   %3 = load <4 x float>, ptr %__s0_812, align 8
# |   %4 = load <8 x bfloat>, ptr %__s1_812, align 8
# |   %5 = load <4 x float>, ptr %__s2_812, align 8
# |   store <4 x float> %5, ptr %__s0, align 8
# |   %6 = load <16 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <16 x i8> %6 to <4 x float>
# |   %lane = shufflevector <4 x float> %7, <4 x float> %7, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
# |   store <4 x float> %lane, ptr %ref.tmp1, align 8
# |   %8 = load <4 x float>, ptr %ref.tmp1, align 8
# |   store <4 x float> %8, ptr %__ret, align 8
# |   %9 = load <4 x float>, ptr %__ret, align 8
# |   store <4 x float> %9, ptr %tmp, align 8
# |   %10 = load <4 x float>, ptr %tmp, align 8
# |   store <4 x float> %10, ptr %ref.tmp, align 8
# |   %11 = load <8 x bfloat>, ptr %ref.tmp, align 8
# |   store <4 x float> %3, ptr %__p0.addr.i, align 8
# |   store <8 x bfloat> %4, ptr %__p1.addr.i, align 8
# |   store <8 x bfloat> %11, ptr %__p2.addr.i, align 8
# |   %12 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %13 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %14 = load <16 x i8>, ptr %__p2.addr.i, align 8
# |   %vbfdot.i = bitcast <16 x i8> %12 to <4 x float>
# |   %vbfdot1.i = bitcast <16 x i8> %13 to <8 x bfloat>
# |   %vbfdot2.i = bitcast <16 x i8> %14 to <8 x bfloat>
# |   %vbfdot3.i = call <4 x float> @llvm.arm.neon.bfdot.v4f32.v8bf16(<4 x float> %vbfdot.i, <8 x bfloat> %vbfdot1.i, <8 x bfloat> %vbfdot2.i)
# |   store <4 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8
# |   %15 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %15, ptr %__ret.i, align 8
# |   %16 = load <4 x float>, ptr %__ret.i, align 8
# |   store <4 x float> %16, ptr %__ret_812, align 8
# |   %17 = load <4 x float>, ptr %__ret_812, align 8
# |   store <4 x float> %17, ptr %tmp2, align 8
# |   %18 = load <4 x float>, ptr %tmp2, align 8
# |   ret <4 x float> %18
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vbfdot_laneq_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x bfloat>, align 8
# |   %__p2.addr.i = alloca <4 x bfloat>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   %b.addr = alloca <8 x bfloat>, align 8
# |   %__ret_814 = alloca <2 x float>, al
# | ...
# `---data was truncated (10240/54174) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055f5a0688eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f5a0685e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f5a068962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc0f1e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc0f1ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc0f1e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc0f1e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f5a061ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f5a061ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f5a06038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f5a02b2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f5a02b2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc0f1e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc0f1e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc0f1e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f5a02b2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c (3133 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056374afeeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056374afebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056374afef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8bc7533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8bc758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8bc7533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8bc751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056374af84bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056374af84a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056374af698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056374ac18e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056374ac18b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8bc751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8bc751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8bc751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056374ac18a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c (3134 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8ff_v_i8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8ff_v_i8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8ff_v_i8m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_u8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8ff_v_u8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8ff_v_u8mf2
# | ...
# `---data was truncated (10240/54694) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a09e509eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a09e506e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a09e50a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2d6b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2d6b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2d6b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2d6b231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a09e49fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a09e49fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a09e4848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a09e133e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a09e133b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2d6b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2d6b2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2d6b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a09e133a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c (3135 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_i8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_i8mf2x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8_v_i8m1x7_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_u8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_u8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_u8mf2x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8_v_u8m1x7_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055884a592eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055884a58fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055884a59362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f376d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f376d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f376d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f376d231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055884a528bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055884a528a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055884a50d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055884a1bce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055884a1bcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f376d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f376d2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f376d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055884a1bca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-v8.2a-neon-intrinsics.c (3136 of 27911)
******************** TEST 'Clang :: CodeGen/arm-v8.2a-neon-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-linux-gnu -target-abi apcs-gnu -target-feature +neon -target-feature +fullfp16  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-linux-gnu -target-abi apcs-gnu -target-feature +neon -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
# | target triple = "armv8.2a-unknown-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vabs_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vabs.i = bitcast <8 x i8> %1 to <4 x half>
# |   %vabs1.i = call <4 x half> @llvm.fabs.v4f16(<4 x half> %vabs.i)
# |   store <4 x half> %vabs1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vabsq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vabs.i = bitcast <16 x i8> %1 to <8 x half>
# |   %vabs1.i = call <8 x half> @llvm.fabs.v8f16(<8 x half> %vabs.i)
# |   store <8 x half> %vabs1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %2, ptr %__ret.i, align 16
# |   %3 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vceqz_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp oeq <4 x half> %2, zeroinitializer
# |   %vceqz.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vceqz.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vceqzq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp oeq <8 x half> %2, zeroinitializer
# |   %vceqz.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vceqz.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcgez_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp oge <4 x half> %2, zeroinitializer
# |   %vcgez.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vcgez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcgezq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp oge <8 x half> %2, zeroinitializer
# |   %vcgez.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vcgez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcgtz_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp ogt <4 x half> %2, zeroinitializer
# |   %vcgtz.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vcgtz.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcgtzq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp ogt <8 x half> %2, zeroinitializer
# |   %vcgtz.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vcgtz.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vclez_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp ole <4 x half> %2, zeroinitializer
# |   %vclez.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vclez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vclezq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp ole <8 x half> %2, zeroinitializer
# |   %vclez.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vclez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcltz_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp olt <4 x half> %2, zeroinitializer
# |   %vcltz.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vcltz.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcltzq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp olt <8 x half> %2, zeroinitializer
# |   %vcltz.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vcltz.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vcvt_f16_s16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloc
# | ...
# `---data was truncated (10240/122004) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055a8d2ad5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a8d2ad2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a8d2ad662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe426e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe426ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe426e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe426e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a8d2a6bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a8d2a6ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a8d2a508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a8d26ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a8d26ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe426e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe426e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe426e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a8d26ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vhcaddq.c (3137 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vhcaddq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot90_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 0, i32 0, <16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32, i32, <16 x i8>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot90_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 0, i32 0, <8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32, i32, <8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot90_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 0, i32 0, <4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32, i32, <4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot270_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 0, i32 1, <16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot270_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 0, i32 1, <8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot270_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 0, i32 1, <4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot90_x_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 0, <16 x i8> undef, <16 x i8> %0, <16 x i8> %1, <16 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32, i32, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot90_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 0, <8 x i16> undef, <8 x i16> %0, <8 x i16> %1, <8 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32, i32, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot90_x_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 0, <4 x i32> undef, <4 x i32> %0, <4 x i32> %1, <4 x i1> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32, i32, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot270_x_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 1, <16 x i8> undef, <16 x i8> %0, <16 x i8> %1, <16 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot270_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 1, <8 x i16> undef, <8 x i16> %0, <8 x i16> %1, <8 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot270_x_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 1, <4 x i32> undef, <4 x i32> %0, <4 x i32> %1, <4 x i1> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot90_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %inactive.addr, align 8
# |  
# | ...
# `---data was truncated (10240/15969) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f2050eceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f2050e9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f2050ed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f62a7333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f62a738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f62a7333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f62a731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f205082bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f205082a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f2050678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f204d16e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f204d16b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f62a731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f62a731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f62a731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f204d16a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c (3138 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_f16mf4x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_f16mf2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_f16m1x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_f16m2x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_i16mf4x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_i16mf2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_i16m1x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tu
# | ...
# `---data was truncated (10240/17844) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005588294daeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005588294d7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005588294db62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffbde649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffbde6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffbde649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffbde631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558829470bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558829470a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005588294558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558829104e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558829104b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffbde632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffbde6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffbde6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558829104a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c (3139 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_bf16mf4_u16mf4(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1bf16.i64(<vscale x 1 x i16> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1bf16.i64(<vscale x 1 x i16>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_bf16mf2_u16mf2(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2bf16.i64(<vscale x 2 x i16> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2bf16.i64(<vscale x 2 x i16>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_bf16m1_u16m1(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4bf16.i64(<vscale x 4 x i16> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4bf16.i64(<vscale x 4 x i16>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_bf16m2_u16m2(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8bf16.i64(<vscale x 8 x i16> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8bf16.i64(<vscale x 8 x i16>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_bf16m4_u16m4(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16bf16.i64(<vscale x 16 x i16> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16bf16.i64(<vscale x 16 x i16>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfclass_v_bf16m8_u16m8(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32bf16.i64(<vscale x 32 x i16> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32bf16.i64(<vscale x 32 x i16>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_bf16mf4_u16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1bf16.i64(<vscale x 1 x i16> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1bf16.i64(<vscale x 1 x i16>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_bf16mf2_u16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2bf16.i64(<vscale x 2 x i16> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2bf16.i64(<vscale x 2 x i16>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_bf16m1_u16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4bf16.i64(<vscale x 4 x i16> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4bf16.i64(<vscale x 4 x i16>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_bf16m2_u16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfclass.mask.nxv8bf16.i64(<vscale x 8 x i16> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.mask.nxv8bf16.i64(<vscale x 8 x i16>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_bf16m4_u16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfclass.mask.nxv16bf16.i64(<vscale x 16 x i16> poison, <vscale x 16 x bfloat> %1, <vsc
# | ...
# `---data was truncated (10240/12290) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dae399deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055dae399ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055dae399e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd5fa849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd5fa8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd5fa849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd5fa831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dae3933bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055dae3933a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055dae39188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055dae35c7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055dae35c7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd5fa832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd5fa8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd5fa8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dae35c7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c (3140 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vghsh_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vghsh_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vghsh_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vghsh_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vghsh_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c4afd94eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c4afd91e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c4afd9562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbde2649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbde26a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbde2649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbde2631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c4afd2abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c4afd2aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c4afd0f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c4af9bee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c4af9beb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbde2632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbde26330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbde26330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c4af9bea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c (3141 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x flo
# | ...
# `---data was truncated (10240/101584) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555fbd753eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555fbd750e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555fbd75462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f488a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f488a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f488a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f488a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555fbd6e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555fbd6e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555fbd6ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555fbd37de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555fbd37db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f488a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f488a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f488a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555fbd37da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c (3142 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_i32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_i32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_u32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_u32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005569d1b0eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005569d1b0be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005569d1b0f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1900049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f19000a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1900049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1900031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005569d1aa4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005569d1aa4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005569d1a898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005569d1738e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005569d1738b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1900032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f19000330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f19000330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005569d1738a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c (3143 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8mf8x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8mf8x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   cal
# | ...
# `---data was truncated (10240/23487) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b37b45eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563b37b42e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563b37b4662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f42a2533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42a258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f42a2533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f42a251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b37adbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563b37adba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563b37ac08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563b3776fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563b3776fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f42a251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42a251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42a251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b3776fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c (3144 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_f16mf4x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_f16mf2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_f16m1x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_f16m2x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_i16mf4x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_i16mf2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_i16m1x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_i16m2x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8
# | ...
# `---data was truncated (10240/15457) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d8a55cceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d8a55c9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d8a55cd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f375db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f375db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f375db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f375db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d8a5562bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d8a5562a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d8a55478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d8a51f6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d8a51f6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f375db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f375db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f375db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d8a51f6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c (3145 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4asu_vx_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4asu_vx_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Functio
# | ...
# `---data was truncated (10240/13657) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aba35f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055aba35eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055aba35f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3babe1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3babe725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3babe1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3babe03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aba3587bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055aba3587a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055aba356c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055aba321be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055aba321bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3babe04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3babe050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3babe050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aba321ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c (3146 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwcvtu_x_x_v_u16mf4(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwcvtu_x_x_v_u16mf2(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwcvtu_x_x_v_u16m1(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwcvtu_x_x_v_u16m2(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwcvtu_x_x_v_u16m4(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwcvtu_x_x_v_u16m8(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwcvtu_x_x_v_u32mf2(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwcvtu_x_x_v_u32m1(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwcvtu_x_x_v_u32m2(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vwcvtu_x_x_v_u32m4(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vwcvtu_x_x_v_u32m8(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vwcvtu_x_x_v_u64m1(<vscale x 1 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> %0, i32 0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i32, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vwcvtu_x_x_v_u64
# | ...
# `---data was truncated (10240/29259) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005648bf766eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005648bf763e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005648bf76762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb40049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb400a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb40049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb40031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005648bf6fcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005648bf6fca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005648bf6e18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005648bf390e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005648bf390b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007feb40032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb400330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb400330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005648bf390a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c (3147 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f16m1x6(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f32m1x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f64m1x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei8_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none
# | ...
# `---data was truncated (10240/61673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055862d377eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055862d374e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055862d37862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2c73933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2c7398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2c73933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2c7391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055862d30dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055862d30da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055862d2f28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055862cfa1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055862cfa1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2c7391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2c7391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2c7391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055862cfa1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c (3148 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>
# | ...
# `---data was truncated (10240/19492) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d1af716eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d1af713e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d1af71762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd48c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd48ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd48c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd48c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d1af6acbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d1af6aca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d1af6918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d1af340e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d1af340b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbd48c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd48c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd48c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d1af340a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c (3149 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f16m1x5(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f32m1x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f64m1x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei32_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005588b8276eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005588b8273e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005588b827762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc0e9849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc0e98a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc0e9849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc0e9831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005588b820cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005588b820ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005588b81f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005588b7ea0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005588b7ea0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc0e9832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc0e98330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc0e98330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005588b7ea0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c (3150 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaadd_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaadd_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaadd_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaadd_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaadd_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaadd_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaadd_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaadd_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaadd_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaadd_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vaadd_vv_i8
# | ...
# `---data was truncated (10240/99577) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e066d5eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e066d5be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e066d5f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f50de905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f50de95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f50de905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f50de8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e066cf4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e066cf4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e066cd98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e066988e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e066988b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f50de8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f50de8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f50de8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e066988a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c (3151 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_f16mf4x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_f16mf2x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_f16m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_i16mf4x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_i16mf2x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_i16m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_u16mf4x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_u16mf2x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_u16m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_f16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_f16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_f16m1x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 
# | ...
# `---data was truncated (10240/17523) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d7c26aeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d7c26abe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d7c26af62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc4c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc4c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc4c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc4c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d7c2644bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d7c2644a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d7c26298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d7c22d8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d7c22d8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdc4c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc4c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc4c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d7c22d8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c (3152 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdm_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdm.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdm.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdm_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdm_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdm_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesdm_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdm_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdm_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | ...
# `---data was truncated (10240/20149) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555f25e5aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555f25e57e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555f25e5b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff6e5b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff6e5b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff6e5b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff6e5b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f25df0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555f25df0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555f25dd58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555f25a84e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555f25a84b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff6e5b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff6e5b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff6e5b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f25a84a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c (3153 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_i32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_i32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_u32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_u32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_f32mf2x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscal
# | ...
# `---data was truncated (10240/35921) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563928bdeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563928bdbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563928bdf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd85c905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd85c95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd85c905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd85c8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563928b74bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563928b74a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563928b598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563928808e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563928808b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd85c8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd85c8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd85c8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563928808a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c (3154 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_f32mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_f32m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_i32mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_i32m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_u32mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_u32m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_i32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_i32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %
# | ...
# `---data was truncated (10240/14001) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056109d0a4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056109d0a1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056109d0a562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f73e2249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f73e22a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f73e2249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f73e2231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056109d03abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056109d03aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056109d01f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056109cccee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056109ccceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f73e2232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73e22330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73e22330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056109cccea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c (3155 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vlse8_v_i8mf8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vlse8_v_i8mf4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vlse8_v_i8mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vlse8_v_i8m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vlse8_v_i8m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vlse8_v_i8m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vlse8_v_i8m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vlse8_v_u8mf8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vlse8_v_u8mf4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vlse8_v_u8mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vlse8_v_u8m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vlse8_v_u8m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vlse8_v_u8m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr 
# | ...
# `---data was truncated (10240/26240) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d5981d3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d5981d0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d5981d462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdab741bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdab74725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdab741ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdab7403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d598169bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d598169a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d59814e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d597dfde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d597dfdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdab7404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdab74050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdab74050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d597dfda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c (3156 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_i16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_i16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_i16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_u16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_u16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_u16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("ri
# | ...
# `---data was truncated (10240/47480) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a6a75c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a6a75bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a6a75c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9007d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9007d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9007d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9007d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a6a7556bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a6a7556a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a6a753b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a6a71eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a6a71eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9007d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9007d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9007d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a6a71eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c (3157 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16mf4_f16m1(<vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16mf2_f16m1(<vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m1_f16m1(<vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m2_f16m1(<vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m4_f16m1(<vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m8_f16m1(<vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32mf2_f32m1(<vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32m1_f32m1(<vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32m2_f32m1(<vscale x 4 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define
# | ...
# `---data was truncated (10240/37564) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f9bd349eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f9bd346e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f9bd34a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb297c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb297ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb297c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb297c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f9bd2dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f9bd2dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f9bd2c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f9bcf73e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f9bcf73b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb297c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb297c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb297c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f9bcf73a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c (3158 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e08f069eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e08f066e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e08f06a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4bf6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4bf6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4bf6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4bf6b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e08efffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e08efffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e08efe48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e08ec93e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e08ec93b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4bf6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4bf6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4bf6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e08ec93a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c (3159 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ef095e0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ef095dde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ef095e162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7028c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7028ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7028c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7028c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ef09576bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ef09576a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ef0955b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ef0920ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ef0920ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7028c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7028c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7028c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ef0920aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c (3160 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_f16mf4x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_f16mf2x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_f16m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_i16mf4x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_i16mf2x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_i16m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_u16mf4x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_u16mf2x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_u16m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_f16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_f16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_f16m1x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 
# | ...
# `---data was truncated (10240/17523) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561c4fbb9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561c4fbb6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561c4fbba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f976aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f976aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f976aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f976aa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561c4fb4fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561c4fb4fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561c4fb348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561c4f7e3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561c4f7e3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f976aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f976aa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f976aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561c4f7e3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c (3161 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.
# | ...
# `---data was truncated (10240/16808) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005577f3b68eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005577f3b65e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005577f3b6962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcad0733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcad078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcad0733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcad071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005577f3afebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005577f3afea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005577f3ae38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005577f3792e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005577f3792b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcad071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcad071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcad071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005577f3792a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c (3162 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>
# | ...
# `---data was truncated (10240/19492) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055780d8ebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055780d8e8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055780d8ec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3cd8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3cd818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3cd8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3cd811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055780d881bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055780d881a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055780d8668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055780d515e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055780d515b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3cd811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3cd811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3cd811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055780d515a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c (3163 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvpackfph -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadt_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadt_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadt_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadt_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(<vscale x 8 x half>, <vscale x 8 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_nds_vfpmadt_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(<vscale x 16 x half>, <vscale x 16 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_nds_vfpmadt_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(<vscale x 32 x half>, <vscale x 32 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadt_vf_f16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load float, ptr %op2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(<vscale x 1 x half> %1, <vscale x 1 x half> %2, float %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadt_vf_f16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load float, ptr %op2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64(<vscale x 2 x half> %1, <vscale x 2 x half> %2, float %3, <vsc
# | ...
# `---data was truncated (10240/59603) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557b2a9f7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557b2a9f4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557b2a9f862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ed2933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ed298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ed2933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ed291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b2a98dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557b2a98da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557b2a9728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557b2a621e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557b2a621b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8ed291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ed291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ed291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b2a621a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c (3164 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>
# | ...
# `---data was truncated (10240/19492) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d43d93feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d43d93ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d43d94062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f013a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f013a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f013a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f013a11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d43d8d5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d43d8d5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d43d8ba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d43d569e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d43d569b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f013a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f013a11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f013a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d43d569a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c (3165 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_i8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_i8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_i8mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8_v_i8m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8_v_i8m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_u8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_u8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_u8mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(targe
# | ...
# `---data was truncated (10240/53734) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556612981eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055661297ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055661298262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efdc4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efdc438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efdc4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efdc431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556612917bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556612917a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005566128fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005566125abe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005566125abb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007efdc431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efdc431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efdc431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005566125aba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c (3166 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8mf8x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_u8mf8x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_u8mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_u8mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_u8m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, al
# | ...
# `---data was truncated (10240/21566) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f74439beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f744398e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f74439c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f65e1533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f65e158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f65e1533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f65e151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f744331bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f744331a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f7443168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f743fc5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f743fc5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f65e151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f65e151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f65e151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f743fc5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c (3167 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_i8mf8x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_i8mf4x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_i8mf2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8_v_i8m1x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8_v_i8m2x3_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_u8mf8x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_u8mf4x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_u8mf2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8_v_u8m1x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x 
# | ...
# `---data was truncated (10240/11943) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f3501feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564f3501ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564f3502062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb80049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb800a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb80049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb80031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f34fb5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564f34fb5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564f34f9a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564f34c49e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564f34c49b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ffb80032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb800330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb800330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f34c49a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c (3168 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfadd_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfadd_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfadd_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfadd_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfadd_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfadd_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfadd_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfadd_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfadd_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfadd.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfadd.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfadd_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscal
# | ...
# `---data was truncated (10240/29510) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bceeb4eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bceeb4be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bceeb4f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ba1a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ba1aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ba1a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ba1a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bceeae4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bceeae4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bceeac98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bcee778e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bcee778b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8ba1a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ba1a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ba1a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bcee778a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c (3169 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f16m1x3(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_f16m2x3(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f32m1x3(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_f32m2x3(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f64m1x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), p
# | ...
# `---data was truncated (10240/87316) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564b97e77eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564b97e74e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564b97e7862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f03e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f03ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f03e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f03e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564b97e0dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564b97e0da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564b97df28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564b97aa1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564b97aa1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2f03e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f03e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f03e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564b97aa1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c (3170 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vx_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmulh_vv_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmulh_vx_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmulh_vv_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmulh_vx_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmulh_vv_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmulh_vx_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, alig
# | ...
# `---data was truncated (10240/41669) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b54e4d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b54e4d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b54e4d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7695505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f769555c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7695505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f76954ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b54e46ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b54e46ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b54e4538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b54e102e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b54e102b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f76954eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f76954ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f76954ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b54e102a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c (3171 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabda_vv_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabda_vx_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabda_vv_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabda_vx_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabda_vv_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabda_vx_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabda_vv_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabda_vx_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwabda_vv_u16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   s
# | ...
# `---data was truncated (10240/58326) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561467b6ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561467b69e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561467b6d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f793b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f793b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f793b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f793b31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561467b02bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561467b02a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561467ae78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561467796e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561467796b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f793b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f793b31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f793b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561467796a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c (3172 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_bf16m1x3_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64
# | ...
# `---data was truncated (10240/24373) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e40b6b2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e40b6afe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e40b6b362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007effa3133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007effa318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007effa3133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007effa311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e40b648bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e40b648a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e40b62d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e40b2dce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e40b2dcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007effa311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007effa311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007effa311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e40b2dca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c (3173 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563820bc5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563820bc2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563820bc662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbb2d81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbb2d8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbb2d81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbb2d803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563820b5bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563820b5ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563820b408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005638207efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005638207efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbb2d804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbb2d8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbb2d8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005638207efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c (3174 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055623c042eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055623c03fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055623c04362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8db9905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8db995c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8db9905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8db98ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055623bfd8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055623bfd8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055623bfbd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055623bc6ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055623bc6cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8db98eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8db98ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8db98ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055623bc6ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c (3175 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005643d6de3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005643d6de0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005643d6de462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8013333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f801338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8013333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f801331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005643d6d79bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005643d6d79a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005643d6d5e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005643d6a0de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005643d6a0db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f801331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f801331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f801331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005643d6a0da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c (3176 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16mf4x8(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16mf2x8(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16m1x8(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b01b77eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b01b77be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b01b77f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7893333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f789338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7893333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f789331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b01b714bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b01b714a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b01b6f98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b01b3a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b01b3a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f789331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f789331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f789331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b01b3a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c (3177 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_2x8x2_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_2x8x2_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_2x8x2_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_2x8x2_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd91b30eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fd91b2de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fd91b3162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe539533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe53958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe539533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe53951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd91ac6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fd91ac6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fd91aab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fd9175ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fd9175ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe53951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe53951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe53951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd9175aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c (3178 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005593aa197eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005593aa194e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005593aa19862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff031c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff031ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff031c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff031c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005593aa12dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005593aa12da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005593aa1128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005593a9dc1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005593a9dc1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff031c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff031c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff031c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005593a9dc1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c (3179 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_f16mf4x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_f16mf2x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_f16m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_i16mf4x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_i16mf2x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_i16m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_u16mf4x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_u16mf2x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_u16m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_f16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_f16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_f16m1x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 
# | ...
# `---data was truncated (10240/17523) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556a5951ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556a59519e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556a5951d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee64649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee646a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee64649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee64631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556a594b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556a594b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556a594978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556a59146e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556a59146b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fee64632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee646330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee646330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556a59146a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c (3180 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmacc_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmacc_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmacc_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmacc_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmacc_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmacc_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmacc_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmacc_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <
# | ...
# `---data was truncated (10240/34430) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c9989a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c9989a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c9989a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9cdb049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9cdb0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9cdb049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9cdb031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c99893cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c99893ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c9989218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c9985d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c9985d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9cdb032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9cdb0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9cdb0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c9985d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c (3181 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vle.nxv1f64.p0.i64(<vscale x 1 x double> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x double> @llvm.riscv.vle.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64_v_f64m2_tu(<vscale x 2 x double> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vle.nxv2f64.p0.i64(<vscale x 2 x double> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.riscv.vle.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vle64_v_f64m4_tu(<vscale x 4 x double> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.vle.nxv4f64.p0.i64(<vscale x 4 x double> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x double> @llvm.riscv.vle.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vle64_v_f64m8_tu(<vscale x 8 x double> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.vle.nxv8f64.p0.i64(<vscale x 8 x double> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x double> @llvm.riscv.vle.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64_v_i64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64_v_i64m2_tu(<vscale x 2 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64_v_i64m4_tu(<vscale x 4 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64_v_i64m8_tu(<vscale x 8 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.p0.i64(<vscale x 8 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64_v_u64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64_v_u64m2_tu(<vscale x 2 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64_v_u64m4_tu(<vscale x 4 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,10
# | ...
# `---data was truncated (10240/48393) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005617192cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005617192cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005617192ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f542ae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f542aea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f542ae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f542ae31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561719263bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561719263a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005617192488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561718ef7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561718ef7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f542ae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f542ae330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f542ae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561718ef7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c (3182 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i16> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale
# | ...
# `---data was truncated (10240/15707) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559d0b203eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559d0b200e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559d0b20462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe4cd905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe4cd95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe4cd905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe4cd8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559d0b199bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559d0b199a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559d0b17e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559d0ae2de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559d0ae2db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe4cd8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe4cd8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe4cd8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559d0ae2da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c (3183 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfabs_v_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfabs_v_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfabs_v_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1_tum(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# | ...
# `---data was truncated (10240/29304) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005594beaeceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005594beae9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005594beaed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4740849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f47408a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4740849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4740831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005594bea82bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005594bea82a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005594bea678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005594be716e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005594be716b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4740832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f47408330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f47408330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005594be716a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c (3184 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_4x8x4_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_4x8x4_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_4x8x4_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_4x8x4_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562400375eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562400372e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056240037662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f645d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f645d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f645d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f645d431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056240030bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056240030ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005624002f08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005623fff9fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005623fff9fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f645d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f645d4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f645d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005623fff9fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c (3185 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfle_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfle_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfle_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 32 x bflo
# | ...
# `---data was truncated (10240/27786) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559942c81eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559942c7ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559942c8262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fef0db05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fef0db5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fef0db05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fef0daed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559942c17bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559942c17a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559942bfc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005599428abe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005599428abb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fef0daeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fef0daef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fef0daef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005599428aba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c (3186 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005624d2441eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005624d243ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005624d244262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f98f1133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f98f118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f98f1133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f98f111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005624d23d7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005624d23d7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005624d23bc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005624d206be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005624d206bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f98f111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f98f111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f98f111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005624d206ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c (3187 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { ta
# | ...
# `---data was truncated (10240/27858) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a26c338eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a26c335e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a26c33962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba5ae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba5aea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba5ae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba5ae31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a26c2cebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a26c2cea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a26c2b38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a26bf62e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a26bf62b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fba5ae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba5ae330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba5ae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a26bf62a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c (3188 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8mf8(ptr noundef %base, <vscale x 1 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i8.p0.i64(<vscale x 1 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8mf4(ptr noundef %base, <vscale x 2 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i8.p0.i64(<vscale x 2 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8mf2(ptr noundef %base, <vscale x 4 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i8.p0.i64(<vscale x 4 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8m1(ptr noundef %base, <vscale x 8 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i8.p0.i64(<vscale x 8 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8m2(ptr noundef %base, <vscale x 16 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16i8.p0.i64(<vscale x 16 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8m4(ptr noundef %base, <vscale x 32 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv32i8.p0.i64(<vscale x 32 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8m8(ptr noundef %base, <vscale x 64 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 64 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 64 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv64i8.p0.i64(<vscale x 64 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8mf8(ptr noundef %base, <vscale x 1 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i8.p0.i64(<vscale x 1 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8mf4(ptr noundef %base, <vscale x 2 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i8.p0.i64(<vscale x 2 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8mf2(ptr noundef %base, <vscale x 4 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i8.p0.i64(<vscale x 4 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8m1(ptr noundef %base, <vscale x 8 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i8.p0.i64(<vscale x 8 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8m2(ptr noundef %base, <vscale x 16 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16i8.p0.i64(<vscale x 16 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8m4(ptr noundef %base, <vscale x 32 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv32i8.p0.i64(<vscale x 32 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | 
# | ...
# `---data was truncated (10240/25279) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bad4c7deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bad4c7ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bad4c7e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa0d7e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa0d7ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa0d7e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa0d7e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bad4c13bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bad4c13a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bad4bf88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bad48a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bad48a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa0d7e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa0d7e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa0d7e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bad48a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c (3189 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2ch_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2ch_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2ch_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2ch_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2ch_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2ch_vv_u64m1_tu(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2ch_vv_u64m2_tu(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2ch_vv_u64m4_tu(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(
# | ...
# `---data was truncated (10240/12227) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055584bec4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055584bec1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055584bec562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4c2fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4c2fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4c2fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4c2fc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055584be5abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055584be5aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055584be3f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055584baeee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055584baeeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4c2fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4c2fc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4c2fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055584baeea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c (3190 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vle16_v_f16mf4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vle.nxv1f16.p0.i64(<vscale x 1 x half> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x half> @llvm.riscv.vle.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vle16_v_f16mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vle.nxv2f16.p0.i64(<vscale x 2 x half> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x half> @llvm.riscv.vle.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vle16_v_f16m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vle.nxv4f16.p0.i64(<vscale x 4 x half> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x half> @llvm.riscv.vle.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vle16_v_f16m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vle.nxv8f16.p0.i64(<vscale x 8 x half> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x half> @llvm.riscv.vle.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vle16_v_f16m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vle.nxv16f16.p0.i64(<vscale x 16 x half> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x half> @llvm.riscv.vle.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vle16_v_f16m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vle.nxv32f16.p0.i64(<vscale x 32 x half> poison, ptr %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x half> @llvm.riscv.vle.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16_v_i16mf4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16.p0.i64(<vscale x 1 x i16> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16_v_i16mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16.p0.i64(<vscale x 2 x i16> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vle16_v_i16m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16.p0.i64(<vscale x 4 x i16> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vle16_v_i16m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.p0.i64(<vscale x 8 x i16> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.p0.i64(<vscale x 8 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vle16_v_i16m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vle.nxv16i16.p0.i64(<vscale x 16 x i16> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i16> @llvm.riscv.vle.nxv16i16.p0.i64(<vscale x 16 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vle16_v_i16m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vle.nxv32i16.p0.i64(<vscale x 32 x i16> poison, ptr %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i16> @llvm.riscv.vle.nxv32i16.p0.i64(<vscale x 32 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16_v_u16mf4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16.p0.i64(<vscale x 1 x i16> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16_v_u16mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16.p0.i64(<vscale x 2 x i16> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_v
# | ...
# `---data was truncated (10240/29273) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563bcb4a0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563bcb49de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000563bcb4a162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f98fa933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f98fa98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f98fa933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f98fa91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563bcb436bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563bcb436a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000563bcb41b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000563bcb0cae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000563bcb0cab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f98fa91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f98fa91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f98fa91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563bcb0caa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c (3191 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh    -target-feature +xsfvfexpa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexpa_v_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexpa_v_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexpa_v_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexpa_v_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexpa_v_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vfexpa_v_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 32 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexpa_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexpa_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexpa_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexpa_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32.i64(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 
# | ...
# `---data was truncated (10240/47772) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d501b52eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d501b4fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d501b5362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f310cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f310cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f310cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f310cb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d501ae8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d501ae8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d501acd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d50177ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d50177cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f310cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f310cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f310cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d50177ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c (3192 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vneg_v_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vneg_v_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vneg_v_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vneg_v_i8m1(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vneg_v_i8m2(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vneg_v_i8m4(<vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vneg_v_i8m8(<vscale x 64 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vneg_v_i16mf4(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vneg_v_i16mf2(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vneg_v_i16m1(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vneg_v_i16m2(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vrsub.nxv8i16.i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vrsub.nxv8i16.i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vneg_v_i16m4(<vscale x 16 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vrsub.nxv16i16.i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vrsub.nxv16i16.i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vneg_v_i16m8(<vscale x 32 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vsc
# | ...
# `---data was truncated (10240/41425) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e2d9c39eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e2d9c36e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e2d9c3a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ff9133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ff918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ff9133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ff911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e2d9bcfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e2d9bcfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e2d9bb48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e2d9863e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e2d9863b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5ff911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ff911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ff911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2d9863a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c (3193 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vlse64_v_f64m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64.p0.i64(<vscale x 1 x double> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vlse64_v_f64m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64.p0.i64(<vscale x 2 x double> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vlse64_v_f64m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64.p0.i64(<vscale x 4 x double> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vlse64_v_f64m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64.p0.i64(<vscale x 8 x double> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vlse64_v_i64m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vlse64_v_i64m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.p0.i64(<vscale x 2 x i64> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vlse64_v_i64m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.p0.i64(<vscale x 4 x i64> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vlse64_v_i64m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.p0.i64(<vscale x 8 x i64> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vlse64_v_u64m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vlse64_v_u64m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.p0.i64(<vscale x 2 x i64> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vlse64_v_u64m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.p0.i64(<vscale x 4 x i64> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vlse64_v_u64m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.p0.i64(<vscale x 8 x i64> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vs
# | ...
# `---data was truncated (10240/23775) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa7b07deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fa7b07ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fa7b07e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9270c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9270ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9270c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9270c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa7b013bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fa7b013a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fa7aff88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fa7aca7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fa7aca7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9270c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9270c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9270c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa7aca7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c (3194 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_e4m3_e5m2_w4_f8e4m3m8_f8e5m2m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561907cb1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561907caee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561907cb262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa3cb933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa3cb98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa3cb933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa3cb91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561907c47bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561907c47a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561907c2c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005619078dbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005619078dbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa3cb91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa3cb91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa3cb91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005619078dba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbkc.c (3195 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbkc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkc -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c  -check-prefix=RV32ZBKC
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkc -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clmul_32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.clmul.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clmulh_32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.clmulh.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.clmul.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.clmulh.i32(i32, i32) #2
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbkc" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zbkc1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561d82dc8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561d82dc5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561d82dc962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f616dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f616dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f616dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f616dc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561d82d5ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561d82d5ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561d82d438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561d829f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561d829f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f616dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f616dc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f616dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561d829f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c -check-prefix=RV32ZBKC
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c -check-prefix=RV32ZBKC
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c (3196 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_f64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_f64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_f64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_i64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_i64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_i64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_u64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_u64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_u64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, ali
# | ...
# `---data was truncated (10240/47706) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556fa4ce7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556fa4ce4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556fa4ce862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3d2c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3d2c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3d2c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3d2c231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556fa4c7dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556fa4c7da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556fa4c628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556fa4911e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556fa4911b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3d2c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3d2c2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3d2c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556fa4911a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c (3197 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i8> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i8> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i8> %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> %2, ptr %0, <vscale x 32 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 4 x bfloat> %vs3,
# | ...
# `---data was truncated (10240/15512) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055922c38beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055922c388e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055922c38c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec5f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec5f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec5f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec5f11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055922c321bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055922c321a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055922c3068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055922bfb5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055922bfb5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fec5f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec5f11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec5f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055922bfb5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c (3198 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_f64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_f64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_i64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_i64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_u64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_u64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Functi
# | ...
# `---data was truncated (10240/15986) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d0c5318eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d0c5315e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d0c531962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcfe2249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcfe22a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcfe2249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcfe2231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0c52aebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d0c52aea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d0c52938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d0c4f42e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d0c4f42b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcfe2232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcfe22330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcfe22330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d0c4f42a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c (3199 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vle32_v_f32mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vle.nxv1f32.p0.i64(<vscale x 1 x float> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x float> @llvm.riscv.vle.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vle32_v_f32m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vle.nxv2f32.p0.i64(<vscale x 2 x float> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x float> @llvm.riscv.vle.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vle32_v_f32m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vle.nxv4f32.p0.i64(<vscale x 4 x float> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.riscv.vle.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vle32_v_f32m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vle.nxv8f32.p0.i64(<vscale x 8 x float> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x float> @llvm.riscv.vle.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vle32_v_f32m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.p0.i64(<vscale x 16 x float> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32_v_i32mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.p0.i64(<vscale x 1 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32_v_i32m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.p0.i64(<vscale x 2 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32_v_i32m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.p0.i64(<vscale x 4 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vle32_v_i32m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32.p0.i64(<vscale x 8 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vle32_v_i32m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.p0.i64(<vscale x 16 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.p0.i64(<vscale x 16 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32_v_u32mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.p0.i64(<vscale x 1 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32_v_u32m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.p0.i64(<vscale x 2 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32_v_u32m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.p0.i64(<vscale x 4 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vle32_v_u32m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32.p0.i64(<vscale x 8 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vle32_v_u32m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.p0.i64(<vscale x 16 x i32> p
# | ...
# `---data was truncated (10240/24606) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f0e7c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559f0e7bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559f0e7c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2155533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f215558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2155533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f215551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f0e757bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559f0e757a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559f0e73c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559f0e3ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559f0e3ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f215551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f215551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f215551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f0e3eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqmovn.c (3200 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqmovn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 0, i32 0, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8>, <8 x i16>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 0, i32 0, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16>, <4 x i32>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 1, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 1, i32 1, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovntq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 0, i32 0, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovntq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 0, i32 0, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovntq_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 1, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovntq_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 1, i32 1, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovunbq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 0, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovunbq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 1, i32 0, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovuntq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 0, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovuntq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 1, i32 0, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_m_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 0, i32 0, i32 0, <8 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8>, <8 x i16>, i32, i32, i32, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_m_s32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vqmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 0, i32 0, i32 0, <4 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vqmovn.predicated.v8i16.v4i32.v4i1(<8 x i16>, <4 x i32>, i32, i32, i32, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_m_u16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 1, i32 1, i32 0, <8 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_m_u32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   
# | ...
# `---data was truncated (10240/17536) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005560a0258eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005560a0255e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005560a025962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd1aff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd1aff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd1aff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd1aff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005560a01eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005560a01eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005560a01d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055609fe82e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055609fe82b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd1aff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd1aff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd1aff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055609fe82a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c (3201 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e955ccdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e955ccae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e955cce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fde0eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fde0eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fde0eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fde0eb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e955c63bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e955c63a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e955c488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e9558f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e9558f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fde0eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fde0eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fde0eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e9558f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c (3202 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlsseg2e8_v_i8mf8x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e8_v_i8mf4x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e8_v_i8mf2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e8_v_i8m1x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e8_v_i8m2x2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e8_v_i8m4x2_m(<vscale x 32 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv32i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 32 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv32i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, <vscale x 32 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlsseg2e8_v_u8mf8x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e8_v_u8mf4x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 nounde
# | ...
# `---data was truncated (10240/16083) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ef10e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564ef10e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564ef10ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb1d7e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb1d7e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb1d7e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb1d7e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ef107fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564ef107fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564ef10648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564ef0d13e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564ef0d13b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb1d7e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb1d7e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb1d7e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ef0d13a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c (3203 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vunzipe_v_f16mf4(<vscale x 2 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(<vscale x 1 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(<vscale x 1 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vunzipe_v_f16mf2(<vscale x 4 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(<vscale x 2 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(<vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vunzipe_v_f16m1(<vscale x 8 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vunzipe_v_f16m2(<vscale x 16 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(<vscale x 8 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(<vscale x 8 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vunzipe_v_f16m4(<vscale x 32 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(<vscale x 16 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(<vscale x 16 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vunzipe_v_f32mf2(<vscale x 2 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(<vscale x 1 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(<vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vunzipe_v_f32m1(<vscale x 4 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vunzipe_v_f32m2(<vscale x 8 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(<vscale x 4 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(<vscale x 4 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vunzipe_v_f32m4(<vscale x 16 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(<vscale x 8 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(<vscale x 8 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vunzipe_v_f64m1(<vscale x 2 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64(<vscale x 1 x double>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vunzipe_v_f64m2(<vscale x 4 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.vunzipe.nxv2f64.nxv4f64.i64(<vscale x 2 x double> poison, <vscale x 4 x double> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vunzipe.nxv2f64.nxv4f64.i64(<vscale x 2 x double>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vunzipe_v_f64m4(<vscale x 8 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.vunzipe.nxv4f64.nxv8f64.i64(<vscale x 4 x double> poison, <vscale x 8 x double> %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.vunzipe.nxv4f64.nxv8f64.i64(<vscale x 4 x double>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @
# | ...
# `---data was truncated (10240/35774) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055670297feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055670297ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055670298062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe0c2505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe0c255c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe0c2505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe0c24ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556702915bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556702915a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005567028fa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005567025a9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005567025a9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe0c24eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe0c24ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe0c24ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005567025a9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c (3204 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# | ...
# `---data was truncated (10240/18506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ef6be8aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ef6be87e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ef6be8b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdca8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdca818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdca8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdca811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ef6be20bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ef6be20a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ef6be058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ef6bab4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ef6bab4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdca811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdca811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdca811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ef6bab4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c (3205 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_i16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_i16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_i16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_u16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_u16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_u16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ta
# | ...
# `---data was truncated (10240/47488) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f58dd16eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f58dd13e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f58dd1762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9a73933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9a7398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9a73933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9a7391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f58dcacbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f58dcaca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f58dc918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f58d940e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f58d940b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9a7391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9a7391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9a7391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f58d940a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c (3206 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmacc_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmacc_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmacc_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmacc_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmacc_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmacc_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmacc_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmacc_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3
# | ...
# `---data was truncated (10240/64366) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560bd1340eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560bd133de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560bd134162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0462249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f04622a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0462249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0462231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560bd12d6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560bd12d6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560bd12bb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560bd0f6ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560bd0f6ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0462232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f04622330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f04622330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560bd0f6aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c (3207 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_2x8x2_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_2x8x2_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_2x8x2_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_2x8x2_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562afce33eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562afce30e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562afce3462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb240049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb2400a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb240049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb240031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562afcdc9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562afcdc9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562afcdae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562afca5de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562afca5db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb240032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb2400330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb2400330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562afca5da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c (3208 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_f16mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_f16mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_f16m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_i16mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_i16mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_i16m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_u16mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_u16mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_u16m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, pt
# | ...
# `---data was truncated (10240/24016) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bd9a871eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bd9a86ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bd9a87262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb3e7249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb3e72a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb3e7249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb3e7231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bd9a807bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bd9a807a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bd9a7ec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bd9a49be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bd9a49bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb3e7232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb3e72330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb3e72330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bd9a49ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c (3209 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nx
# | ...
# `---data was truncated (10240/18660) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d944b4beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d944b48e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d944b4c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f40dfd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f40dfd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f40dfd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f40dfd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d944ae1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d944ae1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d944ac68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d944775e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d944775b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f40dfd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f40dfd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f40dfd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d944775a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c (3210 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei32_v_i8mf8x7
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005629d24c5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005629d24c2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005629d24c662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f012281bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f01228725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f012281ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0122803507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005629d245bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005629d245ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005629d24408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005629d20efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005629d20efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0122804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f01228050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f01228050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005629d20efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c (3211 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_bf16mf4x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_bf16mf2x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_bf16m1x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_bf16m2x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_bf16m4x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwin
# | ...
# `---data was truncated (10240/13581) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560242ce9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560242ce6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560242cea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9135a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9135aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9135a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9135a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560242c7fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560242c7fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560242c648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560242913e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560242913b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9135a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9135a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9135a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560242913a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbkb.c (3212 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbkb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c  -check-prefix=RV32ZBKB
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @brev8_32(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.brev8.i32(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @zip(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.zip.i32(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @unzip(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.unzip.i32(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.brev8.i32(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.zip.i32(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.unzip.i32(i32) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbkb" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zbkb1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055624b39deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055624b39ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055624b39e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff3eab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff3eab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff3eab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff3eab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055624b333bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055624b333a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055624b3188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055624afc7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055624afc7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff3eab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff3eab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff3eab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055624afc7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c -check-prefix=RV32ZBKB
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c -check-prefix=RV32ZBKB
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vandq.c (3213 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vandq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vandq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = and <16 x i8> %0, %1
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vandq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = and <8 x i16> %0, %1
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vandq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = and <4 x i32> %0, %1
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vandq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = and <4 x i32> %1, %3
# |   %5 = bitcast <4 x i32> %4 to <4 x float>
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vandq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.and.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.and.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vandq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vandq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vandq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <8 x i16>
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = bitcast <8 x half> %2 to <8 x i16>
# |   %4 = load i16, ptr %p.addr, align 2
# |   %5 = zext i16 %4 to i32
# |   %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5)
# |   %7 = load <8 x half>, ptr %inactive.addr, align 8
# |   %8 = bitcast <8 x half> %7 to <8 x i16>
# |   %9 = call <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8)
# |   %10 = bitcast <8 x i16> %9 to <8 x half>
# |   ret <8 x half> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vandq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.and.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vandq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vandq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vandq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = load i16, ptr %p.addr, align 2
# |   %5 = zext i16 %4 to i32
# |   %6 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %5)
# |   %7 = call <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x
# | ...
# `---data was truncated (10240/10901) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555f90178eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555f90175e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555f9017962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0090333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f009038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0090333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f009031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f9010ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555f9010ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555f900f38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555f8fda2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555f8fda2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f009031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f009031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f009031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f8fda2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c (3214 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005555aa971eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005555aa96ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005555aa97262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7863505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f786355c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7863505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f78634ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005555aa907bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005555aa907a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005555aa8ec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005555aa59be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005555aa59bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f78634eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f78634ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f78634ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005555aa59ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c (3215 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_bf16m1x4_tum(<v
# | ...
# `---data was truncated (10240/25687) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e68680ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e686809e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e68680d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f275ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f275ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f275ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f275ab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e6867a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e6867a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e6867878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e686436e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e686436b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f275ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f275ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f275ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e686436a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c (3216 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1up_vf_bf16mf4(<vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1up_vf_bf16mf2(<vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1up_vf_bf16m1(<vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfslide1up_vf_bf16m2(<vscale x 8 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfslide1up_vf_bf16m4(<vscale x 16 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfslide1up_vf_bf16m8(<vscale x 32 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1up_vf_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1up_vf_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1up_vf_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vsc
# | ...
# `---data was truncated (10240/14832) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556aec159eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556aec156e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556aec15a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9ebde49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9ebdea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9ebde49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9ebde31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556aec0efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556aec0efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556aec0d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556aebd83e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556aebd83b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9ebde32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9ebde330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9ebde330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556aebd83a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c (3217 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8ff_v_i8mf8x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8ff_v_i8mf4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8ff_v_i8mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8ff_v_i8m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8ff_v_i8m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8ff_v_i8m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8ff_v_u8mf8x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8ff_v_u8mf4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vect
# | ...
# `---data was truncated (10240/32932) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e8edc15eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e8edc12e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e8edc1662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4420449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f44204a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4420449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4420431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e8edbabbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e8edbaba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e8edb908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e8ed83fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e8ed83fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4420432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44204330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44204330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e8ed83fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c (3218 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_x_f_w_bf16mf4_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_x_f_w_bf16mf2_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_x_f_w_bf16m1_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_x_f_w_bf16m2_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_x_f_w_bf16m4_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_x_f_w_bf16m8_i8m4_tu(<vscale x 32 x i8> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_xu_f_w_bf16mf4_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_xu_f_w_bf16mf2_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_xu_f_w_bf16m1_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_xu_f_w_bf16m2_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm
# | ...
# `---data was truncated (10240/53200) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559283765eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559283762e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055928376662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd2c5f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd2c5f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd2c5f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd2c5f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005592836fbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005592836fba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005592836e08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055928338fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055928338fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd2c5f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd2c5f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd2c5f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055928338fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c (3219 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1_tu(<vscale x 1 x double> %vd, <vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64.i64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x double> @test_sf_vfexpa_v_f64m2_tu(<vscale x 2 x double> %vd, <vscale x 2 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x double>, align 8
# |   %vs2.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64.i64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64.i64(<vscale x 2 x double>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x double> @test_sf_vfexpa_v_f64m4_tu(<vscale x 4 x double> %vd, <vscale x 4 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x double>, align 8
# |   %vs2.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64.i64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i64 %2)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64.i64(<vscale x 4 x double>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vfexpa_v_f64m8_tu(<vscale x 8 x double> %vd, <vscale x 8 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x double>, align 8
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64.i64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, i64 %2)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64.i64(<vscale x 8 x double>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1_tum(<vscale x 1 x i1> %vm, <vscale x 1 x double> %vd, <vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(<vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x double> @test_sf_vfexpa_v_f64m2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x double> %vd, <vscale x 2 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x double>, align 8
# |   %vs2.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 2 x double>, ptr %vs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(<vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x double> @test_sf_vfexpa_v_f64m4_tum(<vscale x 4 x i1> %vm, <vscale x 4 x double> %vd, <vscale x 4 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x double>, align 8
# |   %vs2.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 4 x double>, ptr %vs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(<vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(<vscale x 4 x double>, <vscale x 4 x double>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vfexpa_v_f64m8_tum(<vscale x 8 x i1> %vm, <vscale x 8 x double> %vd, <vscale x 8 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x double>, align 8
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(<vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(<vscale x 8 x double>, <vscale x 8 x double>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1_tumu(<vscale x 1 x i1> %vm, <vscale x 1 x double> %vd, <vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %3 
# | ...
# `---data was truncated (10240/18303) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560ad9ee1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560ad9edee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560ad9ee262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2209133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f220918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2209133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f220911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ad9e77bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560ad9e77a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560ad9e5c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560ad9b0be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560ad9b0bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f220911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f220911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f220911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ad9b0ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c (3220 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vbrev_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vbrev_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vbrev.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vbrev.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vbrev_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vbrev.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vbrev.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vbrev_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vbrev.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vbrev.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vbrev_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vbrev.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vbrev.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vbrev_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vbrev.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vbrev.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vbrev_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vbrev.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vbrev.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vbrev_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vbrev.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vbrev.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vbrev_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vbrev.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vbrev.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vbrev_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vbrev.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vbrev.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vbrev_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vbrev.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vbrev.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vbrev_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vbrev.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vbrev.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vbrev_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vbrev.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: noca
# | ...
# `---data was truncated (10240/40803) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560863966eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560863963e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056086396762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2fdb01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2fdb0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2fdb01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2fdb003507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005608638fcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005608638fca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005608638e18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560863590e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560863590b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2fdb004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2fdb0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2fdb0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560863590a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c (3221 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_2x8x2_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_2x8x2_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_2x8x2_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_2x8x2_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005590bb8f7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005590bb8f4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005590bb8f862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f437db05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f437db5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f437db05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f437daed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005590bb88dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005590bb88da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005590bb8728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005590bb521e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005590bb521b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f437daeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f437daef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f437daef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005590bb521a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c (3222 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrec7_v_bf16mf4(<vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrec7_v_bf16mf2(<vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrec7_v_bf16m1(<vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrec7_v_bf16m2(<vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrec7_v_bf16m4(<vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrec7_v_bf16m8(<vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrec7_v_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrec7_v_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrec7_v_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrec7.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrec7.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrec7_v_bf16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrec7.mask.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrec7.mask.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrec7_v_bf16m4_m(<vscale x 16 x i1> %mask, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, ali
# | ...
# `---data was truncated (10240/12688) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb89e9ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055fb89e99e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055fb89e9d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe6f9849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe6f98a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe6f9849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe6f9831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb89e32bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055fb89e32a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055fb89e178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055fb89ac6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055fb89ac6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe6f9832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe6f98330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe6f98330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb89ac6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c (3223 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i32> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i32> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale
# | ...
# `---data was truncated (10240/13161) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560464a85eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560464a82e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560464a8662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa04a905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa04a95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa04a905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa04a8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560464a1bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560464a1ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560464a008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005604646afe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005604646afb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa04a8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa04a8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa04a8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005604646afa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c (3224 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vzip_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vzip_vv_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr
# | ...
# `---data was truncated (10240/27541) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f751c61eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f751c5ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f751c6262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f402841bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f40284725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f402841ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4028403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f751bf7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f751bf7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f751bdc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f75188be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f75188bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4028404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f40284050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f40284050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f75188ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c (3225 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_f32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_f32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_f32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_i32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_i32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_i32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_u32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_u32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_u32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tu
# | ...
# `---data was truncated (10240/23405) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005645419e1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005645419dee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005645419e262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f73fed05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f73fed5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f73fed05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f73feced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564541977bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564541977a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056454195c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056454160be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056454160bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f73feceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73fecef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73fecef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056454160ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c (3226 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_bf16mf2x6(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_bf16m1x6(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560310b81eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560310b7ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560310b8262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9509f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9509f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9509f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9509f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560310b17bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560310b17a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000560310afc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005603107abe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005603107abb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9509f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9509f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9509f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005603107aba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c (3227 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4a_vv_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4a_vv_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, 
# | ...
# `---data was truncated (10240/26468) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005612558d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005612558d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005612558d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc21db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc21db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc21db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc21db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056125586bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056125586ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005612558508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005612554ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005612554ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc21db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc21db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc21db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005612554ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c (3228 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8ff_v_i8mf8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8ff_v_i8mf4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(<vscale x 2 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8ff_v_i8mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(<vscale x 4 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8ff_v_i8m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(<vscale x 8 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 8 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 8 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8ff_v_i8m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(<vscale x 16 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 16 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8ff_v_i8m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(<vscale x 32 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 32 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 32 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8ff_v_i8m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(<vscale x 64 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 64 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 64 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8ff_v_u8mf8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8ff_v_u8mf4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(<vscale x 2 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8ff_v_u8mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(<vscale x 4 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8ff_v_u8m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, al
# | ...
# `---data was truncated (10240/30013) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005587bcf40eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005587bcf3de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005587bcf4162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb117f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb117f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb117f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb117f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005587bced6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005587bced6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005587bcebb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005587bcb6ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005587bcb6ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb117f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb117f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb117f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005587bcb6aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c (3229 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_i8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_i8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8_v_i8mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8_v_i8m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8_v_i8m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_u8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_u8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8_v_u8mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(targe
# | ...
# `---data was truncated (10240/53734) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005591274f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005591274efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005591274f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f78e1e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f78e1ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f78e1e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f78e1e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559127488bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559127488a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055912746d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055912711ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055912711cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f78e1e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f78e1e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f78e1e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055912711ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c (3230 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vlse8_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vlse8_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vlse8_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vlse8_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vlse8_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.p0.i64(<vscale x 16 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vlse8_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8.p0.i64(<vscale x 32 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vlse8_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8.p0.i64(<vscale x 64 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vlse8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vlse8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vlse8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.a
# | ...
# `---data was truncated (10240/63518) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a3a2814eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a3a2811e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a3a281562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd75649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd756a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd75649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd75631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a3a27aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a3a27aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a3a278f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a3a243ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a3a243eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcd75632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd756330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd756330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a3a243ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c (3231 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjx_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjx_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjx_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjx_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjx_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjx_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjx_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjx_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnjx_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnjx_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %
# | ...
# `---data was truncated (10240/29210) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e9b1083eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e9b1080e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e9b108462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0863133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f086318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0863133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f086311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e9b1019bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e9b1019a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e9b0ffe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e9b0cade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e9b0cadb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f086311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f086311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f086311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e9b0cada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c (3232 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgatherei16_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgatherei16_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgatherei16_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vrgatherei16_vv_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, <vscale x 32 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/32701) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bf4b499eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055bf4b496e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055bf4b49a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f624cf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f624cf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f624cf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f624ceed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bf4b42fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055bf4b42fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055bf4b4148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055bf4b0c3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055bf4b0c3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f624ceeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f624ceef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f624ceef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bf4b0c3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c (3233 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsif_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsif_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsif_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsif_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsif_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsif_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsif_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsif_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1> poison, <vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsif_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1> poison, <vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsif_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1> poison, <vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsif_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1> poison, <vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsif_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1.i64(<vscale x 4 x i1> poison, <vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback n
# | ...
# `---data was truncated (10240/13031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055827a6b9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055827a6b6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055827a6ba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e93649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e936a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e93649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e93631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055827a64fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055827a64fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055827a6348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055827a2e3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055827a2e3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0e93632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e936330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e936330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055827a2e3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c (3234 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zvfhmin -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -target-feature +zve64d    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_bf16m8(i64 noundef %tss, <vscale x 32 x bfloat> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv32bf16.i64(i64 %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv32bf16.i64(i64, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_f16m8(i64 noundef %tss, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv32f16.i64(i64 %0, <vscale x 32 x half> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv32f16.i64(i64, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_f32m8(i64 noundef %tss, <vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv16f32.i64(i64 %0, <vscale x 16 x float> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv16f32.i64(i64, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_f64m8(i64 noundef %tss, <vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv8f64.i64(i64 %0, <vscale x 8 x double> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv8f64.i64(i64, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_i8m8(i64 noundef %tss, <vscale x 64 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_i16m8(i64 noundef %tss, <vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64 %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_i32m8(i64 noundef %tss, <vscale x 16 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 16 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64 %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64, <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_i64m8(i64 noundef %tss, <vscale x 8 x i64> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 8 x i64> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64 %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_u8m8(i64 noundef %tss, <vscale x 64 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_u16m8(i64 noundef %tss, <vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64 %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_u32m8(i64 noundef %tss, <vscale x 16 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 16 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64 %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_u64m8(i64 noundef %tss, <vscale x 8 x i64> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 8 x i64> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64 %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_f8e4m3m8(i64 noundef %tss, <vscale x 64 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, <vscale x 64 x 
# | ...
# `---data was truncated (10240/11632) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555f43533eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555f43530e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000555f4353462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3e3de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3e3dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3e3de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3e3de31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f434c9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555f434c9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000555f434ae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555f4315de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555f4315db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3e3de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3e3de330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3e3de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f4315da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c (3235 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b32_m(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | 
# | ...
# `---data was truncated (10240/11938) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556e1fb69eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556e1fb66e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556e1fb6a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f211e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f211e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f211e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f211e31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e1faffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556e1faffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556e1fae48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556e1f793e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556e1f793b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f211e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f211e31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f211e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e1f793a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c (3236 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsub_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsub_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsub_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsub_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsub_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsub_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsub_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsub_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bflo
# | ...
# `---data was truncated (10240/34364) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055afb8f30eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055afb8f2de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055afb8f3162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3020505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f302055c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3020505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f30204ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055afb8ec6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055afb8ec6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055afb8eab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055afb8b5ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055afb8b5ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f30204eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f30204ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f30204ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055afb8b5aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c (3237 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d035c8eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d035c8be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d035c8f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5a7a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5a7a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5a7a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5a7a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d035c24bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d035c24a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d035c098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d0358b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d0358b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5a7a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5a7a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5a7a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d0358b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c (3238 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsltu_vv_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsltu_vx_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsltu_vv_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsltu_vx_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsltu_vv_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsltu_vx_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsltu_vv_u8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vsca
# | ...
# `---data was truncated (10240/63705) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561dad051eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000561dad04ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000561dad05262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f253ba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f253baa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f253ba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f253ba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561dacfe7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561dacfe7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000561dacfcc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561dacc7be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561dacc7bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f253ba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f253ba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f253ba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561dacc7ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c (3239 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005646f444deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005646f444ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005646f444e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6123533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f612358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6123533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f612351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005646f43e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005646f43e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005646f43c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005646f4077e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005646f4077b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f612351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f612351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f612351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005646f4077a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c (3240 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosy
# | ...
# `---data was truncated (10240/12666) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005571547cceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005571547c9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005571547cd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6558449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f65584a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6558449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6558431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557154762bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557154762a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005571547478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005571543f6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005571543f6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6558432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f65584330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f65584330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005571543f6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c (3241 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_f32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_i32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_i32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_i32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_u32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# | ...
# `---data was truncated (10240/60691) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005605117f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005605117f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005605117f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa713a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa713aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa713a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa713a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560511789bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000560511789a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056051176e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056051141de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056051141db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa713a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa713a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa713a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056051141da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c (3242 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_f16mf4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_f16mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_f16m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_f16m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_f16m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_i16mf4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_i16mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_i16m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_i16m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_i16m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.r
# | ...
# `---data was truncated (10240/33423) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e834a7eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e834a7be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e834a7f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e76249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e762a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e76249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e76231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e834a14bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e834a14a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e8349f98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e8346a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e8346a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0e76232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e762330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e762330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e8346a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c (3243 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_f32mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_f32m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_i32mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_i32m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_u32mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_u32m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_i32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_i32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry
# | ...
# `---data was truncated (10240/14002) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005568a3e5ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005568a3e59e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005568a3e5d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa4bb649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa4bb6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa4bb649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa4bb631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005568a3df2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005568a3df2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005568a3dd78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005568a3a86e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005568a3a86b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fa4bb632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4bb6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4bb6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005568a3a86a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c (3244 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsmul_vv_i64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsmul_vx_i64m1(<vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsmul_vv_i64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsmul_vx_i64m2(<vscale x 2 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsmul_vv_i64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 4 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsmul_vx_i64m4(<vscale x 4 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsmul_vv_i64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 8 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsmul_vx_i64m8(<vscale x 8 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsmul_vv_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsmul_vx_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr 
# | ...
# `---data was truncated (10240/18895) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba640adeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ba640aae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ba640ae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbce9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbce998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbce9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbce991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba64043bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ba64043a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ba640288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ba63cd7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ba63cd7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fbce991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbce991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbce991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba63cd7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c (3245 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrev8_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrev8_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vrev8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrev8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrev8_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vrev8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrev8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrev8_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vrev8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrev8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrev8_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vrev8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrev8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vrev8_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vrev8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrev8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vrev8_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vrev8.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrev8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vrev8_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vrev8.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrev8.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vrev8_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vrev8.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrev8.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vrev8_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vrev8.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrev8.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vrev8_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vrev8.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vrev8.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vrev8_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vrev8.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vrev8.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vrev8_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vrev8.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: noca
# | ...
# `---data was truncated (10240/40803) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558946cc1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558946cbee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558946cc262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe218133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe21818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe218133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe21811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558946c57bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558946c57a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558946c3c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005589468ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005589468ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe21811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe21811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe21811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005589468eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c (3246 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_f32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_i32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_i32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_i32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_u32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_u32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_u32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i6
# | ...
# `---data was truncated (10240/47604) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564e02422eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564e0241fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564e0242362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f445021bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f44502725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f445021ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4450203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564e023b8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564e023b8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564e0239d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564e0204ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564e0204cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4450204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44502050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44502050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564e0204ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c (3247 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_bf16mf2x5(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_bf16m1x5(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e63fefceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e63fef9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e63fefd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faa51e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faa51ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faa51e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faa51e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e63fe92bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e63fe92a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e63fe778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e63fb26e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e63fb26b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007faa51e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faa51e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faa51e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e63fb26a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c (3248 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8(<vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4(<vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2(<vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1(<vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_xu_f_qf_u8m2(<vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 8 x 
# | ...
# `---data was truncated (10240/12463) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b5a33e1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b5a33dee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b5a33e262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6615c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6615c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6615c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6615c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b5a3377bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b5a3377a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b5a335c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b5a300be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b5a300bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6615c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6615c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6615c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b5a300ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c (3249 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfadd_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfadd_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfadd_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfadd_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfadd_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfadd_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfadd_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfadd_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfadd_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfadd.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfadd.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfadd_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   stor
# | ...
# `---data was truncated (10240/29518) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556ce8ed6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000556ce8ed3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000556ce8ed762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe88dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe88dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe88dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe88dc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ce8e6cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556ce8e6ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000556ce8e518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556ce8b00e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556ce8b00b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe88dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe88dc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe88dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556ce8b00a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c (3250 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005560f2cd1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005560f2ccee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005560f2cd262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc783333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc78338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc783333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc78331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005560f2c67bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005560f2c67a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005560f2c4c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005560f28fbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005560f28fbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc78331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc78331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc78331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005560f28fba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c (3251 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b66e0c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055b66e0c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055b66e0c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fef98f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fef98f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fef98f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fef98f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b66e05abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055b66e05aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055b66e03f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055b66dceee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055b66dceeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fef98f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fef98f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fef98f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b66dceea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c (3252 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e6da55eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e6da55be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e6da55f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ec6249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ec62a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ec6249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ec6231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e6da4f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e6da4f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e6da4d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e6da188e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e6da188b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5ec6232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ec62330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ec62330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e6da188a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c (3253 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_f64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_f64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_f64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_i64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_i64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_i64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_u64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_u64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_u64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %
# | ...
# `---data was truncated (10240/47698) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005643ff7b2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005643ff7afe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005643ff7b362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7a75849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7a758a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7a75849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7a75831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005643ff748bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005643ff748a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005643ff72d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005643ff3dce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005643ff3dcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7a75832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7a758330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7a758330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005643ff3dca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c (3254 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsof_m_b1_mu(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %maskedoff, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %2, <vscale x 64 x i1> %0, i64 %3)
# |   ret <vscale x 64 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsof_m_b2_mu(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %maskedoff, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %2, <vscale x 32 x i1> %0, i64 %3)
# |   ret <vscale x 32 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsof_m_b4_mu(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %maskedoff, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %2, <vscale x 16 x i1> %0, i64 %3)
# |   ret <vscale x 16 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsof_m_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %2, <vscale x 8 x i1> %0, i64 %3)
# |   ret <vscale x 8 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsof_m_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %2, <vscale x 4 x i1> %0, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsof_m_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %2, <vscale x 2 x i1> %0, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsof_m_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1.i64(<vscale x 1 x i1> %1, <vscale x 1 x i1> %2, <vscale x 1 x i1> %0, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e410ee7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e410ee4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e410ee862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc7c9505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc7c955c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc7c9505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc7c94ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e410e7dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e410e7da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e410e628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e410b11e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e410b11b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc7c94eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc7c94ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc7c94ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e410b11a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c (3255 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f16m1x8(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f32m1x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f64m1x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei64_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055576746ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000555767469e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055576746d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff845733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff84578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff845733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff84571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555767402bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000555767402a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005557673e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000555767096e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000555767096b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff84571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff84571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff84571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555767096a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c (3256 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf4_f32m1(<vscale x 1 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float>, <vscale x 1 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf2_f32m1(<vscale x 2 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m1_f32m1(<vscale x 4 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float>, <vscale x 4 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m2_f32m1(<vscale x 8 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float>, <vscale x 8 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m4_f32m1(<vscale x 16 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float>, <vscale x 16 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m8_f32m1(<vscale x 32 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float>, <vscale x 32 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32mf2_f64m1(<vscale x 1 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m1_f64m1(<vscale x 2 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64(<vscale x 1 x double>, <vscale x 2 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m2_f64m1(<vscale x 4 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret 
# | ...
# `---data was truncated (10240/50516) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005630e1ee0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005630e1edde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005630e1ee162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb7bd849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb7bd8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb7bd849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb7bd831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005630e1e76bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005630e1e76a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005630e1e5b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005630e1b0ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005630e1b0ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb7bd832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb7bd8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb7bd8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005630e1b0aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c (3257 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_i64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_u64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_i64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_u64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.ve
# | ...
# `---data was truncated (10240/18498) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560158a59eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000560158a56e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000560158a5a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2bec105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2bec15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2bec105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2bec0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005601589efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005601589efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005601589d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000560158683e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000560158683b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f2bec0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2bec0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2bec0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560158683a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c (3258 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>
# | ...
# `---data was truncated (10240/19492) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564e921cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000564e921cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000564e921ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f37d881bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f37d88725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f37d881ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f37d8803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564e92163bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564e92163a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000564e921488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564e91df7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564e91df7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f37d8804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f37d88050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f37d88050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564e91df7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c (3259 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005614012a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056140129fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005614012a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd2a8c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd2a8c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd2a8c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd2a8c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561401238bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000561401238a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056140121d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000561400ecce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000561400eccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd2a8c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd2a8c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd2a8c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561400ecca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c (3260 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4au_vx_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4au_vx_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | ...
# `---data was truncated (10240/13625) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005588484e6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005588484e3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005588484e762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd725449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd7254a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd725449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd725431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055884847cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055884847ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005588484618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558848110e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558848110b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd725432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd7254330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd7254330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558848110a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c (3261 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i8> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, <vscale x
# | ...
# `---data was truncated (10240/15615) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005585750d9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005585750d6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005585750da62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e89249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e892a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e89249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e89231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055857506fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055857506fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005585750548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558574d03e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558574d03b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1e89232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e892330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e892330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558574d03a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c (3262 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8mf8x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_u8mf8x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_u8mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_u8mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_u8m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, a
# | ...
# `---data was truncated (10240/26721) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005564883a0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055648839de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005564883a162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f84a1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f84a178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f84a1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f84a171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556488336bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000556488336a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055648831b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000556487fcae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000556487fcab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f84a171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f84a171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f84a171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556487fcaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c (3263 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a3a856ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055a3a8569e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055a3a856d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f630361bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f63036725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f630361ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6303603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a3a8502bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055a3a8502a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055a3a84e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055a3a8196e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055a3a8196b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6303604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f63036050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f63036050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a3a8196a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c (3264 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_i32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_i32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_u32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_u32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c1b8efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562c1b8ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562c1b8f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f98b8333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f98b838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f98b8333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f98b831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c1b885bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562c1b885a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562c1b86a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562c1b519e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562c1b519b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f98b831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f98b831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f98b831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c1b519a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c (3265 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e8bc09eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e8bc09be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e8bc09f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe84db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe84db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe84db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe84db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e8bc034bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e8bc034a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e8bc0198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e8bbcc8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e8bbcc8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fe84db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe84db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe84db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e8bbcc8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c (3266 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_f32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_i32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_i32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_i32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_u32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_u32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_u32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align
# | ...
# `---data was truncated (10240/47596) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055870ba6ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055870ba69e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055870ba6d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0d7c305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0d7c35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0d7c305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0d7c2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055870ba02bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055870ba02a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055870b9e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055870b696e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055870b696b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f0d7c2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0d7c2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0d7c2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055870b696a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c (3267 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558de5fa5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558de5fa2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000558de5fa662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcf03e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcf03ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcf03e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcf03e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558de5f3bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558de5f3ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558de5f208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558de5bcfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558de5bcfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fcf03e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcf03e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcf03e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558de5bcfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c (3268 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_f32mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_f32m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_f32m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_i32mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_i32m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_i32m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_u32mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_u32m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_u32m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1
# | ...
# `---data was truncated (10240/24072) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056469046feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056469046ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056469047062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e37b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e37b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e37b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e37b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564690405bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000564690405a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005646903ea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000564690099e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000564690099b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f4e37b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e37b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e37b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564690099a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c (3269 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_f32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_i32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_i32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_i32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_u32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# | ...
# `---data was truncated (10240/60691) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055be194cceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055be194c9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055be194cd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8364049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83640a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8364049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8364031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055be19462bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055be19462a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055be194478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055be190f6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055be190f6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8364032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83640330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83640330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055be190f6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c (3270 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei32_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei32_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei32_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Fun
# | ...
# `---data was truncated (10240/12067) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005601b19c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005601b19bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005601b19c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5717933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f571798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5717933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f571791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005601b1957bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005601b1957a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005601b193c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005601b15ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005601b15ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f571791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f571791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f571791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005601b15eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c (3271 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056132f6c5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056132f6c2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056132f6c662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3fb0a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3fb0aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3fb0a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3fb0a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056132f65bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056132f65ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056132f6408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056132f2efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056132f2efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3fb0a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3fb0a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3fb0a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056132f2efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c (3272 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562ca5ffceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562ca5ff9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562ca5ffd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff288f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff288f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff288f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff288f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562ca5f92bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562ca5f92a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562ca5f778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562ca5c26e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562ca5c26b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007ff288f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff288f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff288f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562ca5c26a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c (3273 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("risc
# | ...
# `---data was truncated (10240/21103) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562fc7685eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000562fc7682e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000562fc768662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f77a8533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f77a858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f77a8533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f77a851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562fc761bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000562fc761ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000562fc76008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000562fc72afe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000562fc72afb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f77a851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f77a851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f77a851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562fc72afa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c (3274 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f16m1x5(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f32m1x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f64m1x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei8_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vsca
# | ...
# `---data was truncated (10240/61665) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056442cd00eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056442ccfde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056442cd0162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f742bc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f742bca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f742bc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f742bc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056442cc96bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056442cc96a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056442cc7b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056442c92ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056442c92ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f742bc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f742bc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f742bc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056442c92aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c (3275 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8mf8x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_u8mf8x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_u8mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | 
# | ...
# `---data was truncated (10240/31868) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055883804beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000558838048e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055883804c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf6c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf6c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf6c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf6c91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558837fe1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000558837fe1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000558837fc68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000558837c75e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000558837c75b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fdf6c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf6c91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf6c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558837c75a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGenHIP/offload-pgo-sections.hip (3276 of 27911)
******************** TEST 'Clang :: CodeGenHIP/offload-pgo-sections.hip' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -cuid=abc    -fprofile-instrument=clang -emit-llvm -o - -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip    | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=instrprof -S    | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefix=DEV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -cuid=abc -fprofile-instrument=clang -emit-llvm -o - -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip"
# | target datalayout = "e-m:e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-p10:32:32-p11:32:32-p12:32:32-p13:32:32-p14:32:32-p15:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
# | target triple = "amdgpu-amd-amdhsa"
# | 
# | $__profc__Z6helperi = comdat any
# | 
# | $__llvm_prf_unifcnt__Z6helperi = comdat any
# | 
# | $__profc__Z6kernelPi = comdat any
# | 
# | $__llvm_prf_unifcnt__Z6kernelPi = comdat any
# | 
# | @__hip_cuid_b04fd23c98500190 = addrspace(1) global i8 0
# | @__profc__Z6helperi = linkonce_odr protected addrspace(1) global [1 x i64] zeroinitializer, section "__llvm_prf_cnts", comdat, align 8
# | @__llvm_prf_unifcnt__Z6helperi = linkonce_odr protected addrspace(1) global [1 x i64] zeroinitializer, section "__llvm_prf_ucnts", comdat, align 8
# | @__profd__Z6helperi = linkonce_odr protected addrspace(1) global { i64, i64, i64, i64, i64, ptr, ptr, i32, [3 x i16], i16, i32 } { i64 6265860958107916728, i64 24, i64 sub (i64 ptrtoint (ptr addrspace(1) @__profc__Z6helperi to i64), i64 ptrtoint (ptr addrspace(1) @__profd__Z6helperi to i64)), i64 sub (i64 ptrtoint (ptr addrspace(1) @__llvm_prf_unifcnt__Z6helperi to i64), i64 ptrtoint (ptr addrspace(1) @__profd__Z6helperi to i64)), i64 0, ptr null, ptr null, i32 1, [3 x i16] zeroinitializer, i16 0, i32 0 }, section "__llvm_prf_data", comdat($__profc__Z6helperi), align 8
# | @__profc__Z6kernelPi = linkonce_odr protected addrspace(1) global [1 x i64] zeroinitializer, section "__llvm_prf_cnts", comdat, align 8
# | @__llvm_prf_unifcnt__Z6kernelPi = linkonce_odr protected addrspace(1) global [1 x i64] zeroinitializer, section "__llvm_prf_ucnts", comdat, align 8
# | @__profd__Z6kernelPi = linkonce_odr protected addrspace(1) global { i64, i64, i64, i64, i64, ptr, ptr, i32, [3 x i16], i16, i32 } { i64 4905896731224577586, i64 0, i64 sub (i64 ptrtoint (ptr addrspace(1) @__profc__Z6kernelPi to i64), i64 ptrtoint (ptr addrspace(1) @__profd__Z6kernelPi to i64)), i64 sub (i64 ptrtoint (ptr addrspace(1) @__llvm_prf_unifcnt__Z6kernelPi to i64), i64 ptrtoint (ptr addrspace(1) @__profd__Z6kernelPi to i64)), i64 0, ptr null, ptr null, i32 1, [3 x i16] zeroinitializer, i16 0, i32 0 }, section "__llvm_prf_data", comdat($__profc__Z6kernelPi), align 8
# | @__llvm_prf_nm_b04fd23c98500190 = protected addrspace(1) constant [32 x i8] c"\16\1Ex\DA\8B\8F2\CBH\CD)H-\CAd\8C\8F2\CBN-\CAK\CD\09\C8\04\00Z\AD\08\03", section "__llvm_prf_names", align 1
# | @__start___llvm_prf_names = external hidden addrspace(1) global i8
# | @__stop___llvm_prf_names = external hidden addrspace(1) global i8
# | @__start___llvm_prf_cnts = external hidden addrspace(1) global i8
# | @__stop___llvm_prf_cnts = external hidden addrspace(1) global i8
# | @__start___llvm_prf_data = external hidden addrspace(1) global i8
# | @__stop___llvm_prf_data = external hidden addrspace(1) global i8
# | @__start___llvm_prf_ucnts = external hidden addrspace(1) global i8
# | @__stop___llvm_prf_ucnts = external hidden addrspace(1) global i8
# | @__llvm_profile_raw_version = external addrspace(1) constant i64
# | @__llvm_profile_sections_b04fd23c98500190 = protected addrspace(1) constant { ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1) } { ptr addrspace(1) @__start___llvm_prf_names, ptr addrspace(1) @__stop___llvm_prf_names, ptr addrspace(1) @__start___llvm_prf_cnts, ptr addrspace(1) @__stop___llvm_prf_cnts, ptr addrspace(1) @__start___llvm_prf_data, ptr addrspace(1) @__stop___llvm_prf_data, ptr addrspace(1) @__start___llvm_prf_ucnts, ptr addrspace(1) @__stop___llvm_prf_ucnts, ptr addrspace(1) @__llvm_profile_raw_version }
# | @llvm.compiler.used = appending addrspace(1) global [6 x ptr] [ptr addrspacecast (ptr addrspace(1) @__hip_cuid_b04fd23c98500190 to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_prf_unifcnt__Z6helperi to ptr), ptr addrspacecast (ptr addrspace(1) @__profd__Z6helperi to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_prf_unifcnt__Z6kernelPi to ptr), ptr addrspacecast (ptr addrspace(1) @__profd__Z6kernelPi to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_profile_sections_b04fd23c98500190 to ptr)], section "llvm.metadata"
# | @llvm.used = appending addrspace(1) global [1 x ptr] [ptr addrspacecast (ptr addrspace(1) @__llvm_prf_nm_b04fd23c98500190 to ptr)], section "llvm.metadata"
# | 
# | ; Function Attrs: convergent mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z6helperi(i32 noundef %x) #0 {
# | entry:
# |   %0 = call i32 @llvm.amdgcn.wavefrontsize()
# |   %wavesize.i16 = trunc i32 %0 to i16
# |   store i16 %wavesize.i16, ptr addrspace(1) getelementptr inbounds nuw (i8, ptr addrspace(1) @__profd__Z6helperi, i64 66), align 2
# |   %pgo.sampled = call i32 @__llvm_profile_sampling_gpu(i32 3)
# |   %pgo.matched = icmp ne i32 %pgo.sampled, 0
# |   %x.addr = alloca i32, align 4, addrspace(5)
# |   %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr
# |   store i32 %x, ptr %x.addr.ascast, align 4
# |   br i1 %pgo.matched, label %po_then, label %po_cont
# | 
# | po_cont:                                          ; preds = %po_then, %entry
# |   %1 = load i32, ptr %x.addr.ascast, align 4
# |   %add = add nsw i32 %1, 1
# |   ret i32 %add
# | 
# | po_then:                                          ; preds = %entry
# |   call void @__llvm_profile_instrument_gpu(ptr addrspacecast (ptr addrspace(1) @__profc__Z6helperi to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_prf_unifcnt__Z6helperi to ptr), i64 1)
# |   br label %po_cont
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.instrprof.increment(ptr, i64, i32, i32) #1
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind optnone
# | define dso_local amdgpu_kernel void @_Z6kernelPi(ptr addrspace(1) noundef %p.coerce) #2 {
# | entry:
# |   %0 = call i32 @llvm.amdgcn.wavefrontsize()
# |   %wavesize.i16 = trunc i32 %0 to i16
# |   store i16 %wavesize.i16, ptr addrspace(1) getelementptr inbounds nuw (i8, ptr addrspace(1) @__profd__Z6kernelPi, i64 66), align 2
# |   %pgo.sampled = call i32 @__llvm_profile_sampling_gpu(i32 3)
# |   %pgo.matched = icmp ne i32 %pgo.sampled, 0
# |   %p = alloca ptr, align 8, addrspace(5)
# |   %p.addr = alloca ptr, align 8, addrspace(5)
# |   %p.addr.ascast = addrspacecast ptr addrspace(5) %p.addr to ptr
# |   store ptr addrspace(1) %p.coerce, ptr addrspace(5) %p, align 8
# |   %p1 = load ptr, ptr addrspace(5) %p, align 8
# |   store ptr %p1, ptr %p.addr.ascast, align 8
# |   br i1 %pgo.matched, label %po_then, label %po_cont
# | 
# | po_cont:                                          ; preds = %po_then, %entry
# |   %1 = load ptr, ptr %p.addr.ascast, align 8
# |   %2 = load i32, ptr %1, align 4
# |   %call = call noundef i32 @_Z6helperi(i32 noundef %2) #4
# |   %3 = load ptr, ptr %p.addr.ascast, align 8
# |   store i32 %call, ptr %3, align 4
# |   ret void
# | 
# | po_then:                                          ; preds = %entry
# |   call void @__llvm_profile_instrument_gpu(ptr addrspacecast (ptr addrspace(1) @__profc__Z6kernelPi to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_prf_unifcnt__Z6kernelPi to ptr), i64 1)
# |   br label %po_cont
# | }
# | 
# | declare i32 @__llvm_profile_sampling_gpu(i32)
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare noundef range(i32 32, 65) i32 @llvm.amdgcn.wavefrontsize() #3
# | 
# | declare void @__llvm_profile_instrument_gpu(ptr, ptr, i64)
# | 
# | attributes #0 = { convergent mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size" }
# | attributes #1 = { nounwind }
# | attributes #2 = { convergent mustprogress noinline norecurse nounwind optnone "amdgpu-flat-work-group-size"="1,1024" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size" }
# | attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #4 = { convergent nounwind "uniform-work-group-size" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 2, !"EnableValueProfiling", i32 0}
# | !1 = !{i32 1, !"amdhsa_code_object_version", i32 600}
# | !2 = !{i32 1, !"amdgpu_printf_kind", !"hostcall"}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=instrprof -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=instrprof -S
# |  #0 0x0000557ec412aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000557ec4127e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000557ec412b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4224133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f422418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4224133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f422411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ec40c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000557ec40c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000557ec40a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000557ec3d54e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000557ec3d54b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f422411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f422411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f422411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ec3d54a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefix=DEV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefix=DEV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c (3277 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesef_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesef_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesef_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare
# | ...
# `---data was truncated (10240/20141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f4f3a8beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f4f3a88e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f4f3a8c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9975649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f99756a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9975649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9975631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f4f3a21bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f4f3a21a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f4f3a068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f4f36b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f4f36b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9975632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f99756330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f99756330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f4f36b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c (3278 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559fc280eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000559fc280be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x0000559fc280f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc1ef849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc1ef8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc1ef849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc1ef831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559fc27a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000559fc27a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x0000559fc27898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x0000559fc2438e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x0000559fc2438b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fc1ef832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc1ef8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc1ef8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559fc2438a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c (3279 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { targ
# | ...
# `---data was truncated (10240/21111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f2c7c48eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055f2c7c45e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055f2c7c4962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f07dd133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f07dd18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f07dd133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f07dd11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f2c7bdebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055f2c7bdea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055f2c7bc38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055f2c7872e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055f2c7872b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f07dd11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f07dd11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f07dd11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f2c7872a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vaddv.c (3280 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vaddv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %0, i32 0)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.addv.v16i8(<16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v8i16(<8 x i16> %0, i32 0)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.addv.v8i16(<8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v4i32(<4 x i32> %0, i32 0)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.addv.v4i32(<4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %0, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v8i16(<8 x i16> %0, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v4i32(<4 x i32> %0, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_s8(i32 noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %b.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %0, i32 0)
# |   %2 = load i32, ptr %a.addr, align 4
# |   %3 = add i32 %1, %2
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_s16(i32 noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v8i16(<8 x i16> %0, i32 0)
# |   %2 = load i32, ptr %a.addr, align 4
# |   %3 = add i32 %1, %2
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_s32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v4i32(<4 x i32> %0, i32 0)
# |   %2 = load i32, ptr %a.addr, align 4
# |   %3 = add i32 %1, %2
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_u8(i32 noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %b.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %0, i32 1)
# |   %2 = load i32, ptr %a.addr, align 4
# |   %3 = add i32 %1, %2
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_u16(i32 noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v8i16(<8 x i16> %0, i32 1)
# |   %2 = load i32, ptr %a.addr, align 4
# |   %3 = add i32 %1, %2
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_u32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v4i32(<4 x i32> %0, i32 1)
# |   %2 = load i32, ptr %a.addr, align 4
# |   %3 = add i32 %1, %2
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_s8(<16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = call i32 @llvm.arm.mve.addv.predicated.v16i8.v16i1(<16 x i8> %0, i32 0, <16 x i1> %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.addv.predicated.v16i8.v16i1(<16 x i8>, i32, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_s16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %0, i32 0, <8 x i1> %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16>, i32, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_s32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32>, i32, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_u8(<16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = call i32 @llvm.arm.mve.addv.predicated.v16i8.v16i1(<16 x i8> %0, i32 1, <16 x i1> %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_u16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %0, i32 1, <8 x i1> %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_u32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 1, <4 x i1> %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_p_s8(i32 noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 =
# | ...
# `---data was truncated (10240/19190) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005607bb088eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005607bb085e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005607bb08962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9bd7a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9bd7aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9bd7a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9bd7a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607bb01ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005607bb01ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005607bb0038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005607bacb2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005607bacb2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f9bd7a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9bd7a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9bd7a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607bacb2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c (3281 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055da0afe5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055da0afe2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055da0afe662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8194049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f81940a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8194049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8194031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da0af7bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055da0af7ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055da0af608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055da0ac0fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055da0ac0fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f8194032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f81940330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f81940330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da0ac0fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c (3282 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_f32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_f32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_f32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_i32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_i32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_i32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_u32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_u32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_u32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tu
# | ...
# `---data was truncated (10240/23405) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e0e4fc9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e0e4fc6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e0e4fca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b06333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b0638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b06333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b0631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e0e4f5fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e0e4f5fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e0e4f448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e0e4bf3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e0e4bf3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3b0631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b0631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b0631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e0e4bf3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c (3283 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e99d788eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e99d785e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e99d78962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd199733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd19978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd199733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd19971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e99d71ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e99d71ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e99d7038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e99d3b2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e99d3b2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd19971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd19971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd19971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e99d3b2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c (3284 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2cl_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2cl_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2cl_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2cl_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2cl_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2cl_vv_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2cl_vv_u64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2cl_vv_u64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | 
# | ...
# `---data was truncated (10240/12216) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005608e82dbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005608e82d8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005608e82dc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd52bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd52bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd52bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd52bd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005608e8271bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005608e8271a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005608e82568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005608e7f05e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005608e7f05b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fd52bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd52bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd52bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005608e7f05a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c (3285 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f16m1x7(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f32m1x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f64m1x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei64_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d0113c7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055d0113c4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055d0113c862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f179f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f179f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f179f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f179f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d01135dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055d01135da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055d0113428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055d010ff1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055d010ff1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f179f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f179f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f179f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d010ff1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c (3286 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_i16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_i16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_i16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_u16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, ali
# | ...
# `---data was truncated (10240/60543) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c5f5185eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c5f5182e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c5f518662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e91049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e910a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e91049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e91031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c5f511bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c5f511ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c5f51008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c5f4dafe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c5f4dafb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6e91032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e910330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e910330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c5f4dafa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c (3287 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdm_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdm.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdm.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdm_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdm_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdm_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesdm_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdm_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdm_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretur
# | ...
# `---data was truncated (10240/20190) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c73ad02eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055c73acffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055c73ad0362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fad69e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fad69ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fad69e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fad69e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c73ac98bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055c73ac98a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055c73ac7d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055c73a92ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055c73a92cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fad69e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fad69e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fad69e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c73a92ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c (3288 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vgmul_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vgmul_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vgmul_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vgmul_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vgmul_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e4305dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055e4305dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055e4305e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1121649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f11216a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1121649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1121631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e430575bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055e430575a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055e43055a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055e430209e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055e430209b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f1121632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f11216330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f11216330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e430209a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c (3289 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlse16_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vlse.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vlse.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlse16_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vlse.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vlse.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlse16_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vlse.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vlse.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlse16_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vlse.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vlse.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlse16_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vlse.nxv16bf16.p0.i64(<vscale x 16 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vlse.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlse16_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vlse.nxv32bf16.p0.i64(<vscale x 32 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vlse.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlse16_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlse16_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlse16_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 
# | ...
# `---data was truncated (10240/28361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005573a0abbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005573a0ab8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005573a0abc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f521a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f521a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f521a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f521a631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005573a0a51bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005573a0a51a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005573a0a368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005573a06e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005573a06e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f521a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f521a6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f521a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005573a06e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c (3290 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei32_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei32_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei32_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, <vscale x 8 x i1>, i64, i64 immarg) #
# | ...
# `---data was truncated (10240/12075) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056311049ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x0000563110499e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056311049d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fea89333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fea8938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fea89333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fea8931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563110432bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x0000563110432a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005631104178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005631100c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005631100c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fea8931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fea8931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fea8931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005631100c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c (3291 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005622ef53ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005622ef539e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005622ef53d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3d1ab05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3d1ab5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3d1ab05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3d1aaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005622ef4d2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005622ef4d2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005622ef4b78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005622ef166e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005622ef166b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f3d1aaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3d1aaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3d1aaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005622ef166a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c (3292 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_i64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_u64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_f64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_i64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_u64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple
# | ...
# `---data was truncated (10240/20903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055676dcebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055676dce8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055676dcec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f87f3449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87f34a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f87f3449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87f3431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055676dc81bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055676dc81a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055676dc668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055676d915e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055676d915b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f87f3432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87f34330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87f34330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055676d915a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c (3293 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjn_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjn_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjn_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjn_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjn_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjn_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjn_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjn_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnjn_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnjn_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %
# | ...
# `---data was truncated (10240/29210) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ead8a6ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055ead8a69e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055ead8a6d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb7ca21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb7ca2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb7ca21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb7ca203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ead8a02bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055ead8a02a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055ead89e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055ead8696e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055ead8696b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007fb7ca204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb7ca2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb7ca2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ead8696a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c (3294 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei32_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale
# | ...
# `---data was truncated (10240/32108) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005597a71b2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x00005597a71afe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x00005597a71b362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b32d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b32d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b32d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b32d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005597a7148bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x00005597a7148a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x00005597a712d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x00005597a6ddce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x00005597a6ddcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f5b32d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b32d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b32d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005597a6ddca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c (3295 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesem_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesem.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesem.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesem_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesem_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesem_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesem_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesem_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesem_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | ...
# `---data was truncated (10240/20149) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055734bd8deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000055734bd8ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000055734bd8e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6179b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6179b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6179b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6179b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055734bd23bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000055734bd23a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000055734bd088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000055734b9b7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000055734b9b7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f6179b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6179b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6179b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055734b9b7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c (3296 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_f64m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_i64m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_u64m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056281ccbceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056281ccb9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056281ccbd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c38649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c386a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c38649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c38631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056281cc52bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056281cc52a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056281cc378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056281c8e6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056281c8e6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f7c38632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c386330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c386330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056281c8e6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c (3611 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_i8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e8_v_i8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e8_v_i8m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_u8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_u8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e8_v_u8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/48313) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056122af44eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb)
# |  #1 0x000056122af41e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85)
# |  #2 0x000056122af4562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f31bab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f31bab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f31bab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f31bab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056122aedabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd)
# |  #8 0x000056122aedaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06)
# |  #9 0x000056122aebf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9)
# | #10 0x000056122ab6ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46)
# | #11 0x000056122ab6eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63)
# | #12 0x00007f31bab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31bab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31bab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056122ab6ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90..
********************
Failed Tests (3297):
  Clang :: CodeGen/2005-06-15-ExpandGotoInternalProblem.c
  Clang :: CodeGen/2005-09-24-AsmUserPrefix.c
  Clang :: CodeGen/2008-07-17-no-emit-on-error.c
  Clang :: CodeGen/AArch64/atomic-hint-template.cpp
  Clang :: CodeGen/AArch64/bf16-dotprod-intrinsics.c
  Clang :: CodeGen/AArch64/bf16-getset-intrinsics.c
  Clang :: CodeGen/AArch64/bf16-lane-intrinsics.c
  Clang :: CodeGen/AArch64/bf16-reinterpret-intrinsics.c
  Clang :: CodeGen/AArch64/builtin-shufflevector-fp8.c
  Clang :: CodeGen/AArch64/f16f32dot-intrinsics.c
  Clang :: CodeGen/AArch64/fp8-cast.c
  Clang :: CodeGen/AArch64/fp8-extract.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c
  Clang :: CodeGen/AArch64/neon-2velem.c
  Clang :: CodeGen/AArch64/neon-3v.c
  Clang :: CodeGen/AArch64/neon-dot-product.c
  Clang :: CodeGen/AArch64/neon-extract.c
  Clang :: CodeGen/AArch64/neon-fma.c
  Clang :: CodeGen/AArch64/neon-fp16fml.c
  Clang :: CodeGen/AArch64/neon-intrinsics-constrained.c
  Clang :: CodeGen/AArch64/neon-intrinsics.c
  Clang :: CodeGen/AArch64/neon-ldst-one-rcpc3.c
  Clang :: CodeGen/AArch64/neon-misc-constrained.c
  Clang :: CodeGen/AArch64/neon-misc.c
  Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c
  Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem.c
  Clang :: CodeGen/AArch64/neon-shifts.c
  Clang :: CodeGen/AArch64/neon-tbl.c
  Clang :: CodeGen/AArch64/neon-vcmla.c
  Clang :: CodeGen/AArch64/neon-vcombine.c
  Clang :: CodeGen/AArch64/neon-vget-hilo.c
  Clang :: CodeGen/AArch64/neon-vsqadd-float-conversion.c
  Clang :: CodeGen/AArch64/neon/add.c
  Clang :: CodeGen/AArch64/neon/bf16-getset.c
  Clang :: CodeGen/AArch64/neon/conversion-fullfp16.c
  Clang :: CodeGen/AArch64/neon/f16-getset.c
  Clang :: CodeGen/AArch64/neon/fullfp16-constrained.c
  Clang :: CodeGen/AArch64/neon/fullfp16.c
  Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c
  Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16.c
  Clang :: CodeGen/AArch64/neon/fused-multiply-constrained.c
  Clang :: CodeGen/AArch64/neon/fused-multiply.c
  Clang :: CodeGen/AArch64/neon/getset.c
  Clang :: CodeGen/AArch64/neon/intrinsics-constrained.c
  Clang :: CodeGen/AArch64/neon/intrinsics.c
  Clang :: CodeGen/AArch64/neon/load.c
  Clang :: CodeGen/AArch64/neon/perm.c
  Clang :: CodeGen/AArch64/neon/rounding-v8.5.c
  Clang :: CodeGen/AArch64/neon/rounding.c
  Clang :: CodeGen/AArch64/neon/store.c
  Clang :: CodeGen/AArch64/neon/subtraction.c
  Clang :: CodeGen/AArch64/neon/vpaddl.c
  Clang :: CodeGen/AArch64/neon/widen.c
  Clang :: CodeGen/AArch64/poly128.c
  Clang :: CodeGen/AArch64/poly64.c
  Clang :: CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp
  Clang :: CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c
  Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c
  Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c
  Clang :: CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_add.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_and.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c
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  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c
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  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c
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  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_div.c
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  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c
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  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c
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  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c
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  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_max.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_min.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_not.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c
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  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c
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  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c
  Clang :: CodeGen/AArch64/sve-vector-arith-ops.c
  Clang :: CodeGen/AArch64/sve-vector-bitwise-ops.c
  Clang :: CodeGen/AArch64/sve-vector-compare-ops.c
  Clang :: CodeGen/AArch64/sve-vector-shift-ops.c
  Clang :: CodeGen/AArch64/sve-vector-subscript-ops.c
  Clang :: CodeGen/AArch64/sve-vls-arith-ops.c
  Clang :: CodeGen/AArch64/sve-vls-bitwise-ops.c
  Clang :: CodeGen/AArch64/sve-vls-compare-ops.c
  Clang :: CodeGen/AArch64/sve-vls-shift-ops.c
  Clang :: CodeGen/AArch64/sve-vls-subscript-ops.c
  Clang :: CodeGen/AArch64/sve/addv.c
  Clang :: CodeGen/AArch64/sve/andv.c
  Clang :: CodeGen/AArch64/sve/dup.c
  Clang :: CodeGen/AArch64/sve/eorv.c
  Clang :: CodeGen/AArch64/sve/len.c
  Clang :: CodeGen/AArch64/sve/maxnmv.c
  Clang :: CodeGen/AArch64/sve/maxv.c
  Clang :: CodeGen/AArch64/sve/minnmv.c
  Clang :: CodeGen/AArch64/sve/minv.c
  Clang :: CodeGen/AArch64/sve/nand.c
  Clang :: CodeGen/AArch64/sve/nor.c
  Clang :: CodeGen/AArch64/sve/orn.c
  Clang :: CodeGen/AArch64/sve/orv.c
  Clang :: CodeGen/AArch64/sve/pfalse.c
  Clang :: CodeGen/AArch64/sve/recpe.c
  Clang :: CodeGen/AArch64/sve/recps.c
  Clang :: CodeGen/AArch64/sve/rsqrte.c
  Clang :: CodeGen/AArch64/sve/rsqrts.c
  Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c
  Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c
  Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c
  Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c
  Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c
  Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c
  Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c
  Clang :: CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c
  Clang :: CodeGen/AArch64/v8.1a-neon-intrinsics.c
  Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c
  Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics.c
  Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c
  Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c
  Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics.c
  Clang :: CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c
  Clang :: CodeGen/AArch64/v8.6a-neon-intrinsics.c
  Clang :: CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c
  Clang :: CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c
  Clang :: CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c
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  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c
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  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c
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  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c
  Clang :: CodeGen/RISCV/builtin-cpu-is.c
  Clang :: CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c
  Clang :: CodeGen/RISCV/riscv-xandesbfhcvt.c
  Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c
  Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c
  Clang :: CodeGen/RISCV/riscv-xandesperf-rv32.c
  Clang :: CodeGen/RISCV/riscv-xandesperf-rv64.c
  Clang :: CodeGen/RISCV/riscv-xcvalu-c-api.c
  Clang :: CodeGen/RISCV/riscv-xcvalu.c
  Clang :: CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c
  Clang :: CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c
  Clang :: CodeGen/RISCV/rvb-intrinsics/zbb.c
  Clang :: CodeGen/RISCV/rvb-intrinsics/zbc.c
  Clang :: CodeGen/RISCV/rvb-intrinsics/zbkb.c
  Clang :: CodeGen/RISCV/rvb-intrinsics/zbkc.c
  Clang :: CodeGen/RISCV/rvb-intrinsics/zbkx.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/zksed.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/zksh.c
  Clang :: CodeGen/RISCV/rvp-intrinsics.c
  Clang :: CodeGen/RISCV/rvv-builtin-reduce-ops.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c
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  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c
  Clang :: CodeGen/RISCV/rvv-vls-arith-ops.c
  Clang :: CodeGen/RISCV/rvv-vls-bitwise-ops.c
  Clang :: CodeGen/RISCV/rvv-vls-compare-ops.c
  Clang :: CodeGen/RISCV/rvv-vls-shift-ops.c
  Clang :: CodeGen/RISCV/rvv-vls-subscript-ops.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c
  Clang :: CodeGen/SystemZ/zvector.c
  Clang :: CodeGen/WebAssembly/builtins-table-externref.c
  Clang :: CodeGen/WebAssembly/builtins-table-funcref.c
  Clang :: CodeGen/X86/avx-cmp-builtins.c
  Clang :: CodeGen/X86/avx-shuffle-builtins.c
  Clang :: CodeGen/X86/bfloat16-convert-half.c
  Clang :: CodeGen/X86/sse.c
  Clang :: CodeGen/aapcs-bitfield.c
  Clang :: CodeGen/arm-bf16-convert-intrinsics.c
  Clang :: CodeGen/arm-bf16-dotprod-intrinsics.c
  Clang :: CodeGen/arm-bf16-params-returns.c
  Clang :: CodeGen/arm-bf16-reinterpret-intrinsics.c
  Clang :: CodeGen/arm-cde-gpr.c
  Clang :: CodeGen/arm-cde-reinterpret.c
  Clang :: CodeGen/arm-cde-vec.c
  Clang :: CodeGen/arm-cde-vfp.c
  Clang :: CodeGen/arm-crc32.c
  Clang :: CodeGen/arm-mfp8.c
  Clang :: CodeGen/arm-mve-intrinsics/absneg.c
  Clang :: CodeGen/arm-mve-intrinsics/admin.c
  Clang :: CodeGen/arm-mve-intrinsics/bitwise-imm.c
  Clang :: CodeGen/arm-mve-intrinsics/compare.c
  Clang :: CodeGen/arm-mve-intrinsics/cplusplus.cpp
  Clang :: CodeGen/arm-mve-intrinsics/dup.c
  Clang :: CodeGen/arm-mve-intrinsics/get-set-lane.c
  Clang :: CodeGen/arm-mve-intrinsics/idup.c
  Clang :: CodeGen/arm-mve-intrinsics/load-store.c
  Clang :: CodeGen/arm-mve-intrinsics/predicates.c
  Clang :: CodeGen/arm-mve-intrinsics/reinterpret.c
  Clang :: CodeGen/arm-mve-intrinsics/scalar-shifts.c
  Clang :: CodeGen/arm-mve-intrinsics/scatter-gather.c
  Clang :: CodeGen/arm-mve-intrinsics/ternary.c
  Clang :: CodeGen/arm-mve-intrinsics/vabavq.c
  Clang :: CodeGen/arm-mve-intrinsics/vabdq.c
  Clang :: CodeGen/arm-mve-intrinsics/vadc.c
  Clang :: CodeGen/arm-mve-intrinsics/vaddq.c
  Clang :: CodeGen/arm-mve-intrinsics/vaddv.c
  Clang :: CodeGen/arm-mve-intrinsics/vandq.c
  Clang :: CodeGen/arm-mve-intrinsics/vbicq.c
  Clang :: CodeGen/arm-mve-intrinsics/vbrsrq.c
  Clang :: CodeGen/arm-mve-intrinsics/vcaddq.c
  Clang :: CodeGen/arm-mve-intrinsics/vclz.c
  Clang :: CodeGen/arm-mve-intrinsics/vcmlaq.c
  Clang :: CodeGen/arm-mve-intrinsics/vcmulq.c
  Clang :: CodeGen/arm-mve-intrinsics/vcvt.c
  Clang :: CodeGen/arm-mve-intrinsics/vcvt_anpm.c
  Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c
  Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm.c
  Clang :: CodeGen/arm-mve-intrinsics/vector-shift-var.c
  Clang :: CodeGen/arm-mve-intrinsics/veorq.c
  Clang :: CodeGen/arm-mve-intrinsics/vhaddq.c
  Clang :: CodeGen/arm-mve-intrinsics/vhcaddq.c
  Clang :: CodeGen/arm-mve-intrinsics/vhsubq.c
  Clang :: CodeGen/arm-mve-intrinsics/vld24.c
  Clang :: CodeGen/arm-mve-intrinsics/vldr.c
  Clang :: CodeGen/arm-mve-intrinsics/vmaxaq.c
  Clang :: CodeGen/arm-mve-intrinsics/vmaxnmaq.c
  Clang :: CodeGen/arm-mve-intrinsics/vmaxnmq.c
  Clang :: CodeGen/arm-mve-intrinsics/vmaxq.c
  Clang :: CodeGen/arm-mve-intrinsics/vminaq.c
  Clang :: CodeGen/arm-mve-intrinsics/vminnmaq.c
  Clang :: CodeGen/arm-mve-intrinsics/vminnmq.c
  Clang :: CodeGen/arm-mve-intrinsics/vminq.c
  Clang :: CodeGen/arm-mve-intrinsics/vminvq.c
  Clang :: CodeGen/arm-mve-intrinsics/vmldav.c
  Clang :: CodeGen/arm-mve-intrinsics/vmlldav.c
  Clang :: CodeGen/arm-mve-intrinsics/vmovl.c
  Clang :: CodeGen/arm-mve-intrinsics/vmovn.c
  Clang :: CodeGen/arm-mve-intrinsics/vmulhq.c
  Clang :: CodeGen/arm-mve-intrinsics/vmullbq.c
  Clang :: CodeGen/arm-mve-intrinsics/vmulltq.c
  Clang :: CodeGen/arm-mve-intrinsics/vmulq.c
  Clang :: CodeGen/arm-mve-intrinsics/vornq.c
  Clang :: CodeGen/arm-mve-intrinsics/vorrq.c
  Clang :: CodeGen/arm-mve-intrinsics/vqaddq.c
  Clang :: CodeGen/arm-mve-intrinsics/vqdmlad.c
  Clang :: CodeGen/arm-mve-intrinsics/vqdmulhq.c
  Clang :: CodeGen/arm-mve-intrinsics/vqdmullbq.c
  Clang :: CodeGen/arm-mve-intrinsics/vqdmulltq.c
  Clang :: CodeGen/arm-mve-intrinsics/vqmovn.c
  Clang :: CodeGen/arm-mve-intrinsics/vqrdmulhq.c
  Clang :: CodeGen/arm-mve-intrinsics/vqsubq.c
  Clang :: CodeGen/arm-mve-intrinsics/vrev.c
  Clang :: CodeGen/arm-mve-intrinsics/vrhaddq.c
  Clang :: CodeGen/arm-mve-intrinsics/vrmulhq.c
  Clang :: CodeGen/arm-mve-intrinsics/vrnd.c
  Clang :: CodeGen/arm-mve-intrinsics/vshlc.c
  Clang :: CodeGen/arm-mve-intrinsics/vsubq.c
  Clang :: CodeGen/arm-neon-directed-rounding-constrained.c
  Clang :: CodeGen/arm-neon-directed-rounding.c
  Clang :: CodeGen/arm-neon-dot-product.c
  Clang :: CodeGen/arm-neon-endianness.c
  Clang :: CodeGen/arm-neon-fma.c
  Clang :: CodeGen/arm-neon-numeric-maxmin.c
  Clang :: CodeGen/arm-neon-shifts.c
  Clang :: CodeGen/arm-neon-vcadd.c
  Clang :: CodeGen/arm-neon-vcvtX.c
  Clang :: CodeGen/arm-neon-vget.c
  Clang :: CodeGen/arm-neon-vld.c
  Clang :: CodeGen/arm-neon-vst.c
  Clang :: CodeGen/arm-poly-add.c
  Clang :: CodeGen/arm-v8.1a-neon-intrinsics.c
  Clang :: CodeGen/arm-v8.2a-neon-intrinsics-generic.c
  Clang :: CodeGen/arm-v8.2a-neon-intrinsics.c
  Clang :: CodeGen/arm-v8.6a-neon-intrinsics.c
  Clang :: CodeGen/arm-vector_type-params-returns.c
  Clang :: CodeGen/arm64-crc32.c
  Clang :: CodeGen/arm64-lanes.c
  Clang :: CodeGen/arm64_vcopy.c
  Clang :: CodeGen/arm64_vcreate.c
  Clang :: CodeGen/arm64_vdupq_n_f64.c
  Clang :: CodeGen/arm_acle.c
  Clang :: CodeGen/arm_acle_swp.c
  Clang :: CodeGen/arm_neon_intrinsics.c
  Clang :: CodeGen/attr-counted-by-issue200014.c
  Clang :: CodeGen/builtin-align.c
  Clang :: CodeGen/builtins-arm-exclusive.c
  Clang :: CodeGen/builtins-arm.c
  Clang :: CodeGen/builtins-arm64.c
  Clang :: CodeGen/builtins-loongarch.c
  Clang :: CodeGen/builtins-riscv.c
  Clang :: CodeGen/cx-complex-range-real.c
  Clang :: CodeGen/cx-complex-range.c
  Clang :: CodeGen/distributed-thin-lto/backend-skip.ll
  Clang :: CodeGen/distributed-thin-lto/basic.ll
  Clang :: CodeGen/distributed-thin-lto/cfi-devirt.ll
  Clang :: CodeGen/distributed-thin-lto/cfi.ll
  Clang :: CodeGen/distributed-thin-lto/newpm.ll
  Clang :: CodeGen/distributed-thin-lto/objc-contract-pass.ll
  Clang :: CodeGen/distributed-thin-lto/supports-hot-cold-new.ll
  Clang :: CodeGen/linker-diagnostic.ll
  Clang :: CodeGen/memcmp-inline-builtin-to-asm.c
  Clang :: CodeGen/mozilla-ms-inline-asm.c
  Clang :: CodeGen/packed-structure.c
  Clang :: CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll
  Clang :: CodeGen/thinlto-funcattr-prop.ll
  Clang :: CodeGen/thinlto-multi-module.ll
  Clang :: CodeGen/thinlto-opaque-typed-mix.ll
  Clang :: CodeGen/thinlto_backend.ll
  Clang :: CodeGen/thinlto_backend_local_name_conflict.ll
  Clang :: CodeGen/thinlto_embed_bitcode.ll
  Clang :: CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu
  Clang :: CodeGenCXX/aarch64-sve-vector-conditional-op.cpp
  Clang :: CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp
  Clang :: CodeGenCXX/attr-musttail.cpp
  Clang :: CodeGenCXX/ctor-globalopt.cpp
  Clang :: CodeGenCXX/inline-then-fold-variadics.cpp
  Clang :: CodeGenCXX/thinlto_public_type_test_distributed.ll
  Clang :: CodeGenCXX/virtual-base-ctor.cpp
  Clang :: CodeGenCoroutines/coro-gro4.cpp
  Clang :: CodeGenCoroutines/pr65054.cpp
  Clang :: CodeGenHIP/offload-pgo-sections.hip
  Clang :: CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl
  Clang :: Modules/pr93497.cppm


Testing Time: 162.29s

Total Discovered Tests: 55927
  Skipped          :    37 (0.07%)
  Unsupported      :  1675 (2.99%)
  Passed           : 50889 (90.99%)
  Expectedly Failed:    29 (0.05%)
  Failed           :  3297 (5.90%)
FAILED: gen/clang/test/run-lit 
python3 bin/llvm-lit -sv ../../clang/test
ninja: build stopped: subcommand failed.
Command '['ninja', '-C', 'out/gn', 'check-clang']' returned non-zero exit status 1.